mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 20:31:14 +00:00
exo2: minor fixes, now completes main and receives SMCs on hw
This commit is contained in:
parent
27843314a4
commit
8c4c1db506
11 changed files with 134 additions and 47 deletions
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@ -125,7 +125,7 @@ namespace ams::secmon::boot {
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SetL3BlockEntry(l3, MemoryRegionVirtualTzramConfigurationData.GetAddress(), MemoryRegionPhysicalTzramConfigurationData.GetAddress(), MemoryRegionVirtualTzramConfigurationData.GetSize(), MappingAttributesEl3SecureRwData);
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/* Map the page tables. */
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SetL3BlockEntry(l3, util::AlignDown(MemoryRegionVirtualTzramL1PageTable.GetAddress(), PageSize), util::AlignDown(MemoryRegionPhysicalTzramL1PageTable.GetAddress(), PageSize), PageSize, MappingAttributesEl3SecureDevice);
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SetL3BlockEntry(l3, util::AlignDown(MemoryRegionVirtualTzramL1PageTable.GetAddress(), PageSize), util::AlignDown(MemoryRegionPhysicalTzramL1PageTable.GetAddress(), PageSize), PageSize, MappingAttributesEl3SecureRwData);
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SetL3BlockEntry(l3, MemoryRegionVirtualTzramL2L3PageTable.GetAddress(), MemoryRegionPhysicalTzramL2L3PageTable.GetAddress(), MemoryRegionVirtualTzramL2L3PageTable.GetSize(), MappingAttributesEl3SecureRwData);
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}
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}
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@ -19,6 +19,26 @@
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namespace ams::diag {
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void AbortImpl() {
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/* TODO: This is here for debugging. Remove this when exo2 is working. */
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#if 1
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{
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x00) = 0xDDDDDDDD;
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u64 temp_reg;
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__asm__ __volatile__("mov %0, lr" : "=r"(temp_reg) :: "memory");
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x10) = static_cast<u32>(temp_reg >> 0);
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x14) = static_cast<u32>(temp_reg >> 32);
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__asm__ __volatile__("mov %0, sp" : "=r"(temp_reg) :: "memory");
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for (int i = 0; i < 0x100; i += 4) {
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x20 + i) = *(volatile u32 *)(temp_reg + i);
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}
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*(volatile u32 *)(secmon::MemoryRegionVirtualDevicePmc.GetAddress() + 0x50) = 0x02;
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*(volatile u32 *)(secmon::MemoryRegionVirtualDevicePmc.GetAddress() + 0x00) = 0x10;
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}
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#endif
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secmon::SetError(pkg1::ErrorInfo_UnknownAbort);
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secmon::ErrorReboot();
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}
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@ -36,6 +56,42 @@ namespace ams::secmon {
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}
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NORETURN void ErrorReboot() {
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/* TODO: This is here for debugging. Remove this when exo2 is working. */
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#if 1
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{
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u64 temp_reg;
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x00) = 0x5A5A5A5A;
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__asm__ __volatile__("mrs %0, esr_el3" : "=r"(temp_reg) :: "memory");
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x08) = static_cast<u32>(temp_reg >> 0);
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x0C) = static_cast<u32>(temp_reg >> 32);
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__asm__ __volatile__("mrs %0, elr_el3" : "=r"(temp_reg) :: "memory");
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x18) = static_cast<u32>(temp_reg >> 0);
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x1C) = static_cast<u32>(temp_reg >> 32);
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__asm__ __volatile__("mrs %0, far_el3" : "=r"(temp_reg) :: "memory");
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x18) = static_cast<u32>(temp_reg >> 0);
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x1C) = static_cast<u32>(temp_reg >> 32);
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__asm__ __volatile__("mov %0, lr" : "=r"(temp_reg) :: "memory");
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x20) = static_cast<u32>(temp_reg >> 0);
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x24) = static_cast<u32>(temp_reg >> 32);
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__asm__ __volatile__("mov %0, sp" : "=r"(temp_reg) :: "memory");
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x30) = static_cast<u32>(temp_reg >> 0);
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x34) = static_cast<u32>(temp_reg >> 32);
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for (int i = 0; i < 0x100; i += 4) {
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*(volatile u32 *)(secmon::MemoryRegionVirtualDebug.GetAddress() + 0x40 + i) = *(volatile u32 *)(temp_reg + i);
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}
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*(volatile u32 *)(secmon::MemoryRegionVirtualDevicePmc.GetAddress() + 0x50) = 0x02;
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*(volatile u32 *)(secmon::MemoryRegionVirtualDevicePmc.GetAddress() + 0x00) = 0x10;
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util::WaitMicroSeconds(1000);
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}
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#endif
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/* Lockout the security engine. */
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se::Lockout();
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@ -21,6 +21,9 @@ namespace ams::secmon {
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namespace {
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constexpr inline const uintptr_t BootCodeAddress = MemoryRegionVirtualTzramBootCode.GetAddress();
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constexpr inline const size_t BootCodeSize = MemoryRegionVirtualTzramBootCode.GetSize();
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using namespace ams::mmu;
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constexpr void UnmapBootCodeImpl(u64 *l1, u64 *l2, u64 *l3, uintptr_t boot_code, size_t boot_code_size) {
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@ -39,6 +42,20 @@ namespace ams::secmon {
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InvalidateL1Entries(l1, MemoryRegionPhysical.GetAddress(), MemoryRegionPhysical.GetSize());
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}
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void ClearLow(uintptr_t address, size_t size) {
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/* Clear the low part. */
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util::ClearMemory(reinterpret_cast<void *>(address), size / 2);
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}
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void ClearHigh(uintptr_t address, size_t size) {
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/* Clear the high part. */
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util::ClearMemory(reinterpret_cast<void *>(address + size / 2), size / 2);
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}
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}
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void ClearBootCodeHigh() {
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ClearHigh(BootCodeAddress, BootCodeSize);
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}
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void UnmapBootCode() {
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@ -46,15 +63,11 @@ namespace ams::secmon {
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u64 * const l1 = MemoryRegionVirtualTzramL1PageTable.GetPointer<u64>();
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u64 * const l2_l3 = MemoryRegionVirtualTzramL2L3PageTable.GetPointer<u64>();
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/* Get the boot code region. */
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const uintptr_t boot_code = MemoryRegionVirtualTzramBootCode.GetAddress();
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const size_t boot_code_size = MemoryRegionVirtualTzramBootCode.GetSize();
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/* Clear the boot code. */
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util::ClearMemory(reinterpret_cast<void *>(boot_code), boot_code_size);
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/* Clear the low boot code region; high was already cleared by a previous call. */
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ClearLow(BootCodeAddress, BootCodeSize);
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/* Unmap. */
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UnmapBootCodeImpl(l1, l2_l3, l2_l3, boot_code, boot_code_size);
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UnmapBootCodeImpl(l1, l2_l3, l2_l3, BootCodeAddress, BootCodeSize);
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/* Ensure the mappings are consistent. */
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secmon::EnsureMappingConsistency();
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@ -52,7 +52,7 @@ namespace ams::secmon {
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constinit const se::StickyBits ExpectedSeStickyBits = {
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.se_security = (1 << 0), /* SE_HARD_SETTING */
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.tzram_security = 0,
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.crypto_security_perkey = 0,
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.crypto_security_perkey = (1 << pkg1::AesKeySlot_UserEnd) - 1,
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.crypto_keytable_access = {
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(1 << 6) | (1 << 5) | (0 << 4) | (1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), /* 0: User keyslot. KEYUSE, UIVUPDATE, OIVUPDATE, KEYUPDATE enabled. UIVREAD, OIVREAD, KEYREAD disabled. */
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(1 << 6) | (1 << 5) | (0 << 4) | (1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), /* 1: User keyslot. KEYUSE, UIVUPDATE, OIVUPDATE, KEYUPDATE enabled. UIVREAD, OIVREAD, KEYREAD disabled. */
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@ -60,15 +60,15 @@ namespace ams::secmon {
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(1 << 6) | (1 << 5) | (0 << 4) | (1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), /* 3: User keyslot. KEYUSE, UIVUPDATE, OIVUPDATE, KEYUPDATE enabled. UIVREAD, OIVREAD, KEYREAD disabled. */
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(1 << 6) | (1 << 5) | (0 << 4) | (1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), /* 4: User keyslot. KEYUSE, UIVUPDATE, OIVUPDATE, KEYUPDATE enabled. UIVREAD, OIVREAD, KEYREAD disabled. */
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(1 << 6) | (1 << 5) | (0 << 4) | (1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), /* 5: User keyslot. KEYUSE, UIVUPDATE, OIVUPDATE, KEYUPDATE enabled. UIVREAD, OIVREAD, KEYREAD disabled. */
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(0 << 6) | (1 << 5) | (0 << 4) | (1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), /* 6: Unused keyslot. UIVUPDATE, OIVUPDATE, KEYUPDATE enabled. KEYUSE, UIVREAD, OIVREAD, KEYREAD disabled. */
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(0 << 6) | (1 << 5) | (0 << 4) | (1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), /* 7: Unused keyslot. UIVUPDATE, OIVUPDATE, KEYUPDATE enabled. KEYUSE, UIVREAD, OIVREAD, KEYREAD disabled. */
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(0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (0 << 1) | (0 << 0), /* 6: Unused keyslot. KEYUSE, UIVUPDATE, UIVREAD, OIVUPDATE, OIVREAD, KEYUPDATE, KEYREAD disabled. */
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(0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (0 << 1) | (0 << 0), /* 7: Unused keyslot. KEYUSE, UIVUPDATE, UIVREAD, OIVUPDATE, OIVREAD, KEYUPDATE, KEYREAD disabled. */
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(0 << 6) | (1 << 5) | (0 << 4) | (1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), /* 8: Temp keyslot. UIVUPDATE, OIVUPDATE, KEYUPDATE enabled. KEYUSE, UIVREAD, OIVREAD, KEYREAD disabled. */
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(0 << 6) | (1 << 5) | (0 << 4) | (1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), /* 9: SmcTemp keyslot. UIVUPDATE, OIVUPDATE, KEYUPDATE enabled. KEYUSE, UIVREAD, OIVREAD, KEYREAD disabled. */
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(0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (0 << 1) | (0 << 0), /* 10: Wrap1 keyslot. KEYUSE, UIVUPDATE, UIVREAD, OIVUPDATE, OIVREAD, KEYUPDATE, KEYREAD disabled. */
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(0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (0 << 1) | (0 << 0), /* 11: Wrap2 keyslot. KEYUSE, UIVUPDATE, UIVREAD, OIVUPDATE, OIVREAD, KEYUPDATE, KEYREAD disabled. */
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(0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (0 << 1) | (0 << 0), /* 12: DMaster keyslot. KEYUSE, UIVUPDATE, UIVREAD, OIVUPDATE, OIVREAD, KEYUPDATE, KEYREAD disabled. */
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(0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (0 << 1) | (0 << 0), /* 13: Master keyslot. KEYUSE, UIVUPDATE, UIVREAD, OIVUPDATE, OIVREAD, KEYUPDATE, KEYREAD disabled. */
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(0 << 6) | (1 << 5) | (0 << 4) | (1 << 3) | (0 << 2) | (1 << 1) | (0 << 0), /* 14: Unused keyslot. UIVUPDATE, OIVUPDATE, KEYUPDATE enabled. KEYUSE, UIVREAD, OIVREAD, KEYREAD disabled. */
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(0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (0 << 1) | (0 << 0), /* 14: Unused keyslot. KEYUSE, UIVUPDATE, UIVREAD, OIVUPDATE, OIVREAD, KEYUPDATE, KEYREAD disabled. */
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(0 << 6) | (0 << 5) | (0 << 4) | (0 << 3) | (0 << 2) | (0 << 1) | (0 << 0), /* 13: Device keyslot. KEYUSE, UIVUPDATE, UIVREAD, OIVUPDATE, OIVREAD, KEYUPDATE, KEYREAD disabled. */
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},
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.rsa_security_perkey = 0,
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@ -24,7 +24,7 @@ _ZN3ams6secmon5StartEv:
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mov sp, x20
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/* Set SPSEL 0 stack pointer to a temporary location in volatile memory. */
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msr spsel, #1
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msr spsel, #0
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ldr x20, =0x1F01C0800
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mov sp, x20
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@ -34,17 +34,20 @@ _ZN3ams6secmon5StartEv:
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/* Invoke main. */
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bl _ZN3ams6secmon4MainEv
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/* Clear boot code high. */
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bl _ZN3ams6secmon17ClearBootCodeHighEv
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/* Set the stack pointer to the core 3 exception stack address. */
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ldr x20, =0x1F01F9000
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mov sp, x20
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/* Unmap the boot code region (and clear the low part). */
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bl _ZN3ams6secmon13UnmapBootCodeEv
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/* Initialize the random cache. */
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/* NOTE: Nintendo does this much earlier, but we reuse volatile space. */
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bl _ZN3ams6secmon3smc15FillRandomCacheEv
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/* Unmap the boot code region. */
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bl _ZN3ams6secmon13UnmapBootCodeEv
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/* Jump to lower exception level. */
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b _ZN3ams6secmon25JumpToLowerExceptionLevelEv
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@ -169,7 +172,6 @@ _ZN3ams6secmon25ReleaseCommonSmcStackLockEv:
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/* Return. */
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ret
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ret
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.section .text._ZN3ams6secmon26ReleaseCommonWarmbootStackEv, "ax", %progbits
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.align 4
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@ -228,6 +228,21 @@ namespace ams::secmon::smc {
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/* Set the invocation result. */
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args.r[0] = static_cast<u64>(InvokeSmcHandler(info, args));
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/* TODO: For debugging. Remove this when exo2 is complete. */
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#if 1
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if (args.r[0] == static_cast<u64>(SmcResult::NotImplemented)) {
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*(volatile u32 *)(MemoryRegionVirtualDebug.GetAddress()) = 0xBBBBBBBB;
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*(volatile u32 *)(MemoryRegionVirtualDebug.GetAddress() + 0x10) = static_cast<u32>(info.function_id);
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for (size_t i = 0; i < sizeof(args) / sizeof(u32); ++i) {
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((volatile u32 *)(MemoryRegionVirtualDebug.GetAddress() + 0x20))[i] = reinterpret_cast<u32 *>(std::addressof(args))[i];
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}
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*(volatile u32 *)(MemoryRegionVirtualDevicePmc.GetAddress() + 0x50) = 0x02;
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*(volatile u32 *)(MemoryRegionVirtualDevicePmc.GetAddress() + 0x00) = 0x10;
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util::WaitMicroSeconds(1000);
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}
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#endif
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}
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}
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@ -201,22 +201,29 @@ namespace ams::mmu::arch::arm64 {
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return ((address >> L3EntryShift) & TableEntryIndexMask);
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}
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constexpr ALWAYS_INLINE void SetTableImpl(u64 *table, u64 index, u64 value) {
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/* Ensure (for constexpr validation purposes) that the entry we set is clear. */
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if (table[index]) {
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__builtin_unreachable();
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}
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/* Set the value. */
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constexpr ALWAYS_INLINE void SetTableEntryImpl(volatile u64 *table, u64 index, u64 value) {
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/* Write the value. */
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table[index] = value;
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}
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constexpr ALWAYS_INLINE void SetTableEntry(u64 *table, u64 index, u64 value) {
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/* Ensure (for constexpr validation purposes) that the entry we set is clear. */
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if (std::is_constant_evaluated()) {
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if (table[index]) {
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__builtin_unreachable();
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}
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}
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/* Set the value. */
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SetTableEntryImpl(table, index, value);
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}
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constexpr void SetL1TableEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, PageTableTableAttribute attr) {
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SetTableImpl(table, GetL1EntryIndex(virt_addr), MakeTableEntry(phys_addr & TableEntryMask, attr));
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SetTableEntry(table, GetL1EntryIndex(virt_addr), MakeTableEntry(phys_addr & TableEntryMask, attr));
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}
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constexpr void SetL2TableEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, PageTableTableAttribute attr) {
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SetTableImpl(table, GetL2EntryIndex(virt_addr), MakeTableEntry(phys_addr & TableEntryMask, attr));
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SetTableEntry(table, GetL2EntryIndex(virt_addr), MakeTableEntry(phys_addr & TableEntryMask, attr));
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}
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constexpr void SetL1BlockEntry(u64 *table, uintptr_t virt_addr, uintptr_t phys_addr, size_t size, PageTableMappingAttribute attr) {
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const u64 count = (size >> L1EntryShift);
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for (u64 i = 0; i < count; ++i) {
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SetTableImpl(table, start + i, MakeL1BlockEntry((phys_addr & L1EntryMask) + (i << L1EntryShift), attr));
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SetTableEntry(table, start + i, MakeL1BlockEntry((phys_addr & L1EntryMask) + (i << L1EntryShift), attr));
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}
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}
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@ -233,7 +240,7 @@ namespace ams::mmu::arch::arm64 {
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const u64 count = (size >> L2EntryShift);
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for (u64 i = 0; i < count; ++i) {
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SetTableImpl(table, start + i, MakeL2BlockEntry((phys_addr & L2EntryMask) + (i << L2EntryShift), attr));
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SetTableEntry(table, start + i, MakeL2BlockEntry((phys_addr & L2EntryMask) + (i << L2EntryShift), attr));
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}
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}
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@ -242,11 +249,11 @@ namespace ams::mmu::arch::arm64 {
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const u64 count = (size >> L3EntryShift);
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for (u64 i = 0; i < count; ++i) {
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SetTableImpl(table, start + i, MakeL3BlockEntry((phys_addr & L3EntryMask) + (i << L3EntryShift), attr));
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SetTableEntry(table, start + i, MakeL3BlockEntry((phys_addr & L3EntryMask) + (i << L3EntryShift), attr));
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}
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}
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constexpr void InvalidateL1Entries(u64 *table, uintptr_t virt_addr, size_t size) {
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constexpr void InvalidateL1Entries(volatile u64 *table, uintptr_t virt_addr, size_t size) {
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const u64 start = GetL1EntryIndex(virt_addr);
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const u64 count = (size >> L1EntryShift);
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const u64 end = start + count;
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@ -256,7 +263,7 @@ namespace ams::mmu::arch::arm64 {
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}
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}
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constexpr void InvalidateL2Entries(u64 *table, uintptr_t virt_addr, size_t size) {
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constexpr void InvalidateL2Entries(volatile u64 *table, uintptr_t virt_addr, size_t size) {
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const u64 start = GetL2EntryIndex(virt_addr);
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const u64 count = (size >> L2EntryShift);
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const u64 end = start + count;
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@ -266,7 +273,7 @@ namespace ams::mmu::arch::arm64 {
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}
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}
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constexpr void InvalidateL3Entries(u64 *table, uintptr_t virt_addr, size_t size) {
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constexpr void InvalidateL3Entries(volatile u64 *table, uintptr_t virt_addr, size_t size) {
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const u64 start = GetL3EntryIndex(virt_addr);
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const u64 count = (size >> L3EntryShift);
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const u64 end = start + count;
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@ -30,17 +30,17 @@ namespace ams::secmon {
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EmummcConfiguration emummc_cfg;
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u8 _raw_emummc_config[0x120];
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};
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union {
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u8 _misc_data[0x400 - sizeof(_raw_exosphere_config) - sizeof(_raw_emummc_config)];
|
||||
};
|
||||
u8 sealed_device_keys[pkg1::KeyGeneration_Max][se::AesBlockSize];
|
||||
u8 sealed_master_keys[pkg1::KeyGeneration_Max][se::AesBlockSize];
|
||||
pkg1::BootConfig boot_config;
|
||||
u8 rsa_private_exponents[4][se::RsaSize];
|
||||
union {
|
||||
u8 _misc_data[0xFC0 - sizeof(_raw_exosphere_config) - sizeof(_raw_emummc_config) - sizeof(sealed_device_keys) - sizeof(sealed_master_keys) - sizeof(boot_config) - sizeof(rsa_private_exponents)];
|
||||
};
|
||||
static_assert(sizeof(ConfigurationContext) == 0x1000);
|
||||
/* u8 l1_page_table[0x40]; */
|
||||
};
|
||||
static_assert(sizeof(ConfigurationContext) == 0xFC0);
|
||||
static_assert(util::is_pod<ConfigurationContext>::value);
|
||||
static_assert(offsetof(ConfigurationContext, sealed_device_keys) == 0x400);
|
||||
|
||||
namespace impl {
|
||||
|
||||
|
|
|
@ -101,14 +101,14 @@ namespace ams::se {
|
|||
void ExecuteOperationSingleBlock(volatile SecurityEngineRegisters *SE, void *dst, size_t dst_size, const void *src, size_t src_size) {
|
||||
/* Validate sizes. */
|
||||
AMS_ABORT_UNLESS(dst_size <= AesBlockSize);
|
||||
AMS_ABORT_UNLESS(src_size == AesBlockSize);
|
||||
AMS_ABORT_UNLESS(src_size <= AesBlockSize);
|
||||
|
||||
/* Set the block count to 1. */
|
||||
reg::Write(SE->SE_CRYPTO_LAST_BLOCK, 0);
|
||||
|
||||
/* Create an aligned buffer. */
|
||||
util::AlignedBuffer<hw::DataCacheLineSize, AesBlockSize> aligned;
|
||||
std::memcpy(aligned, src, AesBlockSize);
|
||||
std::memcpy(aligned, src, src_size);
|
||||
hw::FlushDataCache(aligned, AesBlockSize);
|
||||
hw::DataSynchronizationBarrierInnerShareable();
|
||||
|
||||
|
|
|
@ -62,12 +62,6 @@ namespace ams::se {
|
|||
void SetPerKeySecure() {
|
||||
auto *SE = GetRegisters();
|
||||
|
||||
/* Clear AES PerKey security. */
|
||||
SE->SE_CRYPTO_SECURITY_PERKEY = 0;
|
||||
|
||||
/* Clear RSA PerKey security. */
|
||||
SE->SE_RSA_SECURITY_PERKEY = 0;
|
||||
|
||||
/* Update PERKEY_SETTING to secure. */
|
||||
reg::ReadWrite(SE->SE_SE_SECURITY, SE_REG_BITS_ENUM(SECURITY_PERKEY_SETTING, SECURE));
|
||||
}
|
||||
|
|
|
@ -44,8 +44,8 @@ namespace ams::se {
|
|||
if (!TestRegister(SE->SE_CRYPTO_KEYTABLE_ACCESS[i], bits.crypto_keytable_access[i])) { return false; }
|
||||
}
|
||||
|
||||
/* Test RSA_SCEURITY_PERKEY */
|
||||
if (!TestRegister(SE->SE_CRYPTO_SECURITY_PERKEY, bits.rsa_security_perkey)) { return false; }
|
||||
/* Test RSA_SECURITY_PERKEY */
|
||||
if (!TestRegister(SE->SE_RSA_SECURITY_PERKEY, bits.rsa_security_perkey)) { return false; }
|
||||
|
||||
/* Check RSA_KEYTABLE_ACCESS. */
|
||||
for (int i = 0; i < RsaKeySlotCount; ++i) {
|
||||
|
|
Loading…
Reference in a new issue