mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-11-09 22:56:35 +00:00
sept: fixes to work with new hwinit/etc
This commit is contained in:
Michael Scire
SciresM
parent
cf7ae775e8
commit
8b1835368a
13 changed files with 144 additions and 206 deletions
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@ -15,14 +15,14 @@ MEMORY
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{
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main : ORIGIN = 0xF0000000, LENGTH = 0x10000000
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high_iram : ORIGIN = 0x40010000, LENGTH = 0x8000
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low_iram : ORIGIN = 0x40003000, LENGTH = 0x8000
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low_iram : ORIGIN = 0x40002000, LENGTH = 0x6000
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}
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SECTIONS
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{
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PROVIDE(__start__ = 0xF0000000);
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PROVIDE(__stack_top__ = 0x40020000);
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PROVIDE(__stack_bottom__ = 0x40018000);
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PROVIDE(__stack_top__ = 0x40010000);
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PROVIDE(__stack_bottom__ = 0x40008000);
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PROVIDE(__heap_start__ = 0x90020000);
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PROVIDE(__heap_end__ = 0xA0020000);
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@ -13,14 +13,14 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef FUSEE_CHAINLOADER_H
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#define FUSEE_CHAINLOADER_H
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#include <stddef.h>
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#include <stdint.h>
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#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x6200
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#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x5400
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#define CHAINLOADER_MAX_ENTRIES 128
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typedef struct chainloader_entry_t {
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@ -96,4 +96,5 @@ _start:
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ldr x0, =__start__
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mov sp, x0
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mov fp, #0x0
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bl derive_keys
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@ -13,15 +13,15 @@ PHDRS
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MEMORY
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{
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NULL : ORIGIN = 0x00000000, LENGTH = 0x1000
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main : ORIGIN = 0x40010000, LENGTH = 0x28000
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low_iram : ORIGIN = 0x40003000, LENGTH = 0x8000
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main : ORIGIN = 0x40010000, LENGTH = 0x20000
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low_iram : ORIGIN = 0x40002000, LENGTH = 0x6000
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}
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SECTIONS
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{
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PROVIDE(__start__ = 0x40010000);
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PROVIDE(__stack_top__ = 0x4003C000);
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PROVIDE(__stack_bottom__ = 0x40038000);
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PROVIDE(__stack_top__ = 0x40010000);
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PROVIDE(__stack_bottom__ = 0x40008000);
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PROVIDE(__heap_start__ = 0);
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PROVIDE(__heap_end__ = 0);
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@ -13,14 +13,14 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef FUSEE_CHAINLOADER_H
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#define FUSEE_CHAINLOADER_H
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#include <stddef.h>
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#include <stdint.h>
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#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x6200
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#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x5400
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#define CHAINLOADER_MAX_ENTRIES 128
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typedef struct chainloader_entry_t {
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@ -22,114 +22,83 @@
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#include "sysreg.h"
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#include "i2c.h"
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#include "car.h"
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#include "fuse.h"
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#include "mc.h"
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#include "timers.h"
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#include "pmc.h"
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#include "max77620.h"
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#include "max77812.h"
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/* Determine the current SoC for Mariko specific code. */
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static bool is_soc_mariko() {
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return (fuse_get_soc_type() == 1);
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void _cluster_enable_power()
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{
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/* Reboot I2C5. */
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clkrst_reboot(CARDEVICE_I2C5);
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i2c_init(I2C_5);
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
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val &= 0xDF;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
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val = 0x09;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
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/* Enable power. */
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val = 0x20;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
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val = 0x8D;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
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val = 0xB7;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
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val = 0xB7;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
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}
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static void cluster_enable_power(uint32_t regulator) {
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switch (regulator) {
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case 0: /* Regulator_Max77621 */
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{
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
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val &= 0xDF;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
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val = 0x09;
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i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
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val = 0x20;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
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val = 0x8D;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
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val = 0xB7;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
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val = 0xB7;
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i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
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}
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break;
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case 1: /* Regulator_Max77812PhaseConfiguration31 */
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{
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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if (val) {
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val |= 0x40;
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i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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}
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val = 0x6E;
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i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
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}
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break;
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case 2: /* Regulator_Max77812PhaseConfiguration211 */
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{
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uint8_t val = 0;
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i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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if (val) {
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val |= 0x40;
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i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
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}
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val = 0x6E;
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i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
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}
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break;
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default: return;
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}
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}
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static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
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int _cluster_pmc_enable_partition(uint32_t part, uint32_t toggle)
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{
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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/* Check if the partition has already been turned on. */
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if (pmc->pwrgate_status & part) {
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return;
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}
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if (pmc->pwrgate_status & part)
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return 1;
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uint32_t i = 5001;
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while (pmc->pwrgate_toggle & 0x100) {
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while (pmc->pwrgate_toggle & 0x100)
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{
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udelay(1);
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i--;
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if (i < 1) {
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return;
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}
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if (i < 1)
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return 0;
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}
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/* Turn the partition on. */
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pmc->pwrgate_toggle = (toggle | 0x100);
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i = 5001;
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while (i > 0) {
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/* Check if the partition has already been turned on. */
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if (pmc->pwrgate_status & part) {
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while (i > 0)
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{
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if (pmc->pwrgate_status & part)
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break;
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}
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udelay(1);
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i--;
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}
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return 1;
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}
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void cluster_boot_cpu0(uint32_t entry) {
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void cluster_boot_cpu0(uint32_t entry)
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{
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volatile tegra_car_t *car = car_get_regs();
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bool is_mariko = is_soc_mariko();
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/* Set ACTIVE_CLUSER to FAST. */
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FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE;
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/* Enable VddCpu. */
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cluster_enable_power(is_mariko ? fuse_get_regulator() : 0);
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_cluster_enable_power();
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if (!(car->pllx_base & 0x40000000)) {
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if (!(car->pllx_base & 0x40000000))
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{
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car->pllx_misc3 &= 0xFFFFFFF7;
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udelay(2);
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if (!is_mariko) {
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car->pllx_base = 0x80404E02;
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car->pllx_base = 0x404E02;
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}
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car->pllx_base = 0x80404E02;
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car->pllx_base = 0x404E02;
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car->pllx_misc = ((car->pllx_misc & 0xFFFBFFFF) | 0x40000);
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car->pllx_base = 0x40404E02;
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}
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@ -138,28 +107,28 @@ void cluster_boot_cpu0(uint32_t entry) {
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/* Wait. */
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}
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/* Set MSELECT clock. */
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clk_enable(CARDEVICE_MSELECT);
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/* Configure MSELECT source and enable clock. */
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car->clk_source_mselect = ((car->clk_source_mselect & 0x1FFFFF00) | 6);
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car->clk_out_enb_v = ((car->clk_out_enb_v & 0xFFFFFFF7) | 8);
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/* Configure initial CPU clock frequency and enable clock. */
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car->cclk_brst_pol = 0x20008888;
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car->super_cclk_div = 0x80000000;
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car->clk_enb_v_set = 1;
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/* Reboot CORESIGHT. */
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clkrst_reboot(CARDEVICE_CORESIGHT);
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/* Set CAR2PMC_CPU_ACK_WIDTH to 0. */
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/* CAR2PMC_CPU_ACK_WIDTH should be set to 0. */
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car->cpu_softrst_ctrl2 &= 0xFFFFF000;
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/* Enable CPU rail. */
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cluster_pmc_enable_partition(1, 0);
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_cluster_pmc_enable_partition(1, 0);
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/* Enable cluster 0 non-CPU. */
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cluster_pmc_enable_partition(0x8000, 15);
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_cluster_pmc_enable_partition(0x8000, 15);
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/* Enable CE0. */
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cluster_pmc_enable_partition(0x4000, 14);
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_cluster_pmc_enable_partition(0x4000, 14);
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/* Request and wait for RAM repair. */
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FLOW_CTLR_RAM_REPAIR_0 = 1;
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@ -169,6 +138,11 @@ void cluster_boot_cpu0(uint32_t entry) {
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MAKE_EXCP_VEC_REG(0x100) = 0;
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/* Check for reset vector lock. */
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if (SB_CSR_0 & 2) {
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generic_panic();
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}
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/* Set reset vector. */
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SB_AA64_RESET_LOW_0 = (entry | 1);
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SB_AA64_RESET_HIGH_0 = 0;
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@ -177,18 +151,28 @@ void cluster_boot_cpu0(uint32_t entry) {
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SB_CSR_0 = 2;
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(void)SB_CSR_0;
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/* Validate reset vector lock + RESET_LOW/HIGH values. */
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if (!(SB_CSR_0 & 2)) {
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generic_panic();
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}
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/* TODO: Should we even bother taking as a parameter? */
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if (SB_AA64_RESET_LOW_0 != (0x4003D000 | 1) || SB_AA64_RESET_HIGH_0 != 0) {
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generic_panic();
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}
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/* Set CPU_STRICT_TZ_APERTURE_CHECK. */
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/* NOTE: This breaks Exosphère. */
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/* NOTE: [4.0.0+] This was added, but it breaks Exosphère. */
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/* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */
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/* Clear MSELECT reset. */
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rst_disable(CARDEVICE_MSELECT);
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car->rst_dev_v &= 0xFFFFFFF7;
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if (!is_mariko) {
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/* Clear NONCPU reset. */
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car->rst_cpug_cmplx_clr = 0x20000000;
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}
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/* Clear NONCPU reset. */
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car->rst_cpug_cmplx_clr = 0x20000000;
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/* Clear CPU{0} POR and CORE, CX0, L2, and DBG reset.*/
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/* Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.*/
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/* NOTE: [5.0.0+] This was changed so only CPU0 reset is cleared. */
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/* car->rst_cpug_cmplx_clr = 0x411F000F; */
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car->rst_cpug_cmplx_clr = 0x41010001;
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}
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@ -15,7 +15,7 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hwinit.h"
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#include "apb_misc.h"
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#include "car.h"
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@ -42,12 +42,12 @@ static bool is_soc_mariko() {
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static void config_oscillators(void) {
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volatile tegra_car_t *car = car_get_regs();
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volatile tegra_pmc_t *pmc = pmc_get_regs();
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car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4);
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SYSCTR0_CNTFID0_0 = 19200000;
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TIMERUS_USEC_CFG_0 = 0x45F;
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car->osc_ctrl = 0x50000071;
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pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE);
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pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFBFFFFF) | 0x400000);
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@ -64,10 +64,10 @@ static void config_oscillators(void) {
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static void config_gpios(void) {
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volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
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bool is_mariko = is_soc_mariko();
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if (is_mariko) {
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uint32_t hardware_type = fuse_get_hardware_type();
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/* Only for HardwareType_Iowa and HardwareType_Five. */
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if ((hardware_type == 3) || (hardware_type == 5)) {
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pinmux->uart2_tx = 0;
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@ -81,7 +81,7 @@ static void config_gpios(void) {
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pinmux->uart2_tx = 0;
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pinmux->uart3_tx = 0;
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}
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pinmux->pe6 = PINMUX_INPUT;
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pinmux->ph6 = PINMUX_INPUT;
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if (!is_mariko) {
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@ -106,7 +106,7 @@ static void config_gpios(void) {
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gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO);
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gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT);
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gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT);
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if (is_mariko) {
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/* Configure home button as input. */
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gpio_configure_mode(TEGRA_GPIO(Y, 1), GPIO_MODE_GPIO);
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@ -116,7 +116,7 @@ static void config_gpios(void) {
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static void mbist_workaround(void) {
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volatile tegra_car_t *car = car_get_regs();
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car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF);
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car->plld_base |= 0x40800000u;
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car->rst_dev_y_clr = 0x40;
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@ -135,7 +135,7 @@ static void mbist_workaround(void) {
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MAKE_I2S_REG(0x388) &= 0xFFFFFFFE;
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MAKE_I2S_REG(0x4A0) |= 0x400;
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MAKE_I2S_REG(0x488) &= 0xFFFFFFFE;
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MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4;
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MAKE_VIC_REG(0x8C) = 0xFFFFFFFF;
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udelay(2);
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@ -144,7 +144,7 @@ static void mbist_workaround(void) {
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car->rst_dev_y_set = 0x40;
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car->rst_dev_l_set = 0x18000000;
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car->rst_dev_x_set = 0x40000;
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/* Clock out enables. */
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car->clk_out_enb_h = 0xC0;
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car->clk_out_enb_l = 0x80000130;
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@ -153,14 +153,14 @@ static void mbist_workaround(void) {
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car->clk_out_enb_w = 0x402000FC;
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car->clk_out_enb_x = 0x23000780;
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car->clk_out_enb_y = 0x300;
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|
||||
/* LVL2 clock gate overrides. */
|
||||
car->lvl2_clk_gate_ovra = 0;
|
||||
car->lvl2_clk_gate_ovrb = 0;
|
||||
car->lvl2_clk_gate_ovrc = 0;
|
||||
car->lvl2_clk_gate_ovrd = 0;
|
||||
car->lvl2_clk_gate_ovre = 0;
|
||||
|
||||
|
||||
/* Configure clock sources. */
|
||||
car->plld_base &= 0x1F7FFFFF;
|
||||
car->clk_source_sor1 &= 0xFFFF3FFF;
|
||||
|
|
@ -173,23 +173,23 @@ static void config_se_brom(void) {
|
|||
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
|
||||
|
||||
/* Bootrom part we skipped. */
|
||||
uint32_t sbk[4] = {fuse_chip->FUSE_PRIVATE_KEY[0], fuse_chip->FUSE_PRIVATE_KEY[1], fuse_chip->FUSE_PRIVATE_KEY[2], fuse_chip->FUSE_PRIVATE_KEY[3]};
|
||||
set_aes_keyslot(0xE, sbk, 0x10);
|
||||
|
||||
|
||||
/* Lock SBK from being read. */
|
||||
se->SE_CRYPTO_KEYTABLE_ACCESS[0xE] = 0x7E;
|
||||
|
||||
|
||||
/* This memset needs to happen here, else TZRAM will behave weirdly later on. */
|
||||
memset((void *)0x7C010000, 0, 0x10000);
|
||||
|
||||
|
||||
pmc->crypto_op = 0;
|
||||
se->SE_INT_STATUS = 0x1F;
|
||||
|
||||
|
||||
/* Lock SSK (although it's not set and unused anyways). */
|
||||
se->SE_CRYPTO_KEYTABLE_ACCESS[0xF] = 0x7E;
|
||||
|
||||
|
||||
/* Clear the boot reason to avoid problems later */
|
||||
pmc->scratch200 = 0;
|
||||
pmc->rst_status = 0;
|
||||
|
|
@ -199,18 +199,18 @@ void nx_hwinit(bool enable_log) {
|
|||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
bool is_mariko = is_soc_mariko();
|
||||
|
||||
|
||||
if (!is_mariko) {
|
||||
/* Bootrom stuff we skipped by going through RCM. */
|
||||
config_se_brom();
|
||||
|
||||
|
||||
AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
|
||||
pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);
|
||||
|
||||
|
||||
/* Apply the memory built-in self test workaround. */
|
||||
mbist_workaround();
|
||||
}
|
||||
|
||||
|
||||
/* Enable SE clock. */
|
||||
clkrst_reboot(CARDEVICE_SE);
|
||||
if (is_mariko) {
|
||||
|
|
@ -228,10 +228,10 @@ void nx_hwinit(bool enable_log) {
|
|||
|
||||
/* Configure oscillators. */
|
||||
config_oscillators();
|
||||
|
||||
|
||||
/* Disable pinmux tristate input clamping. */
|
||||
APB_MISC_PP_PINMUX_GLOBAL_0 = 0;
|
||||
|
||||
|
||||
/* Configure GPIOs. */
|
||||
config_gpios();
|
||||
|
||||
|
|
@ -240,22 +240,22 @@ void nx_hwinit(bool enable_log) {
|
|||
clkrst_reboot(CARDEVICE_UARTA);
|
||||
uart_init(UART_A, 115200);
|
||||
}
|
||||
|
||||
|
||||
/* Enable CL-DVFS clock. */
|
||||
clkrst_reboot(CARDEVICE_CL_DVFS);
|
||||
|
||||
|
||||
/* Enable I2C1 clock. */
|
||||
clkrst_reboot(CARDEVICE_I2C1);
|
||||
|
||||
|
||||
/* Enable I2C5 clock. */
|
||||
clkrst_reboot(CARDEVICE_I2C5);
|
||||
|
||||
|
||||
/* Enable TZRAM clock. */
|
||||
clkrst_reboot(CARDEVICE_TZRAM);
|
||||
|
||||
/* Initialize I2C5. */
|
||||
i2c_init(I2C_5);
|
||||
|
||||
|
||||
/* Configure the PMIC. */
|
||||
if (is_mariko) {
|
||||
uint8_t val = 0x40;
|
||||
|
|
@ -283,11 +283,11 @@ void nx_hwinit(bool enable_log) {
|
|||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD1, &val, 1);
|
||||
val = 0x1B;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1);
|
||||
|
||||
|
||||
/* NOTE: [3.0.0+] This was added. */
|
||||
val = 0x22;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_GPIO3, &val, 1);
|
||||
|
||||
|
||||
/* TODO: In 3.x+, if the unit is SDEV, the MBLPD bit is set. */
|
||||
/*
|
||||
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
|
||||
|
|
@ -299,29 +299,29 @@ void nx_hwinit(bool enable_log) {
|
|||
/* Configure SD0 voltage. */
|
||||
uint8_t val = 0x24;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
|
||||
|
||||
|
||||
/* Enable LDO8 in HardwareType_Hoag only. */
|
||||
if (is_mariko && (fuse_get_hardware_type() == 2)) {
|
||||
val = 0xE8;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO8_CFG, &val, 1);
|
||||
}
|
||||
|
||||
|
||||
/* Initialize I2C1. */
|
||||
i2c_init(I2C_1);
|
||||
|
||||
/* Set super clock burst policy. */
|
||||
car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333);
|
||||
|
||||
|
||||
if (is_mariko) {
|
||||
/* Mariko only PMC configuration for TZRAM. */
|
||||
pmc->tzram_pwr_cntrl &= 0xFFFFFFFE;
|
||||
pmc->tzram_non_sec_disable = 0x3;
|
||||
pmc->tzram_sec_disable = 0x3;
|
||||
}
|
||||
|
||||
|
||||
/* Save SDRAM parameters to scratch. */
|
||||
sdram_save_params(sdram_get_params(fuse_get_dram_id()));
|
||||
|
||||
|
||||
/* Initialize SDRAM. */
|
||||
sdram_init();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
|
|
@ -81,66 +81,11 @@ void __program_exit(int rc) {
|
|||
for (;;);
|
||||
}
|
||||
|
||||
#ifdef SEPT_STAGE1_SRC
|
||||
|
||||
static void __program_parse_argc_argv(int argc, char *argdata) {
|
||||
__program_argc = 0;
|
||||
__program_argv = NULL;
|
||||
}
|
||||
#elif defined(SEPT_STAGE2_SRC)
|
||||
#include "stage2.h"
|
||||
static void __program_parse_argc_argv(int argc, char *argdata) {
|
||||
size_t pos = 0, len;
|
||||
|
||||
__program_argc = argc;
|
||||
|
||||
__program_argv = malloc(argc * sizeof(void **));
|
||||
if (__program_argv == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
len = strlen(argdata);
|
||||
__program_argv[0] = malloc(len + 1);
|
||||
if (__program_argv[0] == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
strcpy((char *)__program_argv[0], argdata);
|
||||
pos += len + 1;
|
||||
|
||||
__program_argv[1] = malloc(sizeof(stage2_args_t));
|
||||
if (__program_argv[1] == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
memcpy(__program_argv[1], argdata + pos, sizeof(stage2_args_t));
|
||||
}
|
||||
#else
|
||||
static void __program_parse_argc_argv(int argc, char *argdata) {
|
||||
size_t pos = 0, len;
|
||||
|
||||
__program_argc = argc;
|
||||
|
||||
__program_argv = malloc(argc * sizeof(void **));
|
||||
if (__program_argv == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
for (int i = 0; i < argc; i++) {
|
||||
len = strlen(argdata + pos);
|
||||
__program_argv[i] = malloc(len + 1);
|
||||
if (__program_argv[i] == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
strcpy((char *)__program_argv[i], argdata + pos);
|
||||
pos += len + 1;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __program_cleanup_argv(void) {
|
||||
#ifndef SEPT_STAGE1_SRC
|
||||
for (int i = 0; i < __program_argc; i++) {
|
||||
free(__program_argv[i]);
|
||||
__program_argv[i] = NULL;
|
||||
}
|
||||
free(__program_argv);
|
||||
#endif
|
||||
/* ... */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include "cluster.h"
|
||||
#include "timers.h"
|
||||
#include "fuse.h"
|
||||
#include "uart.h"
|
||||
#include "utils.h"
|
||||
|
||||
#define u8 uint8_t
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include "exception_handlers.h"
|
||||
#include "panic.h"
|
||||
#include "hwinit.h"
|
||||
#include "car.h"
|
||||
#include "di.h"
|
||||
#include "se.h"
|
||||
#include "pmc.h"
|
||||
|
|
@ -93,13 +94,13 @@ static void exfiltrate_keys_and_reboot_if_needed(uint32_t version) {
|
|||
static void display_splash_screen(void) {
|
||||
/* Draw splash. */
|
||||
draw_splash((volatile uint32_t *)g_framebuffer);
|
||||
|
||||
|
||||
/* Turn on the backlight. */
|
||||
display_backlight(true);
|
||||
|
||||
|
||||
/* Ensure the splash screen is displayed for at least one second. */
|
||||
mdelay(1000);
|
||||
|
||||
|
||||
/* Turn off the backlight. */
|
||||
display_backlight(false);
|
||||
}
|
||||
|
|
@ -118,7 +119,7 @@ static void setup_env(void) {
|
|||
|
||||
/* Set the framebuffer. */
|
||||
display_init_framebuffer(g_framebuffer);
|
||||
|
||||
|
||||
/* Set up the exception handlers. */
|
||||
setup_exception_handlers();
|
||||
|
||||
|
|
@ -129,7 +130,7 @@ static void setup_env(void) {
|
|||
static void cleanup_env(void) {
|
||||
/* Unmount the SD card. */
|
||||
unmount_sd();
|
||||
|
||||
|
||||
/* Terminate the display. */
|
||||
display_end();
|
||||
}
|
||||
|
|
@ -164,7 +165,7 @@ int sept_main(uint32_t version) {
|
|||
|
||||
/* Load the loader payload into DRAM. */
|
||||
load_stage2();
|
||||
|
||||
|
||||
/* Display the splash screen. */
|
||||
display_splash_screen();
|
||||
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include "se.h"
|
||||
#include "fuse.h"
|
||||
#include "utils.h"
|
||||
#include "uart.h"
|
||||
|
||||
static uint32_t g_panic_code = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ _start:
|
|||
.word 0x00000000 /* Reserved. */
|
||||
|
||||
begin_relocation_loop:
|
||||
|
||||
/* Relocate ourselves if necessary */
|
||||
ldr r2, =__start__
|
||||
adr r3, _start
|
||||
|
|
@ -43,7 +44,6 @@ _start:
|
|||
mov r1, #0x0
|
||||
str r1, [r0]
|
||||
|
||||
ldr r4, =_relocation_loop_end
|
||||
mov r4, #0x1000
|
||||
mov r1, #0x0
|
||||
_relocation_loop:
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FUSEE_UART_H
|
||||
#define FUSEE_UART_H
|
||||
|
||||
|
|
@ -79,7 +79,7 @@ typedef enum {
|
|||
0 = Transmit 1 stop bit
|
||||
1 = Transmit 2 stop bits (receiver always checks for 1 stop bit)
|
||||
*/
|
||||
UART_LCR_STOP = 1 << 2,
|
||||
UART_LCR_STOP = 1 << 2,
|
||||
UART_LCR_PAR = 1 << 3, /* Parity enabled */
|
||||
UART_LCR_EVEN = 1 << 4, /* Even parity format. There will always be an even number of 1s in the binary representation (PAR = 1) */
|
||||
UART_LCR_SET_P = 1 << 5, /* Set (force) parity to value in LCR[4] */
|
||||
|
|
@ -115,7 +115,7 @@ typedef enum {
|
|||
0 = FIFO_COUNT_GREATER_1
|
||||
1 = FIFO_COUNT_GREATER_4
|
||||
2 = FIFO_COUNT_GREATER_8
|
||||
3 = FIFO_COUNT_GREATER_16
|
||||
3 = FIFO_COUNT_GREATER_16
|
||||
*/
|
||||
UART_FCR_RX_TRIG = 3 << 6,
|
||||
UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_1 = 0 << 6,
|
||||
|
|
@ -163,6 +163,11 @@ void uart_wait_idle(UartDevice dev, UartVendorStatus status);
|
|||
void uart_send(UartDevice dev, const void *buf, size_t len);
|
||||
void uart_recv(UartDevice dev, void *buf, size_t len);
|
||||
|
||||
static inline void uart_send_text(UartDevice dev, const char *str) {
|
||||
uart_send(dev, str, strlen(str));
|
||||
uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE);
|
||||
}
|
||||
|
||||
static inline volatile tegra_uart_t *uart_get_regs(UartDevice dev) {
|
||||
static const size_t offsets[] = {0, 0x40, 0x200, 0x300, 0x400};
|
||||
return (volatile tegra_uart_t *)(UART_BASE + offsets[dev]);
|
||||
|
|
|
|||
Loading…
Reference in a new issue