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sept: fixes to work with new hwinit/etc

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This commit is contained in:
Michael Scire 2021-01-04 17:18:13 -08:00 committed by SciresM
parent cf7ae775e8
commit 8b1835368a
13 changed files with 144 additions and 206 deletions
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6
fusee/fusee-secondary/linker.ld
View file

@ -15,14 +15,14 @@ MEMORY
{
main : ORIGIN = 0xF0000000, LENGTH = 0x10000000
high_iram : ORIGIN = 0x40010000, LENGTH = 0x8000
low_iram : ORIGIN = 0x40003000, LENGTH = 0x8000
low_iram : ORIGIN = 0x40002000, LENGTH = 0x6000
}
SECTIONS
{
PROVIDE(__start__ = 0xF0000000);
PROVIDE(__stack_top__ = 0x40020000);
PROVIDE(__stack_bottom__ = 0x40018000);
PROVIDE(__stack_top__ = 0x40010000);
PROVIDE(__stack_bottom__ = 0x40008000);
PROVIDE(__heap_start__ = 0x90020000);
PROVIDE(__heap_end__ = 0xA0020000);

2
fusee/fusee-secondary/src/chainloader.h
View file

@ -20,7 +20,7 @@
#include <stddef.h>
#include <stdint.h>
#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x6200
#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x5400
#define CHAINLOADER_MAX_ENTRIES 128
typedef struct chainloader_entry_t {

1
sept/sept-secondary/key_derivation/src/start.s
View file

@ -96,4 +96,5 @@ _start:
ldr x0, =__start__
mov sp, x0
mov fp, #0x0
bl derive_keys

8
sept/sept-secondary/linker.ld
View file

@ -13,15 +13,15 @@ PHDRS
MEMORY
{
NULL : ORIGIN = 0x00000000, LENGTH = 0x1000
main : ORIGIN = 0x40010000, LENGTH = 0x28000
low_iram : ORIGIN = 0x40003000, LENGTH = 0x8000
main : ORIGIN = 0x40010000, LENGTH = 0x20000
low_iram : ORIGIN = 0x40002000, LENGTH = 0x6000
}
SECTIONS
{
PROVIDE(__start__ = 0x40010000);
PROVIDE(__stack_top__ = 0x4003C000);
PROVIDE(__stack_bottom__ = 0x40038000);
PROVIDE(__stack_top__ = 0x40010000);
PROVIDE(__stack_bottom__ = 0x40008000);
PROVIDE(__heap_start__ = 0);
PROVIDE(__heap_end__ = 0);

2
sept/sept-secondary/src/chainloader.h
View file

@ -20,7 +20,7 @@
#include <stddef.h>
#include <stdint.h>
#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x6200
#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x5400
#define CHAINLOADER_MAX_ENTRIES 128
typedef struct chainloader_entry_t {

124
sept/sept-secondary/src/cluster.c
View file

@ -22,28 +22,26 @@
#include "sysreg.h"
#include "i2c.h"
#include "car.h"
#include "fuse.h"
#include "mc.h"
#include "timers.h"
#include "pmc.h"
#include "max77620.h"
#include "max77812.h"
/* Determine the current SoC for Mariko specific code. */
static bool is_soc_mariko() {
return (fuse_get_soc_type() == 1);
}
static void cluster_enable_power(uint32_t regulator) {
switch (regulator) {
case 0: /* Regulator_Max77621 */
void _cluster_enable_power()
{
/* Reboot I2C5. */
clkrst_reboot(CARDEVICE_I2C5);
i2c_init(I2C_5);
uint8_t val = 0;
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
val &= 0xDF;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
val = 0x09;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
/* Enable power. */
val = 0x20;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
val = 0x8D;
@ -53,83 +51,54 @@ static void cluster_enable_power(uint32_t regulator) {
val = 0xB7;
i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
}
break;
case 1: /* Regulator_Max77812PhaseConfiguration31 */
{
uint8_t val = 0;
i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
if (val) {
val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
}
break;
case 2: /* Regulator_Max77812PhaseConfiguration211 */
{
uint8_t val = 0;
i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
if (val) {
val |= 0x40;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
}
val = 0x6E;
i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
}
break;
default: return;
}
}
static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
int _cluster_pmc_enable_partition(uint32_t part, uint32_t toggle)
{
volatile tegra_pmc_t *pmc = pmc_get_regs();
/* Check if the partition has already been turned on. */
if (pmc->pwrgate_status & part) {
return;
}
if (pmc->pwrgate_status & part)
return 1;
uint32_t i = 5001;
while (pmc->pwrgate_toggle & 0x100) {
while (pmc->pwrgate_toggle & 0x100)
{
udelay(1);
i--;
if (i < 1) {
return;
}
if (i < 1)
return 0;
}
/* Turn the partition on. */
pmc->pwrgate_toggle = (toggle | 0x100);
i = 5001;
while (i > 0) {
/* Check if the partition has already been turned on. */
if (pmc->pwrgate_status & part) {
while (i > 0)
{
if (pmc->pwrgate_status & part)
break;
}
udelay(1);
i--;
}
return 1;
}
void cluster_boot_cpu0(uint32_t entry) {
void cluster_boot_cpu0(uint32_t entry)
{
volatile tegra_car_t *car = car_get_regs();
bool is_mariko = is_soc_mariko();
/* Set ACTIVE_CLUSER to FAST. */
FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE;
/* Enable VddCpu. */
cluster_enable_power(is_mariko ? fuse_get_regulator() : 0);
_cluster_enable_power();
if (!(car->pllx_base & 0x40000000)) {
if (!(car->pllx_base & 0x40000000))
{
car->pllx_misc3 &= 0xFFFFFFF7;
udelay(2);
if (!is_mariko) {
car->pllx_base = 0x80404E02;
car->pllx_base = 0x404E02;
}
car->pllx_misc = ((car->pllx_misc & 0xFFFBFFFF) | 0x40000);
car->pllx_base = 0x40404E02;
}
@ -138,28 +107,28 @@ void cluster_boot_cpu0(uint32_t entry) {
/* Wait. */
}
/* Set MSELECT clock. */
clk_enable(CARDEVICE_MSELECT);
/* Configure MSELECT source and enable clock. */
car->clk_source_mselect = ((car->clk_source_mselect & 0x1FFFFF00) | 6);
car->clk_out_enb_v = ((car->clk_out_enb_v & 0xFFFFFFF7) | 8);
/* Configure initial CPU clock frequency and enable clock. */
car->cclk_brst_pol = 0x20008888;
car->super_cclk_div = 0x80000000;
car->clk_enb_v_set = 1;
/* Reboot CORESIGHT. */
clkrst_reboot(CARDEVICE_CORESIGHT);
/* Set CAR2PMC_CPU_ACK_WIDTH to 0. */
/* CAR2PMC_CPU_ACK_WIDTH should be set to 0. */
car->cpu_softrst_ctrl2 &= 0xFFFFF000;
/* Enable CPU rail. */
cluster_pmc_enable_partition(1, 0);
_cluster_pmc_enable_partition(1, 0);
/* Enable cluster 0 non-CPU. */
cluster_pmc_enable_partition(0x8000, 15);
_cluster_pmc_enable_partition(0x8000, 15);
/* Enable CE0. */
cluster_pmc_enable_partition(0x4000, 14);
_cluster_pmc_enable_partition(0x4000, 14);
/* Request and wait for RAM repair. */
FLOW_CTLR_RAM_REPAIR_0 = 1;
@ -169,6 +138,11 @@ void cluster_boot_cpu0(uint32_t entry) {
MAKE_EXCP_VEC_REG(0x100) = 0;
/* Check for reset vector lock. */
if (SB_CSR_0 & 2) {
generic_panic();
}
/* Set reset vector. */
SB_AA64_RESET_LOW_0 = (entry | 1);
SB_AA64_RESET_HIGH_0 = 0;
@ -177,18 +151,28 @@ void cluster_boot_cpu0(uint32_t entry) {
SB_CSR_0 = 2;
(void)SB_CSR_0;
/* Validate reset vector lock + RESET_LOW/HIGH values. */
if (!(SB_CSR_0 & 2)) {
generic_panic();
}
/* TODO: Should we even bother taking as a parameter? */
if (SB_AA64_RESET_LOW_0 != (0x4003D000 | 1) || SB_AA64_RESET_HIGH_0 != 0) {
generic_panic();
}
/* Set CPU_STRICT_TZ_APERTURE_CHECK. */
/* NOTE: This breaks Exosphère. */
/* NOTE: [4.0.0+] This was added, but it breaks Exosphère. */
/* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */
/* Clear MSELECT reset. */
rst_disable(CARDEVICE_MSELECT);
car->rst_dev_v &= 0xFFFFFFF7;
if (!is_mariko) {
/* Clear NONCPU reset. */
car->rst_cpug_cmplx_clr = 0x20000000;
}
/* Clear CPU{0} POR and CORE, CX0, L2, and DBG reset.*/
/* Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.*/
/* NOTE: [5.0.0+] This was changed so only CPU0 reset is cleared. */
/* car->rst_cpug_cmplx_clr = 0x411F000F; */
car->rst_cpug_cmplx_clr = 0x41010001;
}

59
sept/sept-secondary/src/init.c
View file

@ -81,66 +81,11 @@ void __program_exit(int rc) {
for (;;);
}
#ifdef SEPT_STAGE1_SRC
static void __program_parse_argc_argv(int argc, char *argdata) {
__program_argc = 0;
__program_argv = NULL;
}
#elif defined(SEPT_STAGE2_SRC)
#include "stage2.h"
static void __program_parse_argc_argv(int argc, char *argdata) {
size_t pos = 0, len;
__program_argc = argc;
__program_argv = malloc(argc * sizeof(void **));
if (__program_argv == NULL) {
generic_panic();
}
len = strlen(argdata);
__program_argv[0] = malloc(len + 1);
if (__program_argv[0] == NULL) {
generic_panic();
}
strcpy((char *)__program_argv[0], argdata);
pos += len + 1;
__program_argv[1] = malloc(sizeof(stage2_args_t));
if (__program_argv[1] == NULL) {
generic_panic();
}
memcpy(__program_argv[1], argdata + pos, sizeof(stage2_args_t));
}
#else
static void __program_parse_argc_argv(int argc, char *argdata) {
size_t pos = 0, len;
__program_argc = argc;
__program_argv = malloc(argc * sizeof(void **));
if (__program_argv == NULL) {
generic_panic();
}
for (int i = 0; i < argc; i++) {
len = strlen(argdata + pos);
__program_argv[i] = malloc(len + 1);
if (__program_argv[i] == NULL) {
generic_panic();
}
strcpy((char *)__program_argv[i], argdata + pos);
pos += len + 1;
}
}
#endif
static void __program_cleanup_argv(void) {
#ifndef SEPT_STAGE1_SRC
for (int i = 0; i < __program_argc; i++) {
free(__program_argv[i]);
__program_argv[i] = NULL;
}
free(__program_argv);
#endif
/* ... */
}

1
sept/sept-secondary/src/key_derivation.c
View file

@ -20,6 +20,7 @@
#include "cluster.h"
#include "timers.h"
#include "fuse.h"
#include "uart.h"
#include "utils.h"
#define u8 uint8_t

1
sept/sept-secondary/src/main.c
View file

@ -18,6 +18,7 @@
#include "exception_handlers.h"
#include "panic.h"
#include "hwinit.h"
#include "car.h"
#include "di.h"
#include "se.h"
#include "pmc.h"

1
sept/sept-secondary/src/panic.c
View file

@ -21,6 +21,7 @@
#include "se.h"
#include "fuse.h"
#include "utils.h"
#include "uart.h"
static uint32_t g_panic_code = 0;

2
sept/sept-secondary/src/start.s
View file

@ -32,6 +32,7 @@ _start:
.word 0x00000000 /* Reserved. */
begin_relocation_loop:
/* Relocate ourselves if necessary */
ldr r2, =__start__
adr r3, _start
@ -43,7 +44,6 @@ _start:
mov r1, #0x0
str r1, [r0]
ldr r4, =_relocation_loop_end
mov r4, #0x1000
mov r1, #0x0
_relocation_loop:

5
sept/sept-secondary/src/uart.h
View file

@ -163,6 +163,11 @@ void uart_wait_idle(UartDevice dev, UartVendorStatus status);
void uart_send(UartDevice dev, const void *buf, size_t len);
void uart_recv(UartDevice dev, void *buf, size_t len);
static inline void uart_send_text(UartDevice dev, const char *str) {
uart_send(dev, str, strlen(str));
uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE);
}
static inline volatile tegra_uart_t *uart_get_regs(UartDevice dev) {
static const size_t offsets[] = {0, 0x40, 0x200, 0x300, 0x400};
return (volatile tegra_uart_t *)(UART_BASE + offsets[dev]);