sept: fixes to work with new hwinit/etc

fusee/fusee-secondary/linker.ld

@@ -15,14 +15,14 @@ MEMORY
 {
     main        : ORIGIN = 0xF0000000, LENGTH = 0x10000000
     high_iram   : ORIGIN = 0x40010000, LENGTH = 0x8000
-    low_iram    : ORIGIN = 0x40003000, LENGTH = 0x8000
+    low_iram    : ORIGIN = 0x40002000, LENGTH = 0x6000
 }
 
 SECTIONS
 {
     PROVIDE(__start__           = 0xF0000000);
-    PROVIDE(__stack_top__       = 0x40020000);
+    PROVIDE(__stack_top__       = 0x40010000);
-    PROVIDE(__stack_bottom__    = 0x40018000);
+    PROVIDE(__stack_bottom__    = 0x40008000);
     PROVIDE(__heap_start__      = 0x90020000);
     PROVIDE(__heap_end__        = 0xA0020000);
 

fusee/fusee-secondary/src/chainloader.h

@@ -13,14 +13,14 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
- 
+
 #ifndef FUSEE_CHAINLOADER_H
 #define FUSEE_CHAINLOADER_H
 
 #include <stddef.h>
 #include <stdint.h>
 
-#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x6200
+#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x5400
 #define CHAINLOADER_MAX_ENTRIES       128
 
 typedef struct chainloader_entry_t {

sept/sept-secondary/key_derivation/src/start.s

@@ -96,4 +96,5 @@ _start:
     ldr x0, =__start__
     mov sp, x0
     mov fp, #0x0
+
     bl derive_keys

sept/sept-secondary/linker.ld

@@ -13,15 +13,15 @@ PHDRS
 MEMORY
 {
     NULL        : ORIGIN = 0x00000000, LENGTH = 0x1000
-    main        : ORIGIN = 0x40010000, LENGTH = 0x28000
+    main        : ORIGIN = 0x40010000, LENGTH = 0x20000
-    low_iram    : ORIGIN = 0x40003000, LENGTH = 0x8000
+    low_iram    : ORIGIN = 0x40002000, LENGTH = 0x6000
 }
 
 SECTIONS
 {
     PROVIDE(__start__           = 0x40010000);
-    PROVIDE(__stack_top__       = 0x4003C000);
+    PROVIDE(__stack_top__       = 0x40010000);
-    PROVIDE(__stack_bottom__    = 0x40038000);
+    PROVIDE(__stack_bottom__    = 0x40008000);
     PROVIDE(__heap_start__      = 0);
     PROVIDE(__heap_end__        = 0);
 

sept/sept-secondary/src/chainloader.h

@@ -13,14 +13,14 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
- 
+
 #ifndef FUSEE_CHAINLOADER_H
 #define FUSEE_CHAINLOADER_H
 
 #include <stddef.h>
 #include <stdint.h>
 
-#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x6200
+#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x5400
 #define CHAINLOADER_MAX_ENTRIES       128
 
 typedef struct chainloader_entry_t {

sept/sept-secondary/src/cluster.c

@@ -22,114 +22,83 @@
 #include "sysreg.h"
 #include "i2c.h"
 #include "car.h"
-#include "fuse.h"
 #include "mc.h"
 #include "timers.h"
 #include "pmc.h"
 #include "max77620.h"
-#include "max77812.h"
 
-/* Determine the current SoC for Mariko specific code. */
+void _cluster_enable_power()
-static bool is_soc_mariko() {
+{
-    return (fuse_get_soc_type() == 1);
+    /* Reboot I2C5. */
+    clkrst_reboot(CARDEVICE_I2C5);
+    i2c_init(I2C_5);
+
+    uint8_t val = 0;
+    i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
+
+    val &= 0xDF;
+    i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
+    val = 0x09;
+    i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
+
+    /* Enable power. */
+    val = 0x20;
+    i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
+    val = 0x8D;
+    i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
+    val = 0xB7;
+    i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
+    val = 0xB7;
+    i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
 }
 
-static void cluster_enable_power(uint32_t regulator) {
+int _cluster_pmc_enable_partition(uint32_t part, uint32_t toggle)
-    switch (regulator) {
+{
-        case 0:     /* Regulator_Max77621 */
-            {
-                uint8_t val = 0;
-                i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
-                val &= 0xDF;
-                i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1);
-                val = 0x09;
-                i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1);
-                val = 0x20;
-                i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1);
-                val = 0x8D;
-                i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1);
-                val = 0xB7;
-                i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1);
-                val = 0xB7;
-                i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1);
-            }
-            break;
-        case 1:     /* Regulator_Max77812PhaseConfiguration31 */
-            {
-                uint8_t val = 0;
-                i2c_query(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
-                if (val) {
-                    val |= 0x40;
-                    i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
-                }
-                val = 0x6E;
-                i2c_send(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
-            }
-            break;
-        case 2:     /* Regulator_Max77812PhaseConfiguration211 */
-            {
-                uint8_t val = 0;
-                i2c_query(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
-                if (val) {
-                    val |= 0x40;
-                    i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_EN_CTRL, &val, 1);
-                }
-                val = 0x6E;
-                i2c_send(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_M4_VOUT, &val, 1);
-            }
-            break;
-        default: return;
-    }
-}
-
-static void cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) {
     volatile tegra_pmc_t *pmc = pmc_get_regs();
 
     /* Check if the partition has already been turned on. */
-    if (pmc->pwrgate_status & part) {
+    if (pmc->pwrgate_status & part)
-        return;
+        return 1;
-    }
 
     uint32_t i = 5001;
-    while (pmc->pwrgate_toggle & 0x100) {
+    while (pmc->pwrgate_toggle & 0x100)
+    {
         udelay(1);
         i--;
-        if (i < 1) {
+        if (i < 1)
-            return;
+            return 0;
-        }
     }
 
-    /* Turn the partition on. */
     pmc->pwrgate_toggle = (toggle | 0x100);
 
     i = 5001;
-    while (i > 0) {
+    while (i > 0)
-        /* Check if the partition has already been turned on. */
+    {
-        if (pmc->pwrgate_status & part) {
+        if (pmc->pwrgate_status & part)
             break;
-        }
+
         udelay(1);
         i--;
     }
+
+    return 1;
 }
 
-void cluster_boot_cpu0(uint32_t entry) {
+void cluster_boot_cpu0(uint32_t entry)
+{
     volatile tegra_car_t *car = car_get_regs();
-    bool is_mariko = is_soc_mariko();
 
     /* Set ACTIVE_CLUSER to FAST. */
     FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE;
 
-    /* Enable VddCpu. */
+    _cluster_enable_power();
-    cluster_enable_power(is_mariko ? fuse_get_regulator() : 0);
 
-    if (!(car->pllx_base & 0x40000000)) {
+    if (!(car->pllx_base & 0x40000000))
+    {
         car->pllx_misc3 &= 0xFFFFFFF7;
         udelay(2);
-        if (!is_mariko) {
+        car->pllx_base = 0x80404E02;
-            car->pllx_base = 0x80404E02;
+        car->pllx_base = 0x404E02;
-            car->pllx_base = 0x404E02;
-        }
         car->pllx_misc = ((car->pllx_misc & 0xFFFBFFFF) | 0x40000);
         car->pllx_base = 0x40404E02;
     }
@@ -138,28 +107,28 @@ void cluster_boot_cpu0(uint32_t entry) {
         /* Wait. */
     }
 
-    /* Set MSELECT clock. */
+    /* Configure MSELECT source and enable clock. */
-    clk_enable(CARDEVICE_MSELECT);
+    car->clk_source_mselect = ((car->clk_source_mselect & 0x1FFFFF00) | 6);
+    car->clk_out_enb_v = ((car->clk_out_enb_v & 0xFFFFFFF7) | 8);
 
     /* Configure initial CPU clock frequency and enable clock. */
     car->cclk_brst_pol = 0x20008888;
     car->super_cclk_div = 0x80000000;
     car->clk_enb_v_set = 1;
 
-    /* Reboot CORESIGHT. */
     clkrst_reboot(CARDEVICE_CORESIGHT);
 
-    /* Set CAR2PMC_CPU_ACK_WIDTH to 0. */
+    /* CAR2PMC_CPU_ACK_WIDTH should be set to 0. */
     car->cpu_softrst_ctrl2 &= 0xFFFFF000;
 
     /* Enable CPU rail. */
-    cluster_pmc_enable_partition(1, 0);
+    _cluster_pmc_enable_partition(1, 0);
 
     /* Enable cluster 0 non-CPU. */
-    cluster_pmc_enable_partition(0x8000, 15);
+    _cluster_pmc_enable_partition(0x8000, 15);
 
     /* Enable CE0. */
-    cluster_pmc_enable_partition(0x4000, 14);
+    _cluster_pmc_enable_partition(0x4000, 14);
 
     /* Request and wait for RAM repair. */
     FLOW_CTLR_RAM_REPAIR_0 = 1;
@@ -169,6 +138,11 @@ void cluster_boot_cpu0(uint32_t entry) {
 
     MAKE_EXCP_VEC_REG(0x100) = 0;
 
+    /* Check for reset vector lock. */
+    if (SB_CSR_0 & 2) {
+        generic_panic();
+    }
+
     /* Set reset vector. */
     SB_AA64_RESET_LOW_0 = (entry | 1);
     SB_AA64_RESET_HIGH_0 = 0;
@@ -177,18 +151,28 @@ void cluster_boot_cpu0(uint32_t entry) {
     SB_CSR_0 = 2;
     (void)SB_CSR_0;
 
+    /* Validate reset vector lock + RESET_LOW/HIGH values. */
+    if (!(SB_CSR_0 & 2)) {
+        generic_panic();
+    }
+
+    /* TODO: Should we even bother taking as a parameter? */
+    if (SB_AA64_RESET_LOW_0 != (0x4003D000 | 1) || SB_AA64_RESET_HIGH_0 != 0) {
+        generic_panic();
+    }
+
     /* Set CPU_STRICT_TZ_APERTURE_CHECK. */
-    /* NOTE: This breaks Exosphère. */
+    /* NOTE: [4.0.0+] This was added, but it breaks Exosphère. */
     /* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */
 
     /* Clear MSELECT reset. */
-    rst_disable(CARDEVICE_MSELECT);
+    car->rst_dev_v &= 0xFFFFFFF7;
 
-    if (!is_mariko) {
+    /* Clear NONCPU reset. */
-        /* Clear NONCPU reset. */
+    car->rst_cpug_cmplx_clr = 0x20000000;
-        car->rst_cpug_cmplx_clr = 0x20000000;
-    }
 
-    /* Clear CPU{0} POR and CORE, CX0, L2, and DBG reset.*/
+    /* Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.*/
+    /* NOTE: [5.0.0+] This was changed so only CPU0 reset is cleared. */
+    /* car->rst_cpug_cmplx_clr = 0x411F000F; */
     car->rst_cpug_cmplx_clr = 0x41010001;
 }

sept/sept-secondary/src/hwinit.c

@@ -15,7 +15,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
- 
+
 #include "hwinit.h"
 #include "apb_misc.h"
 #include "car.h"
@@ -42,12 +42,12 @@ static bool is_soc_mariko() {
 static void config_oscillators(void) {
     volatile tegra_car_t *car = car_get_regs();
     volatile tegra_pmc_t *pmc = pmc_get_regs();
-    
+
     car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4);
-    
+
     SYSCTR0_CNTFID0_0 = 19200000;
     TIMERUS_USEC_CFG_0 = 0x45F;
-    
+
     car->osc_ctrl = 0x50000071;
     pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE);
     pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFBFFFFF) | 0x400000);
@@ -64,10 +64,10 @@ static void config_oscillators(void) {
 static void config_gpios(void) {
     volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
     bool is_mariko = is_soc_mariko();
-    
+
     if (is_mariko) {
         uint32_t hardware_type = fuse_get_hardware_type();
-        
+
         /* Only for HardwareType_Iowa and HardwareType_Five. */
         if ((hardware_type == 3) || (hardware_type == 5)) {
             pinmux->uart2_tx = 0;
@@ -81,7 +81,7 @@ static void config_gpios(void) {
         pinmux->uart2_tx = 0;
         pinmux->uart3_tx = 0;
     }
-    
+
     pinmux->pe6 = PINMUX_INPUT;
     pinmux->ph6 = PINMUX_INPUT;
     if (!is_mariko) {
@@ -106,7 +106,7 @@ static void config_gpios(void) {
     gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO);
     gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT);
     gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT);
-    
+
     if (is_mariko) {
         /* Configure home button as input. */
         gpio_configure_mode(TEGRA_GPIO(Y, 1), GPIO_MODE_GPIO);
@@ -116,7 +116,7 @@ static void config_gpios(void) {
 
 static void mbist_workaround(void) {
     volatile tegra_car_t *car = car_get_regs();
-    
+
     car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF);
     car->plld_base |= 0x40800000u;
     car->rst_dev_y_clr = 0x40;
@@ -135,7 +135,7 @@ static void mbist_workaround(void) {
     MAKE_I2S_REG(0x388) &= 0xFFFFFFFE;
     MAKE_I2S_REG(0x4A0) |= 0x400;
     MAKE_I2S_REG(0x488) &= 0xFFFFFFFE;
-    
+
     MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4;
     MAKE_VIC_REG(0x8C) = 0xFFFFFFFF;
     udelay(2);
@@ -144,7 +144,7 @@ static void mbist_workaround(void) {
     car->rst_dev_y_set = 0x40;
     car->rst_dev_l_set = 0x18000000;
     car->rst_dev_x_set = 0x40000;
-    
+
     /* Clock out enables. */
     car->clk_out_enb_h = 0xC0;
     car->clk_out_enb_l = 0x80000130;
@@ -153,14 +153,14 @@ static void mbist_workaround(void) {
     car->clk_out_enb_w = 0x402000FC;
     car->clk_out_enb_x = 0x23000780;
     car->clk_out_enb_y = 0x300;
-    
+
     /* LVL2 clock gate overrides. */
     car->lvl2_clk_gate_ovra = 0;
     car->lvl2_clk_gate_ovrb = 0;
     car->lvl2_clk_gate_ovrc = 0;
     car->lvl2_clk_gate_ovrd = 0;
     car->lvl2_clk_gate_ovre = 0;
-    
+
     /* Configure clock sources. */
     car->plld_base &= 0x1F7FFFFF;
     car->clk_source_sor1 &= 0xFFFF3FFF;
@@ -173,23 +173,23 @@ static void config_se_brom(void) {
     volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
     volatile tegra_se_t *se = se_get_regs();
     volatile tegra_pmc_t *pmc = pmc_get_regs();
-    
+
     /* Bootrom part we skipped. */
     uint32_t sbk[4] = {fuse_chip->FUSE_PRIVATE_KEY[0], fuse_chip->FUSE_PRIVATE_KEY[1], fuse_chip->FUSE_PRIVATE_KEY[2], fuse_chip->FUSE_PRIVATE_KEY[3]};
     set_aes_keyslot(0xE, sbk, 0x10);
-    
+
     /* Lock SBK from being read. */
     se->SE_CRYPTO_KEYTABLE_ACCESS[0xE] = 0x7E;
-    
+
     /* This memset needs to happen here, else TZRAM will behave weirdly later on. */
     memset((void *)0x7C010000, 0, 0x10000);
-    
+
     pmc->crypto_op = 0;
     se->SE_INT_STATUS = 0x1F;
-    
+
     /* Lock SSK (although it's not set and unused anyways). */
     se->SE_CRYPTO_KEYTABLE_ACCESS[0xF] = 0x7E;
-    
+
     /* Clear the boot reason to avoid problems later */
     pmc->scratch200 = 0;
     pmc->rst_status = 0;
@@ -199,18 +199,18 @@ void nx_hwinit(bool enable_log) {
     volatile tegra_pmc_t *pmc = pmc_get_regs();
     volatile tegra_car_t *car = car_get_regs();
     bool is_mariko = is_soc_mariko();
-    
+
     if (!is_mariko) {
         /* Bootrom stuff we skipped by going through RCM. */
         config_se_brom();
-    
+
         AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
         pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);
-    
+
         /* Apply the memory built-in self test workaround. */
         mbist_workaround();
     }
-    
+
     /* Enable SE clock. */
     clkrst_reboot(CARDEVICE_SE);
     if (is_mariko) {
@@ -228,10 +228,10 @@ void nx_hwinit(bool enable_log) {
 
     /* Configure oscillators. */
     config_oscillators();
-    
+
     /* Disable pinmux tristate input clamping. */
     APB_MISC_PP_PINMUX_GLOBAL_0 = 0;
-    
+
     /* Configure GPIOs. */
     config_gpios();
 
@@ -240,22 +240,22 @@ void nx_hwinit(bool enable_log) {
         clkrst_reboot(CARDEVICE_UARTA);
         uart_init(UART_A, 115200);
     }
-    
+
    /* Enable CL-DVFS clock. */
     clkrst_reboot(CARDEVICE_CL_DVFS);
-    
+
     /* Enable I2C1 clock. */
     clkrst_reboot(CARDEVICE_I2C1);
-    
+
     /* Enable I2C5 clock. */
     clkrst_reboot(CARDEVICE_I2C5);
-    
+
     /* Enable TZRAM clock. */
     clkrst_reboot(CARDEVICE_TZRAM);
 
     /* Initialize I2C5. */
     i2c_init(I2C_5);
-    
+
     /* Configure the PMIC. */
     if (is_mariko) {
         uint8_t val = 0x40;
@@ -283,11 +283,11 @@ void nx_hwinit(bool enable_log) {
         i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD1, &val, 1);
         val = 0x1B;
         i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1);
-        
+
         /* NOTE: [3.0.0+] This was added. */
         val = 0x22;
         i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_GPIO3, &val, 1);
-        
+
         /* TODO: In 3.x+, if the unit is SDEV, the MBLPD bit is set. */
         /*
         i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
@@ -299,29 +299,29 @@ void nx_hwinit(bool enable_log) {
     /* Configure SD0 voltage. */
     uint8_t val = 0x24;
     i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
-    
+
     /* Enable LDO8 in HardwareType_Hoag only. */
     if (is_mariko && (fuse_get_hardware_type() == 2)) {
         val = 0xE8;
         i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO8_CFG, &val, 1);
     }
-    
+
     /* Initialize I2C1. */
     i2c_init(I2C_1);
 
     /* Set super clock burst policy. */
     car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333);
-    
+
     if (is_mariko) {
         /* Mariko only PMC configuration for TZRAM. */
         pmc->tzram_pwr_cntrl &= 0xFFFFFFFE;
         pmc->tzram_non_sec_disable = 0x3;
         pmc->tzram_sec_disable = 0x3;
     }
-    
+
     /* Save SDRAM parameters to scratch. */
     sdram_save_params(sdram_get_params(fuse_get_dram_id()));
-    
+
     /* Initialize SDRAM. */
     sdram_init();
-}
+}

sept/sept-secondary/src/init.c

@@ -13,7 +13,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
- 
+
 #include <stdint.h>
 #include <stddef.h>
 #include <string.h>
@@ -81,66 +81,11 @@ void __program_exit(int rc) {
     for (;;);
 }
 
-#ifdef SEPT_STAGE1_SRC
+
 static void __program_parse_argc_argv(int argc, char *argdata) {
     __program_argc = 0;
     __program_argv = NULL;
 }
-#elif defined(SEPT_STAGE2_SRC)
-#include "stage2.h"
-static void __program_parse_argc_argv(int argc, char *argdata) {
-    size_t pos = 0, len;
-
-    __program_argc = argc;
-
-    __program_argv = malloc(argc * sizeof(void **));
-    if (__program_argv == NULL) {
-        generic_panic();
-    }
-
-    len = strlen(argdata);
-    __program_argv[0] = malloc(len + 1);
-    if (__program_argv[0] == NULL) {
-        generic_panic();
-    }
-    strcpy((char *)__program_argv[0], argdata);
-    pos += len + 1;
-
-    __program_argv[1] = malloc(sizeof(stage2_args_t));
-    if (__program_argv[1] == NULL) {
-        generic_panic();
-    }
-    memcpy(__program_argv[1], argdata + pos, sizeof(stage2_args_t));
-}
-#else
-static void __program_parse_argc_argv(int argc, char *argdata) {
-    size_t pos = 0, len;
-
-    __program_argc = argc;
-
-    __program_argv = malloc(argc * sizeof(void **));
-    if (__program_argv == NULL) {
-        generic_panic();
-    }
-
-    for (int i = 0; i < argc; i++) {
-        len = strlen(argdata + pos);
-        __program_argv[i] = malloc(len + 1);
-        if (__program_argv[i] == NULL) {
-            generic_panic();
-        }
-        strcpy((char *)__program_argv[i], argdata + pos);
-        pos += len + 1;
-    }
-}
-#endif
-
 static void __program_cleanup_argv(void) {
-#ifndef SEPT_STAGE1_SRC
+    /* ... */
-    for (int i = 0; i < __program_argc; i++) {
-        free(__program_argv[i]);
-        __program_argv[i] = NULL;
-    }
-    free(__program_argv);
-#endif
 }

sept/sept-secondary/src/key_derivation.c

@@ -20,6 +20,7 @@
 #include "cluster.h"
 #include "timers.h"
 #include "fuse.h"
+#include "uart.h"
 #include "utils.h"
 
 #define u8 uint8_t

sept/sept-secondary/src/main.c

@@ -18,6 +18,7 @@
 #include "exception_handlers.h"
 #include "panic.h"
 #include "hwinit.h"
+#include "car.h"
 #include "di.h"
 #include "se.h"
 #include "pmc.h"
@@ -93,13 +94,13 @@ static void exfiltrate_keys_and_reboot_if_needed(uint32_t version) {
 static void display_splash_screen(void) {
     /* Draw splash. */
     draw_splash((volatile uint32_t *)g_framebuffer);
-    
+
     /* Turn on the backlight. */
     display_backlight(true);
-    
+
     /* Ensure the splash screen is displayed for at least one second. */
     mdelay(1000);
-    
+
     /* Turn off the backlight. */
     display_backlight(false);
 }
@@ -118,7 +119,7 @@ static void setup_env(void) {
 
     /* Set the framebuffer. */
     display_init_framebuffer(g_framebuffer);
-    
+
     /* Set up the exception handlers. */
     setup_exception_handlers();
 
@@ -129,7 +130,7 @@ static void setup_env(void) {
 static void cleanup_env(void) {
     /* Unmount the SD card. */
     unmount_sd();
-    
+
     /* Terminate the display. */
     display_end();
 }
@@ -164,7 +165,7 @@ int sept_main(uint32_t version) {
 
     /* Load the loader payload into DRAM. */
     load_stage2();
-    
+
     /* Display the splash screen. */
     display_splash_screen();
 

sept/sept-secondary/src/panic.c

@@ -21,6 +21,7 @@
 #include "se.h"
 #include "fuse.h"
 #include "utils.h"
+#include "uart.h"
 
 static uint32_t g_panic_code = 0;
 

sept/sept-secondary/src/start.s

@@ -32,6 +32,7 @@ _start:
     .word 0x00000000 /* Reserved. */
 
     begin_relocation_loop:
+
     /* Relocate ourselves if necessary */
     ldr r2, =__start__
     adr r3, _start
@@ -43,7 +44,6 @@ _start:
     mov r1, #0x0
     str r1, [r0]
 
-    ldr r4, =_relocation_loop_end
     mov r4, #0x1000
     mov r1, #0x0
     _relocation_loop:

sept/sept-secondary/src/uart.h

@@ -14,7 +14,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
- 
+
 #ifndef FUSEE_UART_H
 #define FUSEE_UART_H
 
@@ -79,7 +79,7 @@ typedef enum {
     0 = Transmit 1 stop bit
     1 = Transmit 2 stop bits (receiver always checks for 1 stop bit)
     */
-    UART_LCR_STOP        = 1 << 2, 
+    UART_LCR_STOP        = 1 << 2,
     UART_LCR_PAR         = 1 << 3, /* Parity enabled */
     UART_LCR_EVEN        = 1 << 4, /* Even parity format. There will always be an even number of 1s in the binary representation (PAR = 1) */
     UART_LCR_SET_P       = 1 << 5, /* Set (force) parity to value in LCR[4] */
@@ -115,7 +115,7 @@ typedef enum {
     0 = FIFO_COUNT_GREATER_1
     1 = FIFO_COUNT_GREATER_4
     2 = FIFO_COUNT_GREATER_8
-    3 = FIFO_COUNT_GREATER_16 
+    3 = FIFO_COUNT_GREATER_16
     */
     UART_FCR_RX_TRIG                       = 3 << 6,
     UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_1  = 0 << 6,
@@ -163,6 +163,11 @@ void uart_wait_idle(UartDevice dev, UartVendorStatus status);
 void uart_send(UartDevice dev, const void *buf, size_t len);
 void uart_recv(UartDevice dev, void *buf, size_t len);
 
+static inline void uart_send_text(UartDevice dev, const char *str) {
+    uart_send(dev, str, strlen(str));
+    uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE);
+}
+
 static inline volatile tegra_uart_t *uart_get_regs(UartDevice dev) {
     static const size_t offsets[] = {0, 0x40, 0x200, 0x300, 0x400};
     return (volatile tegra_uart_t *)(UART_BASE + offsets[dev]);