From 828b170aac5f3d3091c8a13babda748586261560 Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Mon, 29 Jun 2020 05:40:09 -0700 Subject: [PATCH] exo: add mariko spare reg write during setup --- exosphere/program/source/secmon_setup_warm.cpp | 7 +++++++ .../include/exosphere/tegra/tegra_ahb_arbc.hpp | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/exosphere/program/source/secmon_setup_warm.cpp b/exosphere/program/source/secmon_setup_warm.cpp index 331502e02..a0f1bbe38 100644 --- a/exosphere/program/source/secmon_setup_warm.cpp +++ b/exosphere/program/source/secmon_setup_warm.cpp @@ -264,6 +264,13 @@ namespace ams::secmon { { reg::Write(AHB_ARBC(AHB_GIZMO_TZRAM), (1u << 7)); } + + /* NOTE: This is Mariko only in Nintendo's firmware. */ + /* Still, it seems to have no adverse effects on Erista... */ + /* TODO: Find a way to get access to SocType this early (fuse driver isn't alive yet), only write on mariko? */ + { + reg::ReadWrite(AHB_ARBC(AHB_AHB_SPARE_REG), AHB_REG_BITS_VALUE(AHB_SPARE_REG_AHB_SPARE_REG, 0xE0000)); + } } void SetupSocDmaControllersCpuMemoryControllersEnableMmuWarmboot() { diff --git a/libraries/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp b/libraries/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp index d8a5d4321..b130ada97 100644 --- a/libraries/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp +++ b/libraries/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp @@ -23,6 +23,7 @@ #define AHB_MASTER_SWID (0x018) #define AHB_MASTER_SWID_1 (0x038) #define AHB_GIZMO_TZRAM (0x054) +#define AHB_AHB_SPARE_REG (0x110) #define AHB_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (AHB_, NAME) #define AHB_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (AHB_, NAME, VALUE) @@ -39,3 +40,8 @@ DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_COP, 1, ENABLE, DISABLE); DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_AHBDMA, 5, ENABLE, DISABLE); DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB, 6, ENABLE, DISABLE); DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB2, 18, ENABLE, DISABLE); + +DEFINE_AHB_REG(AHB_SPARE_REG_CSITE_PADMACRO3_TRIM_SEL, 0, 5); +DEFINE_AHB_REG_BIT_ENUM(AHB_SPARE_REG_OBS_OVERRIDE_EN, 5, DISABLE, ENABLE); +DEFINE_AHB_REG_BIT_ENUM(AHB_SPARE_REG_APB2JTAG_OVERRIDE_EN, 6, DISABLE, ENABLE); +DEFINE_AHB_REG(AHB_SPARE_REG_AHB_SPARE_REG, 12, 32-12);