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thermosphere: the fpu cache is only being really modified by gdb anyway

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This commit is contained in:
TuxSH 2020-02-03 01:57:11 +00:00
parent edf2bbc30e
commit 788f331de0
3 changed files with 16 additions and 12 deletions
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13
thermosphere/src/fpu.c
View file

@ -17,7 +17,7 @@
#include "fpu.h" #include "fpu.h"
#include "core_ctx.h" #include "core_ctx.h"
static FpuRegisterCache TEMPORARY g_fpuRegisterCache[4] = { 0 }; static FpuRegisterCache TEMPORARY g_fpuRegisterCache = { 0 };
// fpu_regs_load_store.s // fpu_regs_load_store.s
void fpuLoadRegistersFromCache(const FpuRegisterCache *cache); void fpuLoadRegistersFromCache(const FpuRegisterCache *cache);
@ -25,12 +25,13 @@ void fpuStoreRegistersToCache(FpuRegisterCache *cache);
FpuRegisterCache *fpuGetRegisterCache(void) FpuRegisterCache *fpuGetRegisterCache(void)
{ {
return &g_fpuRegisterCache[currentCoreCtx->coreId]; g_fpuRegisterCache.coreId = currentCoreCtx->coreId;
return &g_fpuRegisterCache;
} }
FpuRegisterCache *fpuReadRegisters(void) FpuRegisterCache *fpuReadRegisters(void)
{ {
FpuRegisterCache *cache = &g_fpuRegisterCache[currentCoreCtx->coreId]; FpuRegisterCache *cache = &g_fpuRegisterCache;
if (!cache->valid) { if (!cache->valid) {
fpuStoreRegistersToCache(cache); fpuStoreRegistersToCache(cache);
cache->valid = true; cache->valid = true;
@ -40,7 +41,7 @@ FpuRegisterCache *fpuReadRegisters(void)
void fpuCommitRegisters(void) void fpuCommitRegisters(void)
{ {
FpuRegisterCache *cache = &g_fpuRegisterCache[currentCoreCtx->coreId]; FpuRegisterCache *cache = &g_fpuRegisterCache;
cache->dirty = true; cache->dirty = true;
// Because the caller rewrote the entire cache in the event it didn't read it before: // Because the caller rewrote the entire cache in the event it didn't read it before:
@ -49,8 +50,8 @@ void fpuCommitRegisters(void)
void fpuCleanInvalidateRegisterCache(void) void fpuCleanInvalidateRegisterCache(void)
{ {
FpuRegisterCache *cache = &g_fpuRegisterCache[currentCoreCtx->coreId]; FpuRegisterCache *cache = &g_fpuRegisterCache;
if (cache->dirty) { if (cache->dirty && cache->coreId == currentCoreCtx->coreId) {
fpuLoadRegistersFromCache(cache); fpuLoadRegistersFromCache(cache);
cache->dirty = false; cache->dirty = false;
} }

3
thermosphere/src/fpu.h
View file

@ -17,11 +17,12 @@
#pragma once #pragma once
#include "utils.h" #include "utils.h"
#include "spinlock.h"
typedef struct FpuRegisterCache { typedef struct FpuRegisterCache {
u128 q[32]; u128 q[32];
u64 fpsr; u64 fpsr;
u64 fpcr; u64 fpcr;
u32 coreId;
bool valid; bool valid;
bool dirty; bool dirty;
} FpuRegisterCache; } FpuRegisterCache;

2
thermosphere/src/gdb/context.c
View file

@ -41,6 +41,7 @@
#include "../breakpoints.h" #include "../breakpoints.h"
#include "../software_breakpoints.h" #include "../software_breakpoints.h"
#include "../watchpoints.h" #include "../watchpoints.h"
#include "../fpu.h"
static TEMPORARY char g_gdbWorkBuffer[GDB_WORK_BUF_LEN]; static TEMPORARY char g_gdbWorkBuffer[GDB_WORK_BUF_LEN];
static TEMPORARY char g_gdbBuffer[GDB_BUF_LEN + 4 + 1]; static TEMPORARY char g_gdbBuffer[GDB_BUF_LEN + 4 + 1];
@ -236,6 +237,7 @@ void GDB_ReleaseContext(GDBContext *ctx)
void GDB_MigrateRxIrq(GDBContext *ctx, u32 coreId) void GDB_MigrateRxIrq(GDBContext *ctx, u32 coreId)
{ {
fpuCleanInvalidateRegisterCache();
transportInterfaceSetInterruptAffinity(ctx->transportInterface, BIT(coreId)); transportInterfaceSetInterruptAffinity(ctx->transportInterface, BIT(coreId));
} }