From 77cc53227af7b6e551e4594c1c0ffa9246d793d1 Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Thu, 19 Jan 2023 21:47:19 -0700 Subject: [PATCH] sdmmc: fix wrong mode select for GcAsic(Fpga)Speed --- .../impl/sdmmc_sdmmc_controller.board.nintendo_nx.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/libraries/libvapours/source/sdmmc/impl/sdmmc_sdmmc_controller.board.nintendo_nx.cpp b/libraries/libvapours/source/sdmmc/impl/sdmmc_sdmmc_controller.board.nintendo_nx.cpp index e86240833..a3e6e149a 100644 --- a/libraries/libvapours/source/sdmmc/impl/sdmmc_sdmmc_controller.board.nintendo_nx.cpp +++ b/libraries/libvapours/source/sdmmc/impl/sdmmc_sdmmc_controller.board.nintendo_nx.cpp @@ -388,12 +388,16 @@ namespace ams::sdmmc::impl { break; case SpeedMode_SdCardSdr50: case SpeedMode_SdCardSdr104: - case SpeedMode_GcAsicFpgaSpeed: - case SpeedMode_GcAsicSpeed: /* Set as SDR104, 1.8V. */ reg::ReadWrite(m_sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_UHS_MODE_SELECT, SDR104)); reg::ReadWrite(m_sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_1_8V_SIGNALING_ENABLE, 1_8V_SIGNALING)); break; + case SpeedMode_GcAsicFpgaSpeed: + case SpeedMode_GcAsicSpeed: + /* Set as HS200, 1.8V. */ + reg::ReadWrite(m_sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_UHS_MODE_SELECT, HS200)); + reg::ReadWrite(m_sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_1_8V_SIGNALING_ENABLE, 1_8V_SIGNALING)); + break; AMS_UNREACHABLE_DEFAULT_CASE(); } SdHostStandardController::EnsureControl();