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fusee: Properly finalize SDMMC1 (fixes 8.0.0 issues with PCV)

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hexkyz 2019-04-20 17:30:03 +01:00 committed by SciresM
parent a3389e25c9
commit 732a6159f7
4 changed files with 33 additions and 2 deletions
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3
fusee/fusee-primary/src/sdmmc/sdmmc_core.c
View file

@ -1202,6 +1202,9 @@ void sdmmc_finish(sdmmc_t *sdmmc)
/* Power cycle for 100ms without power. */ /* Power cycle for 100ms without power. */
mdelay(100); mdelay(100);
/* Disable the regulator. */
max77620_regulator_enable(REGULATOR_LDO2, 0);
} }
/* Force a register read to refresh the clock control value. */ /* Force a register read to refresh the clock control value. */

26
fusee/fusee-secondary/src/nxfs.c
View file

@ -52,7 +52,8 @@ SdmmcPartitionNum g_current_emmc_partition = SDMMC_PARTITION_INVALID;
static int mmc_partition_initialize(device_partition_t *devpart) { static int mmc_partition_initialize(device_partition_t *devpart) {
mmc_partition_info_t *mmcpart = (mmc_partition_info_t *)devpart->device_struct; mmc_partition_info_t *mmcpart = (mmc_partition_info_t *)devpart->device_struct;
if (devpart->read_cipher != NULL || devpart->write_cipher != NULL) { /* Allocate the crypto work buffer. */
if ((devpart->read_cipher != NULL) || (devpart->write_cipher != NULL)) {
devpart->crypto_work_buffer = memalign(16, devpart->sector_size * 16); devpart->crypto_work_buffer = memalign(16, devpart->sector_size * 16);
if (devpart->crypto_work_buffer == NULL) { if (devpart->crypto_work_buffer == NULL) {
return ENOMEM; return ENOMEM;
@ -70,6 +71,7 @@ static int mmc_partition_initialize(device_partition_t *devpart) {
g_ahb_redirect_enabled = true; g_ahb_redirect_enabled = true;
} }
/* Initialize hardware. */
if (mmcpart->device == &g_sd_device) { if (mmcpart->device == &g_sd_device) {
if (!g_sd_device_initialized) { if (!g_sd_device_initialized) {
int rc = sdmmc_device_sd_init(mmcpart->device, &g_sd_sdmmc, SDMMC_BUS_WIDTH_4BIT, SDMMC_SPEED_SDR104) ? 0 : EIO; int rc = sdmmc_device_sd_init(mmcpart->device, &g_sd_sdmmc, SDMMC_BUS_WIDTH_4BIT, SDMMC_SPEED_SDR104) ? 0 : EIO;
@ -94,13 +96,33 @@ static int mmc_partition_initialize(device_partition_t *devpart) {
} }
static void mmc_partition_finalize(device_partition_t *devpart) { static void mmc_partition_finalize(device_partition_t *devpart) {
free(devpart->crypto_work_buffer); mmc_partition_info_t *mmcpart = (mmc_partition_info_t *)devpart->device_struct;
/* Finalize hardware. */
if (mmcpart->device == &g_sd_device) {
if (g_sd_device_initialized) {
sdmmc_device_finish(&g_sd_device);
g_sd_device_initialized = false;
}
devpart->initialized = false;
} else if (mmcpart->device == &g_emmc_device) {
if (g_emmc_device_initialized) {
sdmmc_device_finish(&g_emmc_device);
g_emmc_device_initialized = false;
}
devpart->initialized = false;
}
/* Disable AHB redirection if necessary. */ /* Disable AHB redirection if necessary. */
if (g_ahb_redirect_enabled) { if (g_ahb_redirect_enabled) {
mc_disable_ahb_redirect(); mc_disable_ahb_redirect();
g_ahb_redirect_enabled = false; g_ahb_redirect_enabled = false;
} }
/* Free the crypto work buffer. */
if (devpart->crypto_work_buffer != NULL) {
free(devpart->crypto_work_buffer);
}
} }
static int mmc_partition_read(device_partition_t *devpart, void *dst, uint64_t sector, uint64_t num_sectors) { static int mmc_partition_read(device_partition_t *devpart, void *dst, uint64_t sector, uint64_t num_sectors) {

3
fusee/fusee-secondary/src/sdmmc/sdmmc_core.c
View file

@ -1202,6 +1202,9 @@ void sdmmc_finish(sdmmc_t *sdmmc)
/* Power cycle for 100ms without power. */ /* Power cycle for 100ms without power. */
mdelay(100); mdelay(100);
/* Disable the regulator. */
max77620_regulator_enable(REGULATOR_LDO2, 0);
} }
/* Force a register read to refresh the clock control value. */ /* Force a register read to refresh the clock control value. */

3
sept/sept-secondary/src/sdmmc/sdmmc_core.c
View file

@ -1202,6 +1202,9 @@ void sdmmc_finish(sdmmc_t *sdmmc)
/* Power cycle for 100ms without power. */ /* Power cycle for 100ms without power. */
mdelay(100); mdelay(100);
/* Disable the regulator. */
max77620_regulator_enable(REGULATOR_LDO2, 0);
} }
/* Force a register read to refresh the clock control value. */ /* Force a register read to refresh the clock control value. */