mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-23 12:51:13 +00:00
thermopshere: refactor jump-to-kernel ,add single-step code
not working under qemu yet though
This commit is contained in:
parent
9c9f6c04cc
commit
731d50a3a3
8 changed files with 108 additions and 15 deletions
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@ -70,6 +70,7 @@ CFLAGS := \
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-std=gnu11 \
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-std=gnu11 \
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-Werror \
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-Werror \
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-Wall \
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-Wall \
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-Wno-main \
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$(ARCH) $(DEFINES)
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$(ARCH) $(DEFINES)
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CFLAGS += $(INCLUDE)
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CFLAGS += $(INCLUDE)
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@ -140,7 +141,7 @@ all: $(BUILD)
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ifeq ($(PLATFORM), qemu)
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ifeq ($(PLATFORM), qemu)
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QEMUFLAGS := -nographic -machine virt,secure=on,virtualization=on,gic-version=2 -cpu cortex-a57 -smp 4 -m 1024\
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QEMUFLAGS := -nographic -machine virt,secure=on,virtualization=on,gic-version=2 -cpu cortex-a57 -smp 4 -m 1024\
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-bios bl1.bin -d unimp,int,mmu -semihosting-config enable,target=native -serial mon:stdio
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-bios bl1.bin -d unimp,int -semihosting-config enable,target=native -serial mon:stdio
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# NOTE: copy bl1.bin, bl2.bin, bl31.bin from your own build of Arm Trusted Firmware!
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# NOTE: copy bl1.bin, bl2.bin, bl31.bin from your own build of Arm Trusted Firmware!
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@ -24,6 +24,7 @@ typedef struct CoreCtx {
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u64 scratch; // @0x18
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u64 scratch; // @0x18
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u32 coreId; // @0x20
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u32 coreId; // @0x20
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bool isBootCore; // @0x24
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bool isBootCore; // @0x24
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bool wasSingleStepping; // @0x25 (for pIRQ handler)
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} CoreCtx;
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} CoreCtx;
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extern CoreCtx g_coreCtxs[4];
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extern CoreCtx g_coreCtxs[4];
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@ -135,6 +135,7 @@ vector_entry fiq_sp0
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.endfunc
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.endfunc
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.cfi_endproc
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.cfi_endproc
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/* To save space, insert in an unused vector segment. */
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/* To save space, insert in an unused vector segment. */
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.global _restore_all_regs
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_restore_all_regs:
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_restore_all_regs:
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ldp x30, x20, [sp, #0xF0]
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ldp x30, x20, [sp, #0xF0]
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ldp x21, x22, [sp, #0x100]
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ldp x21, x22, [sp, #0x100]
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@ -161,7 +162,7 @@ vector_entry fiq_sp0
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ldp x26, x27, [sp, #0xD0]
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ldp x26, x27, [sp, #0xD0]
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ldp x28, x29, [sp, #0xE0]
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ldp x28, x29, [sp, #0xE0]
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add sp, sp, #0x210
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add sp, sp, #0x120
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eret
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eret
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vector_entry serror_sp0
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vector_entry serror_sp0
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@ -19,6 +19,7 @@
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#include "sysreg_traps.h"
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#include "sysreg_traps.h"
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#include "smc.h"
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#include "smc.h"
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#include "core_ctx.h"
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#include "core_ctx.h"
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#include "single_step.h"
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#include "debug_log.h"
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#include "debug_log.h"
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@ -110,6 +111,10 @@ void handleLowerElSyncException(ExceptionStackFrame *frame, ExceptionSyndromeReg
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handleMsrMrsTrap(frame, esr);
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handleMsrMrsTrap(frame, esr);
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break;
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break;
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case Exception_SoftwareStepLowerEl:
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handleSingleStep(frame, esr);
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break;
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default:
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default:
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DEBUG("Lower EL sync exception, EC = 0x%02llx IL=%llu ISS=0x%06llx\n", (u64)esr.ec, esr.il, esr.iss);
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DEBUG("Lower EL sync exception, EC = 0x%02llx IL=%llu ISS=0x%06llx\n", (u64)esr.ec, esr.il, esr.iss);
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dumpStackFrame(frame, false);
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dumpStackFrame(frame, false);
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@ -1,3 +1,5 @@
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#include <string.h>
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#include "utils.h"
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#include "utils.h"
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#include "core_ctx.h"
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#include "core_ctx.h"
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#include "debug_log.h"
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#include "debug_log.h"
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@ -5,6 +7,8 @@
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#include "semihosting.h"
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#include "semihosting.h"
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#include "traps.h"
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#include "traps.h"
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#include "sysreg.h"
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#include "sysreg.h"
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#include "exceptions.h"
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#include "single_step.h"
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extern const u8 __start__[];
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extern const u8 __start__[];
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@ -31,9 +35,10 @@ static void loadKernelViaSemihosting(void)
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currentCoreCtx->kernelEntrypoint = buf;
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currentCoreCtx->kernelEntrypoint = buf;
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}
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}
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int main(void)
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void main(ExceptionStackFrame *frame)
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{
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{
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enableTraps();
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enableTraps();
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enableSingleStepExceptions();
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if (currentCoreCtx->isBootCore) {
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if (currentCoreCtx->isBootCore) {
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uartInit(115200);
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uartInit(115200);
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@ -50,8 +55,14 @@ int main(void)
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}
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}
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else {
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else {
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DEBUG("EL2: core %u reached main!\n", currentCoreCtx->coreId);
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DEBUG("EL2: core %u reached main!\n", currentCoreCtx->coreId);
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DEBUG("Test 0x%08llx %016llx\n", get_physical_address_el1_stage12(0x08010000ull), GET_SYSREG(par_el1));
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//DEBUG("Test 0x%08llx %016llx\n", get_physical_address_el1_stage12(0x08010000ull), GET_SYSREG(par_el1));
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}
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}
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return 0;
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// Set up exception frame: init regs to 0, set spsr, elr, etc.
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memset(frame, 0, sizeof(ExceptionStackFrame));
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frame->spsr_el2 = (0xF << 6) | (1 << 2) | 1; // EL1h+DAIF
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frame->elr_el2 = currentCoreCtx->kernelEntrypoint;
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frame->x[0] = currentCoreCtx->kernelArgument;
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//setSingleStep(frame, false);
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}
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}
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48
thermosphere/src/single_step.c
Normal file
48
thermosphere/src/single_step.c
Normal file
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@ -0,0 +1,48 @@
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/*
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* Copyright (c) 2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "single_step.h"
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#include "core_ctx.h"
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#include "sysreg.h"
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#include "debug_log.h"
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void enableSingleStepExceptions(void)
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{
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u64 mdscr = GET_SYSREG(mdscr_el1);
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// Enable Single Step functionality
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mdscr |= BIT(0);
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SET_SYSREG(mdscr_el1, mdscr);
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}
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void setSingleStep(ExceptionStackFrame *frame, bool singleStep)
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{
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// Set or clear SPSR.SS
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if (singleStep) {
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frame->spsr_el2 |= BITL(22);
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} else {
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frame->spsr_el2 &= ~BITL(22);
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}
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currentCoreCtx->wasSingleStepping = singleStep;
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}
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void handleSingleStep(ExceptionStackFrame *frame, ExceptionSyndromeRegister esr)
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{
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DEBUG("Single-step exeception ELR = 0x%016llx, ISV = %u, EX = %u\n", frame->elr_el2, (esr.iss >> 24) & 1, (esr.iss >> 6) & 1);
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setSingleStep(frame, true); // hehe boi
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}
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26
thermosphere/src/single_step.h
Normal file
26
thermosphere/src/single_step.h
Normal file
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "utils.h"
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#include "exceptions.h"
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void enableSingleStepExceptions(void);
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void setSingleStep(ExceptionStackFrame *frame, bool singleStep);
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void handleSingleStep(ExceptionStackFrame *frame, ExceptionSyndromeRegister esr);
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@ -44,7 +44,7 @@ _startCommon:
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add x8, x8, #:lo12:__vectors_start__
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add x8, x8, #:lo12:__vectors_start__
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msr vbar_el2, x8
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msr vbar_el2, x8
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// Set system to sane defaults, aarch64 for el1
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// Set system to sane defaults, aarch64 for el1, mmu disabled
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mov x4, #0x0838
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mov x4, #0x0838
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movk x4, #0xC5, lsl #16
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movk x4, #0xC5, lsl #16
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orr x1, x4, #0x30000000
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orr x1, x4, #0x30000000
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@ -70,7 +70,7 @@ _startCommon:
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cmp x0, #4
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cmp x0, #4
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bhs .
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bhs .
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// Set tmp stack (__stacks_top__ is aligned)
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// Set stack pointer
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adrp x8, __stacks_top__
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adrp x8, __stacks_top__
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lsl x9, x0, #10
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lsl x9, x0, #10
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sub sp, x8, x9
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sub sp, x8, x9
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@ -80,6 +80,9 @@ _startCommon:
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bl coreCtxInit
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bl coreCtxInit
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stp x18, xzr, [sp, #-0x10]!
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stp x18, xzr, [sp, #-0x10]!
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// Reserve space for exception frame
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sub sp, sp, #0x120
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// Don't call init array to save space?
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// Don't call init array to save space?
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// Clear BSS & call main for the first core executing this code
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// Clear BSS & call main for the first core executing this code
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cbz x19, _enable_mmu
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cbz x19, _enable_mmu
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@ -101,16 +104,13 @@ _enable_mmu:
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dsb sy
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dsb sy
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isb
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isb
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mov x0, sp
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bl main
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bl main
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// Jump to kernel
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mov x8, #(0b1111 << 6 | 0b0101) // EL1h+DAIF
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msr spsr_el2, x8
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ldp x0, x1, [x18]
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msr elr_el2, x1
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dsb sy
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dsb sy
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isb
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isb
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eret
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// Jump to kernel
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b _restore_all_regs
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.pool
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.pool
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