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Fix uart init

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This commit is contained in:
TuxSH 2019-07-24 00:37:24 +02:00
parent 39d041466d
commit 72dd25a99e
3 changed files with 72 additions and 21 deletions
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31
exosphere/src/uart.c
View file

@ -19,9 +19,19 @@
#include "timers.h" #include "timers.h"
#include "pinmux.h" #include "pinmux.h"
static inline void uart_wait_cycles(uint32_t baud, uint32_t num)
{
wait((num * 1000000 + 16 * baud - 1) / (16 * baud));
}
static inline void uart_wait_syms(uint32_t baud, uint32_t num)
{
wait((num * 1000000 + baud - 1) / baud);
}
void uart_config(UartDevice dev) { void uart_config(UartDevice dev) {
volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
switch (dev) { switch (dev) {
case UART_A: case UART_A:
pinmux->uart1_tx = 0; pinmux->uart1_tx = 0;
@ -60,7 +70,7 @@ void uart_init(UartDevice dev, uint32_t baud) {
/* Wait for idle state. */ /* Wait for idle state. */
uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE); uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE);
/* Calculate baud rate. */ /* Calculate baud rate, round to nearest. */
uint32_t rate = (8 * baud + 408000000) / (16 * baud); uint32_t rate = (8 * baud + 408000000) / (16 * baud);
/* Setup UART in FIFO mode. */ /* Setup UART in FIFO mode. */
@ -70,12 +80,19 @@ void uart_init(UartDevice dev, uint32_t baud) {
uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */ uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */
uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */ uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */
uart->UART_LCR &= ~(UART_LCR_DLAB); /* Disable DLAB. */ uart->UART_LCR &= ~(UART_LCR_DLAB); /* Disable DLAB. */
uart->UART_SPR; /* Dummy read. */
uart_wait_syms(baud, 3); /* Wait for 3 symbols at the new baudrate. */
/* Enable FIFO with default settings. */
uart->UART_IIR_FCR = UART_FCR_FCR_EN_FIFO;
uart->UART_SPR; /* Dummy read as mandated by TRM. */
uart_wait_cycles(baud, 3); /* Wait for 3 baud cycles, as mandated by TRM (erratum). */
/* Flush FIFO. */ /* Flush FIFO. */
uart->UART_IIR_FCR = (UART_FCR_FCR_EN_FIFO | UART_FCR_RX_CLR | UART_FCR_TX_CLR); /* Enable and clear TX and RX FIFOs. */ uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE); /* Make sure there's no data being written in TX FIFO (TRM). */
wait(3 * ((baud + 999999) / baud)); uart->UART_IIR_FCR |= UART_FCR_RX_CLR | UART_FCR_TX_CLR; /* Clear TX and RX FIFOs. */
uart_wait_cycles(baud, 32); /* Wait for 32 baud cycles (TRM, erratum). */
/* Wait for idle state. */ /* Wait for idle state (TRM). */
uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE); uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE);
} }

31
fusee/fusee-primary/src/uart.c
View file

@ -19,9 +19,19 @@
#include "timers.h" #include "timers.h"
#include "pinmux.h" #include "pinmux.h"
static inline void uart_wait_cycles(uint32_t baud, uint32_t num)
{
udelay((num * 1000000 + 16 * baud - 1) / (16 * baud));
}
static inline void uart_wait_syms(uint32_t baud, uint32_t num)
{
udelay((num * 1000000 + baud - 1) / baud);
}
void uart_config(UartDevice dev) { void uart_config(UartDevice dev) {
volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
switch (dev) { switch (dev) {
case UART_A: case UART_A:
pinmux->uart1_tx = 0; pinmux->uart1_tx = 0;
@ -60,7 +70,7 @@ void uart_init(UartDevice dev, uint32_t baud) {
/* Wait for idle state. */ /* Wait for idle state. */
uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE); uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE);
/* Calculate baud rate. */ /* Calculate baud rate, round to nearest. */
uint32_t rate = (8 * baud + 408000000) / (16 * baud); uint32_t rate = (8 * baud + 408000000) / (16 * baud);
/* Setup UART in FIFO mode. */ /* Setup UART in FIFO mode. */
@ -70,12 +80,19 @@ void uart_init(UartDevice dev, uint32_t baud) {
uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */ uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */
uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */ uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */
uart->UART_LCR &= ~(UART_LCR_DLAB); /* Disable DLAB. */ uart->UART_LCR &= ~(UART_LCR_DLAB); /* Disable DLAB. */
uart->UART_SPR; /* Dummy read. */
uart_wait_syms(baud, 3); /* Wait for 3 symbols at the new baudrate. */
/* Enable FIFO with default settings. */
uart->UART_IIR_FCR = UART_FCR_FCR_EN_FIFO;
uart->UART_SPR; /* Dummy read as mandated by TRM. */
uart_wait_cycles(baud, 3); /* Wait for 3 baud cycles, as mandated by TRM (erratum). */
/* Flush FIFO. */ /* Flush FIFO. */
uart->UART_IIR_FCR = (UART_FCR_FCR_EN_FIFO | UART_FCR_RX_CLR | UART_FCR_TX_CLR); /* Enable and clear TX and RX FIFOs. */ uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE); /* Make sure there's no data being written in TX FIFO (TRM). */
udelay(3 * ((baud + 999999) / baud)); uart->UART_IIR_FCR |= UART_FCR_RX_CLR | UART_FCR_TX_CLR; /* Clear TX and RX FIFOs. */
uart_wait_cycles(baud, 32); /* Wait for 32 baud cycles (TRM, erratum). */
/* Wait for idle state. */ /* Wait for idle state (TRM). */
uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE); uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE);
} }

31
sept/sept-secondary/src/uart.c
View file

@ -19,9 +19,19 @@
#include "timers.h" #include "timers.h"
#include "pinmux.h" #include "pinmux.h"
static inline void uart_wait_cycles(uint32_t baud, uint32_t num)
{
udelay((num * 1000000 + 16 * baud - 1) / (16 * baud));
}
static inline void uart_wait_syms(uint32_t baud, uint32_t num)
{
udelay((num * 1000000 + baud - 1) / baud);
}
void uart_config(UartDevice dev) { void uart_config(UartDevice dev) {
volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
switch (dev) { switch (dev) {
case UART_A: case UART_A:
pinmux->uart1_tx = 0; pinmux->uart1_tx = 0;
@ -60,7 +70,7 @@ void uart_init(UartDevice dev, uint32_t baud) {
/* Wait for idle state. */ /* Wait for idle state. */
uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE); uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE);
/* Calculate baud rate. */ /* Calculate baud rate, round to nearest. */
uint32_t rate = (8 * baud + 408000000) / (16 * baud); uint32_t rate = (8 * baud + 408000000) / (16 * baud);
/* Setup UART in FIFO mode. */ /* Setup UART in FIFO mode. */
@ -70,12 +80,19 @@ void uart_init(UartDevice dev, uint32_t baud) {
uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */ uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */
uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */ uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */
uart->UART_LCR &= ~(UART_LCR_DLAB); /* Disable DLAB. */ uart->UART_LCR &= ~(UART_LCR_DLAB); /* Disable DLAB. */
uart->UART_SPR; /* Dummy read. */
uart_wait_syms(baud, 3); /* Wait for 3 symbols at the new baudrate. */
/* Enable FIFO with default settings. */
uart->UART_IIR_FCR = UART_FCR_FCR_EN_FIFO;
uart->UART_SPR; /* Dummy read as mandated by TRM. */
uart_wait_cycles(baud, 3); /* Wait for 3 baud cycles, as mandated by TRM (erratum). */
/* Flush FIFO. */ /* Flush FIFO. */
uart->UART_IIR_FCR = (UART_FCR_FCR_EN_FIFO | UART_FCR_RX_CLR | UART_FCR_TX_CLR); /* Enable and clear TX and RX FIFOs. */ uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE); /* Make sure there's no data being written in TX FIFO (TRM). */
udelay(3 * ((baud + 999999) / baud)); uart->UART_IIR_FCR |= UART_FCR_RX_CLR | UART_FCR_TX_CLR; /* Clear TX and RX FIFOs. */
uart_wait_cycles(baud, 32); /* Wait for 32 baud cycles (TRM, erratum). */
/* Wait for idle state. */ /* Wait for idle state (TRM). */
uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE); uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE);
} }