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fusee: Minor hardware configuration fixes.

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This commit is contained in:
hexkyz 2018-11-17 21:50:31 +00:00
parent ac391d9c5e
commit 6e7eb47d33
3 changed files with 12 additions and 3 deletions
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2
fusee/fusee-primary/src/hwinit.c
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@ -234,7 +234,7 @@ void nx_hwinit()
/* Reboot SE. */ /* Reboot SE. */
/* NOTE: [4.0.0+] This was removed. */ /* NOTE: [4.0.0+] This was removed. */
clkrst_reboot(CARDEVICE_SE); /* clkrst_reboot(CARDEVICE_SE); */
/* Reboot unknown device. */ /* Reboot unknown device. */
clkrst_reboot(CARDEVICE_UNK); clkrst_reboot(CARDEVICE_UNK);

4
fusee/fusee-primary/src/mc.c
View file

@ -160,7 +160,9 @@ void mc_enable()
car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000); car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000);
/* Clear EMC and MC reset. */ /* Clear EMC and MC reset. */
car->rst_dev_h_set = 0x2000001; /* NOTE: [4.0.0+] This was changed to use the right register. */
/* car->rst_dev_h_set = 0x2000001; */
car->rst_dev_h_clr = 0x2000001;
udelay(5); udelay(5);
mc_disable_ahb_redirect(); mc_disable_ahb_redirect();

9
fusee/fusee-secondary/src/cluster.c
View file

@ -22,6 +22,7 @@
#include "sysreg.h" #include "sysreg.h"
#include "i2c.h" #include "i2c.h"
#include "car.h" #include "car.h"
#include "mc.h"
#include "timers.h" #include "timers.h"
#include "pmc.h" #include "pmc.h"
#include "max77620.h" #include "max77620.h"
@ -141,6 +142,10 @@ void cluster_boot_cpu0(uint32_t entry)
SB_CSR_0 = 2; SB_CSR_0 = 2;
(void)SB_CSR_0; (void)SB_CSR_0;
/* Set CPU_STRICT_TZ_APERTURE_CHECK. */
/* NOTE: [4.0.0+] This was added, but it breaks Exosphère. */
/* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */
/* Clear MSELECT reset. */ /* Clear MSELECT reset. */
car->rst_dev_v &= 0xFFFFFFF7; car->rst_dev_v &= 0xFFFFFFF7;
@ -148,5 +153,7 @@ void cluster_boot_cpu0(uint32_t entry)
car->rst_cpug_cmplx_clr = 0x20000000; car->rst_cpug_cmplx_clr = 0x20000000;
/* Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.*/ /* Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.*/
car->rst_cpug_cmplx_clr = 0x411F000F; /* NOTE: [5.0.0+] This was changed so only CPU0 reset is cleared. */
/* car->rst_cpug_cmplx_clr = 0x411F000F; */
car->rst_cpug_cmplx_clr = 0x41010001;
} }