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Implement flush_dcache_all_tzram_pa and invalidate_icache_all_inner_shareable_tzram_pa for the crt0s

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TuxSH 2018-02-28 19:06:41 +01:00
parent e5f293e004
commit 6be5b0a52f
5 changed files with 38 additions and 17 deletions
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3
exosphere/src/arm.h
View file

@ -15,7 +15,8 @@ void invalidate_dcache_all(void);
void flush_dcache_range(const void *start, const void *end); void flush_dcache_range(const void *start, const void *end);
void invalidate_dcache_range(const void *start, const void *end); void invalidate_dcache_range(const void *start, const void *end);
void invalidate_icache_inner_shareable(void); void invalidate_icache_all_inner_shareable(void);
void invalidate_icache_all(void);
void finalize_powerdown(void); void finalize_powerdown(void);
void call_with_stack_pointer(uintptr_t stack_pointer, void (*function)(void)); void call_with_stack_pointer(uintptr_t stack_pointer, void (*function)(void));

19
exosphere/src/arm.s
View file

@ -217,10 +217,10 @@ invalidate_dcache_range:
* *
* invalidate all icache entries. * invalidate all icache entries.
*/ */
.section .text.invalidate_icache_inner_shareable, "ax", %progbits .section .text.invalidate_icache_all_inner_shareable, "ax", %progbits
.type invalidate_icache_inner_shareable, %function .type invalidate_icache_all_inner_shareable, %function
.global invalidate_icache_inner_shareable .global invalidate_icache_all_inner_shareable
invalidate_icache_inner_shareable: invalidate_icache_all_inner_shareable:
dsb ish dsb ish
isb isb
ic ialluis ic ialluis
@ -228,6 +228,17 @@ invalidate_icache_inner_shareable:
isb isb
ret ret
.section .text.invalidate_icache_all, "ax", %progbits
.type invalidate_icache_all, %function
.global invalidate_icache_all
invalidate_icache_all:
dsb sy
isb
ic iallu
dsb sy
isb
ret
/* Final steps before power down. */ /* Final steps before power down. */
.section .text.finalize_powerdown, "ax", %progbits .section .text.finalize_powerdown, "ax", %progbits
.type finalize_powerdown, %function .type finalize_powerdown, %function

4
exosphere/src/coldboot_init.c
View file

@ -12,7 +12,7 @@ extern const uint8_t __vectors_start__[], __vectors_end__[], __vectors_lma__[];
/* warmboot_init.c */ /* warmboot_init.c */
void set_memory_registers_enable_mmu(void); void set_memory_registers_enable_mmu(void);
void flush_dcache_all_tzram_pa(void); void flush_dcache_all_tzram_pa(void);
void invalidate_icache_all_tzram_pa(void); void invalidate_icache_all_inner_shareable_tzram_pa(void);
static void identity_map_all_mappings(uintptr_t *mmu_l1_tbl, uintptr_t *mmu_l3_tbl) { static void identity_map_all_mappings(uintptr_t *mmu_l1_tbl, uintptr_t *mmu_l3_tbl) {
static const uintptr_t addrs[] = { TUPLE_FOLD_LEFT_0(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) }; static const uintptr_t addrs[] = { TUPLE_FOLD_LEFT_0(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
@ -130,7 +130,7 @@ void coldboot_init(void) {
set_memory_registers_enable_mmu(); set_memory_registers_enable_mmu();
flush_dcache_all_tzram_pa(); flush_dcache_all_tzram_pa();
invalidate_icache_all_tzram_pa(); invalidate_icache_all_inner_shareable_tzram_pa();
/* At this point we can access all the mapped segments */ /* At this point we can access all the mapped segments */
/* TODO: zero-initialize the cpu context */ /* TODO: zero-initialize the cpu context */
/* Nintendo clears the (emtpy) pk2ldr's BSS section here , but we embed it 0-filled in the binary */ /* Nintendo clears the (emtpy) pk2ldr's BSS section here , but we embed it 0-filled in the binary */

2
exosphere/src/package2.c
View file

@ -380,7 +380,7 @@ void load_package2(void) {
/* Clean up cache. */ /* Clean up cache. */
flush_dcache_all(); flush_dcache_all();
invalidate_icache_inner_shareable(); invalidate_icache_all_inner_shareable();
/* Set CORE0 entrypoint for Package2. */ /* Set CORE0 entrypoint for Package2. */
set_core_entrypoint_and_argument(0, DRAM_BASE_PHYSICAL + header.metadata.entrypoint, 0); set_core_entrypoint_and_argument(0, DRAM_BASE_PHYSICAL + header.metadata.entrypoint, 0);

17
exosphere/src/warmboot_init.c
View file

@ -1,16 +1,25 @@
#include "utils.h" #include "utils.h"
#include "memory_map.h" #include "memory_map.h"
#include "arm.h"
extern const uint8_t __main_start__[];
/* start.s */ /* start.s */
void __set_memory_registers(uintptr_t ttbr0, uintptr_t vbar, uint64_t cpuectlr, uint32_t scr, void __set_memory_registers(uintptr_t ttbr0, uintptr_t vbar, uint64_t cpuectlr, uint32_t scr,
uint32_t tcr, uint32_t cptr, uint64_t mair, uint32_t sctlr); uint32_t tcr, uint32_t cptr, uint64_t mair, uint32_t sctlr);
void flush_dcache_all_tzram_pa(void) { __attribute__((target("cmodel=large"))) void flush_dcache_all_tzram_pa(void) {
/* TODO */ uintptr_t pa = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN);
uintptr_t main_pa = pa | ((uintptr_t)__main_start__ & 0xFFF);
uintptr_t v = (uintptr_t)flush_dcache_all - (uintptr_t)__main_start__ + (uintptr_t)main_pa;
((void (*)(void))v)();
} }
void invalidate_icache_all_tzram_pa(void) { __attribute__((target("cmodel=large"))) void invalidate_icache_all_inner_shareable_tzram_pa(void) {
/* TODO */ uintptr_t pa = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN);
uintptr_t main_pa = pa | ((uintptr_t)__main_start__ & 0xFFF);
uintptr_t v = (uintptr_t)invalidate_icache_all_inner_shareable - (uintptr_t)__main_start__ + (uintptr_t)main_pa;
((void (*)(void))v)();
} }
uintptr_t get_warmboot_crt0_stack_address(void) { uintptr_t get_warmboot_crt0_stack_address(void) {