diff --git a/libraries/libvapours/include/vapours/tegra.hpp b/libraries/libvapours/include/vapours/tegra.hpp index 52a04cbb5..ac69ce1b2 100644 --- a/libraries/libvapours/include/vapours/tegra.hpp +++ b/libraries/libvapours/include/vapours/tegra.hpp @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp b/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp index 1ceabe5b2..47fa9bcca 100644 --- a/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp +++ b/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp @@ -33,6 +33,9 @@ #define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL (0xAB4) #define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL (0xABC) +/* Mariko only */ +#define APB_MISC_GP_DSI_PAD_CONTROL (0xAC0) + #define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00) #define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00) #define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 (0xc04) diff --git a/libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp b/libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp index 1be60be68..212000363 100644 --- a/libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp +++ b/libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp @@ -240,12 +240,18 @@ DEFINE_CLK_RST_REG(CLK_SOURCE_MSELECT_MSELECT_CLK_DIVISOR, 0, 8); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2); +DEFINE_CLK_RST_REG(CLK_SOURCE_DSIA_LP_DSIA_LP_CLK_DIVISOR, 0, 8); +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DSIA_LP_DSIA_LP_CLK_SRC, 29, PLLP_OUT0, RSVD1, PLLC_OUT0, PLLC4_OUT0, PLLC4_OUT1, PLLC4_OUT2, CLK_M, RSVD7); + DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_REF_DVFS_REF_DIVISOR, 0, 8); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_REF_DVFS_REF_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2); DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_SOC_DVFS_SOC_DIVISOR, 0, 8); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_SOC_DVFS_SOC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2); +DEFINE_CLK_RST_REG(CLK_SOURCE_UART_FST_MIPI_CAL_UART_FST_MIPI_CAL_CLK_DIVISOR, 0, 8); +DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UART_FST_MIPI_CAL_UART_FST_MIPI_CAL_CLK_SRC, 29, PLLP_OUT3, PLLC_OUT0, PLLC2_OUT0_2, RSVD3, PLLC2_OUT0_4, RSVD5, CLK_M, RSVD7); + DEFINE_CLK_RST_REG(CLK_SOURCE_LEGACY_TM_CLK_DIVISOR, 0, 8); DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_LEGACY_TM_CLK_SRC, 29, PLLP_OUT3, PLLC_OUT0, PLLC2_OUT0, CLK_M, PLLP_OUT0, PLLC4_OUT0, PLLC4_OUT1, PLLC4_OUT2); @@ -264,59 +270,65 @@ DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET3, 19, DISABLE, ENA DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENABLE); /* TODO: Actually include all devices. */ -#define CLK_RST_FOREACH_DEVICE(HANDLER) \ - HANDLER(L, CPU, 0, 0) \ - HANDLER(L, RTC, 0, 4) \ - HANDLER(L, TMR, 0, 5) \ - HANDLER(L, GPIO, 0, 8) \ - HANDLER(L, SDMMC2, 0, 9) \ - HANDLER(L, SDMMC1, 0, 14) \ - HANDLER(L, SDMMC4, 0, 15) \ - HANDLER(L, USBD, 0, 22) \ - HANDLER(L, CACHE2, 0, 31) \ - HANDLER(H, MEM, 1, 0) \ - HANDLER(H, AHBDMA, 1, 1) \ - HANDLER(H, APBDMA, 1, 2) \ - HANDLER(H, PMC, 1, 6) \ - HANDLER(H, FUSE, 1, 7) \ - HANDLER(H, KFUSE, 1, 8) \ - HANDLER(H, I2C5, 1, 15) \ - HANDLER(H, EMC, 1, 25) \ - HANDLER(H, USB2, 1, 26) \ - HANDLER(U, SDMMC3, 2, 5) \ - HANDLER(U, CSITE, 2, 9) \ - HANDLER(U, IRAMA, 2, 20) \ - HANDLER(U, IRAMB, 2, 21) \ - HANDLER(U, IRAMC, 2, 22) \ - HANDLER(U, IRAMD, 2, 23) \ - HANDLER(U, CRAM2, 2, 24) \ - HANDLER(V, CPUG, 3, 0) \ - HANDLER(V, MSELECT, 3, 3) \ - HANDLER(V, SPDIF_DOUBLER, 3, 22) \ - HANDLER(V, ACTMON, 3, 23) \ - HANDLER(V, TZRAM, 3, 30) \ - HANDLER(V, SE, 3, 31) \ - HANDLER(W, PCIERX0, 4, 2) \ - HANDLER(W, PCIERX1, 4, 3) \ - HANDLER(W, PCIERX2, 4, 4) \ - HANDLER(W, PCIERX3, 4, 5) \ - HANDLER(W, PCIERX4, 4, 6) \ - HANDLER(W, PCIERX5, 4, 7) \ - HANDLER(W, ENTROPY, 4, 21) \ - HANDLER(W, DVFS, 4, 27) \ - HANDLER(W, MC1, 4, 30) \ - HANDLER(X, MC_CAPA, 5, 7) \ - HANDLER(X, MC_CBPA, 5, 8) \ - HANDLER(X, MC_CPU, 5, 9) \ - HANDLER(X, MC_BBC, 5, 10) \ - HANDLER(X, EMC_DLL, 5, 14) \ - HANDLER(X, GPU, 5, 24) \ - HANDLER(X, DBGAPB, 5, 25) \ - HANDLER(X, PLLG_REF, 5, 29) \ - HANDLER(Y, LEGACY_TM, 6, 1) \ - HANDLER(Y, MC_CCPA, 6, 8) \ - HANDLER(Y, MC_CDPA, 6, 9) \ - HANDLER(Y, PLLP_OUT_CPU, 6, 31) +#define CLK_RST_FOREACH_DEVICE(HANDLER) \ + HANDLER(L, CPU, 0, 0) \ + HANDLER(L, RTC, 0, 4) \ + HANDLER(L, TMR, 0, 5) \ + HANDLER(L, GPIO, 0, 8) \ + HANDLER(L, SDMMC2, 0, 9) \ + HANDLER(L, SDMMC1, 0, 14) \ + HANDLER(L, SDMMC4, 0, 15) \ + HANDLER(L, USBD, 0, 22) \ + HANDLER(L, DISP1, 0, 27) \ + HANDLER(L, HOST1X, 0, 28) \ + HANDLER(L, CACHE2, 0, 31) \ + HANDLER(H, MEM, 1, 0) \ + HANDLER(H, AHBDMA, 1, 1) \ + HANDLER(H, APBDMA, 1, 2) \ + HANDLER(H, PMC, 1, 6) \ + HANDLER(H, FUSE, 1, 7) \ + HANDLER(H, KFUSE, 1, 8) \ + HANDLER(H, I2C5, 1, 15) \ + HANDLER(H, DSI, 1, 16) \ + HANDLER(H, MIPI_CAL, 1, 24) \ + HANDLER(H, EMC, 1, 25) \ + HANDLER(H, USB2, 1, 26) \ + HANDLER(U, SDMMC3, 2, 5) \ + HANDLER(U, CSITE, 2, 9) \ + HANDLER(U, IRAMA, 2, 20) \ + HANDLER(U, IRAMB, 2, 21) \ + HANDLER(U, IRAMC, 2, 22) \ + HANDLER(U, IRAMD, 2, 23) \ + HANDLER(U, CRAM2, 2, 24) \ + HANDLER(V, CPUG, 3, 0) \ + HANDLER(V, MSELECT, 3, 3) \ + HANDLER(V, SPDIF_DOUBLER, 3, 22) \ + HANDLER(V, ACTMON, 3, 23) \ + HANDLER(V, TZRAM, 3, 30) \ + HANDLER(V, SE, 3, 31) \ + HANDLER(W, PCIERX0, 4, 2) \ + HANDLER(W, PCIERX1, 4, 3) \ + HANDLER(W, PCIERX2, 4, 4) \ + HANDLER(W, PCIERX3, 4, 5) \ + HANDLER(W, PCIERX4, 4, 6) \ + HANDLER(W, PCIERX5, 4, 7) \ + HANDLER(W, DSIA_LP, 4, 19) \ + HANDLER(W, ENTROPY, 4, 21) \ + HANDLER(W, DVFS, 4, 27) \ + HANDLER(W, MC1, 4, 30) \ + HANDLER(X, MC_CAPA, 5, 7) \ + HANDLER(X, MC_CBPA, 5, 8) \ + HANDLER(X, MC_CPU, 5, 9) \ + HANDLER(X, MC_BBC, 5, 10) \ + HANDLER(X, EMC_DLL, 5, 14) \ + HANDLER(X, UART_FST_MIPI_CAL, 5, 17) \ + HANDLER(X, GPU, 5, 24) \ + HANDLER(X, DBGAPB, 5, 25) \ + HANDLER(X, PLLG_REF, 5, 29) \ + HANDLER(Y, LEGACY_TM, 6, 1) \ + HANDLER(Y, MC_CCPA, 6, 8) \ + HANDLER(Y, MC_CDPA, 6, 9) \ + HANDLER(Y, PLLP_OUT_CPU, 6, 31) #define CLK_RST_DEFINE_SET_CLR_REG(REGISTER, DEVICE, REGISTER_INDEX, DEVICE_INDEX) \ DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_SET_SET_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \ diff --git a/libraries/libvapours/include/vapours/tegra/tegra_mipi_cal.hpp b/libraries/libvapours/include/vapours/tegra/tegra_mipi_cal.hpp new file mode 100644 index 000000000..efff2ed97 --- /dev/null +++ b/libraries/libvapours/include/vapours/tegra/tegra_mipi_cal.hpp @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2018-2020 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once +#include +#include +#include +#include +#include +#include + +#define MIPI_CAL_MIPI_CAL_CTRL (0x000) +#define MIPI_CAL_CIL_MIPI_CAL_STATUS (0x008) +#define MIPI_CAL_CILA_MIPI_CAL_CONFIG (0x014) +#define MIPI_CAL_CILB_MIPI_CAL_CONFIG (0x018) +#define MIPI_CAL_CILC_MIPI_CAL_CONFIG (0x01C) +#define MIPI_CAL_CILD_MIPI_CAL_CONFIG (0x020) +#define MIPI_CAL_CILE_MIPI_CAL_CONFIG (0x024) +#define MIPI_CAL_CILF_MIPI_CAL_CONFIG (0x028) +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG (0x038) +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG (0x03C) +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG (0x040) +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG (0x044) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 (0x058) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 (0x05C) +#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 (0x060) +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 (0x064) +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 (0x068) +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 (0x070) +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x074) + +#define MIPI_CAL_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (MIPI_CAL, NAME) +#define MIPI_CAL_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (MIPI_CAL, NAME, VALUE) +#define MIPI_CAL_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (MIPI_CAL, NAME, ENUM) +#define MIPI_CAL_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(MIPI_CAL, NAME, __COND__, TRUE_ENUM, FALSE_ENUM) + +#define DEFINE_MIPI_CAL_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (MIPI_CAL, NAME, __OFFSET__, __WIDTH__) +#define DEFINE_MIPI_CAL_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (MIPI_CAL, NAME, __OFFSET__, ZERO, ONE) +#define DEFINE_MIPI_CAL_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (MIPI_CAL, NAME, __OFFSET__, ZERO, ONE, TWO, THREE) +#define DEFINE_MIPI_CAL_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(MIPI_CAL, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) +#define DEFINE_MIPI_CAL_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (MIPI_CAL, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) diff --git a/libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp b/libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp index e518c6684..17a35201b 100644 --- a/libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp +++ b/libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp @@ -210,7 +210,8 @@ DEFINE_PMC_REG_BIT_ENUM(PWR_DET_VAL_SDMMC1, 12, DISABLE, ENABLE); DEFINE_PMC_REG(SET_SW_CLAMP_CRAIL, 0, 1); -DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3); +DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3); +DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD2_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3); DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CRAIL, 0, DISABLE, ENABLE); DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_TE, 1, DISABLE, ENABLE); diff --git a/stratosphere/boot/source/boot_display.cpp b/stratosphere/boot/source/boot_display.cpp index 254de4639..02f53a5db 100644 --- a/stratosphere/boot/source/boot_display.cpp +++ b/stratosphere/boot/source/boot_display.cpp @@ -75,6 +75,8 @@ namespace ams::boot { constinit dd::DeviceAddressSpaceType g_device_address_space; + constinit pwm::driver::ChannelSession g_lcd_backlight_session; + constinit u32 *g_frame_buffer = nullptr; constinit u8 g_frame_buffer_storage[DeviceAddressSpaceAlignSize + FrameBufferSize]; @@ -112,17 +114,18 @@ namespace ams::boot { switch (g_soc_type) { case spl::SocType_Erista: DoRegisterWrites(base_address, reg_writes_erista, num_writes_erista); break; case spl::SocType_Mariko: DoRegisterWrites(base_address, reg_writes_mariko, num_writes_mariko); break; + AMS_UNREACHABLE_DEFAULT_CASE(); } } - inline void DoDsiSleepOrRegisterWrites(const DsiSleepOrRegisterWrite *reg_writes, size_t num_writes) { + inline void DoSleepOrRegisterWrites(uintptr_t base_address, const SleepOrRegisterWrite *reg_writes, size_t num_writes) { for (size_t i = 0; i < num_writes; i++) { switch (reg_writes[i].kind) { - case DsiSleepOrRegisterWriteKind_Write: - reg::Write(g_dsi_regs + sizeof(u32) * reg_writes[i].offset, reg_writes[i].value); + case SleepOrRegisterWriteKind_Write: + reg::Write(base_address + sizeof(u32) * reg_writes[i].offset, reg_writes[i].value); break; - case DsiSleepOrRegisterWriteKind_Sleep: - svcSleepThread(1'000'000ul * u64(reg_writes[i].offset)); + case SleepOrRegisterWriteKind_Sleep: + os::SleepThread(TimeSpan::FromMilliSeconds(reg_writes[i].offset)); break; AMS_UNREACHABLE_DEFAULT_CASE(); } @@ -131,7 +134,7 @@ namespace ams::boot { #define DO_REGISTER_WRITES(base_address, writes) DoRegisterWrites(base_address, writes, util::size(writes)) #define DO_SOC_DEPENDENT_REGISTER_WRITES(base_address, writes) DoSocDependentRegisterWrites(base_address, writes##Erista, util::size(writes##Erista), writes##Mariko, util::size(writes##Mariko)) - #define DO_DSI_SLEEP_OR_REGISTER_WRITES(writes) DoDsiSleepOrRegisterWrites(writes, util::size(writes)) + #define DO_SLEEP_OR_REGISTER_WRITES(base_address, writes) DoSleepOrRegisterWrites(base_address, writes, util::size(writes)) void InitializeFrameBuffer() { if (g_frame_buffer != nullptr) { @@ -157,7 +160,7 @@ namespace ams::boot { void FinalizeFrameBuffer() { if (g_frame_buffer != nullptr) { - const uintptr_t frame_buffer_aligned = util::AlignUp(reinterpret_cast(g_frame_buffer), DeviceAddressSpaceAlignSize); + const uintptr_t frame_buffer_aligned = util::AlignUp(reinterpret_cast(g_frame_buffer_storage), DeviceAddressSpaceAlignSize); /* Unmap the framebuffer from the DC. */ dd::UnmapDeviceAddressSpace(std::addressof(g_device_address_space), dd::GetCurrentProcessHandle(), frame_buffer_aligned, FrameBufferSize, FrameBufferDeviceAddress); @@ -200,6 +203,48 @@ namespace ams::boot { } } + void EnableBacklightForVendor2050ForHardwareTypeFive(int brightness) { + /* Enable FRAME_END_INT */ + reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_ENABLE, 2); + + /* Configure DSI_LINE_TYPE as FOUR */ + reg::Write(g_dsi_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 1); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 9); + + /* Set and wait for FRAME_END_INT */ + reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_STATUS, 2); + while ((reg::Read(g_disp1_regs + sizeof(u32) * DC_CMD_INT_STATUS) & 2) != 0) { /* ... */ } + + /* Configure display brightness. */ + const u32 brightness_val = ((0x7FF * brightness) / 100); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x339); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, (brightness_val & 0x700) | ((brightness_val & 0xFF) << 16) | 0x51); + + /* Set and wait for FRAME_END_INT */ + reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_STATUS, 2); + while ((reg::Read(g_disp1_regs + sizeof(u32) * DC_CMD_INT_STATUS) & 2) != 0) { /* ... */ } + + /* Set client sync point block reset. */ + reg::Write(g_dsi_regs + sizeof(u32) * DSI_INCR_SYNCPT_CNTRL, 1); + os::SleepThread(TimeSpan::FromMilliSeconds(300)); + + /* Clear client sync point block resest. */ + reg::Write(g_dsi_regs + sizeof(u32) * DSI_INCR_SYNCPT_CNTRL, 0); + os::SleepThread(TimeSpan::FromMilliSeconds(300)); + + /* Clear DSI_LINE_TYPE config. */ + reg::Write(g_dsi_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 0); + + /* Disable FRAME_END_INT */ + reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_ENABLE, 0); + reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_STATUS, 2); + } + + void EnableBacklightForGeneric(int brightness) { + pwm::driver::SetScale(g_lcd_backlight_session, static_cast(brightness)); + pwm::driver::SetEnabled(g_lcd_backlight_session, true); + } + } void InitializeDisplay() { @@ -208,6 +253,9 @@ namespace ams::boot { g_soc_type = spl::GetSocType(); InitializeFrameBuffer(); + /* Get the hardware type. */ + const auto hw_type = spl::GetHardwareType(); + /* Turn on DSI/voltage rail. */ { i2c::driver::I2cSession i2c_session; @@ -218,21 +266,37 @@ namespace ams::boot { WriteI2cRegister(i2c_session, 0x1F, 0x71); } WriteI2cRegister(i2c_session, 0x23, 0xD0); + + i2c::driver::CloseSession(i2c_session); } /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */ - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_H_CLR, 0x1010000); - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_H_SET, 0x1010000); - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_L_CLR, 0x18000000); - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_L_SET, 0x18000000); - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_X_SET, 0x20000); - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL, 0xA); - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_W_SET, 0x80000); - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP, 0xA); + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_H_CLR, CLK_RST_REG_BITS_ENUM(RST_DEV_H_CLR_CLR_MIPI_CAL_RST, ENABLE), + CLK_RST_REG_BITS_ENUM(RST_DEV_H_CLR_CLR_DSI_RST, ENABLE)); - /* DPD idle. */ - dd::WriteIoRegister(PmcBase + APBDEV_PMC_IO_DPD_REQ, 0x40000000); - dd::WriteIoRegister(PmcBase + APBDEV_PMC_IO_DPD2_REQ, 0x40000000); + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_H_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_H_SET_SET_CLK_ENB_MIPI_CAL, ENABLE), + CLK_RST_REG_BITS_ENUM(CLK_ENB_H_SET_SET_CLK_ENB_DSI, ENABLE)); + + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_L_CLR, CLK_RST_REG_BITS_ENUM(RST_DEV_L_CLR_CLR_HOST1X_RST, ENABLE), + CLK_RST_REG_BITS_ENUM(RST_DEV_L_CLR_CLR_DISP1_RST, ENABLE)); + + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_L_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_L_SET_SET_CLK_ENB_HOST1X, ENABLE), + CLK_RST_REG_BITS_ENUM(CLK_ENB_L_SET_SET_CLK_ENB_DISP1, ENABLE)); + + + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_X_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_X_SET_SET_CLK_ENB_UART_FST_MIPI_CAL, ENABLE)); + + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_UART_FST_MIPI_CAL_UART_FST_MIPI_CAL_CLK_DIVISOR, 10), + CLK_RST_REG_BITS_ENUM (CLK_SOURCE_UART_FST_MIPI_CAL_UART_FST_MIPI_CAL_CLK_SRC, PLLP_OUT3)); + + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_W_SET, CLK_RST_REG_BITS_ENUM(CLK_ENB_W_SET_SET_CLK_ENB_DSIA_LP, ENABLE)); + + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP, CLK_RST_REG_BITS_VALUE(CLK_SOURCE_DSIA_LP_DSIA_LP_CLK_DIVISOR, 10), + CLK_RST_REG_BITS_ENUM (CLK_SOURCE_DSIA_LP_DSIA_LP_CLK_SRC, PLLP_OUT0)); + + /* Set IO_DPD_REQ to DPD_OFF. */ + dd::WriteIoRegister(PmcBase + APBDEV_PMC_IO_DPD_REQ, reg::Encode(PMC_REG_BITS_ENUM(IO_DPD_REQ_CODE, DPD_OFF))); + dd::WriteIoRegister(PmcBase + APBDEV_PMC_IO_DPD2_REQ, reg::Encode(PMC_REG_BITS_ENUM(IO_DPD2_REQ_CODE, DPD_OFF))); /* Configure LCD pinmux tristate + passthrough. */ reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_NFC_EN, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE))); @@ -241,29 +305,39 @@ namespace ams::boot { reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_BL_EN, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE))); reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_RST, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE))); - /* Configure LCD power, VDD. */ - reg::SetBits(g_gpio_regs + GPIO_PORT3_CNF_0, 0x3); - reg::SetBits(g_gpio_regs + GPIO_PORT3_OE_0, 0x3); - reg::SetBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x1); - svcSleepThread(10'000'000ul); - reg::SetBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x2); - svcSleepThread(10'000'000ul); + if (hw_type == spl::HardwareType::_Five_) { + /* Configure LCD backlight. */ + reg::SetBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x4); + reg::SetBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x4); + } else { + /* Configure LCD power, VDD. */ + reg::SetBits(g_gpio_regs + GPIO_PORT3_CNF_0, 0x3); + reg::SetBits(g_gpio_regs + GPIO_PORT3_OE_0, 0x3); + reg::SetBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x1); + os::SleepThread(TimeSpan::FromMilliSeconds(10)); - /* Configure LCD backlight. */ - reg::SetBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x7); - reg::SetBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x7); - reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x2); + reg::SetBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x2); + os::SleepThread(TimeSpan::FromMilliSeconds(10)); + + /* Configure LCD backlight. */ + R_ABORT_UNLESS(pwm::driver::OpenSession(std::addressof(g_lcd_backlight_session), pwm::DeviceCode_LcdBacklight)); + pwm::driver::SetPeriod(g_lcd_backlight_session, TimeSpan::FromNanoSeconds(33898)); + + reg::SetBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x6); + reg::SetBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x6); + reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x2); + } /* Configure display interface and display. */ - reg::Write(g_mipi_cal_regs + 0x060, 0); + reg::Write(g_mipi_cal_regs + MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0); if (g_soc_type == spl::SocType_Mariko) { - reg::Write(g_mipi_cal_regs + 0x058, 0); - reg::Write(g_apb_misc_regs + 0xAC0, 0); + reg::Write(g_mipi_cal_regs + MIPI_CAL_MIPI_BIAS_PAD_CFG0, 0); + reg::Write(g_apb_misc_regs + APB_MISC_GP_DSI_PAD_CONTROL, 0); } /* Execute configs. */ DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld01); - DO_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc01); + DO_SLEEP_OR_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc01); DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init01); /* NOTE: Nintendo bug here. */ /* As of 8.0.0, Nintendo writes this list to CAR instead of DSI */ @@ -276,14 +350,18 @@ namespace ams::boot { DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init06); DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming); DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init07); - - svcSleepThread(10'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(10)); /* Enable backlight reset. */ reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x4); - svcSleepThread(60'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(60)); + + if (hw_type == spl::HardwareType::_Five_) { + reg::Write(g_dsi_regs + sizeof(u32) * DSI_BTA_TIMING, 0x40103); + } else { + reg::Write(g_dsi_regs + sizeof(u32) * DSI_BTA_TIMING, 0x50204); + } - reg::Write(g_dsi_regs + sizeof(u32) * DSI_BTA_TIMING, 0x50204); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x337); reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); WaitDsiTrigger(); @@ -294,7 +372,7 @@ namespace ams::boot { reg::Write(g_dsi_regs + sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC); WaitDsiHostControl(); - svcSleepThread(5'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); /* Parse LCD vendor. */ { @@ -318,62 +396,77 @@ namespace ams::boot { /* LCD vendor specific configuration. */ switch (g_lcd_vendor) { - case 0xF30: /* AUO first revision screens. */ - reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(180'000'000ul); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(5'000'000ul); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x739); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x711148B1); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x143209); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(5'000'000ul); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + case 0x10: /* Japan Display Inc screens. */ + DO_SLEEP_OR_REGISTER_WRITES(g_dsi_regs, DisplayConfigJdiSpecificInit01); break; case 0xF20: /* Innolux first revision screens. */ reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105); reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(180'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(180)); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9); reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(5'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x739); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x751548B1); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x143209); reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(5'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905); reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); break; - case 0x10: /* Japan Display Inc screens. */ - DO_DSI_SLEEP_OR_REGISTER_WRITES(DisplayConfigJdiSpecificInit01); + case 0xF30: /* AUO first revision screens. */ + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + os::SleepThread(TimeSpan::FromMilliSeconds(180)); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x739); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x711148B1); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x143209); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); break; + case 0x2050: /* Unknown (hardware type 5) screen. */ + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + os::SleepThread(TimeSpan::FromMilliSeconds(180)); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0xA015); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x205315); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x339); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x51); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + break; + case 0x1020: /* Innolux second revision screen. */ + case 0x1030: /* AUO second revision screen. */ + case 0x1040: /* Unknown second revision screen. */ default: - /* Innolux and AUO second revision screens. */ - if ((g_lcd_vendor | 0x10) == 0x1030) { - reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(120'000'000ul); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905); - reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - } + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1105); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + os::SleepThread(TimeSpan::FromMilliSeconds(120)); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x2905); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); break; } - svcSleepThread(20'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(20)); DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld02); DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init08); DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming); - DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init09); + DO_SLEEP_OR_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init09); reg::Write(g_disp1_regs + sizeof(u32) * DC_DISP_DISP_CLOCK_CONTROL, SHIFT_CLK_DIVIDER(4)); DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Init10); - svcSleepThread(10'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(10)); /* Configure MIPI CAL. */ DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal01); @@ -388,12 +481,14 @@ namespace ams::boot { DO_SOC_DEPENDENT_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal03); DO_REGISTER_WRITES(g_mipi_cal_regs, DisplayConfigMipiCal04); } - svcSleepThread(10'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(10)); /* Write DISP1, FrameBuffer config. */ - DO_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc02); - DO_REGISTER_WRITES(g_disp1_regs, DisplayConfigFrameBuffer); - svcSleepThread(35'000'000ul); + DO_SLEEP_OR_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc02); + DO_SLEEP_OR_REGISTER_WRITES(g_disp1_regs, DisplayConfigFrameBuffer); + if (g_lcd_vendor != 0x2050) { + os::SleepThread(TimeSpan::FromMilliSeconds(35)); + } g_is_display_intialized = true; } @@ -411,10 +506,14 @@ namespace ams::boot { } } } - armDCacheFlush(g_frame_buffer, FrameBufferSize); + dd::FlushDataCache(g_frame_buffer, FrameBufferSize); /* Enable backlight. */ - reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x1); + if (g_lcd_vendor == 0x2050) { + EnableBacklightForVendor2050ForHardwareTypeFive(g_display_brightness); + } else { + EnableBacklightForGeneric(g_display_brightness); + } } void FinalizeDisplay() { @@ -423,14 +522,19 @@ namespace ams::boot { } /* Disable backlight. */ - reg::ClearBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x1); + if (g_lcd_vendor == 0x2050) { + EnableBacklightForVendor2050ForHardwareTypeFive(0); + } else { + pwm::driver::SetEnabled(g_lcd_backlight_session, true); + pwm::driver::CloseSession(g_lcd_backlight_session); + } reg::Write(g_disp1_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 1); reg::Write(g_disp1_regs + sizeof(u32) * DSI_WR_DATA, 0x2805); /* Nintendo waits 5 frames before continuing. */ { - const uintptr_t host1x_vaddr = dd::GetIoMapping(0x500030a4, 4); + const uintptr_t host1x_vaddr = dd::GetIoMapping(0x500030A4, 4); const u32 start_val = reg::Read(host1x_vaddr); while (reg::Read(host1x_vaddr) < start_val + 5) { /* spinlock here. */ @@ -440,77 +544,100 @@ namespace ams::boot { reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_STATE_ACCESS, (READ_MUX | WRITE_MUX)); reg::Write(g_disp1_regs + sizeof(u32) * DSI_VIDEO_MODE_CONTROL, 0); + DO_REGISTER_WRITES(g_disp1_regs, DisplayConfigDc01Fini01); + os::SleepThread(TimeSpan::FromMilliSeconds(40)); DO_SOC_DEPENDENT_REGISTER_WRITES(g_clk_rst_regs, DisplayConfigPlld01); DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Fini01); DO_SOC_DEPENDENT_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsiPhyTiming); DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigDsi01Fini02); + if (g_lcd_vendor != 0x2050) { + os::SleepThread(TimeSpan::FromMilliSeconds(10)); + } + svcSleepThread(10'000'000ul); /* Vendor specific shutdown. */ switch (g_lcd_vendor) { case 0x10: /* Japan Display Inc screens. */ - DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigJdiSpecificFini01); + DO_SLEEP_OR_REGISTER_WRITES(g_dsi_regs, DisplayConfigJdiSpecificFini01); break; case 0xF30: /* AUO first revision screens. */ - DO_REGISTER_WRITES(g_dsi_regs, DisplayConfigAuoRev1SpecificFini01); - svcSleepThread(5'000'000ul); + DO_SLEEP_OR_REGISTER_WRITES(g_dsi_regs, DisplayConfigAuoRev1SpecificFini01); break; case 0x1020: /* Innolux second revision screens. */ reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9); reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(5'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0xB39); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x751548B1); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x71143209); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x115631); reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(5'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); break; case 0x1030: /* AUO second revision screens. */ reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9); reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(5'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0xB39); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x711148B1); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x71143209); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x114D31); reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(5'000'000ul); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); + break; + case 0x1040: /* Unknown second revision screens. */ + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x439); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x9483FFB9); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0xB39); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x731348B1); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x71243209); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x4C31); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); + os::SleepThread(TimeSpan::FromMilliSeconds(5)); break; default: break; } - svcSleepThread(5'000'000ul); reg::Write(g_dsi_regs + sizeof(u32) * DSI_WR_DATA, 0x1005); reg::Write(g_dsi_regs + sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST); - svcSleepThread(50'000'000ul); + os::SleepThread(g_lcd_vendor == 0x2050 ? TimeSpan::FromMilliSeconds(120) : TimeSpan::FromMilliSeconds(50)); /* Disable backlight RST/Voltage. */ reg::ClearBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x4); - svcSleepThread(10'000'000ul); - reg::ClearBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x2); - svcSleepThread(10'000'000ul); - reg::ClearBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x1); - svcSleepThread(10'000'000ul); + if (g_lcd_vendor == 0x2050) { + os::SleepThread(TimeSpan::FromMilliSeconds(30)); + } else { + os::SleepThread(TimeSpan::FromMilliSeconds(10)); + reg::ClearBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x2); + os::SleepThread(TimeSpan::FromMilliSeconds(10)); + reg::ClearBits(g_gpio_regs + GPIO_PORT3_OUT_0, 0x1); + os::SleepThread(TimeSpan::FromMilliSeconds(10)); + } /* Cut clock to DSI. */ - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_H_SET, 0x1010000); - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_H_CLR, 0x1010000); - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_L_SET, 0x18000000); - reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_L_CLR, 0x18000000); + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_H_SET, CLK_RST_REG_BITS_ENUM(RST_DEV_H_SET_SET_MIPI_CAL_RST, ENABLE), + CLK_RST_REG_BITS_ENUM(RST_DEV_H_SET_SET_DSI_RST, ENABLE)); + + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_H_CLR, CLK_RST_REG_BITS_ENUM(CLK_ENB_H_CLR_CLR_CLK_ENB_MIPI_CAL, ENABLE), + CLK_RST_REG_BITS_ENUM(CLK_ENB_H_CLR_CLR_CLK_ENB_DSI, ENABLE)); + + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_RST_DEV_L_SET, CLK_RST_REG_BITS_ENUM(RST_DEV_L_SET_SET_HOST1X_RST, ENABLE), + CLK_RST_REG_BITS_ENUM(RST_DEV_L_SET_SET_DISP1_RST, ENABLE)); + + reg::Write(g_clk_rst_regs + CLK_RST_CONTROLLER_CLK_ENB_L_CLR, CLK_RST_REG_BITS_ENUM(CLK_ENB_L_CLR_CLR_CLK_ENB_HOST1X, ENABLE), + CLK_RST_REG_BITS_ENUM(CLK_ENB_L_CLR_CLR_CLK_ENB_DISP1, ENABLE)); + reg::Write(g_dsi_regs + sizeof(u32) * DSI_PAD_CONTROL_0, (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF))); reg::Write(g_dsi_regs + sizeof(u32) * DSI_POWER_CONTROL, 0); - /* Final LCD config for PWM */ - reg::ClearBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x1); - reg::SetBits(g_apb_misc_regs + PINMUX_AUX_LCD_BL_PWM, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE))); - reg::ReadWrite(g_apb_misc_regs + PINMUX_AUX_LCD_BL_PWM, 1, 0x3); - /* Unmap framebuffer from DC virtual address space. */ FinalizeFrameBuffer(); g_is_display_intialized = false; diff --git a/stratosphere/boot/source/boot_display_config.inc b/stratosphere/boot/source/boot_display_config.inc index 246b8eea8..21377b97c 100644 --- a/stratosphere/boot/source/boot_display_config.inc +++ b/stratosphere/boot/source/boot_display_config.inc @@ -19,135 +19,135 @@ struct RegisterWrite { u32 value; }; -enum DsiSleepOrRegisterWriteKind : u16 { - DsiSleepOrRegisterWriteKind_Write = 0, - DsiSleepOrRegisterWriteKind_Sleep = 1, +enum SleepOrRegisterWriteKind : u16 { + SleepOrRegisterWriteKind_Write = 0, + SleepOrRegisterWriteKind_Sleep = 1, }; -struct DsiSleepOrRegisterWrite { - DsiSleepOrRegisterWriteKind kind; +struct SleepOrRegisterWrite { + SleepOrRegisterWriteKind kind; u16 offset; u32 value; }; -constexpr RegisterWrite DisplayConfigPlld01Erista[] = { +constexpr const RegisterWrite DisplayConfigPlld01Erista[] = { {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000}, {CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001}, {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020}, {CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA}, }; -constexpr RegisterWrite DisplayConfigPlld01Mariko[] = { +constexpr const RegisterWrite DisplayConfigPlld01Mariko[] = { {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000}, {CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001}, {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000}, {CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00}, }; -constexpr RegisterWrite DisplayConfigDc01[] = { - {sizeof(u32) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(u32) * DC_CMD_REG_ACT_CONTROL, 0x54}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_DISP_DC_MCCIF_FIFOCTRL, 0}, - {sizeof(u32) * DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, - {sizeof(u32) * DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, - {sizeof(u32) * DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, - {sizeof(u32) * DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {sizeof(u32) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_WIN_DV_CONTROL, 0}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, +constexpr const SleepOrRegisterWrite DisplayConfigDc01[] = { + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_ACCESS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {SleepOrRegisterWriteKind_Write, DC_CMD_REG_ACT_CONTROL, 0x54}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DC_MCCIF_FIFOCTRL, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, + {SleepOrRegisterWriteKind_Write, DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_ACCESS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_DV_CONTROL, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, /* Setup default YUV colorspace conversion coefficients */ - {sizeof(u32) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(u32) * DC_WIN_CSC_KUR, 0}, - {sizeof(u32) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(u32) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(u32) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(u32) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(u32) * DC_WIN_CSC_KVB, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_YOF, 0xF0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KYRGB, 0x12A}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUR, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVR, 0x198}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUG, 0x39B}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVG, 0x32F}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUB, 0x204}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVB, 0}, /* End of color coefficients */ - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_WIN_DV_CONTROL, 0}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_DV_CONTROL, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, /* Setup default YUV colorspace conversion coefficients */ - {sizeof(u32) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(u32) * DC_WIN_CSC_KUR, 0}, - {sizeof(u32) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(u32) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(u32) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(u32) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(u32) * DC_WIN_CSC_KVB, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_YOF, 0xF0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KYRGB, 0x12A}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUR, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVR, 0x198}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUG, 0x39B}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVG, 0x32F}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUB, 0x204}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVB, 0}, /* End of color coefficients */ - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_WIN_DV_CONTROL, 0}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_DV_CONTROL, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, /* Setup default YUV colorspace conversion coefficients */ - {sizeof(u32) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(u32) * DC_WIN_CSC_KUR, 0}, - {sizeof(u32) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(u32) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(u32) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(u32) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(u32) * DC_WIN_CSC_KVB, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_YOF, 0xF0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KYRGB, 0x12A}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUR, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVR, 0x198}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUG, 0x39B}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVG, 0x32F}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUB, 0x204}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVB, 0}, /* End of color coefficients */ - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {sizeof(u32) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {sizeof(u32) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {sizeof(u32) * DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {sizeof(u32) * 0x4E4, 0}, - {sizeof(u32) * DC_COM_CRC_CONTROL, 0}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * 0x716, 0x10000FF}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * 0x716, 0x10000FF}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * 0x716, 0x10000FF}, - {sizeof(u32) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_COMMAND, 0}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ} + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {SleepOrRegisterWriteKind_Write, DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {SleepOrRegisterWriteKind_Write, DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {SleepOrRegisterWriteKind_Write, 0x4E4, 0}, + {SleepOrRegisterWriteKind_Write, DC_COM_CRC_CONTROL, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, 0x716, 0x10000FF}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, 0x716, 0x10000FF}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, 0x716, 0x10000FF}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_COMMAND, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ} }; -constexpr RegisterWrite DisplayConfigDsi01Init01[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init01[] = { {sizeof(u32) * DSI_WR_DATA, 0x0}, {sizeof(u32) * DSI_INT_ENABLE, 0x0}, {sizeof(u32) * DSI_INT_STATUS, 0x0}, @@ -158,15 +158,15 @@ constexpr RegisterWrite DisplayConfigDsi01Init01[] = { {sizeof(u32) * DSI_INIT_SEQ_DATA_3, 0x0}, }; -constexpr RegisterWrite DisplayConfigDsi01Init02Erista[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init02Erista[] = { {sizeof(u32) * DSI_INIT_SEQ_DATA_15, 0x0}, }; -constexpr RegisterWrite DisplayConfigDsi01Init02Mariko[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init02Mariko[] = { {sizeof(u32) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0}, }; -constexpr RegisterWrite DisplayConfigDsi01Init03[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init03[] = { {sizeof(u32) * DSI_DCS_CMDS, 0}, {sizeof(u32) * DSI_PKT_SEQ_0_LO, 0}, {sizeof(u32) * DSI_PKT_SEQ_1_LO, 0}, @@ -182,11 +182,11 @@ constexpr RegisterWrite DisplayConfigDsi01Init03[] = { {sizeof(u32) * DSI_PKT_SEQ_5_HI, 0}, }; -constexpr RegisterWrite DisplayConfigDsi01Init04Erista[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init04Erista[] = { /* No register writes. */ }; -constexpr RegisterWrite DisplayConfigDsi01Init04Mariko[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init04Mariko[] = { {sizeof(u32) * DSI_PAD_CONTROL_1, 0}, {sizeof(u32) * DSI_PAD_CONTROL_2, 0}, {sizeof(u32) * DSI_PAD_CONTROL_3, 0}, @@ -196,7 +196,7 @@ constexpr RegisterWrite DisplayConfigDsi01Init04Mariko[] = { {sizeof(u32) * DSI_PAD_CONTROL_7_MARIKO, 0}, }; -constexpr RegisterWrite DisplayConfigDsi01Init05[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init05[] = { {sizeof(u32) * DSI_PAD_CONTROL_CD, 0}, {sizeof(u32) * DSI_SOL_DELAY, 0x18}, {sizeof(u32) * DSI_MAX_THRESHOLD, 0x1E0}, @@ -209,7 +209,7 @@ constexpr RegisterWrite DisplayConfigDsi01Init05[] = { {sizeof(u32) * DSI_PAD_CONTROL_1, 0}, }; -constexpr RegisterWrite DisplayConfigDsi01Init06[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init06[] = { {sizeof(u32) * DSI_PHY_TIMING_1, 0x40A0E05}, {sizeof(u32) * DSI_PHY_TIMING_2, 0x30109}, {sizeof(u32) * DSI_BTA_TIMING, 0x190A14}, @@ -225,7 +225,7 @@ constexpr RegisterWrite DisplayConfigDsi01Init06[] = { }; -constexpr RegisterWrite DisplayConfigDsi01Init07[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init07[] = { {sizeof(u32) * DSI_PHY_TIMING_1, 0x40A0E05}, {sizeof(u32) * DSI_PHY_TIMING_2, 0x30118}, {sizeof(u32) * DSI_BTA_TIMING, 0x190A14}, @@ -242,124 +242,124 @@ constexpr RegisterWrite DisplayConfigDsi01Init07[] = { {sizeof(u32) * DSI_INIT_SEQ_CONTROL, 0} }; -constexpr RegisterWrite DisplayConfigDsiPhyTimingErista[] = { +constexpr const RegisterWrite DisplayConfigDsiPhyTimingErista[] = { {sizeof(u32) * DSI_PHY_TIMING_0, 0x6070601}, }; -constexpr RegisterWrite DisplayConfigDsiPhyTimingMariko[] = { +constexpr const RegisterWrite DisplayConfigDsiPhyTimingMariko[] = { {sizeof(u32) * DSI_PHY_TIMING_0, 0x6070603}, }; -constexpr DsiSleepOrRegisterWrite DisplayConfigJdiSpecificInit01[] = { - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x439}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x9483FFB9}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xBD15}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x1939}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAD8}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAEB}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAEBAAAA}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAAA}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAEB}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAEBAAAA}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAA}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x1BD15}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2739}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFD8}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2BD15}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xF39}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFD8}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFF}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xBD15}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x6D915}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x439}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xB9}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x1105}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {DsiSleepOrRegisterWriteKind_Sleep, 0xB4, 0}, - {DsiSleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2905}, - {DsiSleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, +constexpr const SleepOrRegisterWrite DisplayConfigJdiSpecificInit01[] = { + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x439}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x9483FFB9}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xBD15}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x1939}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAD8}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAEB}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAEBAAAA}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAAA}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAAAAAEB}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAAEBAAAA}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xAA}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x1BD15}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2739}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFD8}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2BD15}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xF39}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFD8}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xFFFFFF}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xBD15}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x6D915}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x439}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xB9}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x1105}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Sleep, 180, 0}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2905}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, }; -constexpr RegisterWrite DisplayConfigPlld02Erista[] = { +constexpr const RegisterWrite DisplayConfigPlld02Erista[] = { {CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001}, {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020}, {CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA}, }; -constexpr RegisterWrite DisplayConfigPlld02Mariko[] = { +constexpr const RegisterWrite DisplayConfigPlld02Mariko[] = { {CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001}, {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000}, {CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00}, }; -constexpr RegisterWrite DisplayConfigDsi01Init08[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init08[] = { {sizeof(u32) * DSI_PAD_CONTROL_1, 0}, }; -constexpr RegisterWrite DisplayConfigDsi01Init09[] = { - {sizeof(u32) * DSI_PHY_TIMING_1, 0x40A0E05}, - {sizeof(u32) * DSI_PHY_TIMING_2, 0x30172}, - {sizeof(u32) * DSI_BTA_TIMING, 0x190A14}, - {sizeof(u32) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, - {sizeof(u32) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, - {sizeof(u32) * DSI_TO_TALLY, 0}, - {sizeof(u32) * DSI_PKT_SEQ_0_LO, 0x40000208}, - {sizeof(u32) * DSI_PKT_SEQ_2_LO, 0x40000308}, - {sizeof(u32) * DSI_PKT_SEQ_4_LO, 0x40000308}, - {sizeof(u32) * DSI_PKT_SEQ_1_LO, 0x40000308}, - {sizeof(u32) * DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, - {sizeof(u32) * DSI_PKT_SEQ_3_HI, 0x2CC}, - {sizeof(u32) * DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, - {sizeof(u32) * DSI_PKT_SEQ_5_HI, 0x2CC}, - {sizeof(u32) * DSI_PKT_LEN_0_1, 0xCE0000}, - {sizeof(u32) * DSI_PKT_LEN_2_3, 0x87001A2}, - {sizeof(u32) * DSI_PKT_LEN_4_5, 0x190}, - {sizeof(u32) * DSI_PKT_LEN_6_7, 0x190}, - {sizeof(u32) * DSI_HOST_CONTROL, 0}, +constexpr const SleepOrRegisterWrite DisplayConfigDsi01Init09[] = { + {SleepOrRegisterWriteKind_Write, DSI_PHY_TIMING_1, 0x40A0E05}, + {SleepOrRegisterWriteKind_Write, DSI_PHY_TIMING_2, 0x30172}, + {SleepOrRegisterWriteKind_Write, DSI_BTA_TIMING, 0x190A14}, + {SleepOrRegisterWriteKind_Write, DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, + {SleepOrRegisterWriteKind_Write, DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, + {SleepOrRegisterWriteKind_Write, DSI_TO_TALLY, 0}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_SEQ_0_LO, 0x40000208}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_SEQ_2_LO, 0x40000308}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_SEQ_4_LO, 0x40000308}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_SEQ_1_LO, 0x40000308}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_SEQ_3_HI, 0x2CC}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_SEQ_5_HI, 0x2CC}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_LEN_0_1, 0xCE0000}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_LEN_2_3, 0x87001A2}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_LEN_4_5, 0x190}, + {SleepOrRegisterWriteKind_Write, DSI_PKT_LEN_6_7, 0x190}, + {SleepOrRegisterWriteKind_Write, DSI_HOST_CONTROL, 0}, }; -constexpr RegisterWrite DisplayConfigDsi01Init10[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init10[] = { {sizeof(u32) * DSI_TRIGGER, 0}, {sizeof(u32) * DSI_CONTROL, 0}, {sizeof(u32) * DSI_SOL_DELAY, 6}, {sizeof(u32) * DSI_MAX_THRESHOLD, 0x1E0}, {sizeof(u32) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, {sizeof(u32) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, {sizeof(u32) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, {sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, {sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} }; -constexpr RegisterWrite DisplayConfigDsi01Init11Erista[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init11Erista[] = { {sizeof(u32) * DSI_PAD_CONTROL_1, 0}, {sizeof(u32) * DSI_PAD_CONTROL_2, 0}, {sizeof(u32) * DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, {sizeof(u32) * DSI_PAD_CONTROL_4, 0} }; -constexpr RegisterWrite DisplayConfigDsi01Init11Mariko[] = { +constexpr const RegisterWrite DisplayConfigDsi01Init11Mariko[] = { {sizeof(u32) * DSI_PAD_CONTROL_1, 0}, {sizeof(u32) * DSI_PAD_CONTROL_2, 0}, {sizeof(u32) * DSI_PAD_CONTROL_3, 0}, @@ -369,226 +369,242 @@ constexpr RegisterWrite DisplayConfigDsi01Init11Mariko[] = { {sizeof(u32) * DSI_PAD_CONTROL_7_MARIKO, 0}, }; -constexpr RegisterWrite DisplayConfigMipiCal01[] = { - {0x60, 0}, - {0x08, 0xF3F10000}, - {0x58, 1}, - {0x60, 0}, +constexpr const RegisterWrite DisplayConfigMipiCal01[] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, + {MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG0, 1}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, }; -constexpr RegisterWrite DisplayConfigMipiCal02Erista[] = { - {0x60, 0x10010}, - {0x5C, 0x300}, +constexpr const RegisterWrite DisplayConfigMipiCal02Erista[] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0x300}, }; -constexpr RegisterWrite DisplayConfigMipiCal02Mariko[] = { - {0x60, 0x10010}, - {0x5C, 0}, +constexpr const RegisterWrite DisplayConfigMipiCal02Mariko[] = { + {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, + {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0}, }; -constexpr RegisterWrite DisplayConfigMipiCal03Erista[] = { - {0x38, 0x200200}, - {0x3C, 0x200200}, - {0x64, 0x200002}, - {0x68, 0x200002}, - {0x14, 0}, - {0x18, 0}, +constexpr const RegisterWrite DisplayConfigMipiCal03Erista[] = { + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200}, + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002}, + {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, }; -constexpr RegisterWrite DisplayConfigMipiCal03Mariko[] = { - {0x38, 0x200006}, - {0x3C, 0x200006}, - {0x64, 0x260000}, - {0x68, 0x260000}, - {0x14, 0}, - {0x18, 0}, +constexpr const RegisterWrite DisplayConfigMipiCal03Mariko[] = { + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200006}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200006}, + {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000}, + {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, }; -constexpr RegisterWrite DisplayConfigMipiCal04[] = { - {0x1C, 0}, - {0x20, 0}, - {0x24, 0}, - {0x28, 0}, - {0x40, 0}, - {0x44, 0}, - {0x68, 0}, - {0x70, 0}, - {0x74, 0}, - {0x00, 0x2A000001}, +constexpr const RegisterWrite DisplayConfigMipiCal04[] = { + {MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILD_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILE_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_CILF_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0}, + {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0}, + {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001}, }; -constexpr RegisterWrite DisplayConfigDc02[] = { - {sizeof(u32) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_WIN_DV_CONTROL, 0}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, +constexpr const SleepOrRegisterWrite DisplayConfigDc02[] = { + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_ACCESS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_DV_CONTROL, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, /* Setup default YUV colorspace conversion coefficients */ - {sizeof(u32) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(u32) * DC_WIN_CSC_KUR, 0}, - {sizeof(u32) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(u32) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(u32) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(u32) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(u32) * DC_WIN_CSC_KVB, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_YOF, 0xF0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KYRGB, 0x12A}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUR, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVR, 0x198}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUG, 0x39B}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVG, 0x32F}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUB, 0x204}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVB, 0}, /* End of color coefficients */ - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_WIN_DV_CONTROL, 0}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_DV_CONTROL, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, /* Setup default YUV colorspace conversion coefficients */ - {sizeof(u32) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(u32) * DC_WIN_CSC_KUR, 0}, - {sizeof(u32) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(u32) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(u32) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(u32) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(u32) * DC_WIN_CSC_KVB, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_YOF, 0xF0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KYRGB, 0x12A}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUR, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVR, 0x198}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUG, 0x39B}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVG, 0x32F}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUB, 0x204}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVB, 0}, /* End of color coefficients */ - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_WIN_DV_CONTROL, 0}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_DV_CONTROL, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, /* Setup default YUV colorspace conversion coefficients */ - {sizeof(u32) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(u32) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(u32) * DC_WIN_CSC_KUR, 0}, - {sizeof(u32) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(u32) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(u32) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(u32) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(u32) * DC_WIN_CSC_KVB, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_YOF, 0xF0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KYRGB, 0x12A}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUR, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVR, 0x198}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUG, 0x39B}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVG, 0x32F}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KUB, 0x204}, + {SleepOrRegisterWriteKind_Write, DC_WIN_CSC_KVB, 0}, /* End of color coefficients */ - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {sizeof(u32) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {sizeof(u32) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {sizeof(u32) * DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {sizeof(u32) * 0x4E4, 0}, - {sizeof(u32) * DC_COM_CRC_CONTROL, 0}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * 0x716, 0x10000FF}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * 0x716, 0x10000FF}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * 0x716, 0x10000FF}, - {sizeof(u32) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_COMMAND, 0}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {sizeof(u32) * DC_CMD_STATE_ACCESS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {SleepOrRegisterWriteKind_Write, DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {SleepOrRegisterWriteKind_Write, DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {SleepOrRegisterWriteKind_Write, 0x4E4, 0}, + {SleepOrRegisterWriteKind_Write, DC_COM_CRC_CONTROL, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, 0x716, 0x10000FF}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, 0x716, 0x10000FF}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, 0x716, 0x10000FF}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_COMMAND, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_ACCESS, 0}, /* Set Display timings */ - {sizeof(u32) * DC_DISP_DISP_TIMING_OPTIONS, 0}, - {sizeof(u32) * DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1. - {sizeof(u32) * DC_DISP_SYNC_WIDTH, 0x10048}, - {sizeof(u32) * DC_DISP_BACK_PORCH, 0x90048}, - {sizeof(u32) * DC_DISP_ACTIVE, 0x50002D0}, - {sizeof(u32) * DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd. + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_TIMING_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1. + {SleepOrRegisterWriteKind_Write, DC_DISP_SYNC_WIDTH, 0x10048}, + {SleepOrRegisterWriteKind_Write, DC_DISP_BACK_PORCH, 0x90048}, + {SleepOrRegisterWriteKind_Write, DC_DISP_ACTIVE, 0x50002D0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd. /* End of Display timings */ - {sizeof(u32) * DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, - {sizeof(u32) * DC_COM_PIN_OUTPUT_ENABLE(1), 0}, - {sizeof(u32) * DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, - {sizeof(u32) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {sizeof(u32) * DC_DISP_DISP_CLOCK_CONTROL, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(u32) * DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, - {sizeof(u32) * DC_DISP_FRONT_PORCH, 0xA0088}, - {sizeof(u32) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(u32) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {sizeof(u32) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(u32) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(u32) * DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, - {sizeof(u32) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {sizeof(u32) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0} + {SleepOrRegisterWriteKind_Write, DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, + {SleepOrRegisterWriteKind_Write, DC_COM_PIN_OUTPUT_ENABLE(1), 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_CLOCK_CONTROL, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, + {SleepOrRegisterWriteKind_Write, DC_DISP_FRONT_PORCH, 0xA0088}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_ACCESS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {SleepOrRegisterWriteKind_Write, DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {SleepOrRegisterWriteKind_Write, DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_ACCESS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_COMMAND_OPTION0, 0} }; constexpr u32 DisplayConfigFrameBufferAddress = 0xC0000000; -constexpr RegisterWrite DisplayConfigFrameBuffer[] = { - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {sizeof(u32) * DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_WIN_POSITION, 0}, //(0,0) - {sizeof(u32) * DC_WIN_H_INITIAL_DDA, 0}, - {sizeof(u32) * DC_WIN_V_INITIAL_DDA, 0}, - {sizeof(u32) * DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. - {sizeof(u32) * DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, - {sizeof(u32) * DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. - {sizeof(u32) * DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. - {sizeof(u32) * DC_WIN_BUFFER_CONTROL, 0}, - {sizeof(u32) * DC_WINBUF_SURFACE_KIND, 0}, //Regular surface. - {sizeof(u32) * DC_WINBUF_START_ADDR, DisplayConfigFrameBufferAddress}, //Framebuffer address. - {sizeof(u32) * DC_WINBUF_ADDR_H_OFFSET, 0}, - {sizeof(u32) * DC_WINBUF_ADDR_V_OFFSET, 0}, - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {sizeof(u32) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(u32) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE - {sizeof(u32) * DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD. - {sizeof(u32) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display. - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update. - {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request. +constexpr const SleepOrRegisterWrite DisplayConfigFrameBuffer[] = { + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {SleepOrRegisterWriteKind_Write, DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_POSITION, 0}, //(0,0) + {SleepOrRegisterWriteKind_Write, DC_WIN_H_INITIAL_DDA, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_V_INITIAL_DDA, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. + {SleepOrRegisterWriteKind_Write, DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, + {SleepOrRegisterWriteKind_Write, DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. + {SleepOrRegisterWriteKind_Write, DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {SleepOrRegisterWriteKind_Write, DC_WIN_BUFFER_CONTROL, 0}, + {SleepOrRegisterWriteKind_Write, DC_WINBUF_SURFACE_KIND, 0}, //Regular surface. + {SleepOrRegisterWriteKind_Write, DC_WINBUF_START_ADDR, DisplayConfigFrameBufferAddress}, //Framebuffer address. + {SleepOrRegisterWriteKind_Write, DC_WINBUF_ADDR_H_OFFSET, 0}, + {SleepOrRegisterWriteKind_Write, DC_WINBUF_ADDR_V_OFFSET, 0}, + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, 0}, + {SleepOrRegisterWriteKind_Write, DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {SleepOrRegisterWriteKind_Write, DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD. + {SleepOrRegisterWriteKind_Write, DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display. + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update. + {SleepOrRegisterWriteKind_Write, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request. }; -constexpr RegisterWrite DisplayConfigDsi01Fini01[] = { +constexpr const RegisterWrite DisplayConfigDc01Fini01[] = { + {sizeof(u32) * DC_DISP_FRONT_PORCH, 0xA0088}, + {sizeof(u32) * DC_CMD_INT_MASK, 0}, + {sizeof(u32) * DC_CMD_STATE_ACCESS, 0}, + {sizeof(u32) * DC_CMD_INT_ENABLE, 0}, + {sizeof(u32) * DC_CMD_CONT_SYNCPT_VSYNC, 0}, + {sizeof(u32) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP}, + {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(u32) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {sizeof(u32) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {sizeof(u32) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, +}; + +constexpr const RegisterWrite DisplayConfigDsi01Fini01[] = { {sizeof(u32) * DSI_POWER_CONTROL, 0}, {sizeof(u32) * DSI_PAD_CONTROL_1, 0}, }; -constexpr RegisterWrite DisplayConfigDsi01Fini02[] = { +constexpr const RegisterWrite DisplayConfigDsi01Fini02[] = { {sizeof(u32) * DSI_PHY_TIMING_1, 0x40A0E05}, - {sizeof(u32) * DSI_PHY_TIMING_2, 0x30109}, + {sizeof(u32) * DSI_PHY_TIMING_2, 0x30118}, {sizeof(u32) * DSI_BTA_TIMING, 0x190A14}, {sizeof(u32) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, - {sizeof(u32) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {sizeof(u32) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, {sizeof(u32) * DSI_TO_TALLY, 0}, {sizeof(u32) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, {sizeof(u32) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, @@ -599,67 +615,68 @@ constexpr RegisterWrite DisplayConfigDsi01Fini02[] = { {sizeof(u32) * DSI_INIT_SEQ_CONTROL, 0} }; -constexpr RegisterWrite DisplayConfigJdiSpecificFini01[] = { - {sizeof(u32) * DSI_WR_DATA, 0x439}, - {sizeof(u32) * DSI_WR_DATA, 0x9483FFB9}, - {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST}, - {sizeof(u32) * DSI_WR_DATA, 0x2139}, - {sizeof(u32) * DSI_WR_DATA, 0x191919D5}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19}, - {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST}, - {sizeof(u32) * DSI_WR_DATA, 0xB39}, - {sizeof(u32) * DSI_WR_DATA, 0x4F0F41B1}, - {sizeof(u32) * DSI_WR_DATA, 0xF179A433}, - {sizeof(u32) * DSI_WR_DATA, 0x2D81}, - {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST}, - {sizeof(u32) * DSI_WR_DATA, 0x439}, - {sizeof(u32) * DSI_WR_DATA, 0xB9}, - {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST}, +constexpr const SleepOrRegisterWrite DisplayConfigJdiSpecificFini01[] = { + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x439}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x9483FFB9}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2139}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x191919D5}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xB39}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x4F0F41B1}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xF179A433}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2D81}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x439}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xB9}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, }; -constexpr RegisterWrite DisplayConfigAuoRev1SpecificFini01[] = { - {sizeof(u32) * DSI_WR_DATA, 0x439}, - {sizeof(u32) * DSI_WR_DATA, 0x9483FFB9}, - {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST}, - {sizeof(u32) * DSI_WR_DATA, 0x2C39}, - {sizeof(u32) * DSI_WR_DATA, 0x191919D5}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST}, - {sizeof(u32) * DSI_WR_DATA, 0x2C39}, - {sizeof(u32) * DSI_WR_DATA, 0x191919D6}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_WR_DATA, 0x19191919}, - {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST}, - {sizeof(u32) * DSI_WR_DATA, 0xB39}, - {sizeof(u32) * DSI_WR_DATA, 0x711148B1}, - {sizeof(u32) * DSI_WR_DATA, 0x71143209}, - {sizeof(u32) * DSI_WR_DATA, 0x114D31}, - {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST}, - {sizeof(u32) * DSI_WR_DATA, 0x439}, - {sizeof(u32) * DSI_WR_DATA, 0xB9}, - {sizeof(u32) * DSI_TRIGGER, DSI_TRIGGER_HOST}, +constexpr const SleepOrRegisterWrite DisplayConfigAuoRev1SpecificFini01[] = { + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x439}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x9483FFB9}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2C39}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x191919D5}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x2C39}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x191919D6}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x19191919}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xB39}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x711148B1}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x71143209}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x114D31}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0x439}, + {SleepOrRegisterWriteKind_Write, DSI_WR_DATA, 0xB9}, + {SleepOrRegisterWriteKind_Write, DSI_TRIGGER, DSI_TRIGGER_HOST}, + {SleepOrRegisterWriteKind_Sleep, 5, 0}, }; diff --git a/stratosphere/boot/source/boot_registers_di.hpp b/stratosphere/boot/source/boot_registers_di.hpp index 2cd55fa74..d49001a31 100644 --- a/stratosphere/boot/source/boot_registers_di.hpp +++ b/stratosphere/boot/source/boot_registers_di.hpp @@ -44,6 +44,7 @@ #define PM0_ENABLE (1 << 16) #define PM1_ENABLE (1 << 18) +#define DC_CMD_INT_STATUS 0x37 #define DC_CMD_INT_MASK 0x38 #define DC_CMD_INT_ENABLE 0x39 @@ -241,6 +242,8 @@ /*! Display serial interface registers. */ #define _DSIREG(reg) ((reg) * 4) +#define DSI_INCR_SYNCPT_CNTRL 0x1 + #define DSI_RD_DATA 0x9 #define DSI_WR_DATA 0xA @@ -346,5 +349,4 @@ #define DSI_PAD_CONTROL_7_MARIKO 0x55 #define DSI_INIT_SEQ_DATA_15 0x5F -#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60 #define DSI_INIT_SEQ_DATA_15_MARIKO 0x62