mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 04:11:18 +00:00
sept: add secondary skeleton + buildscript
This commit is contained in:
Michael Scire
parent
26f45fab19
commit
5fe24b620d
94 changed files with 58543 additions and 5 deletions
5
.gitignore
vendored
5
.gitignore
vendored
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@ -73,10 +73,15 @@ dkms.conf
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*.nam
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*.til
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# KEYS file for sept-secondary.
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*.pyc
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sept/sept-secondary/KEYS.py
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.**/
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# NOTE: make sure to make exceptions to this pattern when needed!
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*.bin
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*.enc
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**/out
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**/build
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@ -88,7 +88,7 @@ export VPATH := $(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
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$(foreach dir,$(DATA),$(CURDIR)/$(dir)) \
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$(AMS)/exosphere $(AMS)/exosphere/lp0fw $(AMS)/exosphere/rebootstub \
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$(AMS)/thermosphere $(AMS)/fusee/fusee-primary $(AMS)/sept/sept-primary \
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$(KIPDIRS)
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$(AMS)/sept/sept-secondary $(KIPDIRS)
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export DEPSDIR := $(CURDIR)/$(BUILD)
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@ -98,7 +98,7 @@ SFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
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KIPFILES := loader.kip pm.kip sm.kip ams_mitm.kip boot_100.kip boot_200.kip
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BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) fusee-primary.bin \
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exosphere.bin lp0fw.bin rebootstub.bin thermosphere.bin splash_screen.bmp \
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sept-primary.bin \
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sept-primary.bin sept-secondary.enc \
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$(KIPFILES)
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#---------------------------------------------------------------------------------
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@ -198,6 +198,11 @@ sept_primary.bin.o sept_primary_bin.h: sept-primary.bin
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@echo $(notdir $<)
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@$(_bin2o)
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sept_secondary.enc.o sept_secondary_enc.h: sept-secondary.enc
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#---------------------------------------------------------------------------------
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@echo $(notdir $<)
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@$(_bin2o)
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%.bin.o %_bin.h: %.bin
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#---------------------------------------------------------------------------------
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@echo $(notdir $<)
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@ -50,6 +50,7 @@
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#define u8 uint8_t
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#define u32 uint32_t
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#include "exosphere_bin.h"
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#include "sept_secondary_enc.h"
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#include "lp0fw_bin.h"
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#include "lib/log.h"
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#undef u8
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@ -413,8 +414,7 @@ uint32_t nxboot_main(void) {
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if (target_firmware == ATMOSPHERE_TARGET_FIRMWARE_700) {
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/* TODO: Detect when we have been loaded by sept-secondary, and thus have keys provided for us. */
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static const uint8_t sept_secondary[0x0] = { /* TODO: link-time magic */ };
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reboot_to_sept(tsec_fw, tsec_fw_size, sept_secondary, sizeof(sept_secondary));
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reboot_to_sept(tsec_fw, tsec_fw_size, sept_secondary_enc, sept_secondary_enc_size);
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}
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print(SCREEN_LOG_LEVEL_MANDATORY, "[NXBOOT]: Loaded firmware from eMMC...\n");
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@ -1,4 +1,4 @@
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SUBFOLDERS := sept-primary
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SUBFOLDERS := sept-primary sept-secondary
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TOPTARGETS := all clean
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173
sept/sept-secondary/Makefile
Normal file
173
sept/sept-secondary/Makefile
Normal file
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@ -0,0 +1,173 @@
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#---------------------------------------------------------------------------------
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.SUFFIXES:
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#---------------------------------------------------------------------------------
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ifeq ($(strip $(DEVKITARM)),)
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$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
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endif
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TOPDIR ?= $(CURDIR)
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AMS := $(TOPDIR)/../../
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include $(DEVKITARM)/base_rules
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AMSBRANCH := $(shell git symbolic-ref --short HEAD)
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AMSREV := $(AMSBRANCH)-$(shell git rev-parse --short HEAD)
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ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
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AMSREV := $(AMSREV)-dirty
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endif
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#---------------------------------------------------------------------------------
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# TARGET is the name of the output
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# BUILD is the directory where object files & intermediate files will be placed
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# SOURCES is a list of directories containing source code
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# DATA is a list of directories containing data files
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# INCLUDES is a list of directories containing header files
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#---------------------------------------------------------------------------------
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TARGET := $(notdir $(CURDIR))
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BUILD := build
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SOURCES := src src/sdmmc src/lib src/lib/fatfs src/display
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DATA := data
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INCLUDES := include ../../common/include
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#---------------------------------------------------------------------------------
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# options for code generation
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#---------------------------------------------------------------------------------
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ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
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DEFINES := -D__BPMP__ -DFUSEE_STAGE1_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"
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CFLAGS := \
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-g \
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-O2 \
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-fomit-frame-pointer \
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-ffunction-sections \
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-fdata-sections \
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-std=gnu11 \
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-Werror \
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-Wall \
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-fstrict-volatile-bitfields \
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$(ARCH) $(DEFINES)
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CFLAGS += $(INCLUDE)
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CXXFLAGS := $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
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ASFLAGS := -g $(ARCH)
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LDFLAGS = -specs=$(TOPDIR)/linker.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
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LIBS :=
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#---------------------------------------------------------------------------------
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# list of directories containing libraries, this must be the top level containing
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# include and lib
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#---------------------------------------------------------------------------------
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LIBDIRS :=
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#---------------------------------------------------------------------------------
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# no real need to edit anything past this point unless you need to add additional
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# rules for different file extensions
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#---------------------------------------------------------------------------------
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ifneq ($(BUILD),$(notdir $(CURDIR)))
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#---------------------------------------------------------------------------------
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export OUTPUT := $(CURDIR)/$(TARGET)
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export TOPDIR := $(CURDIR)
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export VPATH := $(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
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$(foreach dir,$(DATA),$(CURDIR)/$(dir)) \
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$(AMS)/exosphere/rebootstub
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export DEPSDIR := $(CURDIR)/$(BUILD)
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CFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
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CPPFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
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SFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
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BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) rebootstub.bin
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#---------------------------------------------------------------------------------
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# use CXX for linking C++ projects, CC for standard C
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#---------------------------------------------------------------------------------
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ifeq ($(strip $(CPPFILES)),)
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#---------------------------------------------------------------------------------
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export LD := $(CC)
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#---------------------------------------------------------------------------------
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else
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#---------------------------------------------------------------------------------
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export LD := $(CXX)
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#---------------------------------------------------------------------------------
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endif
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#---------------------------------------------------------------------------------
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export OFILES_BIN := $(addsuffix .o,$(BINFILES))
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export OFILES_SRC := $(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
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export OFILES := $(OFILES_BIN) $(OFILES_SRC)
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export HFILES_BIN := $(addsuffix .h,$(subst .,_,$(BINFILES)))
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export INCLUDE := $(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
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$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
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-I$(CURDIR)/$(BUILD)
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export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib)
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.PHONY: $(BUILD) clean all check_rebootstub
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#---------------------------------------------------------------------------------
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all: check_rebootstub $(BUILD)
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check_rebootstub:
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@$(MAKE) -C $(AMS)/exosphere/rebootstub all
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$(BUILD):
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@[ -d $@ ] || mkdir -p $@
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@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
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#---------------------------------------------------------------------------------
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clean:
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@echo clean ...
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@$(MAKE) -C $(AMS)/exosphere/rebootstub clean
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@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
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#---------------------------------------------------------------------------------
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else
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.PHONY: all
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DEPENDS := $(OFILES:.o=.d)
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#---------------------------------------------------------------------------------
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# main targets
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#---------------------------------------------------------------------------------
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all : $(OUTPUT).enc
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$(OUTPUT).enc : $(OUTPUT).bin
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@python $(TOPDIR)/sept_sign.py $< $@
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@echo built ... $(notdir $@)
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$(OUTPUT).bin : $(OUTPUT).elf
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$(OBJCOPY) -S -O binary $< $@
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@echo built ... $(notdir $@)
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$(OUTPUT).elf : $(OFILES)
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%.elf: $(OFILES)
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@echo linking $(notdir $@)
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@$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
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@$(NM) -CSn $@ > $(notdir $*.lst)
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$(OFILES_SRC) : $(HFILES_BIN)
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#---------------------------------------------------------------------------------
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# you need a rule like this for each extension you use as binary data
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#---------------------------------------------------------------------------------
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%.bin.o %_bin.h: %.bin
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#---------------------------------------------------------------------------------
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@echo $(notdir $<)
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@$(bin2o)
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-include $(DEPENDS)
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#---------------------------------------------------------------------------------------
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endif
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#---------------------------------------------------------------------------------------
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192
sept/sept-secondary/linker.ld
Normal file
192
sept/sept-secondary/linker.ld
Normal file
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@ -0,0 +1,192 @@
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OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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PHDRS
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{
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crt0 PT_LOAD;
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chainloader PT_LOAD;
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main PT_LOAD;
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}
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/* Mostly copied from https://github.com/devkitPro/buildscripts/blob/master/dkarm-eabi/crtls/3dsx.ld */
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MEMORY
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{
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NULL : ORIGIN = 0x00000000, LENGTH = 0x1000
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main : ORIGIN = 0x40010000, LENGTH = 0x20000
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low_iram : ORIGIN = 0x40003000, LENGTH = 0x8000
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}
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SECTIONS
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{
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PROVIDE(__start__ = 0x40010000);
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PROVIDE(__stack_top__ = 0x40010000);
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PROVIDE(__stack_bottom__ = 0x4000C000);
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PROVIDE(__heap_start__ = 0);
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PROVIDE(__heap_end__ = 0);
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. = __start__;
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.crt0 :
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{
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KEEP( *(.text.start) )
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KEEP( *(.init) )
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. = ALIGN(32);
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} >main :crt0
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.chainloader_loadable :
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{
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. = ALIGN(32);
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PROVIDE (__chainloader_start__ = ABSOLUTE(.));
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PROVIDE (__chainloader_lma__ = LOADADDR(.chainloader_loadable));
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KEEP(*(.chainloader.text.start))
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chainloader.o(.text*)
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chainloader.o(.rodata*)
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chainloader.o(.data*)
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. = ALIGN(32);
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} >low_iram AT>main :chainloader
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.chainloader_bss (NOLOAD) :
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{
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. = ALIGN(32);
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PROVIDE (__chainloader_bss_start__ = ABSOLUTE(.));
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chainloader.o(.bss* COMMON)
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. = ALIGN(32);
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PROVIDE (__chainloader_end__ = ABSOLUTE(.));
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} >low_iram :NONE
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.text :
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{
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. = ALIGN(32);
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/* .text */
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*(.text)
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*(.text.*)
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*(.glue_7)
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*(.glue_7t)
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*(.stub)
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*(.gnu.warning)
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*(.gnu.linkonce.t*)
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/* .fini */
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KEEP( *(.fini) )
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. = ALIGN(8);
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} >main :main
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.rodata :
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{
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*(.rodata)
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*(.roda)
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*(.rodata.*)
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*all.rodata*(*)
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*(.gnu.linkonce.r*)
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SORT(CONSTRUCTORS)
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. = ALIGN(8);
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} >main
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.preinit_array :
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{
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PROVIDE (__preinit_array_start = .);
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KEEP (*(.preinit_array))
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PROVIDE (__preinit_array_end = .);
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} >main
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.init_array ALIGN(4) :
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{
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PROVIDE (__init_array_start = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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PROVIDE (__init_array_end = .);
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} >main
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.fini_array ALIGN(4) :
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{
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PROVIDE (__fini_array_start = .);
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KEEP (*(.fini_array))
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KEEP (*(SORT(.fini_array.*)))
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PROVIDE (__fini_array_end = .);
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} >main
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.ctors ALIGN(4) :
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{
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KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >main
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|
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.dtors ALIGN(4) :
|
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{
|
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KEEP (*crtbegin.o(.dtors))
|
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
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KEEP (*(SORT(.dtors.*)))
|
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KEEP (*(.dtors))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >main
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.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) __exidx_start = ABSOLUTE(.);} >main
|
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ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) __exidx_end = ABSOLUTE(.);} >main
|
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|
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.data :
|
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{
|
||||
*(.data)
|
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*(.data.*)
|
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*(.gnu.linkonce.d*)
|
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CONSTRUCTORS
|
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. = ALIGN(32);
|
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} >main
|
||||
|
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.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
PROVIDE (__bss_start__ = ABSOLUTE(.));
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b*)
|
||||
*(COMMON)
|
||||
. = ALIGN(32);
|
||||
PROVIDE (__bss_end__ = ABSOLUTE(.));
|
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} >main :NONE
|
||||
__end__ = ABSOLUTE(.) ;
|
||||
|
||||
/* ==================
|
||||
==== Metadata ====
|
||||
================== */
|
||||
|
||||
/* Discard sections that difficult post-processing */
|
||||
/DISCARD/ : { *(.group .comment .note) }
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
}
|
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7
sept/sept-secondary/linker.specs
Normal file
7
sept/sept-secondary/linker.specs
Normal file
|
|
@ -0,0 +1,7 @@
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%rename link old_link
|
||||
|
||||
*link:
|
||||
%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections
|
||||
|
||||
*startfile:
|
||||
crti%O%s crtbegin%O%s
|
||||
38
sept/sept-secondary/sept_sign.py
Normal file
38
sept/sept-secondary/sept_sign.py
Normal file
|
|
@ -0,0 +1,38 @@
|
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#!/usr/bin/env python
|
||||
import sys
|
||||
from struct import pack as pk, unpack as up
|
||||
from Crypto.Cipher import AES
|
||||
from Crypto.Hash import CMAC
|
||||
import KEYS
|
||||
|
||||
def sign_encrypt_code(code, sig_key, enc_key, iv):
|
||||
# Pad with 0x20 of zeroes.
|
||||
code += '\x00' * 0x20
|
||||
code_len = len(code)
|
||||
code_len += 0xFFF
|
||||
code_len &= ~0xFFF
|
||||
code += '\x00' * (code_len - len(code))
|
||||
|
||||
# Add empty trustzone, warmboot segments.
|
||||
code += '\x00'*0x1FE0
|
||||
pk11_hdr = 'PK11' + pk('<IIIIIII', 0x1000, 0, 0, code_len - 0x20, 0, 0x1000, 0)
|
||||
pk11 = pk11_hdr + code
|
||||
enc_pk11 = AES.new(enc_key, AES.MODE_CBC, iv).encrypt(pk11)
|
||||
enc_pk11 = pk('<IIII', len(pk11), 0, 0, 0) + iv + enc_pk11
|
||||
enc_pk11 += CMAC.new(sig_key, enc_pk11, AES).digest()
|
||||
return enc_pk11
|
||||
|
||||
def main(argc, argv):
|
||||
if argc != 3:
|
||||
print('Usage: %s input output' % argv[0])
|
||||
return 1
|
||||
with open(argv[1], 'rb') as f:
|
||||
code = f.read()
|
||||
assert (len(code) & 0xF) == 0
|
||||
# TODO: Support dev unit crypto
|
||||
with open(argv[2], 'wb') as f:
|
||||
f.write(sign_encrypt_code(code, KEYS.HOVI_SIG_KEY_PRD, KEYS.HOVI_ENC_KEY_PRD, KEYS.IV))
|
||||
return 0
|
||||
|
||||
if __name__ == '__main__':
|
||||
sys.exit(main(len(sys.argv), sys.argv))
|
||||
81
sept/sept-secondary/src/apb_misc.h
Normal file
81
sept/sept-secondary/src/apb_misc.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_APB_MISC_H
|
||||
#define FUSEE_APB_MISC_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define APB_MISC_BASE 0x70000000
|
||||
#define APB_PADCTL_BASE 0x70000810
|
||||
#define MAKE_APB_MISC_REG(n) MAKE_REG32(APB_MISC_BASE + n)
|
||||
#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n)
|
||||
|
||||
#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40)
|
||||
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64)
|
||||
#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68)
|
||||
|
||||
#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
|
||||
#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
|
||||
#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
|
||||
#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
|
||||
|
||||
#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
|
||||
#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
|
||||
|
||||
#define PADCTL_SDMMC1_DEEP_LOOPBACK (1 << 0)
|
||||
#define PADCTL_SDMMC3_DEEP_LOOPBACK (1 << 0)
|
||||
#define PADCTL_SDMMC2_ENABLE_DATA_IN (0xFF << 8)
|
||||
#define PADCTL_SDMMC2_ENABLE_CLK_IN (0x3 << 4)
|
||||
#define PADCTL_SDMMC2_DEEP_LOOPBACK (1 << 0)
|
||||
#define PADCTL_SDMMC4_ENABLE_DATA_IN (0xFF << 8)
|
||||
#define PADCTL_SDMMC4_ENABLE_CLK_IN (0x3 << 4)
|
||||
#define PADCTL_SDMMC4_DEEP_LOOPBACK (1 << 0)
|
||||
#define PADCTL_SDMMC1_CD_SOURCE (1 << 0)
|
||||
#define PADCTL_SDMMC1_WP_SOURCE (1 << 1)
|
||||
#define PADCTL_SDMMC3_CD_SOURCE (1 << 2)
|
||||
#define PADCTL_SDMMC3_WP_SOURCE (1 << 3)
|
||||
|
||||
typedef struct {
|
||||
uint32_t asdbgreg; /* 0x810 */
|
||||
uint32_t reserved0[0x31];
|
||||
uint32_t sdmmc1_clk_lpbk_control; /* 0x8D4 */
|
||||
uint32_t sdmmc3_clk_lpbk_control; /* 0x8D8 */
|
||||
uint32_t emmc2_pad_cfg_control; /* 0x8DC */
|
||||
uint32_t emmc4_pad_cfg_control; /* 0x8E0 */
|
||||
uint32_t _todo0[0x6E];
|
||||
uint32_t sdmmc1_pad_cfgpadctrl; /* 0xA98 */
|
||||
uint32_t emmc2_pad_cfgpadctrl; /* 0xA9C */
|
||||
uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */
|
||||
uint32_t emmc2_pad_pupd_cfgpadctrl; /* 0xAA4 */
|
||||
uint32_t _todo1[0x03];
|
||||
uint32_t sdmmc3_pad_cfgpadctrl; /* 0xAB0 */
|
||||
uint32_t emmc4_pad_cfgpadctrl; /* 0xAB4 */
|
||||
uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */
|
||||
uint32_t emmc4_pad_pupd_cfgpadctrl; /* 0xABC */
|
||||
uint32_t _todo2[0x2E];
|
||||
uint32_t vgpio_gpio_mux_sel; /* 0xB74 */
|
||||
uint32_t qspi_sck_lpbk_control; /* 0xB78 */
|
||||
} tegra_padctl_t;
|
||||
|
||||
static inline volatile tegra_padctl_t *padctl_get_regs(void)
|
||||
{
|
||||
return (volatile tegra_padctl_t *)APB_PADCTL_BASE;
|
||||
}
|
||||
|
||||
#endif
|
||||
82
sept/sept-secondary/src/btn.c
Normal file
82
sept/sept-secondary/src/btn.c
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 CTCaer
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "btn.h"
|
||||
#include "i2c.h"
|
||||
#include "gpio.h"
|
||||
#include "timers.h"
|
||||
|
||||
uint32_t btn_read()
|
||||
{
|
||||
uint32_t res = 0;
|
||||
|
||||
if (!gpio_read(GPIO_BUTTON_VOL_DOWN))
|
||||
res |= BTN_VOL_DOWN;
|
||||
|
||||
if (!gpio_read(GPIO_BUTTON_VOL_UP))
|
||||
res |= BTN_VOL_UP;
|
||||
|
||||
uint32_t val = 0;
|
||||
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, 0x15, &val, 1))
|
||||
{
|
||||
if (val & 0x4)
|
||||
res |= BTN_POWER;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
uint32_t btn_wait()
|
||||
{
|
||||
uint32_t res = 0, btn = btn_read();
|
||||
int pwr = 0;
|
||||
|
||||
if (btn & BTN_POWER)
|
||||
{
|
||||
pwr = 1;
|
||||
btn &= ~BTN_POWER;
|
||||
}
|
||||
|
||||
do
|
||||
{
|
||||
res = btn_read();
|
||||
|
||||
if (!(res & BTN_POWER) && pwr)
|
||||
pwr = 0;
|
||||
else if (pwr)
|
||||
res &= ~BTN_POWER;
|
||||
} while (btn == res);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask)
|
||||
{
|
||||
uint32_t timeout = get_time_ms() + time_ms;
|
||||
uint32_t res = btn_read() & mask;
|
||||
|
||||
do
|
||||
{
|
||||
if (!(res & mask))
|
||||
res = btn_read() & mask;
|
||||
} while (get_time_ms() < timeout);
|
||||
|
||||
return res;
|
||||
}
|
||||
30
sept/sept-secondary/src/btn.h
Normal file
30
sept/sept-secondary/src/btn.h
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 CTCaer
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_BTN_H_
|
||||
#define FUSEE_BTN_H_
|
||||
|
||||
#define BTN_POWER 0x1
|
||||
#define BTN_VOL_DOWN 0x2
|
||||
#define BTN_VOL_UP 0x4
|
||||
|
||||
uint32_t btn_read();
|
||||
uint32_t btn_wait();
|
||||
uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask);
|
||||
|
||||
#endif
|
||||
139
sept/sept-secondary/src/car.c
Normal file
139
sept/sept-secondary/src/car.c
Normal file
|
|
@ -0,0 +1,139 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "car.h"
|
||||
#include "timers.h"
|
||||
#include "utils.h"
|
||||
|
||||
static inline uint32_t get_clk_source_reg(CarDevice dev) {
|
||||
switch (dev) {
|
||||
case CARDEVICE_UARTA: return 0x178;
|
||||
case CARDEVICE_UARTB: return 0x17C;
|
||||
case CARDEVICE_UARTC: return 0x1A0;
|
||||
case CARDEVICE_I2C1: return 0x124;
|
||||
case CARDEVICE_I2C5: return 0x128;
|
||||
case CARDEVICE_UNK: return 0;
|
||||
case CARDEVICE_SE: return 0x42C;
|
||||
case CARDEVICE_HOST1X: return 0x180;
|
||||
case CARDEVICE_TSEC: return 0x1F4;
|
||||
case CARDEVICE_SOR_SAFE: return 0;
|
||||
case CARDEVICE_SOR0: return 0;
|
||||
case CARDEVICE_SOR1: return 0x410;
|
||||
case CARDEVICE_KFUSE: return 0;
|
||||
case CARDEVICE_CL_DVFS: return 0;
|
||||
case CARDEVICE_CORESIGHT: return 0x1D4;
|
||||
case CARDEVICE_ACTMON: return 0x3E8;
|
||||
case CARDEVICE_BPMP: return 0;
|
||||
default: generic_panic();
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint32_t get_clk_source_val(CarDevice dev) {
|
||||
switch (dev) {
|
||||
case CARDEVICE_UARTA: return 0;
|
||||
case CARDEVICE_UARTB: return 0;
|
||||
case CARDEVICE_UARTC: return 0;
|
||||
case CARDEVICE_I2C1: return 6;
|
||||
case CARDEVICE_I2C5: return 6;
|
||||
case CARDEVICE_UNK: return 0;
|
||||
case CARDEVICE_SE: return 0;
|
||||
case CARDEVICE_HOST1X: return 4;
|
||||
case CARDEVICE_TSEC: return 0;
|
||||
case CARDEVICE_SOR_SAFE: return 0;
|
||||
case CARDEVICE_SOR0: return 0;
|
||||
case CARDEVICE_SOR1: return 0;
|
||||
case CARDEVICE_KFUSE: return 0;
|
||||
case CARDEVICE_CL_DVFS: return 0;
|
||||
case CARDEVICE_CORESIGHT: return 0;
|
||||
case CARDEVICE_ACTMON: return 6;
|
||||
case CARDEVICE_BPMP: return 0;
|
||||
default: generic_panic();
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint32_t get_clk_source_div(CarDevice dev) {
|
||||
switch (dev) {
|
||||
case CARDEVICE_UARTA: return 0;
|
||||
case CARDEVICE_UARTB: return 0;
|
||||
case CARDEVICE_UARTC: return 0;
|
||||
case CARDEVICE_I2C1: return 0;
|
||||
case CARDEVICE_I2C5: return 0;
|
||||
case CARDEVICE_UNK: return 0;
|
||||
case CARDEVICE_SE: return 0;
|
||||
case CARDEVICE_HOST1X: return 3;
|
||||
case CARDEVICE_TSEC: return 2;
|
||||
case CARDEVICE_SOR_SAFE: return 0;
|
||||
case CARDEVICE_SOR0: return 0;
|
||||
case CARDEVICE_SOR1: return 2;
|
||||
case CARDEVICE_KFUSE: return 0;
|
||||
case CARDEVICE_CL_DVFS: return 0;
|
||||
case CARDEVICE_CORESIGHT: return 4;
|
||||
case CARDEVICE_ACTMON: return 0;
|
||||
case CARDEVICE_BPMP: return 0;
|
||||
default: generic_panic();
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298};
|
||||
static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4};
|
||||
|
||||
void clk_enable(CarDevice dev) {
|
||||
uint32_t clk_source_reg;
|
||||
if ((clk_source_reg = get_clk_source_reg(dev))) {
|
||||
MAKE_CAR_REG(clk_source_reg) = (get_clk_source_val(dev) << 29) | get_clk_source_div(dev);
|
||||
}
|
||||
MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
|
||||
}
|
||||
|
||||
void clk_disable(CarDevice dev) {
|
||||
MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
|
||||
}
|
||||
|
||||
void rst_enable(CarDevice dev) {
|
||||
MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
|
||||
}
|
||||
|
||||
void rst_disable(CarDevice dev) {
|
||||
MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
|
||||
}
|
||||
|
||||
void clkrst_enable(CarDevice dev) {
|
||||
clk_enable(dev);
|
||||
rst_disable(dev);
|
||||
}
|
||||
|
||||
void clkrst_disable(CarDevice dev) {
|
||||
rst_enable(dev);
|
||||
clk_disable(dev);
|
||||
}
|
||||
|
||||
void clkrst_reboot(CarDevice dev) {
|
||||
clkrst_disable(dev);
|
||||
if (dev == CARDEVICE_KFUSE) {
|
||||
/* Workaround for KFUSE clock. */
|
||||
clk_enable(dev);
|
||||
udelay(100);
|
||||
rst_disable(dev);
|
||||
udelay(200);
|
||||
} else {
|
||||
clkrst_enable(dev);
|
||||
}
|
||||
}
|
||||
|
||||
void clkrst_enable_fuse_regs(bool enable) {
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
car->misc_clk_enb = ((car->misc_clk_enb & 0xEFFFFFFF) | ((enable & 1) << 28));
|
||||
}
|
||||
505
sept/sept-secondary/src/car.h
Normal file
505
sept/sept-secondary/src/car.h
Normal file
|
|
@ -0,0 +1,505 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_CAR_H
|
||||
#define FUSEE_CAR_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define CAR_BASE 0x60006000
|
||||
#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n)
|
||||
|
||||
#define CLK_L_SDMMC1 (1 << 14)
|
||||
#define CLK_L_SDMMC2 (1 << 9)
|
||||
#define CLK_U_SDMMC3 (1 << 5)
|
||||
#define CLK_L_SDMMC4 (1 << 15)
|
||||
|
||||
#define CLK_SOURCE_MASK (0b111 << 29)
|
||||
#define CLK_SOURCE_FIRST (0b000 << 29)
|
||||
#define CLK_DIVIDER_MASK (0xff << 0)
|
||||
#define CLK_DIVIDER_UNITY (0x00 << 0)
|
||||
|
||||
#define NUM_CAR_BANKS 7
|
||||
|
||||
/* Clock and reset devices. */
|
||||
typedef enum {
|
||||
CARDEVICE_UARTA = ((0 << 5) | 0x6),
|
||||
CARDEVICE_UARTB = ((0 << 5) | 0x7),
|
||||
CARDEVICE_UARTC = ((1 << 5) | 0x17),
|
||||
CARDEVICE_I2C1 = ((0 << 5) | 0xC),
|
||||
CARDEVICE_I2C5 = ((1 << 5) | 0xF),
|
||||
CARDEVICE_UNK = ((3 << 5) | 0x1E),
|
||||
CARDEVICE_SE = ((3 << 5) | 0x1F),
|
||||
CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
|
||||
CARDEVICE_TSEC = ((2 << 5) | 0x13),
|
||||
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
|
||||
CARDEVICE_SOR0 = ((5 << 5) | 0x16),
|
||||
CARDEVICE_SOR1 = ((5 << 5) | 0x17),
|
||||
CARDEVICE_KFUSE = ((1 << 5) | 0x8),
|
||||
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
|
||||
CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
|
||||
CARDEVICE_ACTMON = ((3 << 5) | 0x17),
|
||||
CARDEVICE_BPMP = ((0 << 5) | 0x1)
|
||||
} CarDevice;
|
||||
|
||||
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
|
||||
typedef struct {
|
||||
uint32_t rst_src; /* _RST_SOURCE_0, 0x00 */
|
||||
|
||||
/* _RST_DEVICES_L/H/U_0 0x4-0xc */
|
||||
uint32_t rst_dev_l;
|
||||
uint32_t rst_dev_h;
|
||||
uint32_t rst_dev_u;
|
||||
|
||||
/* _CLK_OUT_ENB_L/H/U_0 0x10-0x18 */
|
||||
uint32_t clk_out_enb_l;
|
||||
uint32_t clk_out_enb_h;
|
||||
uint32_t clk_out_enb_u;
|
||||
|
||||
uint32_t _0x1C;
|
||||
uint32_t cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
|
||||
uint32_t super_cclk_div; /* _SUPER_CCLK_DIVIDER_0, 0x24 */
|
||||
uint32_t sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
|
||||
uint32_t super_sclk_div; /* _SUPER_SCLK_DIVIDER_0, 0x2c */
|
||||
uint32_t clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
|
||||
uint32_t prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
|
||||
uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0, 0x38 */
|
||||
uint32_t _0x3C;
|
||||
uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0, 0x40 */
|
||||
uint32_t clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */
|
||||
uint32_t misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */
|
||||
uint32_t clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4c */
|
||||
uint32_t osc_ctrl; /* _OSC_CTRL_0, 0x50 */
|
||||
uint32_t pll_lfsr; /* _PLL_LFSR_0, 0x54 */
|
||||
uint32_t osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */
|
||||
uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0, 0x5c */
|
||||
uint32_t _0x60[2];
|
||||
uint32_t plle_ss_cntl; /* _PLLE_SS_CNTL_0, 0x68 */
|
||||
uint32_t plle_misc1; /* _PLLE_MISC1_0, 0x6c */
|
||||
uint32_t _0x70[4];
|
||||
|
||||
/* PLLC 0x80-0x8c */
|
||||
uint32_t pllc_base;
|
||||
uint32_t pllc_out;
|
||||
uint32_t pllc_misc0;
|
||||
uint32_t pllc_misc1;
|
||||
|
||||
/* PLLM 0x90-0x9c */
|
||||
uint32_t pllm_base;
|
||||
uint32_t pllm_out;
|
||||
uint32_t pllm_misc1;
|
||||
uint32_t pllm_misc2;
|
||||
|
||||
/* PLLP 0xa0-0xac */
|
||||
uint32_t pllp_base;
|
||||
uint32_t pllp_outa;
|
||||
uint32_t pllp_outb;
|
||||
uint32_t pllp_misc;
|
||||
|
||||
/* PLLA 0xb0-0xbc */
|
||||
uint32_t plla_base;
|
||||
uint32_t plla_out;
|
||||
uint32_t plla_misc0;
|
||||
uint32_t plla_misc1;
|
||||
|
||||
/* PLLU 0xc0-0xcc */
|
||||
uint32_t pllu_base;
|
||||
uint32_t pllu_out;
|
||||
uint32_t pllu_misc1;
|
||||
uint32_t pllu_misc2;
|
||||
|
||||
/* PLLD 0xd0-0xdc */
|
||||
uint32_t plld_base;
|
||||
uint32_t plld_out;
|
||||
uint32_t plld_misc1;
|
||||
uint32_t plld_misc2;
|
||||
|
||||
/* PLLX 0xe0-0xe4 */
|
||||
uint32_t pllx_base;
|
||||
uint32_t pllx_misc;
|
||||
|
||||
/* PLLE 0xe8-0xf4 */
|
||||
uint32_t plle_base;
|
||||
uint32_t plle_misc;
|
||||
uint32_t plle_ss_cntl1;
|
||||
uint32_t plle_ss_cntl2;
|
||||
|
||||
uint32_t lvl2_clk_gate_ovra; /* _LVL2_CLK_GATE_OVRA_0, 0xf8 */
|
||||
uint32_t lvl2_clk_gate_ovrb; /* _LVL2_CLK_GATE_OVRB_0, 0xfc */
|
||||
|
||||
uint32_t clk_source_i2s2; /* _CLK_SOURCE_I2S2_0, 0x100 */
|
||||
uint32_t clk_source_i2s3; /* _CLK_SOURCE_I2S3_0, 0x104 */
|
||||
uint32_t clk_source_spdif_out; /* _CLK_SOURCE_SPDIF_OUT_0, 0x108 */
|
||||
uint32_t clk_source_spdif_in; /* _CLK_SOURCE_SPDIF_IN_0, 0x10c */
|
||||
uint32_t clk_source_pwm; /* _CLK_SOURCE_PWM_0, 0x110 */
|
||||
uint32_t _0x114;
|
||||
uint32_t clk_source_spi2; /* _CLK_SOURCE_SPI2_0, 0x118 */
|
||||
uint32_t clk_source_spi3; /* _CLK_SOURCE_SPI3_0, 0x11c */
|
||||
uint32_t _0x120;
|
||||
uint32_t clk_source_i2c1; /* _CLK_SOURCE_I2C1_0, 0x124 */
|
||||
uint32_t clk_source_i2c5; /* _CLK_SOURCE_I2C5_0, 0x128 */
|
||||
uint32_t _0x12c[2];
|
||||
uint32_t clk_source_spi1; /* _CLK_SOURCE_SPI1_0, 0x134 */
|
||||
uint32_t clk_source_disp1; /* _CLK_SOURCE_DISP1_0, 0x138 */
|
||||
uint32_t clk_source_disp2; /* _CLK_SOURCE_DISP2_0, 0x13c */
|
||||
uint32_t _0x140;
|
||||
uint32_t clk_source_isp; /* _CLK_SOURCE_ISP_0, 0x144 */
|
||||
uint32_t clk_source_vi; /* _CLK_SOURCE_VI_0, 0x148 */
|
||||
uint32_t _0x14c;
|
||||
uint32_t clk_source_sdmmc1; /* _CLK_SOURCE_SDMMC1_0, 0x150 */
|
||||
uint32_t clk_source_sdmmc2; /* _CLK_SOURCE_SDMMC2_0, 0x154 */
|
||||
uint32_t _0x158[3];
|
||||
uint32_t clk_source_sdmmc4; /* _CLK_SOURCE_SDMMC4_0, 0x164 */
|
||||
uint32_t _0x168[4];
|
||||
uint32_t clk_source_uarta; /* _CLK_SOURCE_UARTA_0, 0x178 */
|
||||
uint32_t clk_source_uartb; /* _CLK_SOURCE_UARTB_0, 0x17c */
|
||||
uint32_t clk_source_host1x; /* _CLK_SOURCE_HOST1X_0, 0x180 */
|
||||
uint32_t _0x184[5];
|
||||
uint32_t clk_source_i2c2; /* _CLK_SOURCE_I2C2_0, 0x198 */
|
||||
uint32_t clk_source_emc; /* _CLK_SOURCE_EMC_0, 0x19c */
|
||||
uint32_t clk_source_uartc; /* _CLK_SOURCE_UARTC_0, 0x1a0 */
|
||||
uint32_t _0x1a4;
|
||||
uint32_t clk_source_vi_sensor; /* _CLK_SOURCE_VI_SENSOR_0, 0x1a8 */
|
||||
uint32_t _0x1ac[2];
|
||||
uint32_t clk_source_spi4; /* _CLK_SOURCE_SPI4_0, 0x1b4 */
|
||||
uint32_t clk_source_i2c3; /* _CLK_SOURCE_I2C3_0, 0x1b8 */
|
||||
uint32_t clk_source_sdmmc3; /* _CLK_SOURCE_SDMMC3_0, 0x1bc */
|
||||
uint32_t clk_source_uartd; /* _CLK_SOURCE_UARTD_0, 0x1c0 */
|
||||
uint32_t _0x1c4[2];
|
||||
uint32_t clk_source_owr; /* _CLK_SOURCE_OWR_0, 0x1cc */
|
||||
uint32_t _0x1d0;
|
||||
uint32_t clk_source_csite; /* _CLK_SOURCE_CSITE_0, 0x1d4 */
|
||||
uint32_t clk_source_i2s1; /* _CLK_SOURCE_I2S1_0, 0x1d8 */
|
||||
uint32_t clk_source_dtv; /* _CLK_SOURCE_DTV_0, 0x1dc */
|
||||
uint32_t _0x1e0[5];
|
||||
uint32_t clk_source_tsec; /* _CLK_SOURCE_TSEC_0, 0x1f4 */
|
||||
uint32_t _0x1f8;
|
||||
|
||||
uint32_t clk_spare2; /* _CLK_SPARE2_0, 0x1fc */
|
||||
uint32_t _0x200[32];
|
||||
|
||||
uint32_t clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */
|
||||
uint32_t clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */
|
||||
uint32_t clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */
|
||||
|
||||
uint32_t rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */
|
||||
uint32_t rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
|
||||
uint32_t rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
|
||||
|
||||
uint32_t clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
|
||||
uint32_t clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
|
||||
uint32_t clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
|
||||
|
||||
uint32_t rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
|
||||
uint32_t rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
|
||||
uint32_t rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
|
||||
|
||||
uint32_t _0x2b0[17];
|
||||
uint32_t dfll_base; /* _DFLL_BASE_0, 0x2f4 */
|
||||
uint32_t _0x2f8[2];
|
||||
|
||||
/* _RST_DEV_L/H/U_SET_0 0x300-0x314 */
|
||||
uint32_t rst_dev_l_set;
|
||||
uint32_t rst_dev_l_clr;
|
||||
uint32_t rst_dev_h_set;
|
||||
uint32_t rst_dev_h_clr;
|
||||
uint32_t rst_dev_u_set;
|
||||
uint32_t rst_dev_u_clr;
|
||||
|
||||
uint32_t _0x318[2];
|
||||
|
||||
/* _CLK_ENB_L/H/U_CLR_0 0x320-0x334 */
|
||||
uint32_t clk_enb_l_set;
|
||||
uint32_t clk_enb_l_clr;
|
||||
uint32_t clk_enb_h_set;
|
||||
uint32_t clk_enb_h_clr;
|
||||
uint32_t clk_enb_u_set;
|
||||
uint32_t clk_enb_u_clr;
|
||||
|
||||
uint32_t _0x338;
|
||||
uint32_t ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD_0, 0x33c */
|
||||
uint32_t rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
|
||||
uint32_t rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
|
||||
|
||||
/* Additional (T30) registers */
|
||||
uint32_t clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
|
||||
uint32_t clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
|
||||
|
||||
uint32_t _0x350[2];
|
||||
uint32_t rst_dev_v; /* _RST_DEVICES_V_0, 0x358 */
|
||||
uint32_t rst_dev_w; /* _RST_DEVICES_W_0, 0x35c */
|
||||
uint32_t clk_out_enb_v; /* _CLK_OUT_ENB_V_0, 0x360 */
|
||||
uint32_t clk_out_enb_w; /* _CLK_OUT_ENB_W_0, 0x364 */
|
||||
uint32_t cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
|
||||
uint32_t super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36c */
|
||||
uint32_t cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
|
||||
uint32_t super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
|
||||
uint32_t clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
|
||||
uint32_t clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37c */
|
||||
uint32_t cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
|
||||
uint32_t cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */
|
||||
uint32_t cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
|
||||
uint32_t _0x38c[5];
|
||||
uint32_t lvl2_clk_gate_ovrc; /* _LVL2_CLK_GATE_OVRC, 0x3a0 */
|
||||
uint32_t lvl2_clk_gate_ovrd; /* _LVL2_CLK_GATE_OVRD, 0x3a4 */
|
||||
uint32_t _0x3a8[2];
|
||||
|
||||
uint32_t _0x3b0;
|
||||
uint32_t clk_source_mselect; /* _CLK_SOURCE_MSELECT_0, 0x3b4 */
|
||||
uint32_t clk_source_tsensor; /* _CLK_SOURCE_TSENSOR_0, 0x3b8 */
|
||||
uint32_t clk_source_i2s4; /* _CLK_SOURCE_I2S4_0, 0x3bc */
|
||||
uint32_t clk_source_i2s5; /* _CLK_SOURCE_I2S5_0, 0x3c0 */
|
||||
uint32_t clk_source_i2c4; /* _CLK_SOURCE_I2C4_0, 0x3c4 */
|
||||
uint32_t _0x3c8[2];
|
||||
uint32_t clk_source_ahub; /* _CLK_SOURCE_AHUB_0, 0x3d0 */
|
||||
uint32_t _0x3d4[4];
|
||||
uint32_t clk_source_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X_0, 0x3e4 */
|
||||
uint32_t clk_source_actmon; /* _CLK_SOURCE_ACTMON_0, 0x3e8 */
|
||||
uint32_t clk_source_extperiph1; /* _CLK_SOURCE_EXTPERIPH1_0, 0x3ec */
|
||||
uint32_t clk_source_extperiph2; /* _CLK_SOURCE_EXTPERIPH2_0, 0x3f0 */
|
||||
uint32_t clk_source_extperiph3; /* _CLK_SOURCE_EXTPERIPH3_0, 0x3f4 */
|
||||
uint32_t _0x3f8;
|
||||
uint32_t clk_source_i2c_slow; /* _CLK_SOURCE_I2C_SLOW_0, 0x3fc */
|
||||
uint32_t clk_source_sys; /* _CLK_SOURCE_SYS_0, 0x400 */
|
||||
uint32_t clk_source_ispb; /* _CLK_SOURCE_ISPB_0, 0x404 */
|
||||
uint32_t _0x408[2];
|
||||
uint32_t clk_source_sor1; /* _CLK_SOURCE_SOR1_0, 0x410 */
|
||||
uint32_t clk_source_sor0; /* _CLK_SOURCE_SOR0_0, 0x414 */
|
||||
uint32_t _0x418[2];
|
||||
uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */
|
||||
uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */
|
||||
uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */
|
||||
uint32_t _0x42c;
|
||||
|
||||
/* _RST_DEV_V/W_SET_0 0x430-0x43c */
|
||||
uint32_t rst_dev_v_set;
|
||||
uint32_t rst_dev_v_clr;
|
||||
uint32_t rst_dev_w_set;
|
||||
uint32_t rst_dev_w_clr;
|
||||
|
||||
/* _CLK_ENB_V/W_CLR_0 0x440-0x44c */
|
||||
uint32_t clk_enb_v_set;
|
||||
uint32_t clk_enb_v_clr;
|
||||
uint32_t clk_enb_w_set;
|
||||
uint32_t clk_enb_w_clr;
|
||||
|
||||
/* Additional (T114+) registers */
|
||||
uint32_t rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
|
||||
uint32_t rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
|
||||
uint32_t rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
|
||||
uint32_t rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45c */
|
||||
uint32_t clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */
|
||||
uint32_t clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */
|
||||
uint32_t clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
|
||||
uint32_t clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46c */
|
||||
uint32_t cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */
|
||||
uint32_t _0x474;
|
||||
uint32_t intstatus; /* _INTSTATUS_0, 0x478 */
|
||||
uint32_t intmask; /* _INTMASK_0, 0x47c */
|
||||
uint32_t utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */
|
||||
uint32_t utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */
|
||||
uint32_t utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */
|
||||
|
||||
uint32_t plle_aux; /* _PLLE_AUX_0, 0x48c */
|
||||
uint32_t sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */
|
||||
uint32_t sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */
|
||||
uint32_t pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */
|
||||
|
||||
uint32_t prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49c */
|
||||
uint32_t audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4a0 */
|
||||
uint32_t audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4a4 */
|
||||
uint32_t audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4a8 */
|
||||
uint32_t audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4ac */
|
||||
uint32_t audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4b0 */
|
||||
uint32_t audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4b4 */
|
||||
|
||||
uint32_t plld2_base; /* _PLLD2_BASE_0, 0x4b8 */
|
||||
uint32_t plld2_misc; /* _PLLD2_MISC_0, 0x4bc */
|
||||
uint32_t utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4c0 */
|
||||
uint32_t pllrefe_base; /* _PLLREFE_BASE_0, 0x4c4 */
|
||||
uint32_t pllrefe_misc; /* _PLLREFE_MISC_0, 0x4c8 */
|
||||
uint32_t pllrefe_out; /* _PLLREFE_OUT_0, 0x4cc */
|
||||
uint32_t cpu_finetrim_byp; /* _CPU_FINETRIM_BYP_0, 0x4d0 */
|
||||
uint32_t cpu_finetrim_select; /* _CPU_FINETRIM_SELECT_0, 0x4d4 */
|
||||
uint32_t cpu_finetrim_dr; /* _CPU_FINETRIM_DR_0, 0x4d8 */
|
||||
uint32_t cpu_finetrim_df; /* _CPU_FINETRIM_DF_0, 0x4dc */
|
||||
uint32_t cpu_finetrim_f; /* _CPU_FINETRIM_F_0, 0x4e0 */
|
||||
uint32_t cpu_finetrim_r; /* _CPU_FINETRIM_R_0, 0x4e4 */
|
||||
uint32_t pllc2_base; /* _PLLC2_BASE_0, 0x4e8 */
|
||||
uint32_t pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4ec */
|
||||
uint32_t pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4f0 */
|
||||
uint32_t pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4f4 */
|
||||
uint32_t pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4f8 */
|
||||
uint32_t pllc3_base; /* _PLLC3_BASE_0, 0x4fc */
|
||||
uint32_t pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */
|
||||
uint32_t pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */
|
||||
uint32_t pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */
|
||||
uint32_t pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50c */
|
||||
uint32_t pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */
|
||||
uint32_t pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */
|
||||
uint32_t pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */
|
||||
uint32_t xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51c */
|
||||
uint32_t xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */
|
||||
uint32_t plle_aux1; /* _PLLE_AUX1_0, 0x524 */
|
||||
uint32_t pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */
|
||||
uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52c */
|
||||
uint32_t pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
|
||||
uint32_t xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */
|
||||
uint32_t _0x538;
|
||||
uint32_t clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53c */
|
||||
uint32_t clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */
|
||||
uint32_t clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */
|
||||
uint32_t pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */
|
||||
uint32_t pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54c */
|
||||
uint32_t pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
|
||||
uint32_t lvl2_clk_gate_ovre; /* _LVL2_CLK_GATE_OVRE, 0x554 */
|
||||
uint32_t super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
|
||||
uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55c */
|
||||
uint32_t audio_sync_clk_dmic1; /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */
|
||||
uint32_t audio_sync_clk_dmic2; /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */
|
||||
|
||||
uint32_t _0x568[2];
|
||||
uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG, 0x570 */
|
||||
uint32_t plld2_ss_ctrl1; /* _PLLD2_SS_CTRL1_0, 0x574 */
|
||||
uint32_t plld2_ss_ctrl2; /* _PLLD2_SS_CTRL2_0, 0x578 */
|
||||
uint32_t _0x57c[5];
|
||||
|
||||
uint32_t plldp_base; /* _PLLDP_BASE, 0x590*/
|
||||
uint32_t plldp_misc; /* _PLLDP_MISC, 0x594 */
|
||||
uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
|
||||
uint32_t plldp_ss_ctrl1; /* _PLLDP_SS_CTRL1_0, 0x59c */
|
||||
uint32_t plldp_ss_ctrl2; /* _PLLDP_SS_CTRL2_0, 0x5a0 */
|
||||
uint32_t pllc4_base; /* _PLLC4_BASE_0, 0x5a4 */
|
||||
uint32_t pllc4_misc; /* _PLLC4_MISC_0, 0x5a8 */
|
||||
uint32_t _0x5ac[6];
|
||||
uint32_t clk_spare0; /* _CLK_SPARE0_0, 0x5c4 */
|
||||
uint32_t clk_spare1; /* _CLK_SPARE1_0, 0x5c8 */
|
||||
uint32_t gpu_isob_ctrl; /* _GPU_ISOB_CTRL_0, 0x5cc */
|
||||
uint32_t pllc_misc2; /* _PLLC_MISC_2_0, 0x5d0 */
|
||||
uint32_t pllc_misc3; /* _PLLC_MISC_3_0, 0x5d4 */
|
||||
uint32_t plla_misc2; /* _PLLA_MISC2_0, 0x5d8 */
|
||||
uint32_t _0x5dc[2];
|
||||
uint32_t pllc4_out; /* _PLLC4_OUT_0, 0x5e4 */
|
||||
uint32_t pllmb_base; /* _PLLMB_BASE_0, 0x5e8 */
|
||||
uint32_t pllmb_misc1; /* _PLLMB_MISC1_0, 0x5ec */
|
||||
uint32_t pllx_misc4; /* _PLLX_MISC_4_0, 0x5f0 */
|
||||
uint32_t pllx_misc5; /* _PLLX_MISC_5_0, 0x5f4 */
|
||||
uint32_t _0x5f8[2];
|
||||
|
||||
uint32_t clk_source_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST_0, 0x600 */
|
||||
uint32_t clk_source_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON_0, 0x604 */
|
||||
uint32_t clk_source_xusb_fs; /* _CLK_SOURCE_XUSB_FS_0, 0x608 */
|
||||
uint32_t clk_source_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV_0, 0x60c */
|
||||
uint32_t clk_source_xusb_ss; /* _CLK_SOURCE_XUSB_SS_0, 0x610 */
|
||||
uint32_t clk_source_cilab; /* _CLK_SOURCE_CILAB_0, 0x614 */
|
||||
uint32_t clk_source_cilcd; /* _CLK_SOURCE_CILCD_0, 0x618 */
|
||||
uint32_t clk_source_cilef; /* _CLK_SOURCE_CILEF_0, 0x61c */
|
||||
uint32_t clk_source_dsia_lp; /* _CLK_SOURCE_DSIA_LP_0, 0x620 */
|
||||
uint32_t clk_source_dsib_lp; /* _CLK_SOURCE_DSIB_LP_0, 0x624 */
|
||||
uint32_t clk_source_entropy; /* _CLK_SOURCE_ENTROPY_0, 0x628 */
|
||||
uint32_t clk_source_dvfs_ref; /* _CLK_SOURCE_DVFS_REF_0, 0x62c */
|
||||
uint32_t clk_source_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC_0, 0x630 */
|
||||
uint32_t _0x634[3];
|
||||
uint32_t clk_source_emc_latency; /* _CLK_SOURCE_EMC_LATENCY_0, 0x640 */
|
||||
uint32_t clk_source_soc_therm; /* _CLK_SOURCE_SOC_THERM_0, 0x644 */
|
||||
uint32_t _0x648;
|
||||
uint32_t clk_source_dmic1; /* _CLK_SOURCE_DMIC1_0, 0x64c */
|
||||
uint32_t clk_source_dmic2; /* _CLK_SOURCE_DMIC2_0, 0x650 */
|
||||
uint32_t _0x654;
|
||||
uint32_t clk_source_vi_sensor2; /* _CLK_SOURCE_VI_SENSOR2_0, 0x658 */
|
||||
uint32_t clk_source_i2c6; /* _CLK_SOURCE_I2C6_0, 0x65c */
|
||||
uint32_t clk_source_mipibif; /* _CLK_SOURCE_MIPIBIF_0, 0x660 */
|
||||
uint32_t clk_source_emc_dll; /* _CLK_SOURCE_EMC_DLL_0, 0x664 */
|
||||
uint32_t _0x668;
|
||||
uint32_t clk_source_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIPI_CAL_0, 0x66c */
|
||||
uint32_t _0x670[2];
|
||||
uint32_t clk_source_vic; /* _CLK_SOURCE_VIC_0, 0x678 */
|
||||
|
||||
uint32_t pllp_outc; /* _PLLP_OUTC_0, 0x67c */
|
||||
uint32_t pllp_misc1; /* _PLLP_MISC1_0, 0x680 */
|
||||
uint32_t _0x684[2];
|
||||
uint32_t emc_div_clk_shaper_ctrl; /* _EMC_DIV_CLK_SHAPER_CTRL_0, 0x68c */
|
||||
uint32_t emc_pllc_shaper_ctrl; /* _EMC_PLLC_SHAPER_CTRL_0, 0x690 */
|
||||
|
||||
uint32_t clk_source_sdmmc_legacy_tm; /* _CLK_SOURCE_SDMMC_LEGACY_TM_0, 0x694 */
|
||||
uint32_t clk_source_nvdec; /* _CLK_SOURCE_NVDEC_0, 0x698 */
|
||||
uint32_t clk_source_nvjpg; /* _CLK_SOURCE_NVJPG_0, 0x69c */
|
||||
uint32_t clk_source_nvenc; /* _CLK_SOURCE_NVENC_0, 0x6a0 */
|
||||
|
||||
uint32_t plla1_base; /* _PLLA1_BASE_0, 0x6a4 */
|
||||
uint32_t plla1_misc0; /* _PLLA1_MISC_0_0, 0x6a8 */
|
||||
uint32_t plla1_misc1; /* _PLLA1_MISC_1_0, 0x6ac */
|
||||
uint32_t plla1_misc2; /* _PLLA1_MISC_2_0, 0x6b0 */
|
||||
uint32_t plla1_misc3; /* _PLLA1_MISC_3_0, 0x6b4 */
|
||||
uint32_t audio_sync_clk_dmic3; /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */
|
||||
|
||||
uint32_t clk_source_dmic3; /* _CLK_SOURCE_DMIC3_0, 0x6bc */
|
||||
uint32_t clk_source_ape; /* _CLK_SOURCE_APE_0, 0x6c0 */
|
||||
uint32_t clk_source_qspi; /* _CLK_SOURCE_QSPI_0, 0x6c4 */
|
||||
uint32_t clk_source_vi_i2c; /* _CLK_SOURCE_VI_I2C_0, 0x6c8 */
|
||||
uint32_t clk_source_usb2_hsic_trk; /* _CLK_SOURCE_USB2_HSIC_TRK_0, 0x6cc */
|
||||
uint32_t clk_source_pex_sata_usb_rx_byp; /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0, 0x6d0 */
|
||||
uint32_t clk_source_maud; /* _CLK_SOURCE_MAUD_0, 0x6d4 */
|
||||
uint32_t clk_source_tsecb; /* _CLK_SOURCE_TSECB_0, 0x6d8 */
|
||||
|
||||
uint32_t clk_cpug_misc1; /* _CLK_CPUG_MISC1_0, 0x6dc */
|
||||
uint32_t aclk_burst_policy; /* _ACLK_BURST_POLICY_0, 0x6e0 */
|
||||
uint32_t super_aclk_divider; /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */
|
||||
|
||||
uint32_t nvenc_super_clk_divider; /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */
|
||||
uint32_t vi_super_clk_divider; /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */
|
||||
uint32_t vic_super_clk_divider; /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */
|
||||
uint32_t nvdec_super_clk_divider; /* _NVDEC_SUPER_CLK_DIVIDER_0, 0x6f4 */
|
||||
uint32_t isp_super_clk_divider; /* _ISP_SUPER_CLK_DIVIDER_0, 0x6f8 */
|
||||
uint32_t ispb_super_clk_divider; /* _ISPB_SUPER_CLK_DIVIDER_0, 0x6fc */
|
||||
uint32_t nvjpg_super_clk_divider; /* _NVJPG_SUPER_CLK_DIVIDER_0, 0x700 */
|
||||
uint32_t se_super_clk_divider; /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */
|
||||
uint32_t tsec_super_clk_divider; /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */
|
||||
uint32_t tsecb_super_clk_divider; /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */
|
||||
|
||||
uint32_t clk_source_uartape; /* _CLK_SOURCE_UARTAPE_0, 0x710 */
|
||||
uint32_t clk_cpug_misc2; /* _CLK_CPUG_MISC2_0, 0x714 */
|
||||
uint32_t clk_source_dbgapb; /* _CLK_SOURCE_DBGAPB_0, 0x718 */
|
||||
uint32_t clk_ccplex_cc4_ret_clk_enb; /* _CLK_CCPLEX_CC4_RET_CLK_ENB_0, 0x71c */
|
||||
uint32_t actmon_cpu_clk; /* _ACTMON_CPU_CLK_0, 0x720 */
|
||||
uint32_t clk_source_emc_safe; /* _CLK_SOURCE_EMC_SAFE_0, 0x724 */
|
||||
uint32_t sdmmc2_pllc4_out0_shaper_ctrl; /* _SDMMC2_PLLC4_OUT0_SHAPER_CTRL_0, 0x728 */
|
||||
uint32_t sdmmc2_pllc4_out1_shaper_ctrl; /* _SDMMC2_PLLC4_OUT1_SHAPER_CTRL_0, 0x72c */
|
||||
uint32_t sdmmc2_pllc4_out2_shaper_ctrl; /* _SDMMC2_PLLC4_OUT2_SHAPER_CTRL_0, 0x730 */
|
||||
uint32_t sdmmc2_div_clk_shaper_ctrl; /* _SDMMC2_DIV_CLK_SHAPER_CTRL_0, 0x734 */
|
||||
uint32_t sdmmc4_pllc4_out0_shaper_ctrl; /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */
|
||||
uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
|
||||
uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
|
||||
uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */
|
||||
} tegra_car_t;
|
||||
|
||||
static inline volatile tegra_car_t *car_get_regs(void) {
|
||||
return (volatile tegra_car_t *)CAR_BASE;
|
||||
}
|
||||
|
||||
void clk_enable(CarDevice dev);
|
||||
void clk_disable(CarDevice dev);
|
||||
void rst_enable(CarDevice dev);
|
||||
void rst_disable(CarDevice dev);
|
||||
|
||||
void clkrst_enable(CarDevice dev);
|
||||
void clkrst_disable(CarDevice dev);
|
||||
void clkrst_reboot(CarDevice dev);
|
||||
|
||||
void clkrst_enable_fuse_regs(bool enable);
|
||||
|
||||
#endif
|
||||
51
sept/sept-secondary/src/chainloader.c
Normal file
51
sept/sept-secondary/src/chainloader.c
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "chainloader.h"
|
||||
|
||||
int g_chainloader_argc = 0;
|
||||
char g_chainloader_arg_data[CHAINLOADER_ARG_DATA_MAX_SIZE] = {0};
|
||||
chainloader_entry_t g_chainloader_entries[CHAINLOADER_MAX_ENTRIES] = {0}; /* keep them sorted */
|
||||
size_t g_chainloader_num_entries = 0;
|
||||
uintptr_t g_chainloader_entrypoint = 0;
|
||||
|
||||
#pragma GCC optimize (3)
|
||||
|
||||
static void *xmemmove(void *dst, const void *src, size_t len)
|
||||
{
|
||||
const uint8_t *src8 = (const uint8_t *)src;
|
||||
uint8_t *dst8 = (uint8_t *)dst;
|
||||
|
||||
if (dst8 < src8) {
|
||||
for (size_t i = 0; i < len; i++) {
|
||||
dst8[i] = src8[i];
|
||||
}
|
||||
} else if (dst8 > src8) {
|
||||
for (size_t i = len; len > 0; len--)
|
||||
dst8[i - 1] = src8[i - 1];
|
||||
}
|
||||
|
||||
return dst;
|
||||
}
|
||||
|
||||
void relocate_and_chainload_main(void) {
|
||||
for(size_t i = 0; i < g_chainloader_num_entries; i++) {
|
||||
chainloader_entry_t *entry = &g_chainloader_entries[i];
|
||||
xmemmove((void *)entry->load_address, (const void *)entry->src_address, entry->size);
|
||||
}
|
||||
|
||||
((void (*)(int, void *))g_chainloader_entrypoint)(g_chainloader_argc, g_chainloader_arg_data);
|
||||
}
|
||||
42
sept/sept-secondary/src/chainloader.h
Normal file
42
sept/sept-secondary/src/chainloader.h
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_CHAINLOADER_H
|
||||
#define FUSEE_CHAINLOADER_H
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x6200
|
||||
#define CHAINLOADER_MAX_ENTRIES 128
|
||||
|
||||
typedef struct chainloader_entry_t {
|
||||
uintptr_t load_address;
|
||||
uintptr_t src_address;
|
||||
size_t size;
|
||||
size_t num;
|
||||
} chainloader_entry_t;
|
||||
|
||||
extern int g_chainloader_argc;
|
||||
extern chainloader_entry_t g_chainloader_entries[CHAINLOADER_MAX_ENTRIES]; /* keep them sorted */
|
||||
extern size_t g_chainloader_num_entries;
|
||||
extern uintptr_t g_chainloader_entrypoint;
|
||||
|
||||
extern char g_chainloader_arg_data[CHAINLOADER_ARG_DATA_MAX_SIZE];
|
||||
|
||||
void relocate_and_chainload(void);
|
||||
|
||||
#endif
|
||||
267
sept/sept-secondary/src/di.c
Normal file
267
sept/sept-secondary/src/di.c
Normal file
|
|
@ -0,0 +1,267 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 CTCaer
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "di.h"
|
||||
#include "timers.h"
|
||||
#include "i2c.h"
|
||||
#include "pmc.h"
|
||||
#include "max77620.h"
|
||||
#include "gpio.h"
|
||||
#include "pinmux.h"
|
||||
#include "car.h"
|
||||
|
||||
#include "di.inl"
|
||||
|
||||
static uint32_t _display_ver = 0;
|
||||
|
||||
static void exec_cfg(uint32_t *base, const cfg_op_t *ops, uint32_t num_ops)
|
||||
{
|
||||
for (uint32_t i = 0; i < num_ops; i++)
|
||||
base[ops[i].off] = ops[i].val;
|
||||
}
|
||||
|
||||
static void _display_dsi_wait(uint32_t timeout, uint32_t off, uint32_t mask)
|
||||
{
|
||||
uint32_t end = get_time_us() + timeout;
|
||||
while ((get_time_us() < end) && (MAKE_DSI_REG(off) & mask)) {
|
||||
/* Wait. */
|
||||
}
|
||||
udelay(5);
|
||||
}
|
||||
|
||||
void display_init()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
|
||||
|
||||
/* Power on. */
|
||||
uint8_t val = 0xD0;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1);
|
||||
val = 0x09;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO7, &val, 1);
|
||||
|
||||
/* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */
|
||||
car->rst_dev_h_clr = 0x1010000;
|
||||
car->clk_enb_h_set = 0x1010000;
|
||||
car->rst_dev_l_clr = 0x18000000;
|
||||
car->clk_enb_l_set = 0x18000000;
|
||||
car->clk_enb_x_set = 0x20000;
|
||||
car->clk_source_uart_fst_mipi_cal = 0xA;
|
||||
car->clk_enb_w_set = 0x80000;
|
||||
car->clk_source_dsia_lp = 0xA;
|
||||
|
||||
/* DPD idle. */
|
||||
pmc->io_dpd_req = 0x40000000;
|
||||
pmc->io_dpd2_req = 0x40000000;
|
||||
|
||||
/* Configure pins. */
|
||||
pinmux->nfc_en &= ~PINMUX_TRISTATE;
|
||||
pinmux->nfc_int &= ~PINMUX_TRISTATE;
|
||||
pinmux->lcd_bl_pwm &= ~PINMUX_TRISTATE;
|
||||
pinmux->lcd_bl_en &= ~PINMUX_TRISTATE;
|
||||
pinmux->lcd_rst &= ~PINMUX_TRISTATE;
|
||||
|
||||
/* Configure Backlight +-5V GPIOs. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT);
|
||||
|
||||
/* Enable Backlight +5V. */
|
||||
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Enable Backlight -5V. */
|
||||
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Configure Backlight PWM, EN and RST GPIOs. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT);
|
||||
gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
|
||||
|
||||
/* Enable Backlight EN. */
|
||||
gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH);
|
||||
|
||||
/* Configure display interface and display. */
|
||||
MAKE_MIPI_CAL_REG(0x60) = 0;
|
||||
|
||||
exec_cfg((uint32_t *)CAR_BASE, _display_config_1, 4);
|
||||
exec_cfg((uint32_t *)DI_BASE, _display_config_2, 94);
|
||||
exec_cfg((uint32_t *)DSI_BASE, _display_config_3, 60);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Enable Backlight RST. */
|
||||
gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH);
|
||||
|
||||
udelay(60000);
|
||||
|
||||
MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204;
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x337;
|
||||
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
|
||||
_display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO));
|
||||
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x406;
|
||||
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
|
||||
_display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO));
|
||||
|
||||
MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC);
|
||||
_display_dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA);
|
||||
|
||||
udelay(5000);
|
||||
|
||||
_display_ver = MAKE_DSI_REG(DSI_RD_DATA);
|
||||
|
||||
if (_display_ver == 0x10)
|
||||
exec_cfg((uint32_t *)DSI_BASE, _display_config_4, 43);
|
||||
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x1105;
|
||||
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
|
||||
|
||||
udelay(180000);
|
||||
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x2905;
|
||||
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
|
||||
|
||||
udelay(20000);
|
||||
|
||||
exec_cfg((uint32_t *)DSI_BASE, _display_config_5, 21);
|
||||
exec_cfg((uint32_t *)CAR_BASE, _display_config_6, 3);
|
||||
|
||||
MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4;
|
||||
exec_cfg((uint32_t *)DSI_BASE, _display_config_7, 10);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_8, 6);
|
||||
exec_cfg((uint32_t *)DSI_BASE, _display_config_9, 4);
|
||||
exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_10, 16);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
exec_cfg((uint32_t *)DI_BASE, _display_config_11, 113);
|
||||
}
|
||||
|
||||
void display_backlight(bool enable)
|
||||
{
|
||||
/* Enable Backlight PWM. */
|
||||
gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
|
||||
}
|
||||
|
||||
void display_end()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
|
||||
|
||||
/* Disable Backlight. */
|
||||
display_backlight(false);
|
||||
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x2805;
|
||||
|
||||
MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
|
||||
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
|
||||
|
||||
exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17);
|
||||
exec_cfg((uint32_t *)DSI_BASE, _display_config_13, 16);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
if (_display_ver == 0x10)
|
||||
exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22);
|
||||
|
||||
MAKE_DSI_REG(DSI_WR_DATA) = 0x1005;
|
||||
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
|
||||
|
||||
udelay(50000);
|
||||
|
||||
/* Disable Backlight RST. */
|
||||
gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Disable Backlight -5V. */
|
||||
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Disable Backlight +5V. */
|
||||
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW);
|
||||
|
||||
udelay(10000);
|
||||
|
||||
/* Disable clocks. */
|
||||
car->rst_dev_h_set = 0x1010000;
|
||||
car->clk_enb_h_clr = 0x1010000;
|
||||
car->rst_dev_l_set = 0x18000000;
|
||||
car->clk_enb_l_clr = 0x18000000;
|
||||
|
||||
MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF));
|
||||
MAKE_DSI_REG(DSI_POWER_CONTROL) = 0;
|
||||
|
||||
/* Backlight PWM. */
|
||||
gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO);
|
||||
|
||||
pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE);
|
||||
pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1);
|
||||
}
|
||||
|
||||
void display_color_screen(uint32_t color)
|
||||
{
|
||||
exec_cfg((uint32_t *)DI_BASE, cfg_display_one_color, 8);
|
||||
|
||||
/* Configure display to show single color. */
|
||||
MAKE_DI_REG(DC_WIN_AD_WIN_OPTIONS) = 0;
|
||||
MAKE_DI_REG(DC_WIN_BD_WIN_OPTIONS) = 0;
|
||||
MAKE_DI_REG(DC_WIN_CD_WIN_OPTIONS) = 0;
|
||||
MAKE_DI_REG(DC_DISP_BLEND_BACKGROUND_COLOR) = color;
|
||||
MAKE_DI_REG(DC_CMD_STATE_CONTROL) = ((MAKE_DI_REG(DC_CMD_STATE_CONTROL) & 0xFFFFFFFE) | GENERAL_ACT_REQ);
|
||||
|
||||
udelay(35000);
|
||||
|
||||
display_backlight(true);
|
||||
}
|
||||
|
||||
uint32_t *display_init_framebuffer(void *address)
|
||||
{
|
||||
static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0};
|
||||
if (conf[0].val == 0) {
|
||||
for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) {
|
||||
conf[i] = cfg_display_framebuffer[i];
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t *lfb_addr = (uint32_t *)address;
|
||||
conf[19].val = (uint32_t)address;
|
||||
|
||||
/* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */
|
||||
exec_cfg((uint32_t *)DI_BASE, conf, 32);
|
||||
|
||||
udelay(35000);
|
||||
|
||||
return lfb_addr;
|
||||
}
|
||||
368
sept/sept-secondary/src/di.h
Normal file
368
sept/sept-secondary/src/di.h
Normal file
|
|
@ -0,0 +1,368 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 CTCaer
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_DI_H_
|
||||
#define FUSEE_DI_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define HOST1X_BASE 0x50000000
|
||||
#define DI_BASE 0x54200000
|
||||
#define DSI_BASE 0x54300000
|
||||
#define VIC_BASE 0x54340000
|
||||
#define MIPI_CAL_BASE 0x700E3000
|
||||
#define MAKE_HOST1X_REG(n) MAKE_REG32(HOST1X_BASE + n)
|
||||
#define MAKE_DI_REG(n) MAKE_REG32(DI_BASE + n * 4)
|
||||
#define MAKE_DSI_REG(n) MAKE_REG32(DSI_BASE + n * 4)
|
||||
#define MAKE_MIPI_CAL_REG(n) MAKE_REG32(MIPI_CAL_BASE + n)
|
||||
#define MAKE_VIC_REG(n) MAKE_REG32(VIC_BASE + n)
|
||||
|
||||
/* Display registers. */
|
||||
#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
|
||||
|
||||
#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
|
||||
#define SYNCPT_CNTRL_NO_STALL (1 << 8)
|
||||
#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
|
||||
|
||||
#define DC_CMD_CONT_SYNCPT_VSYNC 0x28
|
||||
#define SYNCPT_VSYNC_ENABLE (1 << 8)
|
||||
|
||||
#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
|
||||
|
||||
#define DC_CMD_DISPLAY_COMMAND 0x32
|
||||
#define DISP_CTRL_MODE_STOP (0 << 5)
|
||||
#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
|
||||
#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
|
||||
#define DISP_CTRL_MODE_MASK (3 << 5)
|
||||
|
||||
#define DC_CMD_DISPLAY_POWER_CONTROL 0x36
|
||||
#define PW0_ENABLE (1 << 0)
|
||||
#define PW1_ENABLE (1 << 2)
|
||||
#define PW2_ENABLE (1 << 4)
|
||||
#define PW3_ENABLE (1 << 6)
|
||||
#define PW4_ENABLE (1 << 8)
|
||||
#define PM0_ENABLE (1 << 16)
|
||||
#define PM1_ENABLE (1 << 18)
|
||||
|
||||
#define DC_CMD_INT_MASK 0x38
|
||||
#define DC_CMD_INT_ENABLE 0x39
|
||||
|
||||
#define DC_CMD_STATE_ACCESS 0x40
|
||||
#define READ_MUX (1 << 0)
|
||||
#define WRITE_MUX (1 << 2)
|
||||
|
||||
#define DC_CMD_STATE_CONTROL 0x41
|
||||
#define GENERAL_ACT_REQ (1 << 0)
|
||||
#define WIN_A_ACT_REQ (1 << 1)
|
||||
#define WIN_B_ACT_REQ (1 << 2)
|
||||
#define WIN_C_ACT_REQ (1 << 3)
|
||||
#define CURSOR_ACT_REQ (1 << 7)
|
||||
#define GENERAL_UPDATE (1 << 8)
|
||||
#define WIN_A_UPDATE (1 << 9)
|
||||
#define WIN_B_UPDATE (1 << 10)
|
||||
#define WIN_C_UPDATE (1 << 11)
|
||||
#define CURSOR_UPDATE (1 << 15)
|
||||
#define NC_HOST_TRIG (1 << 24)
|
||||
|
||||
#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42
|
||||
#define WINDOW_A_SELECT (1 << 4)
|
||||
#define WINDOW_B_SELECT (1 << 5)
|
||||
#define WINDOW_C_SELECT (1 << 6)
|
||||
|
||||
#define DC_CMD_REG_ACT_CONTROL 0x043
|
||||
|
||||
#define DC_COM_CRC_CONTROL 0x300
|
||||
#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
|
||||
#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
|
||||
|
||||
#define DC_COM_DSC_TOP_CTL 0x33E
|
||||
|
||||
#define DC_DISP_DISP_WIN_OPTIONS 0x402
|
||||
#define HDMI_ENABLE (1 << 30)
|
||||
#define DSI_ENABLE (1 << 29)
|
||||
#define SOR1_TIMING_CYA (1 << 27)
|
||||
#define SOR1_ENABLE (1 << 26)
|
||||
#define SOR_ENABLE (1 << 25)
|
||||
#define CURSOR_ENABLE (1 << 16)
|
||||
|
||||
#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
|
||||
#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
|
||||
#define DC_DISP_DISP_TIMING_OPTIONS 0x405
|
||||
#define DC_DISP_REF_TO_SYNC 0x406
|
||||
#define DC_DISP_SYNC_WIDTH 0x407
|
||||
#define DC_DISP_BACK_PORCH 0x408
|
||||
#define DC_DISP_ACTIVE 0x409
|
||||
#define DC_DISP_FRONT_PORCH 0x40A
|
||||
|
||||
#define DC_DISP_DISP_CLOCK_CONTROL 0x42E
|
||||
#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
|
||||
#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
|
||||
#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
|
||||
|
||||
#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F
|
||||
#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
|
||||
#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
|
||||
#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
|
||||
#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
|
||||
#define DISP_DATA_FORMAT_DF2S (4 << 0)
|
||||
#define DISP_DATA_FORMAT_DF3S (5 << 0)
|
||||
#define DISP_DATA_FORMAT_DFSPI (6 << 0)
|
||||
#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
|
||||
#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
|
||||
#define DISP_ALIGNMENT_MSB (0 << 8)
|
||||
#define DISP_ALIGNMENT_LSB (1 << 8)
|
||||
#define DISP_ORDER_RED_BLUE (0 << 9)
|
||||
#define DISP_ORDER_BLUE_RED (1 << 9)
|
||||
|
||||
#define DC_DISP_DISP_COLOR_CONTROL 0x430
|
||||
#define DITHER_CONTROL_MASK (3 << 8)
|
||||
#define DITHER_CONTROL_DISABLE (0 << 8)
|
||||
#define DITHER_CONTROL_ORDERED (2 << 8)
|
||||
#define DITHER_CONTROL_ERRDIFF (3 << 8)
|
||||
#define BASE_COLOR_SIZE_MASK (0xf << 0)
|
||||
#define BASE_COLOR_SIZE_666 (0 << 0)
|
||||
#define BASE_COLOR_SIZE_111 (1 << 0)
|
||||
#define BASE_COLOR_SIZE_222 (2 << 0)
|
||||
#define BASE_COLOR_SIZE_333 (3 << 0)
|
||||
#define BASE_COLOR_SIZE_444 (4 << 0)
|
||||
#define BASE_COLOR_SIZE_555 (5 << 0)
|
||||
#define BASE_COLOR_SIZE_565 (6 << 0)
|
||||
#define BASE_COLOR_SIZE_332 (7 << 0)
|
||||
#define BASE_COLOR_SIZE_888 (8 << 0)
|
||||
|
||||
#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
|
||||
#define SC1_H_QUALIFIER_NONE (1 << 16)
|
||||
#define SC0_H_QUALIFIER_NONE (1 << 0)
|
||||
|
||||
#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
|
||||
#define DE_SELECT_ACTIVE_BLANK (0 << 0)
|
||||
#define DE_SELECT_ACTIVE (1 << 0)
|
||||
#define DE_SELECT_ACTIVE_IS (2 << 0)
|
||||
#define DE_CONTROL_ONECLK (0 << 2)
|
||||
#define DE_CONTROL_NORMAL (1 << 2)
|
||||
#define DE_CONTROL_EARLY_EXT (2 << 2)
|
||||
#define DE_CONTROL_EARLY (3 << 2)
|
||||
#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
|
||||
|
||||
#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
|
||||
#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4
|
||||
|
||||
#define DC_WIN_CSC_YOF 0x611
|
||||
#define DC_WIN_CSC_KYRGB 0x612
|
||||
#define DC_WIN_CSC_KUR 0x613
|
||||
#define DC_WIN_CSC_KVR 0x614
|
||||
#define DC_WIN_CSC_KUG 0x615
|
||||
#define DC_WIN_CSC_KVG 0x616
|
||||
#define DC_WIN_CSC_KUB 0x617
|
||||
#define DC_WIN_CSC_KVB 0x618
|
||||
#define DC_WIN_AD_WIN_OPTIONS 0xB80
|
||||
#define DC_WIN_BD_WIN_OPTIONS 0xD80
|
||||
#define DC_WIN_CD_WIN_OPTIONS 0xF80
|
||||
|
||||
/* The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER). */
|
||||
#define DC_WIN_WIN_OPTIONS 0x700
|
||||
#define H_DIRECTION (1 << 0)
|
||||
#define V_DIRECTION (1 << 2)
|
||||
#define COLOR_EXPAND (1 << 6)
|
||||
#define CSC_ENABLE (1 << 18)
|
||||
#define WIN_ENABLE (1 << 30)
|
||||
|
||||
#define DC_WIN_COLOR_DEPTH 0x703
|
||||
#define WIN_COLOR_DEPTH_P1 0x0
|
||||
#define WIN_COLOR_DEPTH_P2 0x1
|
||||
#define WIN_COLOR_DEPTH_P4 0x2
|
||||
#define WIN_COLOR_DEPTH_P8 0x3
|
||||
#define WIN_COLOR_DEPTH_B4G4R4A4 0x4
|
||||
#define WIN_COLOR_DEPTH_B5G5R5A 0x5
|
||||
#define WIN_COLOR_DEPTH_B5G6R5 0x6
|
||||
#define WIN_COLOR_DEPTH_AB5G5R5 0x7
|
||||
#define WIN_COLOR_DEPTH_B8G8R8A8 0xC
|
||||
#define WIN_COLOR_DEPTH_R8G8B8A8 0xD
|
||||
#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE
|
||||
#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF
|
||||
#define WIN_COLOR_DEPTH_YCbCr422 0x10
|
||||
#define WIN_COLOR_DEPTH_YUV422 0x11
|
||||
#define WIN_COLOR_DEPTH_YCbCr420P 0x12
|
||||
#define WIN_COLOR_DEPTH_YUV420P 0x13
|
||||
#define WIN_COLOR_DEPTH_YCbCr422P 0x14
|
||||
#define WIN_COLOR_DEPTH_YUV422P 0x15
|
||||
#define WIN_COLOR_DEPTH_YCbCr422R 0x16
|
||||
#define WIN_COLOR_DEPTH_YUV422R 0x17
|
||||
#define WIN_COLOR_DEPTH_YCbCr422RA 0x18
|
||||
#define WIN_COLOR_DEPTH_YUV422RA 0x19
|
||||
|
||||
#define DC_WIN_BUFFER_CONTROL 0x702
|
||||
#define DC_WIN_POSITION 0x704
|
||||
|
||||
#define DC_WIN_SIZE 0x705
|
||||
#define H_SIZE(x) (((x) & 0x1fff) << 0)
|
||||
#define V_SIZE(x) (((x) & 0x1fff) << 16)
|
||||
|
||||
#define DC_WIN_PRESCALED_SIZE 0x706
|
||||
#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
|
||||
#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
|
||||
|
||||
#define DC_WIN_H_INITIAL_DDA 0x707
|
||||
#define DC_WIN_V_INITIAL_DDA 0x708
|
||||
|
||||
#define DC_WIN_DDA_INC 0x709
|
||||
#define H_DDA_INC(x) (((x) & 0xffff) << 0)
|
||||
#define V_DDA_INC(x) (((x) & 0xffff) << 16)
|
||||
|
||||
#define DC_WIN_LINE_STRIDE 0x70A
|
||||
#define DC_WIN_DV_CONTROL 0x70E
|
||||
|
||||
/* The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */
|
||||
#define DC_WINBUF_START_ADDR 0x800
|
||||
#define DC_WINBUF_ADDR_H_OFFSET 0x806
|
||||
#define DC_WINBUF_ADDR_V_OFFSET 0x808
|
||||
#define DC_WINBUF_SURFACE_KIND 0x80B
|
||||
|
||||
/* Display serial interface registers. */
|
||||
#define DSI_RD_DATA 0x9
|
||||
#define DSI_WR_DATA 0xA
|
||||
|
||||
#define DSI_POWER_CONTROL 0xB
|
||||
#define DSI_POWER_CONTROL_ENABLE 1
|
||||
|
||||
#define DSI_INT_ENABLE 0xC
|
||||
#define DSI_INT_STATUS 0xD
|
||||
#define DSI_INT_MASK 0xE
|
||||
|
||||
#define DSI_HOST_CONTROL 0xF
|
||||
#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
|
||||
#define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
|
||||
#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
|
||||
#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
|
||||
#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
|
||||
#define DSI_HOST_CONTROL_RAW (1 << 6)
|
||||
#define DSI_HOST_CONTROL_HS (1 << 5)
|
||||
#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
|
||||
#define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
|
||||
#define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
|
||||
#define DSI_HOST_CONTROL_CS (1 << 1)
|
||||
#define DSI_HOST_CONTROL_ECC (1 << 0)
|
||||
|
||||
#define DSI_CONTROL 0x10
|
||||
#define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
|
||||
#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
|
||||
#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
|
||||
#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
|
||||
#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
|
||||
#define DSI_CONTROL_DCS_ENABLE (1 << 3)
|
||||
#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
|
||||
#define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
|
||||
#define DSI_CONTROL_HOST_ENABLE (1 << 0)
|
||||
|
||||
#define DSI_SOL_DELAY 0x11
|
||||
#define DSI_MAX_THRESHOLD 0x12
|
||||
|
||||
#define DSI_TRIGGER 0x13
|
||||
#define DSI_TRIGGER_HOST (1 << 1)
|
||||
#define DSI_TRIGGER_VIDEO (1 << 0)
|
||||
|
||||
#define DSI_TX_CRC 0x14
|
||||
#define DSI_STATUS 0x15
|
||||
#define DSI_INIT_SEQ_CONTROL 0x1A
|
||||
#define DSI_INIT_SEQ_DATA_0 0x1B
|
||||
#define DSI_INIT_SEQ_DATA_1 0x1C
|
||||
#define DSI_INIT_SEQ_DATA_2 0x1D
|
||||
#define DSI_INIT_SEQ_DATA_3 0x1E
|
||||
#define DSI_PKT_SEQ_0_LO 0x23
|
||||
#define DSI_PKT_SEQ_0_HI 0x24
|
||||
#define DSI_PKT_SEQ_1_LO 0x25
|
||||
#define DSI_PKT_SEQ_1_HI 0x26
|
||||
#define DSI_PKT_SEQ_2_LO 0x27
|
||||
#define DSI_PKT_SEQ_2_HI 0x28
|
||||
#define DSI_PKT_SEQ_3_LO 0x29
|
||||
#define DSI_PKT_SEQ_3_HI 0x2A
|
||||
#define DSI_PKT_SEQ_4_LO 0x2B
|
||||
#define DSI_PKT_SEQ_4_HI 0x2C
|
||||
#define DSI_PKT_SEQ_5_LO 0x2D
|
||||
#define DSI_PKT_SEQ_5_HI 0x2E
|
||||
#define DSI_DCS_CMDS 0x33
|
||||
#define DSI_PKT_LEN_0_1 0x34
|
||||
#define DSI_PKT_LEN_2_3 0x35
|
||||
#define DSI_PKT_LEN_4_5 0x36
|
||||
#define DSI_PKT_LEN_6_7 0x37
|
||||
#define DSI_PHY_TIMING_0 0x3C
|
||||
#define DSI_PHY_TIMING_1 0x3D
|
||||
#define DSI_PHY_TIMING_2 0x3E
|
||||
#define DSI_BTA_TIMING 0x3F
|
||||
|
||||
#define DSI_TIMEOUT_0 0x44
|
||||
#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
|
||||
#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
|
||||
|
||||
#define DSI_TIMEOUT_1 0x45
|
||||
#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
|
||||
#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
|
||||
|
||||
#define DSI_TO_TALLY 0x46
|
||||
|
||||
#define DSI_PAD_CONTROL_0 0x4B
|
||||
#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
|
||||
#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
|
||||
#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
|
||||
#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
|
||||
|
||||
#define DSI_PAD_CONTROL_CD 0x4c
|
||||
#define DSI_VIDEO_MODE_CONTROL 0x4E
|
||||
|
||||
#define DSI_PAD_CONTROL_1 0x4F
|
||||
#define DSI_PAD_CONTROL_2 0x50
|
||||
|
||||
#define DSI_PAD_CONTROL_3 0x51
|
||||
#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
|
||||
#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
|
||||
#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
|
||||
#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
|
||||
|
||||
#define DSI_PAD_CONTROL_4 0x52
|
||||
|
||||
typedef struct _cfg_op_t
|
||||
{
|
||||
uint32_t off;
|
||||
uint32_t val;
|
||||
} cfg_op_t;
|
||||
|
||||
void display_init();
|
||||
void display_end();
|
||||
|
||||
/* Show one single color on the display. */
|
||||
void display_color_screen(uint32_t color);
|
||||
|
||||
/* Switches screen backlight ON/OFF. */
|
||||
void display_backlight(bool enable);
|
||||
|
||||
/* Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */
|
||||
uint32_t *display_init_framebuffer(void *address);
|
||||
|
||||
#endif
|
||||
563
sept/sept-secondary/src/di.inl
Normal file
563
sept/sept-secondary/src/di.inl
Normal file
|
|
@ -0,0 +1,563 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (C) 2018 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
//Clock config.
|
||||
static const cfg_op_t _display_config_1[4] = {
|
||||
{0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1
|
||||
{0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE
|
||||
{0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1
|
||||
{0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC
|
||||
};
|
||||
|
||||
//Display A config.
|
||||
static const cfg_op_t _display_config_2[94] = {
|
||||
{DC_CMD_STATE_ACCESS, 0},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{DC_CMD_REG_ACT_CONTROL, 0x54},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_DISP_DC_MCCIF_FIFOCTRL, 0},
|
||||
{DC_DISP_DISP_MEM_HIGH_PRIORITY, 0},
|
||||
{DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0},
|
||||
{DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE},
|
||||
{DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL},
|
||||
{DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
|
||||
{DC_CMD_STATE_ACCESS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_WIN_DV_CONTROL, 0},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
/* Setup default YUV colorspace conversion coefficients */
|
||||
{DC_WIN_CSC_YOF, 0xF0},
|
||||
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||
{DC_WIN_CSC_KUR, 0},
|
||||
{DC_WIN_CSC_KVR, 0x198},
|
||||
{DC_WIN_CSC_KUG, 0x39B},
|
||||
{DC_WIN_CSC_KVG, 0x32F},
|
||||
{DC_WIN_CSC_KUB, 0x204},
|
||||
{DC_WIN_CSC_KVB, 0},
|
||||
/* End of color coefficients */
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_WIN_DV_CONTROL, 0},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
/* Setup default YUV colorspace conversion coefficients */
|
||||
{DC_WIN_CSC_YOF, 0xF0},
|
||||
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||
{DC_WIN_CSC_KUR, 0},
|
||||
{DC_WIN_CSC_KVR, 0x198},
|
||||
{DC_WIN_CSC_KUG, 0x39B},
|
||||
{DC_WIN_CSC_KVG, 0x32F},
|
||||
{DC_WIN_CSC_KUB, 0x204},
|
||||
{DC_WIN_CSC_KVB, 0},
|
||||
/* End of color coefficients */
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_WIN_DV_CONTROL, 0},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
/* Setup default YUV colorspace conversion coefficients */
|
||||
{DC_WIN_CSC_YOF, 0xF0},
|
||||
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||
{DC_WIN_CSC_KUR, 0},
|
||||
{DC_WIN_CSC_KVR, 0x198},
|
||||
{DC_WIN_CSC_KUG, 0x39B},
|
||||
{DC_WIN_CSC_KVG, 0x32F},
|
||||
{DC_WIN_CSC_KUB, 0x204},
|
||||
{DC_WIN_CSC_KVB, 0},
|
||||
/* End of color coefficients */
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
|
||||
{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
|
||||
{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
|
||||
{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
|
||||
{0x4E4, 0},
|
||||
{DC_COM_CRC_CONTROL, 0},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{0x716, 0x10000FF},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{0x716, 0x10000FF},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{0x716, 0x10000FF},
|
||||
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_COMMAND, 0},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}
|
||||
};
|
||||
|
||||
//DSI Init config.
|
||||
static const cfg_op_t _display_config_3[60] = {
|
||||
{DSI_WR_DATA, 0},
|
||||
{DSI_INT_ENABLE, 0},
|
||||
{DSI_INT_STATUS, 0},
|
||||
{DSI_INT_MASK, 0},
|
||||
{DSI_INIT_SEQ_DATA_0, 0},
|
||||
{DSI_INIT_SEQ_DATA_1, 0},
|
||||
{DSI_INIT_SEQ_DATA_2, 0},
|
||||
{DSI_INIT_SEQ_DATA_3, 0},
|
||||
{DSI_DCS_CMDS, 0},
|
||||
{DSI_PKT_SEQ_0_LO, 0},
|
||||
{DSI_PKT_SEQ_1_LO, 0},
|
||||
{DSI_PKT_SEQ_2_LO, 0},
|
||||
{DSI_PKT_SEQ_3_LO, 0},
|
||||
{DSI_PKT_SEQ_4_LO, 0},
|
||||
{DSI_PKT_SEQ_5_LO, 0},
|
||||
{DSI_PKT_SEQ_0_HI, 0},
|
||||
{DSI_PKT_SEQ_1_HI, 0},
|
||||
{DSI_PKT_SEQ_2_HI, 0},
|
||||
{DSI_PKT_SEQ_3_HI, 0},
|
||||
{DSI_PKT_SEQ_4_HI, 0},
|
||||
{DSI_PKT_SEQ_5_HI, 0},
|
||||
{DSI_CONTROL, 0},
|
||||
{DSI_PAD_CONTROL_CD, 0},
|
||||
{DSI_SOL_DELAY, 0x18},
|
||||
{DSI_MAX_THRESHOLD, 0x1E0},
|
||||
{DSI_TRIGGER, 0},
|
||||
{DSI_INIT_SEQ_CONTROL, 0},
|
||||
{DSI_PKT_LEN_0_1, 0},
|
||||
{DSI_PKT_LEN_2_3, 0},
|
||||
{DSI_PKT_LEN_4_5, 0},
|
||||
{DSI_PKT_LEN_6_7, 0},
|
||||
{DSI_PAD_CONTROL_1, 0},
|
||||
{DSI_PHY_TIMING_0, 0x6070601},
|
||||
{DSI_PHY_TIMING_1, 0x40A0E05},
|
||||
{DSI_PHY_TIMING_2, 0x30109},
|
||||
{DSI_BTA_TIMING, 0x190A14},
|
||||
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
|
||||
{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
|
||||
{DSI_TO_TALLY, 0},
|
||||
{DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable
|
||||
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||
{DSI_POWER_CONTROL, 0},
|
||||
{DSI_POWER_CONTROL, 0},
|
||||
{DSI_PAD_CONTROL_1, 0},
|
||||
{DSI_PHY_TIMING_0, 0x6070601},
|
||||
{DSI_PHY_TIMING_1, 0x40A0E05},
|
||||
{DSI_PHY_TIMING_2, 0x30118},
|
||||
{DSI_BTA_TIMING, 0x190A14},
|
||||
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
|
||||
{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
|
||||
{DSI_TO_TALLY, 0},
|
||||
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
|
||||
{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
|
||||
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||
{DSI_MAX_THRESHOLD, 0x40},
|
||||
{DSI_TRIGGER, 0},
|
||||
{DSI_TX_CRC, 0},
|
||||
{DSI_INIT_SEQ_CONTROL, 0}
|
||||
};
|
||||
|
||||
//DSI config (if ver == 0x10).
|
||||
static const cfg_op_t _display_config_4[43] = {
|
||||
{DSI_WR_DATA, 0x439},
|
||||
{DSI_WR_DATA, 0x9483FFB9},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0xBD15},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0x1939},
|
||||
{DSI_WR_DATA, 0xAAAAAAD8},
|
||||
{DSI_WR_DATA, 0xAAAAAAEB},
|
||||
{DSI_WR_DATA, 0xAAEBAAAA},
|
||||
{DSI_WR_DATA, 0xAAAAAAAA},
|
||||
{DSI_WR_DATA, 0xAAAAAAEB},
|
||||
{DSI_WR_DATA, 0xAAEBAAAA},
|
||||
{DSI_WR_DATA, 0xAA},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0x1BD15},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0x2739},
|
||||
{DSI_WR_DATA, 0xFFFFFFD8},
|
||||
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||
{DSI_WR_DATA, 0xFFFFFF},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0x2BD15},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0xF39},
|
||||
{DSI_WR_DATA, 0xFFFFFFD8},
|
||||
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||
{DSI_WR_DATA, 0xFFFFFFFF},
|
||||
{DSI_WR_DATA, 0xFFFFFF},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0xBD15},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0x6D915},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0x439},
|
||||
{DSI_WR_DATA, 0xB9},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST}
|
||||
};
|
||||
|
||||
//DSI config.
|
||||
static const cfg_op_t _display_config_5[21] = {
|
||||
{DSI_PAD_CONTROL_1, 0},
|
||||
{DSI_PHY_TIMING_0, 0x6070601},
|
||||
{DSI_PHY_TIMING_1, 0x40A0E05},
|
||||
{DSI_PHY_TIMING_2, 0x30172},
|
||||
{DSI_BTA_TIMING, 0x190A14},
|
||||
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
|
||||
{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
|
||||
{DSI_TO_TALLY, 0},
|
||||
{DSI_PKT_SEQ_0_LO, 0x40000208},
|
||||
{DSI_PKT_SEQ_2_LO, 0x40000308},
|
||||
{DSI_PKT_SEQ_4_LO, 0x40000308},
|
||||
{DSI_PKT_SEQ_1_LO, 0x40000308},
|
||||
{DSI_PKT_SEQ_3_LO, 0x3F3B2B08},
|
||||
{DSI_PKT_SEQ_3_HI, 0x2CC},
|
||||
{DSI_PKT_SEQ_5_LO, 0x3F3B2B08},
|
||||
{DSI_PKT_SEQ_5_HI, 0x2CC},
|
||||
{DSI_PKT_LEN_0_1, 0xCE0000},
|
||||
{DSI_PKT_LEN_2_3, 0x87001A2},
|
||||
{DSI_PKT_LEN_4_5, 0x190},
|
||||
{DSI_PKT_LEN_6_7, 0x190},
|
||||
{DSI_HOST_CONTROL, 0},
|
||||
};
|
||||
|
||||
//Clock config.
|
||||
static const cfg_op_t _display_config_6[3] = {
|
||||
{0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE
|
||||
{0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1
|
||||
{0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC
|
||||
};
|
||||
|
||||
//DSI config.
|
||||
static const cfg_op_t _display_config_7[10] = {
|
||||
{DSI_TRIGGER, 0},
|
||||
{DSI_CONTROL, 0},
|
||||
{DSI_SOL_DELAY, 6},
|
||||
{DSI_MAX_THRESHOLD, 0x1E0},
|
||||
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||
{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
|
||||
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
|
||||
{DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
|
||||
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
|
||||
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
|
||||
};
|
||||
|
||||
//MIPI CAL config.
|
||||
static const cfg_op_t _display_config_8[6] = {
|
||||
{0x18, 0},
|
||||
{2, 0xF3F10000},
|
||||
{0x16, 1},
|
||||
{0x18, 0},
|
||||
{0x18, 0x10010},
|
||||
{0x17, 0x300}
|
||||
};
|
||||
|
||||
//DSI config.
|
||||
static const cfg_op_t _display_config_9[4] = {
|
||||
{DSI_PAD_CONTROL_1, 0},
|
||||
{DSI_PAD_CONTROL_2, 0},
|
||||
{DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
|
||||
{DSI_PAD_CONTROL_4, 0}
|
||||
};
|
||||
|
||||
//MIPI CAL config.
|
||||
static const cfg_op_t _display_config_10[16] = {
|
||||
{0xE, 0x200200},
|
||||
{0xF, 0x200200},
|
||||
{0x19, 0x200002},
|
||||
{0x1A, 0x200002},
|
||||
{5, 0},
|
||||
{6, 0},
|
||||
{7, 0},
|
||||
{8, 0},
|
||||
{9, 0},
|
||||
{0xA, 0},
|
||||
{0x10, 0},
|
||||
{0x11, 0},
|
||||
{0x1A, 0},
|
||||
{0x1C, 0},
|
||||
{0x1D, 0},
|
||||
{0, 0x2A000001}
|
||||
};
|
||||
|
||||
//Display A config.
|
||||
static const cfg_op_t _display_config_11[113] = {
|
||||
{DC_CMD_STATE_ACCESS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_WIN_DV_CONTROL, 0},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
/* Setup default YUV colorspace conversion coefficients */
|
||||
{DC_WIN_CSC_YOF, 0xF0},
|
||||
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||
{DC_WIN_CSC_KUR, 0},
|
||||
{DC_WIN_CSC_KVR, 0x198},
|
||||
{DC_WIN_CSC_KUG, 0x39B},
|
||||
{DC_WIN_CSC_KVG, 0x32F},
|
||||
{DC_WIN_CSC_KUB, 0x204},
|
||||
{DC_WIN_CSC_KVB, 0},
|
||||
/* End of color coefficients */
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_WIN_DV_CONTROL, 0},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
/* Setup default YUV colorspace conversion coefficients */
|
||||
{DC_WIN_CSC_YOF, 0xF0},
|
||||
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||
{DC_WIN_CSC_KUR, 0},
|
||||
{DC_WIN_CSC_KVR, 0x198},
|
||||
{DC_WIN_CSC_KUG, 0x39B},
|
||||
{DC_WIN_CSC_KVG, 0x32F},
|
||||
{DC_WIN_CSC_KUB, 0x204},
|
||||
{DC_WIN_CSC_KVB, 0},
|
||||
/* End of color coefficients */
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_WIN_DV_CONTROL, 0},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
/* Setup default YUV colorspace conversion coefficients */
|
||||
{DC_WIN_CSC_YOF, 0xF0},
|
||||
{DC_WIN_CSC_KYRGB, 0x12A},
|
||||
{DC_WIN_CSC_KUR, 0},
|
||||
{DC_WIN_CSC_KVR, 0x198},
|
||||
{DC_WIN_CSC_KUG, 0x39B},
|
||||
{DC_WIN_CSC_KVG, 0x32F},
|
||||
{DC_WIN_CSC_KUB, 0x204},
|
||||
{DC_WIN_CSC_KVB, 0},
|
||||
/* End of color coefficients */
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
|
||||
{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
|
||||
{DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
|
||||
{DC_COM_PIN_OUTPUT_POLARITY(3), 0},
|
||||
{0x4E4, 0},
|
||||
{DC_COM_CRC_CONTROL, 0},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{0x716, 0x10000FF},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{0x716, 0x10000FF},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{0x716, 0x10000FF},
|
||||
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_COMMAND, 0},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
|
||||
{DC_CMD_STATE_ACCESS, 0},
|
||||
/* Set Display timings */
|
||||
{DC_DISP_DISP_TIMING_OPTIONS, 0},
|
||||
{DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1.
|
||||
{DC_DISP_SYNC_WIDTH, 0x10048},
|
||||
{DC_DISP_BACK_PORCH, 0x90048},
|
||||
{DC_DISP_ACTIVE, 0x50002D0},
|
||||
{DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd.
|
||||
/* End of Display timings */
|
||||
{DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
|
||||
{DC_COM_PIN_OUTPUT_ENABLE(1), 0},
|
||||
{DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
|
||||
{DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
|
||||
{DC_DISP_DISP_CLOCK_CONTROL, 0},
|
||||
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX},
|
||||
{DC_DISP_FRONT_PORCH, 0xA0088},
|
||||
{DC_CMD_STATE_ACCESS, 0},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||
{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{DC_CMD_STATE_ACCESS, 0},
|
||||
{DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)},
|
||||
{DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
|
||||
{DC_CMD_DISPLAY_COMMAND_OPTION0, 0}
|
||||
};
|
||||
|
||||
////Display A config.
|
||||
static const cfg_op_t _display_config_12[17] = {
|
||||
{DC_DISP_FRONT_PORCH, 0xA0088},
|
||||
{DC_CMD_INT_MASK, 0},
|
||||
{DC_CMD_STATE_ACCESS, 0},
|
||||
{DC_CMD_INT_ENABLE, 0},
|
||||
{DC_CMD_CONT_SYNCPT_VSYNC, 0},
|
||||
{DC_CMD_DISPLAY_COMMAND, 0},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||
{DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
{DC_CMD_DISPLAY_POWER_CONTROL, 0},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
|
||||
};
|
||||
|
||||
//DSI config.
|
||||
static const cfg_op_t _display_config_13[16] = {
|
||||
{DSI_POWER_CONTROL, 0},
|
||||
{DSI_PAD_CONTROL_1, 0},
|
||||
{DSI_PHY_TIMING_0, 0x6070601},
|
||||
{DSI_PHY_TIMING_1, 0x40A0E05},
|
||||
{DSI_PHY_TIMING_2, 0x30109},
|
||||
{DSI_BTA_TIMING, 0x190A14},
|
||||
{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) },
|
||||
{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
|
||||
{DSI_TO_TALLY, 0},
|
||||
{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
|
||||
{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
|
||||
{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
|
||||
{DSI_MAX_THRESHOLD, 0x40},
|
||||
{DSI_TRIGGER, 0},
|
||||
{DSI_TX_CRC, 0},
|
||||
{DSI_INIT_SEQ_CONTROL, 0}
|
||||
};
|
||||
|
||||
//DSI config (if ver == 0x10).
|
||||
static const cfg_op_t _display_config_14[22] = {
|
||||
{DSI_WR_DATA, 0x439},
|
||||
{DSI_WR_DATA, 0x9483FFB9},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0x2139},
|
||||
{DSI_WR_DATA, 0x191919D5},
|
||||
{DSI_WR_DATA, 0x19191919},
|
||||
{DSI_WR_DATA, 0x19191919},
|
||||
{DSI_WR_DATA, 0x19191919},
|
||||
{DSI_WR_DATA, 0x19191919},
|
||||
{DSI_WR_DATA, 0x19191919},
|
||||
{DSI_WR_DATA, 0x19191919},
|
||||
{DSI_WR_DATA, 0x19191919},
|
||||
{DSI_WR_DATA, 0x19},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0xB39},
|
||||
{DSI_WR_DATA, 0x4F0F41B1},
|
||||
{DSI_WR_DATA, 0xF179A433},
|
||||
{DSI_WR_DATA, 0x2D81},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST},
|
||||
{DSI_WR_DATA, 0x439},
|
||||
{DSI_WR_DATA, 0xB9},
|
||||
{DSI_TRIGGER, DSI_TRIGGER_HOST}
|
||||
};
|
||||
|
||||
//Display A config.
|
||||
static const cfg_op_t cfg_display_one_color[8] = {
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
|
||||
{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display.
|
||||
};
|
||||
|
||||
//Display A config.
|
||||
static const cfg_op_t cfg_display_framebuffer[32] = {
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C.
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B.
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A.
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
|
||||
{DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_WIN_POSITION, 0}, //(0,0)
|
||||
{DC_WIN_H_INITIAL_DDA, 0},
|
||||
{DC_WIN_V_INITIAL_DDA, 0},
|
||||
{DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes.
|
||||
{DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)},
|
||||
{DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels.
|
||||
{DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
|
||||
{DC_WIN_BUFFER_CONTROL, 0},
|
||||
{DC_WINBUF_SURFACE_KIND, 0}, //Regular surface.
|
||||
{DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address.
|
||||
{DC_WINBUF_ADDR_H_OFFSET, 0},
|
||||
{DC_WINBUF_ADDR_V_OFFSET, 0},
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
|
||||
{DC_WIN_WIN_OPTIONS, 0},
|
||||
{DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE
|
||||
{DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD.
|
||||
{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display.
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update.
|
||||
{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request.
|
||||
};
|
||||
1619
sept/sept-secondary/src/display/cfb_console.c
Normal file
1619
sept/sept-secondary/src/display/cfb_console.c
Normal file
File diff suppressed because it is too large
Load diff
57
sept/sept-secondary/src/display/video_fb.h
Normal file
57
sept/sept-secondary/src/display/video_fb.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* (C) Copyright 1997-2002 ELTEC Elektronik AG
|
||||
* Frank Gottschling <fgottschling@eltec.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _VIDEO_FB_H_
|
||||
#define _VIDEO_FB_H_
|
||||
|
||||
#define CONSOLE_BG_COL 0x00
|
||||
#define CONSOLE_FG_COL 0xa0
|
||||
|
||||
/* Try using the small font */
|
||||
#define CONFIG_VIDEO_FONT_SMALL
|
||||
|
||||
/*
|
||||
* Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
|
||||
*/
|
||||
#define GDF__8BIT_INDEX 0
|
||||
#define GDF_15BIT_555RGB 1
|
||||
#define GDF_16BIT_565RGB 2
|
||||
#define GDF_32BIT_X888RGB 3
|
||||
#define GDF_24BIT_888RGB 4
|
||||
#define GDF__8BIT_332RGB 5
|
||||
|
||||
#define CONFIG_VIDEO_FB_LITTLE_ENDIAN
|
||||
#define CONFIG_VIDEO_VISIBLE_COLS 720
|
||||
#define CONFIG_VIDEO_VISIBLE_ROWS 1280
|
||||
#define CONFIG_VIDEO_COLS 768
|
||||
#define CONFIG_VIDEO_PIXEL_SIZE 4
|
||||
#define CONFIG_VIDEO_DATA_FORMAT GDF_32BIT_X888RGB /* BGR actually, but w/e */
|
||||
|
||||
int video_get_col(void);
|
||||
int video_get_row(void);
|
||||
|
||||
int video_init(void *fb);
|
||||
int video_resume(void *fb, int row, int col);
|
||||
void video_puts(const char *s);
|
||||
|
||||
#endif /*_VIDEO_FB_H_ */
|
||||
6181
sept/sept-secondary/src/display/video_font_large.h
Normal file
6181
sept/sept-secondary/src/display/video_font_large.h
Normal file
File diff suppressed because it is too large
Load diff
4630
sept/sept-secondary/src/display/video_font_small.h
Normal file
4630
sept/sept-secondary/src/display/video_font_small.h
Normal file
File diff suppressed because it is too large
Load diff
1089
sept/sept-secondary/src/emc.h
Normal file
1089
sept/sept-secondary/src/emc.h
Normal file
File diff suppressed because it is too large
Load diff
81
sept/sept-secondary/src/exception_handlers.c
Normal file
81
sept/sept-secondary/src/exception_handlers.c
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "exception_handlers.h"
|
||||
#include "utils.h"
|
||||
#include "lib/log.h"
|
||||
|
||||
#define CODE_DUMP_SIZE 0x30
|
||||
#define STACK_DUMP_SIZE 0x60
|
||||
|
||||
extern const uint32_t exception_handler_table[];
|
||||
|
||||
static const char *exception_names[] = {
|
||||
"Reset", "Undefined instruction", "SWI", "Prefetch abort", "Data abort", "Reserved", "IRQ", "FIQ",
|
||||
};
|
||||
|
||||
static const char *register_names[] = {
|
||||
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R8", "R9", "R10", "R11", "R12",
|
||||
"SP", "LR", "PC", "CPSR",
|
||||
};
|
||||
|
||||
void setup_exception_handlers(void) {
|
||||
volatile uint32_t *bpmp_exception_handler_table = (volatile uint32_t *)0x6000F200;
|
||||
for (int i = 0; i < 8; i++) {
|
||||
if (exception_handler_table[i] != 0) {
|
||||
bpmp_exception_handler_table[i] = exception_handler_table[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void exception_handler_main(uint32_t *registers, unsigned int exception_type) {
|
||||
uint8_t code_dump[CODE_DUMP_SIZE];
|
||||
uint8_t stack_dump[STACK_DUMP_SIZE];
|
||||
size_t code_dump_size;
|
||||
size_t stack_dump_size;
|
||||
|
||||
uint32_t pc = registers[15];
|
||||
uint32_t cpsr = registers[16];
|
||||
|
||||
uint32_t instr_addr = pc + ((cpsr & 0x20) ? 2 : 4) - CODE_DUMP_SIZE;
|
||||
|
||||
print(SCREEN_LOG_LEVEL_ERROR, "\nSomething went wrong...\n");
|
||||
|
||||
code_dump_size = safecpy(code_dump, (const void *)instr_addr, CODE_DUMP_SIZE);
|
||||
stack_dump_size = safecpy(stack_dump, (const void *)registers[13], STACK_DUMP_SIZE);
|
||||
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "\nException type: %s\n",
|
||||
exception_names[exception_type]);
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "\nRegisters:\n\n");
|
||||
|
||||
/* Print r0 to pc. */
|
||||
for (int i = 0; i < 16; i += 2) {
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "%-7s%08"PRIX32" %-7s%08"PRIX32"\n",
|
||||
register_names[i], registers[i], register_names[i+1], registers[i+1]);
|
||||
}
|
||||
|
||||
/* Print cpsr. */
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "%-7s%08"PRIX32"\n", register_names[16], registers[16]);
|
||||
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "\nCode dump:\n");
|
||||
hexdump(code_dump, code_dump_size, instr_addr);
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "\nStack dump:\n");
|
||||
hexdump(stack_dump, stack_dump_size, registers[13]);
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "\n");
|
||||
fatal_error("An exception occured!\n");
|
||||
}
|
||||
28
sept/sept-secondary/src/exception_handlers.h
Normal file
28
sept/sept-secondary/src/exception_handlers.h
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_EXCEPTION_HANDLERS_H
|
||||
#define FUSEE_EXCEPTION_HANDLERS_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/* Copies up to len bytes, stops and returns the read length on data fault. */
|
||||
size_t safecpy(void *dst, const void *src, size_t len);
|
||||
|
||||
void setup_exception_handlers(void);
|
||||
|
||||
#endif
|
||||
125
sept/sept-secondary/src/exception_handlers_asm.s
Normal file
125
sept/sept-secondary/src/exception_handlers_asm.s
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
.macro GEN_USUAL_HANDLER name, index, lr_arm_displ, lr_thumb_displ
|
||||
_exception_handler_\name:
|
||||
ldr sp, =_regs
|
||||
stmia sp!, {r0-r7}
|
||||
|
||||
/* Adjust lr to make it point to the location where the exception occured. */
|
||||
mrs r1, spsr
|
||||
tst r1, #0x20
|
||||
subeq lr, lr, #\lr_arm_displ
|
||||
subne lr, lr, #\lr_thumb_displ
|
||||
|
||||
mov r0, sp
|
||||
mov r1, #\index
|
||||
b _exception_handler_common
|
||||
.endm
|
||||
|
||||
.section .text.exception_handlers_asm, "ax", %progbits
|
||||
.arm
|
||||
.align 5
|
||||
|
||||
_exception_handler_common:
|
||||
mrs r2, spsr
|
||||
mrs r3, cpsr
|
||||
|
||||
/* Mask interrupts. */
|
||||
orr r3, #0xC0
|
||||
msr cpsr_cx, r3
|
||||
|
||||
/* Switch to the mode that triggered the interrupt, get the remaining regs, switch back. */
|
||||
ands r4, r2, #0xF
|
||||
moveq r4, #0xF /* usr => sys */
|
||||
bic r5, r3, #0xF
|
||||
orr r5, r4
|
||||
msr cpsr_c, r5
|
||||
stmia r0!, {r8-lr}
|
||||
msr cpsr_c, r3
|
||||
|
||||
str lr, [r0], #4
|
||||
str r2, [r0]
|
||||
|
||||
/* Finally, switch to system mode, setting interrupts and clearing the flags; set sp as well. */
|
||||
msr cpsr_cxsf, #0xDF
|
||||
ldr sp, =(_exception_handler_stack + 0x1000)
|
||||
ldr r0, =_regs
|
||||
bl exception_handler_main
|
||||
b .
|
||||
|
||||
GEN_USUAL_HANDLER undefined_instruction, 1, 4, 2
|
||||
GEN_USUAL_HANDLER swi, 2, 4, 2
|
||||
GEN_USUAL_HANDLER prefetch_abort, 3, 4, 4
|
||||
GEN_USUAL_HANDLER data_abort_normal, 4, 8, 8
|
||||
GEN_USUAL_HANDLER fiq, 7, 4, 4
|
||||
|
||||
_exception_handler_data_abort:
|
||||
/* Mask interrupts (abort mode). */
|
||||
msr cpsr_cx, #0xD7
|
||||
|
||||
adr sp, safecpy+8
|
||||
cmp lr, sp
|
||||
blo _exception_handler_data_abort_normal
|
||||
adr sp, _safecpy_end+8
|
||||
cmp lr, sp
|
||||
bhs _exception_handler_data_abort_normal
|
||||
|
||||
/* Set the flags, set r12 to 0 for safecpy, return from exception. */
|
||||
msr spsr_f, #(1 << 30)
|
||||
mov r12, #0
|
||||
subs pc, lr, #4
|
||||
|
||||
.global safecpy
|
||||
.type safecpy, %function
|
||||
safecpy:
|
||||
push {r4, lr}
|
||||
mov r3, #0
|
||||
movs r12, #1
|
||||
|
||||
_safecpy_loop:
|
||||
ldrb r4, [r1, r3]
|
||||
cmp r12, #0
|
||||
beq _safecpy_loop_end
|
||||
strb r4, [r0, r3]
|
||||
add r3, #1
|
||||
cmp r3, r2
|
||||
blo _safecpy_loop
|
||||
|
||||
_safecpy_loop_end:
|
||||
mov r0, r3
|
||||
pop {r4, lr}
|
||||
bx lr /* Need to do that separately on ARMv4. */
|
||||
|
||||
_safecpy_end:
|
||||
|
||||
.section .rodata.exception_handlers_asm, "a", %progbits
|
||||
.align 2
|
||||
.global exception_handler_table
|
||||
exception_handler_table:
|
||||
.word 0 /* Reset */
|
||||
.word _exception_handler_undefined_instruction
|
||||
.word _exception_handler_swi
|
||||
.word _exception_handler_prefetch_abort
|
||||
.word _exception_handler_data_abort
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* IRQ */
|
||||
.word _exception_handler_fiq
|
||||
|
||||
.section .bss.exception_handlers_asm, "w", %nobits
|
||||
.align 4
|
||||
_exception_handler_stack: .skip 0x1000
|
||||
_regs: .skip (4 * 17)
|
||||
31
sept/sept-secondary/src/flow.h
Normal file
31
sept/sept-secondary/src/flow.h
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_FLOW_CTLR_H
|
||||
#define FUSEE_FLOW_CTLR_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define FLOW_CTLR_BASE 0x60007000
|
||||
#define MAKE_FLOW_REG(n) MAKE_REG32(FLOW_CTLR_BASE + n)
|
||||
|
||||
#define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004)
|
||||
#define FLOW_CTLR_RAM_REPAIR_0 MAKE_FLOW_REG(0x040)
|
||||
#define FLOW_CTLR_FLOW_DBG_QUAL_0 MAKE_FLOW_REG(0x050)
|
||||
#define FLOW_CTLR_L2FLUSH_CONTROL_0 MAKE_FLOW_REG(0x094)
|
||||
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 MAKE_FLOW_REG(0x098)
|
||||
|
||||
#endif
|
||||
136
sept/sept-secondary/src/fs_utils.c
Normal file
136
sept/sept-secondary/src/fs_utils.c
Normal file
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "fs_utils.h"
|
||||
#include "mc.h"
|
||||
#include "lib/fatfs/ff.h"
|
||||
#include "lib/log.h"
|
||||
|
||||
FATFS sd_fs;
|
||||
static bool g_sd_mounted = false;
|
||||
static bool g_sd_initialized = false;
|
||||
static bool g_ahb_redirect_enabled = false;
|
||||
|
||||
bool mount_sd(void)
|
||||
{
|
||||
/* Already mounted. */
|
||||
if (g_sd_mounted)
|
||||
return true;
|
||||
|
||||
/* Enable AHB redirection if necessary. */
|
||||
if (!g_ahb_redirect_enabled) {
|
||||
mc_enable_ahb_redirect();
|
||||
g_ahb_redirect_enabled = true;
|
||||
}
|
||||
|
||||
if (!g_sd_initialized) {
|
||||
/* Initialize SD. */
|
||||
if (sdmmc_device_sd_init(&g_sd_device, &g_sd_sdmmc, SDMMC_BUS_WIDTH_4BIT, SDMMC_SPEED_SDR104))
|
||||
{
|
||||
g_sd_initialized = true;
|
||||
|
||||
/* Mount SD. */
|
||||
if (f_mount(&sd_fs, "", 1) == FR_OK) {
|
||||
print(SCREEN_LOG_LEVEL_INFO, "Mounted SD card!\n");
|
||||
g_sd_mounted = true;
|
||||
}
|
||||
}
|
||||
else
|
||||
fatal_error("Failed to initialize the SD card!.\n");
|
||||
}
|
||||
|
||||
return g_sd_mounted;
|
||||
}
|
||||
|
||||
void unmount_sd(void)
|
||||
{
|
||||
if (g_sd_mounted)
|
||||
{
|
||||
f_mount(NULL, "", 1);
|
||||
sdmmc_device_finish(&g_sd_device);
|
||||
g_sd_mounted = false;
|
||||
}
|
||||
|
||||
/* Disable AHB redirection if necessary. */
|
||||
if (g_ahb_redirect_enabled) {
|
||||
mc_disable_ahb_redirect();
|
||||
g_ahb_redirect_enabled = false;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t get_file_size(const char *filename)
|
||||
{
|
||||
/* SD card hasn't been mounted yet. */
|
||||
if (!g_sd_mounted)
|
||||
return 0;
|
||||
|
||||
/* Open the file for reading. */
|
||||
FIL f;
|
||||
if (f_open(&f, filename, FA_READ) != FR_OK)
|
||||
return 0;
|
||||
|
||||
/* Get the file size. */
|
||||
uint32_t file_size = f_size(&f);
|
||||
|
||||
/* Close the file. */
|
||||
f_close(&f);
|
||||
|
||||
return file_size;
|
||||
}
|
||||
|
||||
int read_from_file(void *dst, uint32_t dst_size, const char *filename)
|
||||
{
|
||||
/* SD card hasn't been mounted yet. */
|
||||
if (!g_sd_mounted)
|
||||
return 0;
|
||||
|
||||
/* Open the file for reading. */
|
||||
FIL f;
|
||||
if (f_open(&f, filename, FA_READ) != FR_OK)
|
||||
return 0;
|
||||
|
||||
/* Sync. */
|
||||
f_sync(&f);
|
||||
|
||||
/* Read from file. */
|
||||
UINT br = 0;
|
||||
int res = f_read(&f, dst, dst_size, &br);
|
||||
f_close(&f);
|
||||
|
||||
return (res == FR_OK) ? (int)br : 0;
|
||||
}
|
||||
|
||||
int write_to_file(void *src, uint32_t src_size, const char *filename)
|
||||
{
|
||||
/* SD card hasn't been mounted yet. */
|
||||
if (!g_sd_mounted)
|
||||
return 0;
|
||||
|
||||
/* Open the file for writing. */
|
||||
FIL f;
|
||||
if (f_open(&f, filename, FA_CREATE_ALWAYS | FA_WRITE) != FR_OK)
|
||||
return 0;
|
||||
|
||||
/* Sync. */
|
||||
f_sync(&f);
|
||||
|
||||
/* Write to file. */
|
||||
UINT bw = 0;
|
||||
int res = f_write(&f, src, src_size, &bw);
|
||||
f_close(&f);
|
||||
|
||||
return (res == FR_OK) ? (int)bw : 0;
|
||||
}
|
||||
35
sept/sept-secondary/src/fs_utils.h
Normal file
35
sept/sept-secondary/src/fs_utils.h
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_FS_UTILS_H
|
||||
#define FUSEE_FS_UTILS_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "sdmmc/sdmmc.h"
|
||||
#include "utils.h"
|
||||
|
||||
sdmmc_t g_sd_sdmmc;
|
||||
sdmmc_device_t g_sd_device;
|
||||
|
||||
bool mount_sd(void);
|
||||
void unmount_sd(void);
|
||||
uint32_t get_file_size(const char *filename);
|
||||
int read_from_file(void *dst, uint32_t dst_size, const char *filename);
|
||||
int write_to_file(void *src, uint32_t src_size, const char *filename);
|
||||
|
||||
#endif
|
||||
260
sept/sept-secondary/src/fuse.c
Normal file
260
sept/sept-secondary/src/fuse.c
Normal file
|
|
@ -0,0 +1,260 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "car.h"
|
||||
#include "fuse.h"
|
||||
#include "timers.h"
|
||||
|
||||
/* Prototypes for internal commands. */
|
||||
void fuse_make_regs_visible(void);
|
||||
|
||||
void fuse_enable_power(void);
|
||||
void fuse_disable_power(void);
|
||||
void fuse_wait_idle(void);
|
||||
|
||||
/* Initialize the fuse driver */
|
||||
void fuse_init(void) {
|
||||
fuse_make_regs_visible();
|
||||
fuse_secondary_private_key_disable();
|
||||
fuse_disable_programming();
|
||||
|
||||
/* TODO: Overrides (iROM patches) and various reads happen here */
|
||||
}
|
||||
|
||||
/* Make all fuse registers visible */
|
||||
void fuse_make_regs_visible(void) {
|
||||
clkrst_enable_fuse_regs(true);
|
||||
}
|
||||
|
||||
/* Enable power to the fuse hardware array */
|
||||
void fuse_enable_power(void) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
fuse->FUSE_PWR_GOOD_SW = 1;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* Disable power to the fuse hardware array */
|
||||
void fuse_disable_power(void) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
fuse->FUSE_PWR_GOOD_SW = 0;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* Wait for the fuse driver to go idle */
|
||||
void fuse_wait_idle(void) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
uint32_t ctrl_val = 0;
|
||||
|
||||
/* Wait for STATE_IDLE */
|
||||
while ((ctrl_val & (0xF0000)) != 0x40000)
|
||||
{
|
||||
udelay(1);
|
||||
ctrl_val = fuse->FUSE_CTRL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read a fuse from the hardware array */
|
||||
uint32_t fuse_hw_read(uint32_t addr) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
fuse_wait_idle();
|
||||
|
||||
/* Program the target address */
|
||||
fuse->FUSE_REG_ADDR = addr;
|
||||
|
||||
/* Enable read operation in control register */
|
||||
uint32_t ctrl_val = fuse->FUSE_CTRL;
|
||||
ctrl_val &= ~0x3;
|
||||
ctrl_val |= 0x1; /* Set FUSE_READ command */
|
||||
fuse->FUSE_CTRL = ctrl_val;
|
||||
|
||||
fuse_wait_idle();
|
||||
|
||||
return fuse->FUSE_REG_READ;
|
||||
}
|
||||
|
||||
/* Write a fuse in the hardware array */
|
||||
void fuse_hw_write(uint32_t value, uint32_t addr) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
fuse_wait_idle();
|
||||
|
||||
/* Program the target address and value */
|
||||
fuse->FUSE_REG_ADDR = addr;
|
||||
fuse->FUSE_REG_WRITE = value;
|
||||
|
||||
/* Enable write operation in control register */
|
||||
uint32_t ctrl_val = fuse->FUSE_CTRL;
|
||||
ctrl_val &= ~0x3;
|
||||
ctrl_val |= 0x2; /* Set FUSE_WRITE command */
|
||||
fuse->FUSE_CTRL = ctrl_val;
|
||||
|
||||
fuse_wait_idle();
|
||||
}
|
||||
|
||||
/* Sense the fuse hardware array into the shadow cache */
|
||||
void fuse_hw_sense(void) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
fuse_wait_idle();
|
||||
|
||||
/* Enable sense operation in control register */
|
||||
uint32_t ctrl_val = fuse->FUSE_CTRL;
|
||||
ctrl_val &= ~0x3;
|
||||
ctrl_val |= 0x3; /* Set FUSE_SENSE command */
|
||||
fuse->FUSE_CTRL = ctrl_val;
|
||||
|
||||
fuse_wait_idle();
|
||||
}
|
||||
|
||||
/* Disables all fuse programming. */
|
||||
void fuse_disable_programming(void) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
fuse->FUSE_DIS_PGM = 1;
|
||||
}
|
||||
|
||||
/* Unknown exactly what this does, but it alters the contents read from the fuse cache. */
|
||||
void fuse_secondary_private_key_disable(void) {
|
||||
volatile tegra_fuse_t *fuse = fuse_get_regs();
|
||||
fuse->FUSE_PRIVATEKEYDISABLE = 0x10;
|
||||
}
|
||||
|
||||
|
||||
/* Read the SKU info register from the shadow cache */
|
||||
uint32_t fuse_get_sku_info(void) {
|
||||
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
|
||||
return fuse_chip->FUSE_SKU_INFO;
|
||||
}
|
||||
|
||||
/* Read the bootrom patch version from a register in the shadow cache */
|
||||
uint32_t fuse_get_bootrom_patch_version(void) {
|
||||
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
|
||||
return fuse_chip->FUSE_SOC_SPEEDO_1;
|
||||
}
|
||||
|
||||
/* Read a spare bit register from the shadow cache */
|
||||
uint32_t fuse_get_spare_bit(uint32_t idx) {
|
||||
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
|
||||
|
||||
if (idx >= 32) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return fuse_chip->FUSE_SPARE_BIT[idx];
|
||||
}
|
||||
|
||||
/* Read a reserved ODM register from the shadow cache */
|
||||
uint32_t fuse_get_reserved_odm(uint32_t idx) {
|
||||
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
|
||||
|
||||
if (idx >= 8) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return fuse_chip->FUSE_RESERVED_ODM[idx];
|
||||
}
|
||||
|
||||
/* Derive the Device ID using values in the shadow cache */
|
||||
uint64_t fuse_get_device_id(void) {
|
||||
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
|
||||
|
||||
uint64_t device_id = 0;
|
||||
uint64_t y_coord = fuse_chip->FUSE_Y_COORDINATE & 0x1FF;
|
||||
uint64_t x_coord = fuse_chip->FUSE_X_COORDINATE & 0x1FF;
|
||||
uint64_t wafer_id = fuse_chip->FUSE_WAFER_ID & 0x3F;
|
||||
uint32_t lot_code = fuse_chip->FUSE_LOT_CODE_0;
|
||||
uint64_t fab_code = fuse_chip->FUSE_FAB_CODE & 0x3F;
|
||||
uint64_t derived_lot_code = 0;
|
||||
for (unsigned int i = 0; i < 5; i++) {
|
||||
derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F);
|
||||
}
|
||||
derived_lot_code &= 0x03FFFFFF;
|
||||
|
||||
device_id |= y_coord << 0;
|
||||
device_id |= x_coord << 9;
|
||||
device_id |= wafer_id << 18;
|
||||
device_id |= derived_lot_code << 24;
|
||||
device_id |= fab_code << 50;
|
||||
return device_id;
|
||||
}
|
||||
|
||||
/* Get the DRAM ID using values in the shadow cache */
|
||||
uint32_t fuse_get_dram_id(void) {
|
||||
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
|
||||
return (fuse_chip->FUSE_RESERVED_ODM[4] >> 3) & 0x7;
|
||||
}
|
||||
|
||||
/* Derive the Hardware Type using values in the shadow cache */
|
||||
uint32_t fuse_get_hardware_type(void) {
|
||||
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
|
||||
|
||||
/* This function is very different between 4.x and < 4.x */
|
||||
uint32_t hardware_type = ((fuse_chip->FUSE_RESERVED_ODM[4] >> 7) & 2) | ((fuse_chip->FUSE_RESERVED_ODM[4] >> 2) & 1);
|
||||
|
||||
/* TODO: choose; if (mkey_get_revision() >= MASTERKEY_REVISION_400_CURRENT) {
|
||||
static const uint32_t types[] = {0,1,4,3};
|
||||
|
||||
hardware_type |= (fuse_chip->FUSE_RESERVED_ODM[4] >> 14) & 0x3C;
|
||||
hardware_type--;
|
||||
return hardware_type > 3 ? 4 : types[hardware_type];
|
||||
} else {*/
|
||||
if (hardware_type >= 1) {
|
||||
return hardware_type > 2 ? 3 : hardware_type - 1;
|
||||
} else if ((fuse_chip->FUSE_SPARE_BIT[9] & 1) == 0) {
|
||||
return 0;
|
||||
} else {
|
||||
return 3;
|
||||
}
|
||||
// }
|
||||
}
|
||||
|
||||
/* Derive the Retail Type using values in the shadow cache */
|
||||
uint32_t fuse_get_retail_type(void) {
|
||||
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
|
||||
|
||||
/* Retail type = IS_RETAIL | UNIT_TYPE */
|
||||
uint32_t retail_type = ((fuse_chip->FUSE_RESERVED_ODM[4] >> 7) & 4) | (fuse_chip->FUSE_RESERVED_ODM[4] & 3);
|
||||
if (retail_type == 4) { /* Standard retail unit, IS_RETAIL | 0. */
|
||||
return 1;
|
||||
} else if (retail_type == 3) { /* Standard dev unit, 0 | DEV_UNIT. */
|
||||
return 0;
|
||||
}
|
||||
return 2; /* IS_RETAIL | DEV_UNIT */
|
||||
}
|
||||
|
||||
/* Derive the 16-byte Hardware Info using values in the shadow cache, and copy to output buffer. */
|
||||
void fuse_get_hardware_info(void *dst) {
|
||||
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
|
||||
uint32_t hw_info[0x4];
|
||||
|
||||
uint32_t unk_hw_fuse = fuse_chip->_0x120 & 0x3F;
|
||||
uint32_t y_coord = fuse_chip->FUSE_Y_COORDINATE & 0x1FF;
|
||||
uint32_t x_coord = fuse_chip->FUSE_X_COORDINATE & 0x1FF;
|
||||
uint32_t wafer_id = fuse_chip->FUSE_WAFER_ID & 0x3F;
|
||||
uint32_t lot_code_0 = fuse_chip->FUSE_LOT_CODE_0;
|
||||
uint32_t lot_code_1 = fuse_chip->FUSE_LOT_CODE_1 & 0x0FFFFFFF;
|
||||
uint32_t fab_code = fuse_chip->FUSE_FAB_CODE & 0x3F;
|
||||
uint32_t vendor_code = fuse_chip->FUSE_VENDOR_CODE & 0xF;
|
||||
|
||||
/* Hardware Info = unk_hw_fuse || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */
|
||||
hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (unk_hw_fuse));
|
||||
hw_info[1] = (uint32_t)((lot_code_0 << 26) | (lot_code_1 >> 2));
|
||||
hw_info[2] = (uint32_t)((fab_code << 26) | (lot_code_0 >> 6));
|
||||
hw_info[3] = (uint32_t)(vendor_code);
|
||||
|
||||
memcpy(dst, hw_info, 0x10);
|
||||
}
|
||||
213
sept/sept-secondary/src/fuse.h
Normal file
213
sept/sept-secondary/src/fuse.h
Normal file
|
|
@ -0,0 +1,213 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_FUSE_H
|
||||
#define FUSEE_FUSE_H
|
||||
|
||||
#define FUSE_BASE 0x7000F800
|
||||
#define FUSE_CHIP_BASE (FUSE_BASE + 0x100)
|
||||
#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n)
|
||||
#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n)
|
||||
|
||||
typedef struct {
|
||||
uint32_t FUSE_CTRL;
|
||||
uint32_t FUSE_REG_ADDR;
|
||||
uint32_t FUSE_REG_READ;
|
||||
uint32_t FUSE_REG_WRITE;
|
||||
uint32_t FUSE_TIME_RD1;
|
||||
uint32_t FUSE_TIME_RD2;
|
||||
uint32_t FUSE_TIME_PGM1;
|
||||
uint32_t FUSE_TIME_PGM2;
|
||||
uint32_t FUSE_PRIV2INTFC;
|
||||
uint32_t FUSE_FUSEBYPASS;
|
||||
uint32_t FUSE_PRIVATEKEYDISABLE;
|
||||
uint32_t FUSE_DIS_PGM;
|
||||
uint32_t FUSE_WRITE_ACCESS;
|
||||
uint32_t FUSE_PWR_GOOD_SW;
|
||||
uint32_t _0x38[0x32];
|
||||
} tegra_fuse_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t FUSE_PRODUCTION_MODE;
|
||||
uint32_t _0x4;
|
||||
uint32_t _0x8;
|
||||
uint32_t _0xC;
|
||||
uint32_t FUSE_SKU_INFO;
|
||||
uint32_t FUSE_CPU_SPEEDO_0;
|
||||
uint32_t FUSE_CPU_IDDQ;
|
||||
uint32_t _0x1C;
|
||||
uint32_t _0x20;
|
||||
uint32_t _0x24;
|
||||
uint32_t FUSE_FT_REV;
|
||||
uint32_t FUSE_CPU_SPEEDO_1;
|
||||
uint32_t FUSE_CPU_SPEEDO_2;
|
||||
uint32_t FUSE_SOC_SPEEDO_0;
|
||||
uint32_t FUSE_SOC_SPEEDO_1;
|
||||
uint32_t FUSE_SOC_SPEEDO_2;
|
||||
uint32_t FUSE_SOC_IDDQ;
|
||||
uint32_t _0x44;
|
||||
uint32_t FUSE_FA;
|
||||
uint32_t _0x4C;
|
||||
uint32_t _0x50;
|
||||
uint32_t _0x54;
|
||||
uint32_t _0x58;
|
||||
uint32_t _0x5C;
|
||||
uint32_t _0x60;
|
||||
uint32_t FUSE_PUBLIC_KEY[0x8];
|
||||
uint32_t FUSE_TSENSOR_1;
|
||||
uint32_t FUSE_TSENSOR_2;
|
||||
uint32_t _0x8C;
|
||||
uint32_t FUSE_CP_REV;
|
||||
uint32_t _0x94;
|
||||
uint32_t FUSE_TSENSOR_0;
|
||||
uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE_REG;
|
||||
uint32_t FUSE_SECURITY_MODE;
|
||||
uint32_t FUSE_PRIVATE_KEY[0x4];
|
||||
uint32_t FUSE_DEVICE_KEY;
|
||||
uint32_t _0xB8;
|
||||
uint32_t _0xBC;
|
||||
uint32_t FUSE_RESERVED_SW;
|
||||
uint32_t FUSE_VP8_ENABLE;
|
||||
uint32_t FUSE_RESERVED_ODM[0x8];
|
||||
uint32_t _0xE8;
|
||||
uint32_t _0xEC;
|
||||
uint32_t FUSE_SKU_USB_CALIB;
|
||||
uint32_t FUSE_SKU_DIRECT_CONFIG;
|
||||
uint32_t _0xF8;
|
||||
uint32_t _0xFC;
|
||||
uint32_t FUSE_VENDOR_CODE;
|
||||
uint32_t FUSE_FAB_CODE;
|
||||
uint32_t FUSE_LOT_CODE_0;
|
||||
uint32_t FUSE_LOT_CODE_1;
|
||||
uint32_t FUSE_WAFER_ID;
|
||||
uint32_t FUSE_X_COORDINATE;
|
||||
uint32_t FUSE_Y_COORDINATE;
|
||||
uint32_t _0x11C;
|
||||
uint32_t _0x120;
|
||||
uint32_t FUSE_SATA_CALIB;
|
||||
uint32_t FUSE_GPU_IDDQ;
|
||||
uint32_t FUSE_TSENSOR_3;
|
||||
uint32_t _0x130;
|
||||
uint32_t _0x134;
|
||||
uint32_t _0x138;
|
||||
uint32_t _0x13C;
|
||||
uint32_t _0x140;
|
||||
uint32_t _0x144;
|
||||
uint32_t FUSE_OPT_SUBREVISION;
|
||||
uint32_t _0x14C;
|
||||
uint32_t _0x150;
|
||||
uint32_t FUSE_TSENSOR_4;
|
||||
uint32_t FUSE_TSENSOR_5;
|
||||
uint32_t FUSE_TSENSOR_6;
|
||||
uint32_t FUSE_TSENSOR_7;
|
||||
uint32_t FUSE_OPT_PRIV_SEC_DIS;
|
||||
uint32_t FUSE_PKC_DISABLE;
|
||||
uint32_t _0x16C;
|
||||
uint32_t _0x170;
|
||||
uint32_t _0x174;
|
||||
uint32_t _0x178;
|
||||
uint32_t _0x17C;
|
||||
uint32_t FUSE_TSENSOR_COMMON;
|
||||
uint32_t _0x184;
|
||||
uint32_t _0x188;
|
||||
uint32_t _0x18C;
|
||||
uint32_t _0x190;
|
||||
uint32_t _0x194;
|
||||
uint32_t _0x198;
|
||||
uint32_t FUSE_DEBUG_AUTH_OVERRIDE;
|
||||
uint32_t _0x1A0;
|
||||
uint32_t _0x1A4;
|
||||
uint32_t _0x1A8;
|
||||
uint32_t _0x1AC;
|
||||
uint32_t _0x1B0;
|
||||
uint32_t _0x1B4;
|
||||
uint32_t _0x1B8;
|
||||
uint32_t _0x1BC;
|
||||
uint32_t _0x1D0;
|
||||
uint32_t FUSE_TSENSOR_8;
|
||||
uint32_t _0x1D8;
|
||||
uint32_t _0x1DC;
|
||||
uint32_t _0x1E0;
|
||||
uint32_t _0x1E4;
|
||||
uint32_t _0x1E8;
|
||||
uint32_t _0x1EC;
|
||||
uint32_t _0x1F0;
|
||||
uint32_t _0x1F4;
|
||||
uint32_t _0x1F8;
|
||||
uint32_t _0x1FC;
|
||||
uint32_t _0x200;
|
||||
uint32_t FUSE_RESERVED_CALIB;
|
||||
uint32_t _0x208;
|
||||
uint32_t _0x20C;
|
||||
uint32_t _0x210;
|
||||
uint32_t _0x214;
|
||||
uint32_t _0x218;
|
||||
uint32_t FUSE_TSENSOR_9;
|
||||
uint32_t _0x220;
|
||||
uint32_t _0x224;
|
||||
uint32_t _0x228;
|
||||
uint32_t _0x22C;
|
||||
uint32_t _0x230;
|
||||
uint32_t _0x234;
|
||||
uint32_t _0x238;
|
||||
uint32_t _0x23C;
|
||||
uint32_t _0x240;
|
||||
uint32_t _0x244;
|
||||
uint32_t _0x248;
|
||||
uint32_t _0x24C;
|
||||
uint32_t FUSE_USB_CALIB_EXT;
|
||||
uint32_t _0x254;
|
||||
uint32_t _0x258;
|
||||
uint32_t _0x25C;
|
||||
uint32_t _0x260;
|
||||
uint32_t _0x264;
|
||||
uint32_t _0x268;
|
||||
uint32_t _0x26C;
|
||||
uint32_t _0x270;
|
||||
uint32_t _0x274;
|
||||
uint32_t _0x278;
|
||||
uint32_t _0x27C;
|
||||
uint32_t FUSE_SPARE_BIT[0x20];
|
||||
} tegra_fuse_chip_t;
|
||||
|
||||
static inline volatile tegra_fuse_t *fuse_get_regs(void) {
|
||||
return (volatile tegra_fuse_t *)FUSE_BASE;
|
||||
}
|
||||
|
||||
static inline volatile tegra_fuse_chip_t *fuse_chip_get_regs(void) {
|
||||
return (volatile tegra_fuse_chip_t *)FUSE_CHIP_BASE;
|
||||
}
|
||||
|
||||
void fuse_init(void);
|
||||
|
||||
uint32_t fuse_hw_read(uint32_t addr);
|
||||
void fuse_hw_write(uint32_t value, uint32_t addr);
|
||||
void fuse_hw_sense(void);
|
||||
void fuse_disable_programming(void);
|
||||
void fuse_secondary_private_key_disable(void);
|
||||
|
||||
uint32_t fuse_get_sku_info(void);
|
||||
uint32_t fuse_get_spare_bit(uint32_t idx);
|
||||
uint32_t fuse_get_reserved_odm(uint32_t idx);
|
||||
|
||||
uint32_t fuse_get_bootrom_patch_version(void);
|
||||
uint64_t fuse_get_device_id(void);
|
||||
uint32_t fuse_get_dram_id(void);
|
||||
uint32_t fuse_get_hardware_type(void);
|
||||
uint32_t fuse_get_retail_type(void);
|
||||
void fuse_get_hardware_info(void *dst);
|
||||
|
||||
#endif
|
||||
145
sept/sept-secondary/src/gpio.c
Normal file
145
sept/sept-secondary/src/gpio.c
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "gpio.h"
|
||||
#include "utils.h"
|
||||
|
||||
/**
|
||||
* Returns a GPIO bank object that corresponds to the given GPIO pin,
|
||||
* which can be created using the TEGRA_GPIO macro or passed from the name macro.
|
||||
*
|
||||
* @param pin The GPIO to get the bank for.
|
||||
* @return The GPIO bank object to use for working with the given bank.
|
||||
*/
|
||||
static volatile tegra_gpio_bank_t *gpio_get_bank(uint32_t pin)
|
||||
{
|
||||
volatile tegra_gpio_t *gpio = gpio_get_regs();
|
||||
uint32_t bank_number = pin >> GPIO_BANK_SHIFT;
|
||||
|
||||
return &gpio->bank[bank_number];
|
||||
}
|
||||
|
||||
/**
|
||||
* @return the port number for working with the given GPIO.
|
||||
*/
|
||||
static volatile uint32_t gpio_get_port(uint32_t pin)
|
||||
{
|
||||
return (pin >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @return a mask to be used to work with the given GPIO
|
||||
*/
|
||||
static volatile uint32_t gpio_get_mask(uint32_t pin)
|
||||
{
|
||||
uint32_t pin_number = pin & GPIO_PIN_MASK;
|
||||
return (1 << pin_number);
|
||||
}
|
||||
|
||||
/**
|
||||
* Performs a simple GPIO configuration operation.
|
||||
*
|
||||
* @param pin The GPIO pin to work with, as created with TEGRA_GPIO, or a named GPIO.
|
||||
* @param should_be_set True iff the relevant bit should be set; or false if it should be cleared.
|
||||
* @param offset The offset into a gpio_bank structure
|
||||
*/
|
||||
static void gpio_simple_register_set(uint32_t pin, bool should_be_set, uint32_t offset)
|
||||
{
|
||||
// Retrieve the register set that corresponds to the given pin and offset.
|
||||
uintptr_t cluster_addr = (uintptr_t)gpio_get_bank(pin) + offset;
|
||||
uint32_t *cluster = (uint32_t *)cluster_addr;
|
||||
|
||||
// Figure out the offset into the cluster,
|
||||
// and the mask to be used.
|
||||
uint32_t port = gpio_get_port(pin);
|
||||
uint32_t mask = gpio_get_mask(pin);
|
||||
|
||||
// Set or clear the bit, as appropriate.
|
||||
if (should_be_set)
|
||||
cluster[port] |= mask;
|
||||
else
|
||||
cluster[port] &= ~mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Performs a simple GPIO configuration operation.
|
||||
*
|
||||
* @param pin The GPIO pin to work with, as created with TEGRA_GPIO, or a named GPIO.
|
||||
* @param should_be_set True iff the relevant bit should be set; or false if it should be cleared.
|
||||
* @param offset The offset into a gpio_bank structure
|
||||
*/
|
||||
static bool gpio_simple_register_get(uint32_t pin, uint32_t offset)
|
||||
{
|
||||
// Retrieve the register set that corresponds to the given pin and offset.
|
||||
uintptr_t cluster_addr = (uintptr_t)gpio_get_bank(pin) + offset;
|
||||
uint32_t *cluster = (uint32_t *)cluster_addr;
|
||||
|
||||
// Figure out the offset into the cluster,
|
||||
// and the mask to be used.
|
||||
uint32_t port = gpio_get_port(pin);
|
||||
uint32_t mask = gpio_get_mask(pin);
|
||||
|
||||
// Convert the given value to a boolean.
|
||||
return !!(cluster[port] & mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Configures a given pin as either GPIO or SFIO.
|
||||
*
|
||||
* @param pin The GPIO pin to work with, as created with TEGRA_GPIO, or a named GPIO.
|
||||
* @param mode The relevant mode.
|
||||
*/
|
||||
void gpio_configure_mode(uint32_t pin, uint32_t mode)
|
||||
{
|
||||
gpio_simple_register_set(pin, mode == GPIO_MODE_GPIO, offsetof(tegra_gpio_bank_t, config));
|
||||
}
|
||||
|
||||
/**
|
||||
* Configures a given pin as either INPUT or OUPUT.
|
||||
*
|
||||
* @param pin The GPIO pin to work with, as created with TEGRA_GPIO, or a named GPIO.
|
||||
* @param direction The relevant direction.
|
||||
*/
|
||||
void gpio_configure_direction(uint32_t pin, uint32_t dir)
|
||||
{
|
||||
gpio_simple_register_set(pin, dir == GPIO_DIRECTION_OUTPUT, offsetof(tegra_gpio_bank_t, direction));
|
||||
}
|
||||
|
||||
/**
|
||||
* Drives a relevant GPIO pin as either HIGH or LOW.
|
||||
*
|
||||
* @param pin The GPIO pin to work with, as created with TEGRA_GPIO, or a named GPIO.
|
||||
* @param mode The relevant mode.
|
||||
*/
|
||||
void gpio_write(uint32_t pin, uint32_t value)
|
||||
{
|
||||
gpio_simple_register_set(pin, value == GPIO_LEVEL_HIGH, offsetof(tegra_gpio_bank_t, out));
|
||||
}
|
||||
|
||||
/**
|
||||
* Drives a relevant GPIO pin as either HIGH or LOW.
|
||||
*
|
||||
* @param pin The GPIO pin to work with, as created with TEGRA_GPIO, or a named GPIO.
|
||||
* @param mode The relevant mode.
|
||||
*/
|
||||
uint32_t gpio_read(uint32_t pin)
|
||||
{
|
||||
return gpio_simple_register_get(pin, offsetof(tegra_gpio_bank_t, in));
|
||||
}
|
||||
127
sept/sept-secondary/src/gpio.h
Normal file
127
sept/sept-secondary/src/gpio.h
Normal file
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_GPIO_H
|
||||
#define FUSEE_GPIO_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define GPIO_BASE 0x6000D000
|
||||
#define MAKE_GPIO_REG(n) MAKE_REG32(GPIO_BASE + n)
|
||||
|
||||
#define TEGRA_GPIO_PORTS 4
|
||||
#define TEGRA_GPIO_BANKS 8
|
||||
#define GPIO_BANK_SHIFT 5
|
||||
#define GPIO_PORT_SHIFT 3
|
||||
#define GPIO_PORT_MASK 0x03
|
||||
#define GPIO_PIN_MASK 0x07
|
||||
|
||||
typedef enum {
|
||||
TEGRA_GPIO_PORT_A = 0,
|
||||
TEGRA_GPIO_PORT_B = 1,
|
||||
TEGRA_GPIO_PORT_C = 2,
|
||||
TEGRA_GPIO_PORT_D = 3,
|
||||
TEGRA_GPIO_PORT_E = 4,
|
||||
TEGRA_GPIO_PORT_F = 5,
|
||||
TEGRA_GPIO_PORT_G = 6,
|
||||
TEGRA_GPIO_PORT_H = 7,
|
||||
TEGRA_GPIO_PORT_I = 8,
|
||||
TEGRA_GPIO_PORT_J = 9,
|
||||
TEGRA_GPIO_PORT_K = 10,
|
||||
TEGRA_GPIO_PORT_L = 11,
|
||||
TEGRA_GPIO_PORT_M = 12,
|
||||
TEGRA_GPIO_PORT_N = 13,
|
||||
TEGRA_GPIO_PORT_O = 14,
|
||||
TEGRA_GPIO_PORT_P = 15,
|
||||
TEGRA_GPIO_PORT_Q = 16,
|
||||
TEGRA_GPIO_PORT_R = 17,
|
||||
TEGRA_GPIO_PORT_S = 18,
|
||||
TEGRA_GPIO_PORT_T = 19,
|
||||
TEGRA_GPIO_PORT_U = 20,
|
||||
TEGRA_GPIO_PORT_V = 21,
|
||||
TEGRA_GPIO_PORT_W = 22,
|
||||
TEGRA_GPIO_PORT_X = 23,
|
||||
TEGRA_GPIO_PORT_Y = 24,
|
||||
TEGRA_GPIO_PORT_Z = 25,
|
||||
TEGRA_GPIO_PORT_AA = 26,
|
||||
TEGRA_GPIO_PORT_BB = 27,
|
||||
TEGRA_GPIO_PORT_CC = 28,
|
||||
TEGRA_GPIO_PORT_DD = 29,
|
||||
TEGRA_GPIO_PORT_EE = 30,
|
||||
TEGRA_GPIO_PORT_FF = 31,
|
||||
} tegra_gpio_port;
|
||||
|
||||
typedef struct {
|
||||
uint32_t config[TEGRA_GPIO_PORTS];
|
||||
uint32_t direction[TEGRA_GPIO_PORTS];
|
||||
uint32_t out[TEGRA_GPIO_PORTS];
|
||||
uint32_t in[TEGRA_GPIO_PORTS];
|
||||
uint32_t int_status[TEGRA_GPIO_PORTS];
|
||||
uint32_t int_enable[TEGRA_GPIO_PORTS];
|
||||
uint32_t int_level[TEGRA_GPIO_PORTS];
|
||||
uint32_t int_clear[TEGRA_GPIO_PORTS];
|
||||
uint32_t masked_config[TEGRA_GPIO_PORTS];
|
||||
uint32_t masked_dir_out[TEGRA_GPIO_PORTS];
|
||||
uint32_t masked_out[TEGRA_GPIO_PORTS];
|
||||
uint32_t masked_in[TEGRA_GPIO_PORTS];
|
||||
uint32_t masked_int_status[TEGRA_GPIO_PORTS];
|
||||
uint32_t masked_int_enable[TEGRA_GPIO_PORTS];
|
||||
uint32_t masked_int_level[TEGRA_GPIO_PORTS];
|
||||
uint32_t masked_int_clear[TEGRA_GPIO_PORTS];
|
||||
} tegra_gpio_bank_t;
|
||||
|
||||
typedef struct {
|
||||
tegra_gpio_bank_t bank[TEGRA_GPIO_BANKS];
|
||||
} tegra_gpio_t;
|
||||
|
||||
static inline volatile tegra_gpio_t *gpio_get_regs(void)
|
||||
{
|
||||
return (volatile tegra_gpio_t *)GPIO_BASE;
|
||||
}
|
||||
|
||||
#define TEGRA_GPIO(port, offset) \
|
||||
((TEGRA_GPIO_PORT_##port * 8) + offset)
|
||||
|
||||
/* Mode select */
|
||||
#define GPIO_MODE_GPIO 0
|
||||
#define GPIO_MODE_SFIO 1
|
||||
|
||||
/* Direction */
|
||||
#define GPIO_DIRECTION_INPUT 0
|
||||
#define GPIO_DIRECTION_OUTPUT 1
|
||||
|
||||
/* Level */
|
||||
#define GPIO_LEVEL_LOW 0
|
||||
#define GPIO_LEVEL_HIGH 1
|
||||
|
||||
/* Named GPIOs */
|
||||
#define GPIO_BUTTON_VOL_DOWN TEGRA_GPIO(X, 7)
|
||||
#define GPIO_BUTTON_VOL_UP TEGRA_GPIO(X, 6)
|
||||
#define GPIO_MICROSD_CARD_DETECT TEGRA_GPIO(Z, 1)
|
||||
#define GPIO_MICROSD_WRITE_PROTECT TEGRA_GPIO(Z, 4)
|
||||
#define GPIO_MICROSD_SUPPLY_ENABLE TEGRA_GPIO(E, 4)
|
||||
#define GPIO_LCD_BL_P5V TEGRA_GPIO(I, 0)
|
||||
#define GPIO_LCD_BL_N5V TEGRA_GPIO(I, 1)
|
||||
#define GPIO_LCD_BL_PWM TEGRA_GPIO(V, 0)
|
||||
#define GPIO_LCD_BL_EN TEGRA_GPIO(V, 1)
|
||||
#define GPIO_LCD_BL_RST TEGRA_GPIO(V, 2)
|
||||
|
||||
void gpio_configure_mode(uint32_t pin, uint32_t mode);
|
||||
void gpio_configure_direction(uint32_t pin, uint32_t dir);
|
||||
void gpio_write(uint32_t pin, uint32_t value);
|
||||
uint32_t gpio_read(uint32_t pin);
|
||||
|
||||
#endif
|
||||
298
sept/sept-secondary/src/hwinit.c
Normal file
298
sept/sept-secondary/src/hwinit.c
Normal file
|
|
@ -0,0 +1,298 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 CTCaer
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "hwinit.h"
|
||||
#include "apb_misc.h"
|
||||
#include "car.h"
|
||||
#include "di.h"
|
||||
#include "fuse.h"
|
||||
#include "gpio.h"
|
||||
#include "i2c.h"
|
||||
#include "max77620.h"
|
||||
#include "mc.h"
|
||||
#include "pinmux.h"
|
||||
#include "pmc.h"
|
||||
#include "se.h"
|
||||
#include "sdram.h"
|
||||
#include "sysctr0.h"
|
||||
#include "sysreg.h"
|
||||
#include "timers.h"
|
||||
#include "uart.h"
|
||||
|
||||
void config_oscillators()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
|
||||
car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4);
|
||||
|
||||
SYSCTR0_CNTFID0_0 = 19200000;
|
||||
TIMERUS_USEC_CFG_0 = 0x45F;
|
||||
|
||||
car->osc_ctrl = 0x50000071;
|
||||
pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE);
|
||||
pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFBFFFFF) | 0x400000);
|
||||
pmc->cntrl2 = ((pmc->cntrl2 & 0xFFFFEFFF) | 0x1000);
|
||||
pmc->scratch188 = ((pmc->scratch188 & 0xFCFFFFFF) | 0x2000000);
|
||||
car->clk_sys_rate = 0x10;
|
||||
car->pllmb_base &= 0xBFFFFFFF;
|
||||
pmc->tsc_mult = ((pmc->tsc_mult & 0xFFFF0000) | 0x249F); /* 0x249F = 19200000 * (16 / 32.768 kHz) */
|
||||
car->sclk_brst_pol = 0x20004444;
|
||||
car->super_sclk_div = 0x80000000;
|
||||
car->clk_sys_rate = 2;
|
||||
}
|
||||
|
||||
void config_gpios()
|
||||
{
|
||||
volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
|
||||
|
||||
pinmux->uart2_tx = 0;
|
||||
pinmux->uart3_tx = 0;
|
||||
pinmux->pe6 = PINMUX_INPUT;
|
||||
pinmux->ph6 = PINMUX_INPUT;
|
||||
|
||||
gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(TEGRA_GPIO(E, 6), GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(TEGRA_GPIO(H, 6), GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(TEGRA_GPIO(G, 0), GPIO_DIRECTION_INPUT);
|
||||
gpio_configure_direction(TEGRA_GPIO(D, 1), GPIO_DIRECTION_INPUT);
|
||||
gpio_configure_direction(TEGRA_GPIO(E, 6), GPIO_DIRECTION_INPUT);
|
||||
gpio_configure_direction(TEGRA_GPIO(H, 6), GPIO_DIRECTION_INPUT);
|
||||
|
||||
pinmux->gen1_i2c_scl = PINMUX_INPUT;
|
||||
pinmux->gen1_i2c_sda = PINMUX_INPUT;
|
||||
pinmux->pwr_i2c_scl = PINMUX_INPUT;
|
||||
pinmux->pwr_i2c_sda = PINMUX_INPUT;
|
||||
pinmux->uart1_rx = 0;
|
||||
pinmux->uart1_tx = (PINMUX_INPUT | PINMUX_PULL_UP);
|
||||
pinmux->uart1_rts = 0;
|
||||
pinmux->uart1_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
|
||||
|
||||
/* Configure volume up/down as inputs. */
|
||||
gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO);
|
||||
gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO);
|
||||
gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT);
|
||||
gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT);
|
||||
}
|
||||
|
||||
void config_pmc_scratch()
|
||||
{
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
|
||||
pmc->scratch20 &= 0xFFF3FFFF;
|
||||
pmc->scratch190 &= 0xFFFFFFFE;
|
||||
pmc->secure_scratch21 |= 0x10;
|
||||
}
|
||||
|
||||
void mbist_workaround()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
|
||||
car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF);
|
||||
car->plld_base |= 0x40800000u;
|
||||
car->rst_dev_y_clr = 0x40;
|
||||
car->rst_dev_x_clr = 0x40000;
|
||||
car->rst_dev_l_clr = 0x18000000;
|
||||
udelay(2);
|
||||
|
||||
/* Setup I2S. */
|
||||
MAKE_I2S_REG(0x0A0) |= 0x400;
|
||||
MAKE_I2S_REG(0x088) &= 0xFFFFFFFE;
|
||||
MAKE_I2S_REG(0x1A0) |= 0x400;
|
||||
MAKE_I2S_REG(0x188) &= 0xFFFFFFFE;
|
||||
MAKE_I2S_REG(0x2A0) |= 0x400;
|
||||
MAKE_I2S_REG(0x288) &= 0xFFFFFFFE;
|
||||
MAKE_I2S_REG(0x3A0) |= 0x400;
|
||||
MAKE_I2S_REG(0x388) &= 0xFFFFFFFE;
|
||||
MAKE_I2S_REG(0x4A0) |= 0x400;
|
||||
MAKE_I2S_REG(0x488) &= 0xFFFFFFFE;
|
||||
|
||||
MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4;
|
||||
MAKE_VIC_REG(0x8C) = 0xFFFFFFFF;
|
||||
udelay(2);
|
||||
|
||||
/* Set devices in reset. */
|
||||
car->rst_dev_y_set = 0x40;
|
||||
car->rst_dev_l_set = 0x18000000;
|
||||
car->rst_dev_x_set = 0x40000;
|
||||
|
||||
/* Clock out enables. */
|
||||
car->clk_out_enb_h = 0xC0;
|
||||
car->clk_out_enb_l = 0x80000130;
|
||||
car->clk_out_enb_u = 0x1F00200;
|
||||
car->clk_out_enb_v = 0x80400808;
|
||||
car->clk_out_enb_w = 0x402000FC;
|
||||
car->clk_out_enb_x = 0x23000780;
|
||||
car->clk_out_enb_y = 0x300;
|
||||
|
||||
/* LVL2 clock gate overrides. */
|
||||
car->lvl2_clk_gate_ovra = 0;
|
||||
car->lvl2_clk_gate_ovrb = 0;
|
||||
car->lvl2_clk_gate_ovrc = 0;
|
||||
car->lvl2_clk_gate_ovrd = 0;
|
||||
car->lvl2_clk_gate_ovre = 0;
|
||||
|
||||
/* Configure clock sources. */
|
||||
car->plld_base &= 0x1F7FFFFF;
|
||||
car->clk_source_sor1 &= 0xFFFF3FFF;
|
||||
car->clk_source_vi = ((car->clk_source_vi & 0x1FFFFFFF) | 0x80000000);
|
||||
car->clk_source_host1x = ((car->clk_source_host1x & 0x1FFFFFFF) | 0x80000000);
|
||||
car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000);
|
||||
}
|
||||
|
||||
void config_se_brom()
|
||||
{
|
||||
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
|
||||
/* Bootrom part we skipped. */
|
||||
uint32_t sbk[4] = {fuse_chip->FUSE_PRIVATE_KEY[0], fuse_chip->FUSE_PRIVATE_KEY[1], fuse_chip->FUSE_PRIVATE_KEY[2], fuse_chip->FUSE_PRIVATE_KEY[3]};
|
||||
set_aes_keyslot(0xE, sbk, 0x10);
|
||||
|
||||
/* Lock SBK from being read. */
|
||||
se->AES_KEYSLOT_FLAGS[0xE] = 0x7E;
|
||||
|
||||
/* This memset needs to happen here, else TZRAM will behave weirdly later on. */
|
||||
memset((void *)0x7C010000, 0, 0x10000);
|
||||
|
||||
pmc->crypto_op = 0;
|
||||
se->INT_STATUS_REG = 0x1F;
|
||||
|
||||
/* Lock SSK (although it's not set and unused anyways). */
|
||||
se->AES_KEYSLOT_FLAGS[0xF] = 0x7E;
|
||||
|
||||
/* Clear the boot reason to avoid problems later */
|
||||
pmc->scratch200 = 0;
|
||||
pmc->reset_status = 0;
|
||||
}
|
||||
|
||||
void nx_hwinit()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
|
||||
/* This stuff was handled by whatever loaded us. */
|
||||
/*
|
||||
config_se_brom();
|
||||
|
||||
AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
|
||||
pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);
|
||||
|
||||
mbist_workaround();
|
||||
|
||||
clkrst_reboot(CARDEVICE_SE);
|
||||
|
||||
fuse_init();
|
||||
|
||||
mc_enable();
|
||||
|
||||
config_oscillators();
|
||||
*/
|
||||
|
||||
/* Disable pinmux tristate input clamping. */
|
||||
APB_MISC_PP_PINMUX_GLOBAL_0 = 0;
|
||||
|
||||
/* Configure GPIOs. */
|
||||
/* NOTE: [3.0.0+] Part of the GPIO configuration is skipped if the unit is SDEV. */
|
||||
/* NOTE: [6.0.0+] The GPIO configuration's order was changed a bit. */
|
||||
config_gpios();
|
||||
|
||||
/* Uncomment for UART debugging. */
|
||||
/*
|
||||
clkrst_reboot(CARDEVICE_UARTC);
|
||||
uart_init(UART_C, 115200);
|
||||
*/
|
||||
|
||||
/* Reboot CL-DVFS. */
|
||||
clkrst_reboot(CARDEVICE_CL_DVFS);
|
||||
|
||||
/* Reboot I2C1. */
|
||||
clkrst_reboot(CARDEVICE_I2C1);
|
||||
|
||||
/* Reboot I2C5. */
|
||||
clkrst_reboot(CARDEVICE_I2C5);
|
||||
|
||||
/* Reboot SE. */
|
||||
/* NOTE: [4.0.0+] This was removed. */
|
||||
/* clkrst_reboot(CARDEVICE_SE); */
|
||||
|
||||
/* Reboot unknown device. */
|
||||
clkrst_reboot(CARDEVICE_UNK);
|
||||
|
||||
/* Initialize I2C1. */
|
||||
/* NOTE: [6.0.0+] This was moved to after the PMIC is configured. */
|
||||
i2c_init(I2C_1);
|
||||
|
||||
/* Initialize I2C5. */
|
||||
i2c_init(I2C_5);
|
||||
|
||||
/* Configure the PMIC. */
|
||||
uint8_t val = 0x40;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1);
|
||||
val = 0x60;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1);
|
||||
val = 0x38;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG0, &val, 1);
|
||||
val = 0x3A;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG1, &val, 1);
|
||||
val = 0x38;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG2, &val, 1);
|
||||
val = 0xF;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO4, &val, 1);
|
||||
val = 0xC7;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO8, &val, 1);
|
||||
val = 0x4F;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD0, &val, 1);
|
||||
val = 0x29;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD1, &val, 1);
|
||||
val = 0x1B;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1);
|
||||
|
||||
/* NOTE: [3.0.0+] This was added. */
|
||||
val = 0x22;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_GPIO3, &val, 1);
|
||||
|
||||
/* TODO: In 3.x+, if the unit is SDEV, the MBLPD bit is set. */
|
||||
/*
|
||||
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
|
||||
val |= 0x40;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
|
||||
*/
|
||||
|
||||
/* Configure SD0 voltage. */
|
||||
val = 42; /* 42 = (1125000 - 600000) / 12500 -> 1.125V */
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
|
||||
|
||||
/* Configure and lock PMC scratch registers. */
|
||||
/* NOTE: [4.0.0+] This was removed. */
|
||||
config_pmc_scratch();
|
||||
|
||||
/* Set super clock burst policy. */
|
||||
car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333);
|
||||
|
||||
/* Configure memory controller carveouts. */
|
||||
/* NOTE: [4.0.0+] This is now done in the Secure Monitor. */
|
||||
/* mc_config_carveout(); */
|
||||
|
||||
/* Initialize SDRAM. */
|
||||
sdram_init();
|
||||
|
||||
/* Save SDRAM LP0 parameters. */
|
||||
sdram_lp0_save_params(sdram_get_params());
|
||||
}
|
||||
27
sept/sept-secondary/src/hwinit.h
Normal file
27
sept/sept-secondary/src/hwinit.h
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 CTCaer
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_HWINIT_H_
|
||||
#define FUSEE_HWINIT_H_
|
||||
|
||||
#define I2S_BASE 0x702D1000
|
||||
#define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n)
|
||||
|
||||
void nx_hwinit();
|
||||
|
||||
#endif
|
||||
219
sept/sept-secondary/src/i2c.c
Normal file
219
sept/sept-secondary/src/i2c.c
Normal file
|
|
@ -0,0 +1,219 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "i2c.h"
|
||||
#include "utils.h"
|
||||
#include "timers.h"
|
||||
|
||||
/* Prototypes for internal commands. */
|
||||
volatile tegra_i2c_t *i2c_get_registers_from_id(unsigned int id);
|
||||
void i2c_load_config(volatile tegra_i2c_t *regs);
|
||||
|
||||
bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size);
|
||||
bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size);
|
||||
|
||||
bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size);
|
||||
bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size);
|
||||
|
||||
/* Initialize I2C based on registers. */
|
||||
void i2c_init(unsigned int id) {
|
||||
volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id);
|
||||
|
||||
/* Setup divisor, and clear the bus. */
|
||||
regs->I2C_I2C_CLK_DIVISOR_REGISTER_0 = 0x50001;
|
||||
regs->I2C_I2C_BUS_CLEAR_CONFIG_0 = 0x90003;
|
||||
|
||||
/* Load hardware configuration. */
|
||||
i2c_load_config(regs);
|
||||
|
||||
/* Wait a while until BUS_CLEAR_DONE is set. */
|
||||
for (unsigned int i = 0; i < 10; i++) {
|
||||
udelay(20000);
|
||||
if (regs->I2C_INTERRUPT_STATUS_REGISTER_0 & 0x800) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read the BUS_CLEAR_STATUS. Result doesn't matter. */
|
||||
regs->I2C_I2C_BUS_CLEAR_STATUS_0;
|
||||
|
||||
/* Read and set the Interrupt Status. */
|
||||
uint32_t int_status = regs->I2C_INTERRUPT_STATUS_REGISTER_0;
|
||||
regs->I2C_INTERRUPT_STATUS_REGISTER_0 = int_status;
|
||||
}
|
||||
|
||||
/* Sets a bit in a PMIC register over I2C during CPU shutdown. */
|
||||
void i2c_send_pmic_cpu_shutdown_cmd(void) {
|
||||
uint32_t val = 0;
|
||||
/* PMIC == Device 4:3C. */
|
||||
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, 0x41, &val, 1);
|
||||
val |= 4;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, 0x41, &val, 1);
|
||||
}
|
||||
|
||||
/* Queries the value of TI charger bit over I2C. */
|
||||
bool i2c_query_ti_charger_bit_7(void) {
|
||||
uint32_t val = 0;
|
||||
/* TI Charger = Device 0:6B. */
|
||||
i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
|
||||
return (val & 0x80) != 0;
|
||||
}
|
||||
|
||||
/* Clears TI charger bit over I2C. */
|
||||
void i2c_clear_ti_charger_bit_7(void) {
|
||||
uint32_t val = 0;
|
||||
/* TI Charger = Device 0:6B. */
|
||||
i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
|
||||
val &= 0x7F;
|
||||
i2c_send(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
|
||||
}
|
||||
|
||||
/* Sets TI charger bit over I2C. */
|
||||
void i2c_set_ti_charger_bit_7(void) {
|
||||
uint32_t val = 0;
|
||||
/* TI Charger = Device 0:6B. */
|
||||
i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
|
||||
val |= 0x80;
|
||||
i2c_send(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
|
||||
}
|
||||
|
||||
/* Get registers pointer based on I2C ID. */
|
||||
volatile tegra_i2c_t *i2c_get_registers_from_id(unsigned int id) {
|
||||
switch (id) {
|
||||
case I2C_1:
|
||||
return I2C1_REGS;
|
||||
case I2C_2:
|
||||
return I2C2_REGS;
|
||||
case I2C_3:
|
||||
return I2C3_REGS;
|
||||
case I2C_4:
|
||||
return I2C4_REGS;
|
||||
case I2C_5:
|
||||
return I2C5_REGS;
|
||||
case I2C_6:
|
||||
return I2C6_REGS;
|
||||
default:
|
||||
generic_panic();
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Load hardware config for I2C4. */
|
||||
void i2c_load_config(volatile tegra_i2c_t *regs) {
|
||||
/* Set MSTR_CONFIG_LOAD, TIMEOUT_CONFIG_LOAD, undocumented bit. */
|
||||
regs->I2C_I2C_CONFIG_LOAD_0 = 0x25;
|
||||
|
||||
/* Wait a bit for master config to be loaded. */
|
||||
for (unsigned int i = 0; i < 20; i++) {
|
||||
udelay(1);
|
||||
if (!(regs->I2C_I2C_CONFIG_LOAD_0 & 1)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Reads a register from a device over I2C, writes result to output. */
|
||||
bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size) {
|
||||
volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id);
|
||||
uint32_t val = r;
|
||||
|
||||
/* Write single byte register ID to device. */
|
||||
if (!i2c_write(regs, device, &val, 1)) {
|
||||
return false;
|
||||
}
|
||||
/* Limit output size to 32-bits. */
|
||||
if (dst_size > 4) {
|
||||
return false;
|
||||
}
|
||||
|
||||
return i2c_read(regs, device, dst, dst_size);
|
||||
}
|
||||
|
||||
/* Writes a value to a register over I2C. */
|
||||
bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size) {
|
||||
uint32_t val = r;
|
||||
if (src_size == 0) {
|
||||
return true;
|
||||
} else if (src_size <= 3) {
|
||||
memcpy(((uint8_t *)&val) + 1, src, src_size);
|
||||
return i2c_write(i2c_get_registers_from_id(id), device, &val, src_size + 1);
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/* Writes bytes to device over I2C. */
|
||||
bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size) {
|
||||
if (src_size > 4) {
|
||||
return false;
|
||||
} else if (src_size == 0) {
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Set device for 7-bit write mode. */
|
||||
regs->I2C_I2C_CMD_ADDR0_0 = device << 1;
|
||||
|
||||
/* Load in data to write. */
|
||||
regs->I2C_I2C_CMD_DATA1_0 = read32le(src, 0);
|
||||
|
||||
/* Set config with LENGTH = src_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */
|
||||
regs->I2C_I2C_CNFG_0 = ((src_size << 1) - 2) | 0x2800;
|
||||
|
||||
i2c_load_config(regs);
|
||||
|
||||
/* Config |= SEND; */
|
||||
regs->I2C_I2C_CNFG_0 = ((regs->I2C_I2C_CNFG_0 & 0xFFFFFDFF) | 0x200);
|
||||
|
||||
while (regs->I2C_I2C_STATUS_0 & 0x100) {
|
||||
/* Wait until not busy. */
|
||||
}
|
||||
|
||||
/* Return CMD1_STAT == SL1_XFER_SUCCESSFUL. */
|
||||
return (regs->I2C_I2C_STATUS_0 & 0xF) == 0;
|
||||
}
|
||||
|
||||
/* Reads bytes from device over I2C. */
|
||||
bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size) {
|
||||
if (dst_size > 4) {
|
||||
return false;
|
||||
} else if (dst_size == 0) {
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Set device for 7-bit read mode. */
|
||||
regs->I2C_I2C_CMD_ADDR0_0 = (device << 1) | 1;
|
||||
|
||||
/* Set config with LENGTH = dst_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */
|
||||
regs->I2C_I2C_CNFG_0 = ((dst_size << 1) - 2) | 0x2840;
|
||||
|
||||
i2c_load_config(regs);
|
||||
|
||||
/* Config |= SEND; */
|
||||
regs->I2C_I2C_CNFG_0 = ((regs->I2C_I2C_CNFG_0 & 0xFFFFFDFF) | 0x200);
|
||||
|
||||
while (regs->I2C_I2C_STATUS_0 & 0x100) {
|
||||
/* Wait until not busy. */
|
||||
}
|
||||
|
||||
/* Ensure success. */
|
||||
if ((regs->I2C_I2C_STATUS_0 & 0xF) != 0) {
|
||||
return false;
|
||||
}
|
||||
|
||||
uint32_t val = regs->I2C_I2C_CMD_DATA1_0;
|
||||
memcpy(dst, &val, dst_size);
|
||||
return true;
|
||||
}
|
||||
101
sept/sept-secondary/src/i2c.h
Normal file
101
sept/sept-secondary/src/i2c.h
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_I2C_H
|
||||
#define FUSEE_I2C_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#define I2C1234_BASE 0x7000C000
|
||||
#define I2C56_BASE 0x7000D000
|
||||
|
||||
#define I2C_1 0
|
||||
#define I2C_2 1
|
||||
#define I2C_3 2
|
||||
#define I2C_4 3
|
||||
#define I2C_5 4
|
||||
#define I2C_6 5
|
||||
|
||||
#define MAX77621_CPU_I2C_ADDR 0x1B
|
||||
#define MAX77621_GPU_I2C_ADDR 0x1C
|
||||
#define MAX17050_I2C_ADDR 0x36
|
||||
#define MAX77620_PWR_I2C_ADDR 0x3C
|
||||
#define MAX77620_RTC_I2C_ADDR 0x68
|
||||
#define BQ24193_I2C_ADDR 0x6B
|
||||
|
||||
typedef struct {
|
||||
uint32_t I2C_I2C_CNFG_0;
|
||||
uint32_t I2C_I2C_CMD_ADDR0_0;
|
||||
uint32_t I2C_I2C_CMD_ADDR1_0;
|
||||
uint32_t I2C_I2C_CMD_DATA1_0;
|
||||
uint32_t I2C_I2C_CMD_DATA2_0;
|
||||
uint32_t _0x14;
|
||||
uint32_t _0x18;
|
||||
uint32_t I2C_I2C_STATUS_0;
|
||||
uint32_t I2C_I2C_SL_CNFG_0;
|
||||
uint32_t I2C_I2C_SL_RCVD_0;
|
||||
uint32_t I2C_I2C_SL_STATUS_0;
|
||||
uint32_t I2C_I2C_SL_ADDR1_0;
|
||||
uint32_t I2C_I2C_SL_ADDR2_0;
|
||||
uint32_t I2C_I2C_TLOW_SEXT_0;
|
||||
uint32_t _0x38;
|
||||
uint32_t I2C_I2C_SL_DELAY_COUNT_0;
|
||||
uint32_t I2C_I2C_SL_INT_MASK_0;
|
||||
uint32_t I2C_I2C_SL_INT_SOURCE_0;
|
||||
uint32_t I2C_I2C_SL_INT_SET_0;
|
||||
uint32_t _0x4C;
|
||||
uint32_t I2C_I2C_TX_PACKET_FIFO_0;
|
||||
uint32_t I2C_I2C_RX_FIFO_0;
|
||||
uint32_t I2C_PACKET_TRANSFER_STATUS_0;
|
||||
uint32_t I2C_FIFO_CONTROL_0;
|
||||
uint32_t I2C_FIFO_STATUS_0;
|
||||
uint32_t I2C_INTERRUPT_MASK_REGISTER_0;
|
||||
uint32_t I2C_INTERRUPT_STATUS_REGISTER_0;
|
||||
uint32_t I2C_I2C_CLK_DIVISOR_REGISTER_0;
|
||||
uint32_t I2C_I2C_INTERRUPT_SOURCE_REGISTER_0;
|
||||
uint32_t I2C_I2C_INTERRUPT_SET_REGISTER_0;
|
||||
uint32_t I2C_I2C_SLV_TX_PACKET_FIFO_0;
|
||||
uint32_t I2C_I2C_SLV_RX_FIFO_0;
|
||||
uint32_t I2C_I2C_SLV_PACKET_STATUS_0;
|
||||
uint32_t I2C_I2C_BUS_CLEAR_CONFIG_0;
|
||||
uint32_t I2C_I2C_BUS_CLEAR_STATUS_0;
|
||||
uint32_t I2C_I2C_CONFIG_LOAD_0;
|
||||
uint32_t _0x90;
|
||||
uint32_t I2C_I2C_INTERFACE_TIMING_0_0;
|
||||
uint32_t I2C_I2C_INTERFACE_TIMING_1_0;
|
||||
uint32_t I2C_I2C_HS_INTERFACE_TIMING_0_0;
|
||||
uint32_t I2C_I2C_HS_INTERFACE_TIMING_1_0;
|
||||
} tegra_i2c_t;
|
||||
|
||||
#define I2C1_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x000))
|
||||
#define I2C2_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x400))
|
||||
#define I2C3_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x500))
|
||||
#define I2C4_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x700))
|
||||
#define I2C5_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x000))
|
||||
#define I2C6_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x100))
|
||||
|
||||
void i2c_init(unsigned int id);
|
||||
bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size);
|
||||
bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size);
|
||||
|
||||
void i2c_send_pmic_cpu_shutdown_cmd(void);
|
||||
bool i2c_query_ti_charger_bit_7(void);
|
||||
void i2c_clear_ti_charger_bit_7(void);
|
||||
void i2c_set_ti_charger_bit_7(void);
|
||||
|
||||
#endif
|
||||
146
sept/sept-secondary/src/init.c
Normal file
146
sept/sept-secondary/src/init.c
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
#include <malloc.h>
|
||||
#include <sys/iosupport.h>
|
||||
#include "utils.h"
|
||||
|
||||
void __libc_init_array(void);
|
||||
void __libc_fini_array(void);
|
||||
|
||||
extern uint8_t __bss_start__[], __bss_end__[];
|
||||
extern uint8_t __heap_start__[], __heap_end__[];
|
||||
|
||||
extern char *fake_heap_start;
|
||||
extern char *fake_heap_end;
|
||||
|
||||
int __program_argc;
|
||||
void **__program_argv;
|
||||
|
||||
void __attribute__((noreturn)) __program_exit(int rc);
|
||||
void __attribute__((noreturn)) (*__program_exit_callback)(int rc) = NULL;
|
||||
|
||||
static void __program_parse_argc_argv(int argc, char *argdata);
|
||||
static void __program_cleanup_argv(void);
|
||||
|
||||
static void __program_init_heap(void) {
|
||||
fake_heap_start = (char*)__heap_start__;
|
||||
fake_heap_end = (char*)__heap_end__;
|
||||
}
|
||||
|
||||
static void __program_init_newlib_hooks(void) {
|
||||
__syscalls.exit = __program_exit; /* For exit, etc. */
|
||||
}
|
||||
|
||||
static void __program_move_additional_sections(void) {
|
||||
#if defined(FUSEE_STAGE1_SRC) || defined(FUSEE_STAGE2_SRC)
|
||||
extern uint8_t __chainloader_lma__[], __chainloader_start__[], __chainloader_bss_start__[], __chainloader_end__[];
|
||||
memcpy(__chainloader_start__, __chainloader_lma__, __chainloader_bss_start__ - __chainloader_start__);
|
||||
memset(__chainloader_bss_start__, 0, __chainloader_end__ - __chainloader_bss_start__);
|
||||
#endif
|
||||
}
|
||||
|
||||
void __program_init(int argc, char *argdata) {
|
||||
/* Zero-fill the .bss section */
|
||||
memset(__bss_start__, 0, __bss_end__ - __bss_start__);
|
||||
|
||||
__program_init_heap();
|
||||
__program_init_newlib_hooks();
|
||||
__program_parse_argc_argv(argc, argdata);
|
||||
|
||||
/* Once argv is parsed, we can discard the low IRAM region */
|
||||
__program_move_additional_sections();
|
||||
__libc_init_array();
|
||||
}
|
||||
|
||||
void __program_exit(int rc) {
|
||||
__libc_fini_array();
|
||||
__program_cleanup_argv();
|
||||
if (__program_exit_callback == NULL) {
|
||||
/* Default callback */
|
||||
generic_panic();
|
||||
} else {
|
||||
__program_exit_callback(rc);
|
||||
}
|
||||
for (;;);
|
||||
}
|
||||
|
||||
#ifdef FUSEE_STAGE1_SRC
|
||||
static void __program_parse_argc_argv(int argc, char *argdata) {
|
||||
__program_argc = 0;
|
||||
__program_argv = NULL;
|
||||
}
|
||||
#elif defined(FUSEE_STAGE2_SRC)
|
||||
#include "stage2.h"
|
||||
static void __program_parse_argc_argv(int argc, char *argdata) {
|
||||
size_t pos = 0, len;
|
||||
|
||||
__program_argc = argc;
|
||||
|
||||
__program_argv = malloc(argc * sizeof(void **));
|
||||
if (__program_argv == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
len = strlen(argdata);
|
||||
__program_argv[0] = malloc(len + 1);
|
||||
if (__program_argv[0] == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
strcpy((char *)__program_argv[0], argdata);
|
||||
pos += len + 1;
|
||||
|
||||
__program_argv[1] = malloc(sizeof(stage2_args_t));
|
||||
if (__program_argv[1] == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
memcpy(__program_argv[1], argdata + pos, sizeof(stage2_args_t));
|
||||
}
|
||||
#else
|
||||
static void __program_parse_argc_argv(int argc, char *argdata) {
|
||||
size_t pos = 0, len;
|
||||
|
||||
__program_argc = argc;
|
||||
|
||||
__program_argv = malloc(argc * sizeof(void **));
|
||||
if (__program_argv == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
for (int i = 0; i < argc; i++) {
|
||||
len = strlen(argdata + pos);
|
||||
__program_argv[i] = malloc(len + 1);
|
||||
if (__program_argv[i] == NULL) {
|
||||
generic_panic();
|
||||
}
|
||||
strcpy((char *)__program_argv[i], argdata + pos);
|
||||
pos += len + 1;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __program_cleanup_argv(void) {
|
||||
#ifndef FUSEE_STAGE1_SRC
|
||||
for (int i = 0; i < __program_argc; i++) {
|
||||
free(__program_argv[i]);
|
||||
__program_argv[i] = NULL;
|
||||
}
|
||||
free(__program_argv);
|
||||
#endif
|
||||
}
|
||||
324
sept/sept-secondary/src/lib/fatfs/00history.txt
Normal file
324
sept/sept-secondary/src/lib/fatfs/00history.txt
Normal file
|
|
@ -0,0 +1,324 @@
|
|||
----------------------------------------------------------------------------
|
||||
Revision history of FatFs module
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
R0.00 (February 26, 2006)
|
||||
|
||||
Prototype.
|
||||
|
||||
|
||||
|
||||
R0.01 (April 29, 2006)
|
||||
|
||||
The first release.
|
||||
|
||||
|
||||
|
||||
R0.02 (June 01, 2006)
|
||||
|
||||
Added FAT12 support.
|
||||
Removed unbuffered mode.
|
||||
Fixed a problem on small (<32M) partition.
|
||||
|
||||
|
||||
|
||||
R0.02a (June 10, 2006)
|
||||
|
||||
Added a configuration option (_FS_MINIMUM).
|
||||
|
||||
|
||||
|
||||
R0.03 (September 22, 2006)
|
||||
|
||||
Added f_rename().
|
||||
Changed option _FS_MINIMUM to _FS_MINIMIZE.
|
||||
|
||||
|
||||
|
||||
R0.03a (December 11, 2006)
|
||||
|
||||
Improved cluster scan algorithm to write files fast.
|
||||
Fixed f_mkdir() creates incorrect directory on FAT32.
|
||||
|
||||
|
||||
|
||||
R0.04 (February 04, 2007)
|
||||
|
||||
Added f_mkfs().
|
||||
Supported multiple drive system.
|
||||
Changed some interfaces for multiple drive system.
|
||||
Changed f_mountdrv() to f_mount().
|
||||
|
||||
|
||||
|
||||
R0.04a (April 01, 2007)
|
||||
|
||||
Supported multiple partitions on a physical drive.
|
||||
Added a capability of extending file size to f_lseek().
|
||||
Added minimization level 3.
|
||||
Fixed an endian sensitive code in f_mkfs().
|
||||
|
||||
|
||||
|
||||
R0.04b (May 05, 2007)
|
||||
|
||||
Added a configuration option _USE_NTFLAG.
|
||||
Added FSINFO support.
|
||||
Fixed DBCS name can result FR_INVALID_NAME.
|
||||
Fixed short seek (<= csize) collapses the file object.
|
||||
|
||||
|
||||
|
||||
R0.05 (August 25, 2007)
|
||||
|
||||
Changed arguments of f_read(), f_write() and f_mkfs().
|
||||
Fixed f_mkfs() on FAT32 creates incorrect FSINFO.
|
||||
Fixed f_mkdir() on FAT32 creates incorrect directory.
|
||||
|
||||
|
||||
|
||||
R0.05a (February 03, 2008)
|
||||
|
||||
Added f_truncate() and f_utime().
|
||||
Fixed off by one error at FAT sub-type determination.
|
||||
Fixed btr in f_read() can be mistruncated.
|
||||
Fixed cached sector is not flushed when create and close without write.
|
||||
|
||||
|
||||
|
||||
R0.06 (April 01, 2008)
|
||||
|
||||
Added fputc(), fputs(), fprintf() and fgets().
|
||||
Improved performance of f_lseek() on moving to the same or following cluster.
|
||||
|
||||
|
||||
|
||||
R0.07 (April 01, 2009)
|
||||
|
||||
Merged Tiny-FatFs as a configuration option. (_FS_TINY)
|
||||
Added long file name feature. (_USE_LFN)
|
||||
Added multiple code page feature. (_CODE_PAGE)
|
||||
Added re-entrancy for multitask operation. (_FS_REENTRANT)
|
||||
Added auto cluster size selection to f_mkfs().
|
||||
Added rewind option to f_readdir().
|
||||
Changed result code of critical errors.
|
||||
Renamed string functions to avoid name collision.
|
||||
|
||||
|
||||
|
||||
R0.07a (April 14, 2009)
|
||||
|
||||
Septemberarated out OS dependent code on reentrant cfg.
|
||||
Added multiple sector size feature.
|
||||
|
||||
|
||||
|
||||
R0.07c (June 21, 2009)
|
||||
|
||||
Fixed f_unlink() can return FR_OK on error.
|
||||
Fixed wrong cache control in f_lseek().
|
||||
Added relative path feature.
|
||||
Added f_chdir() and f_chdrive().
|
||||
Added proper case conversion to extended character.
|
||||
|
||||
|
||||
|
||||
R0.07e (November 03, 2009)
|
||||
|
||||
Septemberarated out configuration options from ff.h to ffconf.h.
|
||||
Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH.
|
||||
Fixed name matching error on the 13 character boundary.
|
||||
Added a configuration option, _LFN_UNICODE.
|
||||
Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
|
||||
|
||||
|
||||
|
||||
R0.08 (May 15, 2010)
|
||||
|
||||
Added a memory configuration option. (_USE_LFN = 3)
|
||||
Added file lock feature. (_FS_SHARE)
|
||||
Added fast seek feature. (_USE_FASTSEEK)
|
||||
Changed some types on the API, XCHAR->TCHAR.
|
||||
Changed .fname in the FILINFO structure on Unicode cfg.
|
||||
String functions support UTF-8 encoding files on Unicode cfg.
|
||||
|
||||
|
||||
|
||||
R0.08a (August 16, 2010)
|
||||
|
||||
Added f_getcwd(). (_FS_RPATH = 2)
|
||||
Added sector erase feature. (_USE_ERASE)
|
||||
Moved file lock semaphore table from fs object to the bss.
|
||||
Fixed f_mkfs() creates wrong FAT32 volume.
|
||||
|
||||
|
||||
|
||||
R0.08b (January 15, 2011)
|
||||
|
||||
Fast seek feature is also applied to f_read() and f_write().
|
||||
f_lseek() reports required table size on creating CLMP.
|
||||
Extended format syntax of f_printf().
|
||||
Ignores duplicated directory separators in given path name.
|
||||
|
||||
|
||||
|
||||
R0.09 (September 06, 2011)
|
||||
|
||||
f_mkfs() supports multiple partition to complete the multiple partition feature.
|
||||
Added f_fdisk().
|
||||
|
||||
|
||||
|
||||
R0.09a (August 27, 2012)
|
||||
|
||||
Changed f_open() and f_opendir() reject null object pointer to avoid crash.
|
||||
Changed option name _FS_SHARE to _FS_LOCK.
|
||||
Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
|
||||
|
||||
|
||||
|
||||
R0.09b (January 24, 2013)
|
||||
|
||||
Added f_setlabel() and f_getlabel().
|
||||
|
||||
|
||||
|
||||
R0.10 (October 02, 2013)
|
||||
|
||||
Added selection of character encoding on the file. (_STRF_ENCODE)
|
||||
Added f_closedir().
|
||||
Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO)
|
||||
Added forced mount feature with changes of f_mount().
|
||||
Improved behavior of volume auto detection.
|
||||
Improved write throughput of f_puts() and f_printf().
|
||||
Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write().
|
||||
Fixed f_write() can be truncated when the file size is close to 4GB.
|
||||
Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error.
|
||||
|
||||
|
||||
|
||||
R0.10a (January 15, 2014)
|
||||
|
||||
Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID)
|
||||
Added a configuration option of minimum sector size. (_MIN_SS)
|
||||
2nd argument of f_rename() can have a drive number and it will be ignored.
|
||||
Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10)
|
||||
Fixed f_close() invalidates the file object without volume lock.
|
||||
Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10)
|
||||
Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07)
|
||||
|
||||
|
||||
|
||||
R0.10b (May 19, 2014)
|
||||
|
||||
Fixed a hard error in the disk I/O layer can collapse the directory entry.
|
||||
Fixed LFN entry is not deleted when delete/rename an object with lossy converted SFN. (appeared at R0.07)
|
||||
|
||||
|
||||
|
||||
R0.10c (November 09, 2014)
|
||||
|
||||
Added a configuration option for the platforms without RTC. (_FS_NORTC)
|
||||
Changed option name _USE_ERASE to _USE_TRIM.
|
||||
Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b)
|
||||
Fixed a potential problem of FAT access that can appear on disk error.
|
||||
Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08)
|
||||
|
||||
|
||||
|
||||
R0.11 (February 09, 2015)
|
||||
|
||||
Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND)
|
||||
Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c)
|
||||
Fixed _FS_NORTC option does not work properly. (appeared at R0.10c)
|
||||
|
||||
|
||||
|
||||
R0.11a (September 05, 2015)
|
||||
|
||||
Fixed wrong media change can lead a deadlock at thread-safe configuration.
|
||||
Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE)
|
||||
Removed some code pages actually not exist on the standard systems. (_CODE_PAGE)
|
||||
Fixed errors in the case conversion teble of code page 437 and 850 (ff.c).
|
||||
Fixed errors in the case conversion teble of Unicode (cc*.c).
|
||||
|
||||
|
||||
|
||||
R0.12 (April 12, 2016)
|
||||
|
||||
Added support for exFAT file system. (_FS_EXFAT)
|
||||
Added f_expand(). (_USE_EXPAND)
|
||||
Changed some members in FINFO structure and behavior of f_readdir().
|
||||
Added an option _USE_CHMOD.
|
||||
Removed an option _WORD_ACCESS.
|
||||
Fixed errors in the case conversion table of Unicode (cc*.c).
|
||||
|
||||
|
||||
|
||||
R0.12a (July 10, 2016)
|
||||
|
||||
Added support for creating exFAT volume with some changes of f_mkfs().
|
||||
Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed.
|
||||
f_forward() is available regardless of _FS_TINY.
|
||||
Fixed f_mkfs() creates wrong volume. (appeared at R0.12)
|
||||
Fixed wrong memory read in create_name(). (appeared at R0.12)
|
||||
Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD.
|
||||
|
||||
|
||||
|
||||
R0.12b (September 04, 2016)
|
||||
|
||||
Made f_rename() be able to rename objects with the same name but case.
|
||||
Fixed an error in the case conversion teble of code page 866. (ff.c)
|
||||
Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12)
|
||||
Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12)
|
||||
Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12)
|
||||
Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12)
|
||||
Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12)
|
||||
Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12)
|
||||
|
||||
|
||||
|
||||
R0.12c (March 04, 2017)
|
||||
|
||||
Improved write throughput at the fragmented file on the exFAT volume.
|
||||
Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN.
|
||||
Fixed successive f_getfree() can return wrong count on the FAT12/16 volume. (appeared at R0.12)
|
||||
Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c)
|
||||
|
||||
|
||||
|
||||
R0.13 (May 21, 2017)
|
||||
|
||||
Changed heading character of configuration keywords "_" to "FF_".
|
||||
Removed ASCII-only configuration, FF_CODE_PAGE = 1. Use FF_CODE_PAGE = 437 instead.
|
||||
Added f_setcp(), run-time code page configuration. (FF_CODE_PAGE = 0)
|
||||
Improved cluster allocation time on stretch a deep buried cluster chain.
|
||||
Improved processing time of f_mkdir() with large cluster size by using FF_USE_LFN = 3.
|
||||
Improved NoFatChain flag of the fragmented file to be set after it is truncated and got contiguous.
|
||||
Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12)
|
||||
Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c)
|
||||
Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c)
|
||||
|
||||
|
||||
|
||||
R0.13a (October 14, 2017)
|
||||
|
||||
Added support for UTF-8 encoding on the API. (FF_LFN_UNICODE = 2)
|
||||
Added options for file name output buffer. (FF_LFN_BUF, FF_SFN_BUF).
|
||||
Added dynamic memory allocation option for working buffer of f_mkfs() and f_fdisk().
|
||||
Fixed f_fdisk() and f_mkfs() create the partition table with wrong CHS parameters. (appeared at R0.09)
|
||||
Fixed f_unlink() can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c)
|
||||
Fixed f_setlabel() rejects some valid characters for exFAT volume. (appeared at R0.12)
|
||||
|
||||
|
||||
|
||||
R0.13b (April 07, 2018)
|
||||
|
||||
Added support for UTF-32 encoding on the API. (FF_LFN_UNICODE = 3)
|
||||
Added support for Unix style volume ID. (FF_STR_VOLUME_ID = 2)
|
||||
Fixed accesing any object on the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c)
|
||||
Fixed f_setlabel() does not reject some invalid characters. (appeared at R0.09b)
|
||||
|
||||
|
||||
|
||||
22
sept/sept-secondary/src/lib/fatfs/00readme.txt
Normal file
22
sept/sept-secondary/src/lib/fatfs/00readme.txt
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
FatFs Module Source Files R0.13b
|
||||
|
||||
|
||||
FILES
|
||||
|
||||
00readme.txt This file.
|
||||
00history.txt Revision history.
|
||||
ff.c FatFs module.
|
||||
ffconf.h Configuration file of FatFs module.
|
||||
ff.h Common include file for FatFs and application module.
|
||||
diskio.h Common include file for FatFs and disk I/O module.
|
||||
diskio.c An example of glue function to attach existing disk I/O module to FatFs.
|
||||
integer.h Integer type definitions for FatFs.
|
||||
ffunicode.c Optional Unicode utility functions.
|
||||
ffsystem.c An example of optional O/S related functions.
|
||||
|
||||
|
||||
Low level disk I/O module is not included in this archive because the FatFs
|
||||
module is only a generic file system layer and it does not depend on any specific
|
||||
storage device. You need to provide a low level disk I/O module written to
|
||||
control the storage device that attached to the target system.
|
||||
|
||||
95
sept/sept-secondary/src/lib/fatfs/diskio.c
Normal file
95
sept/sept-secondary/src/lib/fatfs/diskio.c
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
/*-----------------------------------------------------------------------*/
|
||||
/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2016 */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* If a working storage control module is available, it should be */
|
||||
/* attached to the FatFs via a glue function rather than modifying it. */
|
||||
/* This is an example of glue functions to attach various exsisting */
|
||||
/* storage control modules to the FatFs module with a defined API. */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include "diskio.h" /* FatFs lower layer API */
|
||||
#include "../../fs_utils.h"
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Get Drive Status */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
DSTATUS disk_status (
|
||||
BYTE pdrv /* Physical drive nmuber to identify the drive */
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Inidialize a Drive */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
DSTATUS disk_initialize (
|
||||
BYTE pdrv /* Physical drive nmuber to identify the drive */
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Read Sector(s) */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
DRESULT disk_read (
|
||||
BYTE pdrv, /* Physical drive nmuber to identify the drive */
|
||||
BYTE *buff, /* Data buffer to store read data */
|
||||
DWORD sector, /* Start sector in LBA */
|
||||
UINT count /* Number of sectors to read */
|
||||
)
|
||||
{
|
||||
switch (pdrv) {
|
||||
case 0:
|
||||
return sdmmc_device_read(&g_sd_device, sector, count, (void *)buff) ? RES_OK : RES_ERROR;
|
||||
default:
|
||||
return RES_PARERR;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Write Sector(s) */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
DRESULT disk_write (
|
||||
BYTE pdrv, /* Physical drive nmuber to identify the drive */
|
||||
const BYTE *buff, /* Data to be written */
|
||||
DWORD sector, /* Start sector in LBA */
|
||||
UINT count /* Number of sectors to write */
|
||||
)
|
||||
{
|
||||
switch (pdrv) {
|
||||
case 0:
|
||||
return sdmmc_device_write(&g_sd_device, sector, count, (void *)buff) ? RES_OK : RES_ERROR;
|
||||
default:
|
||||
return RES_PARERR;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/* Miscellaneous Functions */
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
DRESULT disk_ioctl (
|
||||
BYTE pdrv, /* Physical drive nmuber (0..) */
|
||||
BYTE cmd, /* Control code */
|
||||
void *buff /* Buffer to send/receive control data */
|
||||
)
|
||||
{
|
||||
return RES_OK;
|
||||
}
|
||||
|
||||
80
sept/sept-secondary/src/lib/fatfs/diskio.h
Normal file
80
sept/sept-secondary/src/lib/fatfs/diskio.h
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/*-----------------------------------------------------------------------/
|
||||
/ Low level disk interface modlue include file (C)ChaN, 2014 /
|
||||
/-----------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _DISKIO_DEFINED
|
||||
#define _DISKIO_DEFINED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "integer.h"
|
||||
|
||||
|
||||
/* Status of Disk Functions */
|
||||
typedef BYTE DSTATUS;
|
||||
|
||||
/* Results of Disk Functions */
|
||||
typedef enum {
|
||||
RES_OK = 0, /* 0: Successful */
|
||||
RES_ERROR, /* 1: R/W Error */
|
||||
RES_WRPRT, /* 2: Write Protected */
|
||||
RES_NOTRDY, /* 3: Not Ready */
|
||||
RES_PARERR /* 4: Invalid Parameter */
|
||||
} DRESULT;
|
||||
|
||||
|
||||
/*---------------------------------------*/
|
||||
/* Prototypes for disk control functions */
|
||||
|
||||
|
||||
DSTATUS disk_initialize (BYTE pdrv);
|
||||
DSTATUS disk_status (BYTE pdrv);
|
||||
DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
|
||||
DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
|
||||
DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
|
||||
|
||||
|
||||
/* Disk Status Bits (DSTATUS) */
|
||||
|
||||
#define STA_NOINIT 0x01 /* Drive not initialized */
|
||||
#define STA_NODISK 0x02 /* No medium in the drive */
|
||||
#define STA_PROTECT 0x04 /* Write protected */
|
||||
|
||||
|
||||
/* Command code for disk_ioctrl fucntion */
|
||||
|
||||
/* Generic command (Used by FatFs) */
|
||||
#define CTRL_SYNC 0 /* Complete pending write process (needed at FF_FS_READONLY == 0) */
|
||||
#define GET_SECTOR_COUNT 1 /* Get media size (needed at FF_USE_MKFS == 1) */
|
||||
#define GET_SECTOR_SIZE 2 /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
|
||||
#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at FF_USE_MKFS == 1) */
|
||||
#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
|
||||
|
||||
/* Generic command (Not used by FatFs) */
|
||||
#define CTRL_POWER 5 /* Get/Set power status */
|
||||
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
|
||||
#define CTRL_EJECT 7 /* Eject media */
|
||||
#define CTRL_FORMAT 8 /* Create physical format on the media */
|
||||
|
||||
/* MMC/SDC specific ioctl command */
|
||||
#define MMC_GET_TYPE 10 /* Get card type */
|
||||
#define MMC_GET_CSD 11 /* Get CSD */
|
||||
#define MMC_GET_CID 12 /* Get CID */
|
||||
#define MMC_GET_OCR 13 /* Get OCR */
|
||||
#define MMC_GET_SDSTAT 14 /* Get SD status */
|
||||
#define ISDIO_READ 55 /* Read data form SD iSDIO register */
|
||||
#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */
|
||||
#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */
|
||||
|
||||
/* ATA/CF specific ioctl command */
|
||||
#define ATA_GET_REV 20 /* Get F/W revision */
|
||||
#define ATA_GET_MODEL 21 /* Get model name */
|
||||
#define ATA_GET_SN 22 /* Get serial number */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
6535
sept/sept-secondary/src/lib/fatfs/ff.c
Normal file
6535
sept/sept-secondary/src/lib/fatfs/ff.c
Normal file
File diff suppressed because it is too large
Load diff
376
sept/sept-secondary/src/lib/fatfs/ff.h
Normal file
376
sept/sept-secondary/src/lib/fatfs/ff.h
Normal file
|
|
@ -0,0 +1,376 @@
|
|||
/*----------------------------------------------------------------------------/
|
||||
/ FatFs - Generic FAT Filesystem module R0.13b /
|
||||
/-----------------------------------------------------------------------------/
|
||||
/
|
||||
/ Copyright (C) 2018, ChaN, all right reserved.
|
||||
/
|
||||
/ FatFs module is an open source software. Redistribution and use of FatFs in
|
||||
/ source and binary forms, with or without modification, are permitted provided
|
||||
/ that the following condition is met:
|
||||
|
||||
/ 1. Redistributions of source code must retain the above copyright notice,
|
||||
/ this condition and the following disclaimer.
|
||||
/
|
||||
/ This software is provided by the copyright holder and contributors "AS IS"
|
||||
/ and any warranties related to this software are DISCLAIMED.
|
||||
/ The copyright owner or contributors be NOT LIABLE for any damages caused
|
||||
/ by use of this software.
|
||||
/
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef FF_DEFINED
|
||||
#define FF_DEFINED 63463 /* Revision ID */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "integer.h" /* Basic integer types */
|
||||
#include "ffconf.h" /* FatFs configuration options */
|
||||
|
||||
#if FF_DEFINED != FFCONF_DEF
|
||||
#error Wrong configuration file (ffconf.h).
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Definitions of volume management */
|
||||
|
||||
#if FF_MULTI_PARTITION /* Multiple partition configuration */
|
||||
typedef struct {
|
||||
BYTE pd; /* Physical drive number */
|
||||
BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
|
||||
} PARTITION;
|
||||
extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
|
||||
#endif
|
||||
|
||||
#if FF_STR_VOLUME_ID
|
||||
#ifndef FF_VOLUME_STRS
|
||||
extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Type of path name strings on FatFs API */
|
||||
|
||||
#ifndef _INC_TCHAR
|
||||
#define _INC_TCHAR
|
||||
|
||||
#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
|
||||
typedef WCHAR TCHAR;
|
||||
#define _T(x) L ## x
|
||||
#define _TEXT(x) L ## x
|
||||
#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
|
||||
typedef char TCHAR;
|
||||
#define _T(x) u8 ## x
|
||||
#define _TEXT(x) u8 ## x
|
||||
#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
|
||||
typedef DWORD TCHAR;
|
||||
#define _T(x) U ## x
|
||||
#define _TEXT(x) U ## x
|
||||
#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
|
||||
#error Wrong FF_LFN_UNICODE setting
|
||||
#else /* ANSI/OEM code in SBCS/DBCS */
|
||||
typedef char TCHAR;
|
||||
#define _T(x) x
|
||||
#define _TEXT(x) x
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Type of file size variables */
|
||||
|
||||
#if FF_FS_EXFAT
|
||||
typedef QWORD FSIZE_t;
|
||||
#else
|
||||
typedef DWORD FSIZE_t;
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Filesystem object structure (FATFS) */
|
||||
|
||||
typedef struct {
|
||||
BYTE fs_type; /* Filesystem type (0:N/A) */
|
||||
BYTE pdrv; /* Physical drive number */
|
||||
BYTE n_fats; /* Number of FATs (1 or 2) */
|
||||
BYTE wflag; /* win[] flag (b0:dirty) */
|
||||
BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
|
||||
WORD id; /* Volume mount ID */
|
||||
WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
|
||||
WORD csize; /* Cluster size [sectors] */
|
||||
#if FF_MAX_SS != FF_MIN_SS
|
||||
WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
|
||||
#endif
|
||||
#if FF_USE_LFN
|
||||
WCHAR* lfnbuf; /* LFN working buffer */
|
||||
#endif
|
||||
#if FF_FS_EXFAT
|
||||
BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
|
||||
#endif
|
||||
#if FF_FS_REENTRANT
|
||||
FF_SYNC_t sobj; /* Identifier of sync object */
|
||||
#endif
|
||||
#if !FF_FS_READONLY
|
||||
DWORD last_clst; /* Last allocated cluster */
|
||||
DWORD free_clst; /* Number of free clusters */
|
||||
#endif
|
||||
#if FF_FS_RPATH
|
||||
DWORD cdir; /* Current directory start cluster (0:root) */
|
||||
#if FF_FS_EXFAT
|
||||
DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
|
||||
DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
|
||||
DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
|
||||
#endif
|
||||
#endif
|
||||
DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
|
||||
DWORD fsize; /* Size of an FAT [sectors] */
|
||||
DWORD volbase; /* Volume base sector */
|
||||
DWORD fatbase; /* FAT base sector */
|
||||
DWORD dirbase; /* Root directory base sector/cluster */
|
||||
DWORD database; /* Data base sector */
|
||||
DWORD winsect; /* Current sector appearing in the win[] */
|
||||
BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */
|
||||
} FATFS;
|
||||
|
||||
|
||||
|
||||
/* Object ID and allocation information (FFOBJID) */
|
||||
|
||||
typedef struct {
|
||||
FATFS* fs; /* Pointer to the hosting volume of this object */
|
||||
WORD id; /* Hosting volume mount ID */
|
||||
BYTE attr; /* Object attribute */
|
||||
BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:flagmented in this session, b2:sub-directory stretched) */
|
||||
DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
|
||||
FSIZE_t objsize; /* Object size (valid when sclust != 0) */
|
||||
#if FF_FS_EXFAT
|
||||
DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
|
||||
DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
|
||||
DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
|
||||
DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
|
||||
DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
|
||||
#endif
|
||||
#if FF_FS_LOCK
|
||||
UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
|
||||
#endif
|
||||
} FFOBJID;
|
||||
|
||||
|
||||
|
||||
/* File object structure (FIL) */
|
||||
|
||||
typedef struct {
|
||||
FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
|
||||
BYTE flag; /* File status flags */
|
||||
BYTE err; /* Abort flag (error code) */
|
||||
FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
|
||||
DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
|
||||
DWORD sect; /* Sector number appearing in buf[] (0:invalid) */
|
||||
#if !FF_FS_READONLY
|
||||
DWORD dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
|
||||
BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
|
||||
#endif
|
||||
#if FF_USE_FASTSEEK
|
||||
DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
|
||||
#endif
|
||||
#if !FF_FS_TINY
|
||||
BYTE buf[FF_MAX_SS]; /* File private data read/write window */
|
||||
#endif
|
||||
} FIL;
|
||||
|
||||
|
||||
|
||||
/* Directory object structure (DIR) */
|
||||
|
||||
typedef struct {
|
||||
FFOBJID obj; /* Object identifier */
|
||||
DWORD dptr; /* Current read/write offset */
|
||||
DWORD clust; /* Current cluster */
|
||||
DWORD sect; /* Current sector (0:Read operation has terminated) */
|
||||
BYTE* dir; /* Pointer to the directory item in the win[] */
|
||||
BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
|
||||
#if FF_USE_LFN
|
||||
DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
|
||||
#endif
|
||||
#if FF_USE_FIND
|
||||
const TCHAR* pat; /* Pointer to the name matching pattern */
|
||||
#endif
|
||||
} DIR;
|
||||
|
||||
|
||||
|
||||
/* File information structure (FILINFO) */
|
||||
|
||||
typedef struct {
|
||||
FSIZE_t fsize; /* File size */
|
||||
WORD fdate; /* Modified date */
|
||||
WORD ftime; /* Modified time */
|
||||
BYTE fattrib; /* File attribute */
|
||||
#if FF_USE_LFN
|
||||
TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
|
||||
TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
|
||||
#else
|
||||
TCHAR fname[12 + 1]; /* File name */
|
||||
#endif
|
||||
} FILINFO;
|
||||
|
||||
|
||||
|
||||
/* File function return code (FRESULT) */
|
||||
|
||||
typedef enum {
|
||||
FR_OK = 0, /* (0) Succeeded */
|
||||
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
|
||||
FR_INT_ERR, /* (2) Assertion failed */
|
||||
FR_NOT_READY, /* (3) The physical drive cannot work */
|
||||
FR_NO_FILE, /* (4) Could not find the file */
|
||||
FR_NO_PATH, /* (5) Could not find the path */
|
||||
FR_INVALID_NAME, /* (6) The path name format is invalid */
|
||||
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
|
||||
FR_EXIST, /* (8) Access denied due to prohibited access */
|
||||
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
|
||||
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
|
||||
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
|
||||
FR_NOT_ENABLED, /* (12) The volume has no work area */
|
||||
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
|
||||
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
|
||||
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
|
||||
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
|
||||
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
|
||||
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
|
||||
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
|
||||
} FRESULT;
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* FatFs module application interface */
|
||||
|
||||
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
|
||||
FRESULT f_close (FIL* fp); /* Close an open file object */
|
||||
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
|
||||
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
|
||||
FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
|
||||
FRESULT f_truncate (FIL* fp); /* Truncate the file */
|
||||
FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
|
||||
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
|
||||
FRESULT f_closedir (DIR* dp); /* Close an open directory */
|
||||
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
|
||||
FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
|
||||
FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
|
||||
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
|
||||
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
|
||||
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
|
||||
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
|
||||
FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
|
||||
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
|
||||
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
|
||||
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
|
||||
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
|
||||
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
|
||||
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
|
||||
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
|
||||
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
|
||||
FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */
|
||||
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
|
||||
FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */
|
||||
FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */
|
||||
FRESULT f_setcp (WORD cp); /* Set current code page */
|
||||
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
|
||||
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
|
||||
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
|
||||
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
|
||||
|
||||
#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
|
||||
#define f_error(fp) ((fp)->err)
|
||||
#define f_tell(fp) ((fp)->fptr)
|
||||
#define f_size(fp) ((fp)->obj.objsize)
|
||||
#define f_rewind(fp) f_lseek((fp), 0)
|
||||
#define f_rewinddir(dp) f_readdir((dp), 0)
|
||||
#define f_rmdir(path) f_unlink(path)
|
||||
#define f_unmount(path) f_mount(0, path, 0)
|
||||
|
||||
#ifndef EOF
|
||||
#define EOF (-1)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Additional user defined functions */
|
||||
|
||||
/* RTC function */
|
||||
#if !FF_FS_READONLY && !FF_FS_NORTC
|
||||
DWORD get_fattime (void);
|
||||
#endif
|
||||
|
||||
/* LFN support functions */
|
||||
#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
|
||||
WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
|
||||
WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
|
||||
DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
|
||||
#endif
|
||||
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
|
||||
void* ff_memalloc (UINT msize); /* Allocate memory block */
|
||||
void ff_memfree (void* mblock); /* Free memory block */
|
||||
#endif
|
||||
|
||||
/* Sync functions */
|
||||
#if FF_FS_REENTRANT
|
||||
int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
|
||||
int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
|
||||
void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
|
||||
int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Flags and offset address */
|
||||
|
||||
|
||||
/* File access mode and open method flags (3rd argument of f_open) */
|
||||
#define FA_READ 0x01
|
||||
#define FA_WRITE 0x02
|
||||
#define FA_OPEN_EXISTING 0x00
|
||||
#define FA_CREATE_NEW 0x04
|
||||
#define FA_CREATE_ALWAYS 0x08
|
||||
#define FA_OPEN_ALWAYS 0x10
|
||||
#define FA_OPEN_APPEND 0x30
|
||||
|
||||
/* Fast seek controls (2nd argument of f_lseek) */
|
||||
#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
|
||||
|
||||
/* Format options (2nd argument of f_mkfs) */
|
||||
#define FM_FAT 0x01
|
||||
#define FM_FAT32 0x02
|
||||
#define FM_EXFAT 0x04
|
||||
#define FM_ANY 0x07
|
||||
#define FM_SFD 0x08
|
||||
|
||||
/* Filesystem type (FATFS.fs_type) */
|
||||
#define FS_FAT12 1
|
||||
#define FS_FAT16 2
|
||||
#define FS_FAT32 3
|
||||
#define FS_EXFAT 4
|
||||
|
||||
/* File attribute bits for directory entry (FILINFO.fattrib) */
|
||||
#define AM_RDO 0x01 /* Read only */
|
||||
#define AM_HID 0x02 /* Hidden */
|
||||
#define AM_SYS 0x04 /* System */
|
||||
#define AM_DIR 0x10 /* Directory */
|
||||
#define AM_ARC 0x20 /* Archive */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* FF_DEFINED */
|
||||
289
sept/sept-secondary/src/lib/fatfs/ffconf.h
Normal file
289
sept/sept-secondary/src/lib/fatfs/ffconf.h
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/*---------------------------------------------------------------------------/
|
||||
/ FatFs - Configuration file
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FFCONF_DEF 63463 /* Revision ID */
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Function Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_FS_READONLY 0
|
||||
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
|
||||
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
|
||||
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
|
||||
/ and optional writing functions as well. */
|
||||
|
||||
|
||||
#define FF_FS_MINIMIZE 0
|
||||
/* This option defines minimization level to remove some basic API functions.
|
||||
/
|
||||
/ 0: Basic functions are fully enabled.
|
||||
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
|
||||
/ are removed.
|
||||
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
|
||||
/ 3: f_lseek() function is removed in addition to 2. */
|
||||
|
||||
|
||||
#define FF_USE_STRFUNC 2
|
||||
/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
|
||||
/
|
||||
/ 0: Disable string functions.
|
||||
/ 1: Enable without LF-CRLF conversion.
|
||||
/ 2: Enable with LF-CRLF conversion. */
|
||||
|
||||
|
||||
#define FF_USE_FIND 0
|
||||
/* This option switches filtered directory read functions, f_findfirst() and
|
||||
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
|
||||
|
||||
|
||||
#define FF_USE_MKFS 0
|
||||
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_FASTSEEK 0
|
||||
/* This option switches fast seek function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_EXPAND 0
|
||||
/* This option switches f_expand function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_CHMOD 0
|
||||
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
|
||||
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
|
||||
|
||||
|
||||
#define FF_USE_LABEL 0
|
||||
/* This option switches volume label functions, f_getlabel() and f_setlabel().
|
||||
/ (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_FORWARD 0
|
||||
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Locale and Namespace Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_CODE_PAGE 850
|
||||
/* This option specifies the OEM code page to be used on the target system.
|
||||
/ Incorrect code page setting can cause a file open failure.
|
||||
/
|
||||
/ 437 - U.S.
|
||||
/ 720 - Arabic
|
||||
/ 737 - Greek
|
||||
/ 771 - KBL
|
||||
/ 775 - Baltic
|
||||
/ 850 - Latin 1
|
||||
/ 852 - Latin 2
|
||||
/ 855 - Cyrillic
|
||||
/ 857 - Turkish
|
||||
/ 860 - Portuguese
|
||||
/ 861 - Icelandic
|
||||
/ 862 - Hebrew
|
||||
/ 863 - Canadian French
|
||||
/ 864 - Arabic
|
||||
/ 865 - Nordic
|
||||
/ 866 - Russian
|
||||
/ 869 - Greek 2
|
||||
/ 932 - Japanese (DBCS)
|
||||
/ 936 - Simplified Chinese (DBCS)
|
||||
/ 949 - Korean (DBCS)
|
||||
/ 950 - Traditional Chinese (DBCS)
|
||||
/ 0 - Include all code pages above and configured by f_setcp()
|
||||
*/
|
||||
|
||||
|
||||
#define FF_USE_LFN 1
|
||||
#define FF_MAX_LFN 255
|
||||
/* The FF_USE_LFN switches the support for LFN (long file name).
|
||||
/
|
||||
/ 0: Disable LFN. FF_MAX_LFN has no effect.
|
||||
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
|
||||
/ 2: Enable LFN with dynamic working buffer on the STACK.
|
||||
/ 3: Enable LFN with dynamic working buffer on the HEAP.
|
||||
/
|
||||
/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
|
||||
/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
|
||||
/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
|
||||
/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
|
||||
/ be in range of 12 to 255. It is recommended to be set 255 to fully support LFN
|
||||
/ specification.
|
||||
/ When use stack for the working buffer, take care on stack overflow. When use heap
|
||||
/ memory for the working buffer, memory management functions, ff_memalloc() and
|
||||
/ ff_memfree() in ffsystem.c, need to be added to the project. */
|
||||
|
||||
|
||||
#define FF_LFN_UNICODE 2
|
||||
/* This option switches the character encoding on the API when LFN is enabled.
|
||||
/
|
||||
/ 0: ANSI/OEM in current CP (TCHAR = char)
|
||||
/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
|
||||
/ 2: Unicode in UTF-8 (TCHAR = char)
|
||||
/ 3: Unicode in UTF-32 (TCHAR = DWORD)
|
||||
/
|
||||
/ Also behavior of string I/O functions will be affected by this option.
|
||||
/ When LFN is not enabled, this option has no effect. */
|
||||
|
||||
|
||||
#define FF_LFN_BUF 255
|
||||
#define FF_SFN_BUF 12
|
||||
/* This set of options defines size of file name members in the FILINFO structure
|
||||
/ which is used to read out directory items. These values should be suffcient for
|
||||
/ the file names to read. The maximum possible length of the read file name depends
|
||||
/ on character encoding. When LFN is not enabled, these options have no effect. */
|
||||
|
||||
|
||||
#define FF_STRF_ENCODE 3
|
||||
/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
|
||||
/ f_putc(), f_puts and f_printf() convert the character encoding in it.
|
||||
/ This option selects assumption of character encoding ON THE FILE to be
|
||||
/ read/written via those functions.
|
||||
/
|
||||
/ 0: ANSI/OEM in current CP
|
||||
/ 1: Unicode in UTF-16LE
|
||||
/ 2: Unicode in UTF-16BE
|
||||
/ 3: Unicode in UTF-8
|
||||
*/
|
||||
|
||||
|
||||
#define FF_FS_RPATH 0
|
||||
/* This option configures support for relative path.
|
||||
/
|
||||
/ 0: Disable relative path and remove related functions.
|
||||
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
|
||||
/ 2: f_getcwd() function is available in addition to 1.
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Drive/Volume Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_VOLUMES 1
|
||||
/* Number of volumes (logical drives) to be used. (1-10) */
|
||||
|
||||
|
||||
#define FF_STR_VOLUME_ID 0
|
||||
#define FF_VOLUME_STRS "sdmc"
|
||||
/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
|
||||
/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
|
||||
/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
|
||||
/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
|
||||
/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
|
||||
/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
|
||||
/ not defined, a user defined volume string table needs to be defined as:
|
||||
/
|
||||
/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
|
||||
*/
|
||||
|
||||
|
||||
#define FF_MULTI_PARTITION 0
|
||||
/* This option switches support for multiple volumes on the physical drive.
|
||||
/ By default (0), each logical drive number is bound to the same physical drive
|
||||
/ number and only an FAT volume found on the physical drive will be mounted.
|
||||
/ When this function is enabled (1), each logical drive number can be bound to
|
||||
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
|
||||
/ funciton will be available. */
|
||||
|
||||
|
||||
#define FF_MIN_SS 512
|
||||
#define FF_MAX_SS 512
|
||||
/* This set of options configures the range of sector size to be supported. (512,
|
||||
/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
|
||||
/ harddisk. But a larger value may be required for on-board flash memory and some
|
||||
/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
|
||||
/ for variable sector size mode and disk_ioctl() function needs to implement
|
||||
/ GET_SECTOR_SIZE command. */
|
||||
|
||||
|
||||
#define FF_USE_TRIM 0
|
||||
/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
|
||||
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
|
||||
/ disk_ioctl() function. */
|
||||
|
||||
|
||||
#define FF_FS_NOFSINFO 0
|
||||
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
|
||||
/ option, and f_getfree() function at first time after volume mount will force
|
||||
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
|
||||
/
|
||||
/ bit0=0: Use free cluster count in the FSINFO if available.
|
||||
/ bit0=1: Do not trust free cluster count in the FSINFO.
|
||||
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
|
||||
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ System Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_FS_TINY 0
|
||||
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
|
||||
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
|
||||
/ Instead of private sector buffer eliminated from the file object, common sector
|
||||
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
|
||||
|
||||
|
||||
#define FF_FS_EXFAT 1
|
||||
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
|
||||
/ To enable exFAT, also LFN needs to be enabled.
|
||||
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
|
||||
|
||||
|
||||
#define FF_FS_NORTC 1
|
||||
#define FF_NORTC_MON 1
|
||||
#define FF_NORTC_MDAY 1
|
||||
#define FF_NORTC_YEAR 2018
|
||||
/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
|
||||
/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
|
||||
/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
|
||||
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
|
||||
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
|
||||
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
|
||||
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
|
||||
/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
|
||||
|
||||
|
||||
#define FF_FS_LOCK 0
|
||||
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
|
||||
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
|
||||
/ is 1.
|
||||
/
|
||||
/ 0: Disable file lock function. To avoid volume corruption, application program
|
||||
/ should avoid illegal open, remove and rename to the open objects.
|
||||
/ >0: Enable file lock function. The value defines how many files/sub-directories
|
||||
/ can be opened simultaneously under file lock control. Note that the file
|
||||
/ lock control is independent of re-entrancy. */
|
||||
|
||||
|
||||
#define FF_FS_REENTRANT 0
|
||||
#define FF_FS_TIMEOUT 1000
|
||||
#define FF_SYNC_t HANDLE
|
||||
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
|
||||
/ module itself. Note that regardless of this option, file access to different
|
||||
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
|
||||
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
|
||||
/ to the same volume is under control of this function.
|
||||
/
|
||||
/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
|
||||
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
|
||||
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
|
||||
/ function, must be added to the project. Samples are available in
|
||||
/ option/syscall.c.
|
||||
/
|
||||
/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
|
||||
/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
|
||||
/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
|
||||
/ included somewhere in the scope of ff.h. */
|
||||
|
||||
/* #include <windows.h> // O/S definitions */
|
||||
|
||||
|
||||
|
||||
/*--- End of configuration options ---*/
|
||||
171
sept/sept-secondary/src/lib/fatfs/ffsystem.c
Normal file
171
sept/sept-secondary/src/lib/fatfs/ffsystem.c
Normal file
|
|
@ -0,0 +1,171 @@
|
|||
/*------------------------------------------------------------------------*/
|
||||
/* Sample Code of OS Dependent Functions for FatFs */
|
||||
/* (C)ChaN, 2017 */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ff.h"
|
||||
|
||||
|
||||
|
||||
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Allocate a memory block */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
void* ff_memalloc ( /* Returns pointer to the allocated memory block (null on not enough core) */
|
||||
UINT msize /* Number of bytes to allocate */
|
||||
)
|
||||
{
|
||||
return malloc(msize); /* Allocate a new memory block with POSIX API */
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Free a memory block */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
void ff_memfree (
|
||||
void* mblock /* Pointer to the memory block to free (nothing to do for null) */
|
||||
)
|
||||
{
|
||||
free(mblock); /* Free the memory block with POSIX API */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if FF_FS_REENTRANT /* Mutal exclusion */
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Create a Synchronization Object */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called in f_mount() function to create a new
|
||||
/ synchronization object for the volume, such as semaphore and mutex.
|
||||
/ When a 0 is returned, the f_mount() function fails with FR_INT_ERR.
|
||||
*/
|
||||
|
||||
//const osMutexDef_t Mutex[FF_VOLUMES]; /* CMSIS-RTOS */
|
||||
|
||||
|
||||
int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */
|
||||
BYTE vol, /* Corresponding volume (logical drive number) */
|
||||
FF_SYNC_t* sobj /* Pointer to return the created sync object */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
*sobj = CreateMutex(NULL, FALSE, NULL);
|
||||
return (int)(*sobj != INVALID_HANDLE_VALUE);
|
||||
|
||||
/* uITRON */
|
||||
// T_CSEM csem = {TA_TPRI,1,1};
|
||||
// *sobj = acre_sem(&csem);
|
||||
// return (int)(*sobj > 0);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OS_ERR err;
|
||||
// *sobj = OSMutexCreate(0, &err);
|
||||
// return (int)(err == OS_NO_ERR);
|
||||
|
||||
/* FreeRTOS */
|
||||
// *sobj = xSemaphoreCreateMutex();
|
||||
// return (int)(*sobj != NULL);
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// *sobj = osMutexCreate(Mutex + vol);
|
||||
// return (int)(*sobj != NULL);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Delete a Synchronization Object */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called in f_mount() function to delete a synchronization
|
||||
/ object that created with ff_cre_syncobj() function. When a 0 is returned,
|
||||
/ the f_mount() function fails with FR_INT_ERR.
|
||||
*/
|
||||
|
||||
int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to an error */
|
||||
FF_SYNC_t sobj /* Sync object tied to the logical drive to be deleted */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
return (int)CloseHandle(sobj);
|
||||
|
||||
/* uITRON */
|
||||
// return (int)(del_sem(sobj) == E_OK);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OS_ERR err;
|
||||
// OSMutexDel(sobj, OS_DEL_ALWAYS, &err);
|
||||
// return (int)(err == OS_NO_ERR);
|
||||
|
||||
/* FreeRTOS */
|
||||
// vSemaphoreDelete(sobj);
|
||||
// return 1;
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// return (int)(osMutexDelete(sobj) == osOK);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Request Grant to Access the Volume */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called on entering file functions to lock the volume.
|
||||
/ When a 0 is returned, the file function fails with FR_TIMEOUT.
|
||||
*/
|
||||
|
||||
int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */
|
||||
FF_SYNC_t sobj /* Sync object to wait */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
return (int)(WaitForSingleObject(sobj, FF_FS_TIMEOUT) == WAIT_OBJECT_0);
|
||||
|
||||
/* uITRON */
|
||||
// return (int)(wai_sem(sobj) == E_OK);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OS_ERR err;
|
||||
// OSMutexPend(sobj, FF_FS_TIMEOUT, &err));
|
||||
// return (int)(err == OS_NO_ERR);
|
||||
|
||||
/* FreeRTOS */
|
||||
// return (int)(xSemaphoreTake(sobj, FF_FS_TIMEOUT) == pdTRUE);
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// return (int)(osMutexWait(sobj, FF_FS_TIMEOUT) == osOK);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Release Grant to Access the Volume */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called on leaving file functions to unlock the volume.
|
||||
*/
|
||||
|
||||
void ff_rel_grant (
|
||||
FF_SYNC_t sobj /* Sync object to be signaled */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
ReleaseMutex(sobj);
|
||||
|
||||
/* uITRON */
|
||||
// sig_sem(sobj);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OSMutexPost(sobj);
|
||||
|
||||
/* FreeRTOS */
|
||||
// xSemaphoreGive(sobj);
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// osMutexRelease(sobj);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
15597
sept/sept-secondary/src/lib/fatfs/ffunicode.c
Normal file
15597
sept/sept-secondary/src/lib/fatfs/ffunicode.c
Normal file
File diff suppressed because it is too large
Load diff
36
sept/sept-secondary/src/lib/fatfs/integer.h
Normal file
36
sept/sept-secondary/src/lib/fatfs/integer.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*-------------------------------------------*/
|
||||
/* Integer type definitions for FatFs module */
|
||||
/*-------------------------------------------*/
|
||||
|
||||
#ifndef FF_INTEGER
|
||||
#define FF_INTEGER
|
||||
|
||||
#ifdef _WIN32 /* FatFs development platform */
|
||||
|
||||
#include <windows.h>
|
||||
typedef unsigned __int64 QWORD;
|
||||
|
||||
#else /* Embedded platform */
|
||||
|
||||
/* These types MUST be 16-bit or 32-bit */
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
|
||||
/* This type MUST be 8-bit */
|
||||
typedef unsigned char BYTE;
|
||||
|
||||
/* These types MUST be 16-bit */
|
||||
typedef short SHORT;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned short WCHAR;
|
||||
|
||||
/* These types MUST be 32-bit */
|
||||
typedef long LONG;
|
||||
typedef unsigned long DWORD;
|
||||
|
||||
/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
|
||||
typedef unsigned long long QWORD;
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
269
sept/sept-secondary/src/lib/ini.c
Normal file
269
sept/sept-secondary/src/lib/ini.c
Normal file
|
|
@ -0,0 +1,269 @@
|
|||
/* inih -- simple .INI file parser
|
||||
|
||||
inih is released under the New BSD license (see LICENSE.txt). Go to the project
|
||||
home page for more info:
|
||||
|
||||
https://github.com/benhoyt/inih
|
||||
|
||||
*/
|
||||
|
||||
#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_WARNINGS)
|
||||
#define _CRT_SECURE_NO_WARNINGS
|
||||
#endif
|
||||
|
||||
#include <stdio.h>
|
||||
#include <ctype.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "ini.h"
|
||||
|
||||
#if !INI_USE_STACK
|
||||
#include <stdlib.h>
|
||||
#endif
|
||||
|
||||
#define MAX_SECTION 50
|
||||
#define MAX_NAME 50
|
||||
|
||||
/* Used by ini_parse_string() to keep track of string parsing state. */
|
||||
typedef struct {
|
||||
const char* ptr;
|
||||
size_t num_left;
|
||||
} ini_parse_string_ctx;
|
||||
|
||||
/* Strip whitespace chars off end of given string, in place. Return s. */
|
||||
static char* rstrip(char* s)
|
||||
{
|
||||
char* p = s + strlen(s);
|
||||
while (p > s && isspace((unsigned char)(*--p)))
|
||||
*p = '\0';
|
||||
return s;
|
||||
}
|
||||
|
||||
/* Return pointer to first non-whitespace char in given string. */
|
||||
static char* lskip(const char* s)
|
||||
{
|
||||
while (*s && isspace((unsigned char)(*s)))
|
||||
s++;
|
||||
return (char*)s;
|
||||
}
|
||||
|
||||
/* Return pointer to first char (of chars) or inline comment in given string,
|
||||
or pointer to null at end of string if neither found. Inline comment must
|
||||
be prefixed by a whitespace character to register as a comment. */
|
||||
static char* find_chars_or_comment(const char* s, const char* chars)
|
||||
{
|
||||
#if INI_ALLOW_INLINE_COMMENTS
|
||||
int was_space = 0;
|
||||
while (*s && (!chars || !strchr(chars, *s)) &&
|
||||
!(was_space && strchr(INI_INLINE_COMMENT_PREFIXES, *s))) {
|
||||
was_space = isspace((unsigned char)(*s));
|
||||
s++;
|
||||
}
|
||||
#else
|
||||
while (*s && (!chars || !strchr(chars, *s))) {
|
||||
s++;
|
||||
}
|
||||
#endif
|
||||
return (char*)s;
|
||||
}
|
||||
|
||||
/* Version of strncpy that ensures dest (size bytes) is null-terminated. */
|
||||
static char* strncpy0(char* dest, const char* src, size_t size)
|
||||
{
|
||||
strncpy(dest, src, size - 1);
|
||||
dest[size - 1] = '\0';
|
||||
return dest;
|
||||
}
|
||||
|
||||
/* See documentation in header file. */
|
||||
int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler,
|
||||
void* user)
|
||||
{
|
||||
/* Uses a fair bit of stack (use heap instead if you need to) */
|
||||
#if INI_USE_STACK
|
||||
char line[INI_MAX_LINE];
|
||||
int max_line = INI_MAX_LINE;
|
||||
#else
|
||||
char* line;
|
||||
int max_line = INI_INITIAL_ALLOC;
|
||||
#endif
|
||||
#if INI_ALLOW_REALLOC
|
||||
char* new_line;
|
||||
int offset;
|
||||
#endif
|
||||
char section[MAX_SECTION] = "";
|
||||
char prev_name[MAX_NAME] = "";
|
||||
|
||||
char* start;
|
||||
char* end;
|
||||
char* name;
|
||||
char* value;
|
||||
int lineno = 0;
|
||||
int error = 0;
|
||||
|
||||
#if !INI_USE_STACK
|
||||
line = (char*)malloc(INI_INITIAL_ALLOC);
|
||||
if (!line) {
|
||||
return -2;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if INI_HANDLER_LINENO
|
||||
#define HANDLER(u, s, n, v) handler(u, s, n, v, lineno)
|
||||
#else
|
||||
#define HANDLER(u, s, n, v) handler(u, s, n, v)
|
||||
#endif
|
||||
|
||||
/* Scan through stream line by line */
|
||||
while (reader(line, max_line, stream) != NULL) {
|
||||
#if INI_ALLOW_REALLOC
|
||||
offset = strlen(line);
|
||||
while (offset == max_line - 1 && line[offset - 1] != '\n') {
|
||||
max_line *= 2;
|
||||
if (max_line > INI_MAX_LINE)
|
||||
max_line = INI_MAX_LINE;
|
||||
new_line = realloc(line, max_line);
|
||||
if (!new_line) {
|
||||
free(line);
|
||||
return -2;
|
||||
}
|
||||
line = new_line;
|
||||
if (reader(line + offset, max_line - offset, stream) == NULL)
|
||||
break;
|
||||
if (max_line >= INI_MAX_LINE)
|
||||
break;
|
||||
offset += strlen(line + offset);
|
||||
}
|
||||
#endif
|
||||
|
||||
lineno++;
|
||||
|
||||
start = line;
|
||||
#if INI_ALLOW_BOM
|
||||
if (lineno == 1 && (unsigned char)start[0] == 0xEF &&
|
||||
(unsigned char)start[1] == 0xBB &&
|
||||
(unsigned char)start[2] == 0xBF) {
|
||||
start += 3;
|
||||
}
|
||||
#endif
|
||||
start = lskip(rstrip(start));
|
||||
|
||||
if (strchr(INI_START_COMMENT_PREFIXES, *start)) {
|
||||
/* Start-of-line comment */
|
||||
}
|
||||
#if INI_ALLOW_MULTILINE
|
||||
else if (*prev_name && *start && start > line) {
|
||||
/* Non-blank line with leading whitespace, treat as continuation
|
||||
of previous name's value (as per Python configparser). */
|
||||
if (!HANDLER(user, section, prev_name, start) && !error)
|
||||
error = lineno;
|
||||
}
|
||||
#endif
|
||||
else if (*start == '[') {
|
||||
/* A "[section]" line */
|
||||
end = find_chars_or_comment(start + 1, "]");
|
||||
if (*end == ']') {
|
||||
*end = '\0';
|
||||
strncpy0(section, start + 1, sizeof(section));
|
||||
*prev_name = '\0';
|
||||
}
|
||||
else if (!error) {
|
||||
/* No ']' found on section line */
|
||||
error = lineno;
|
||||
}
|
||||
}
|
||||
else if (*start) {
|
||||
/* Not a comment, must be a name[=:]value pair */
|
||||
end = find_chars_or_comment(start, "=:");
|
||||
if (*end == '=' || *end == ':') {
|
||||
*end = '\0';
|
||||
name = rstrip(start);
|
||||
value = end + 1;
|
||||
#if INI_ALLOW_INLINE_COMMENTS
|
||||
end = find_chars_or_comment(value, NULL);
|
||||
if (*end)
|
||||
*end = '\0';
|
||||
#endif
|
||||
value = lskip(value);
|
||||
rstrip(value);
|
||||
|
||||
/* Valid name[=:]value pair found, call handler */
|
||||
strncpy0(prev_name, name, sizeof(prev_name));
|
||||
if (!HANDLER(user, section, name, value) && !error)
|
||||
error = lineno;
|
||||
}
|
||||
else if (!error) {
|
||||
/* No '=' or ':' found on name[=:]value line */
|
||||
error = lineno;
|
||||
}
|
||||
}
|
||||
|
||||
#if INI_STOP_ON_FIRST_ERROR
|
||||
if (error)
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if !INI_USE_STACK
|
||||
free(line);
|
||||
#endif
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
/* See documentation in header file. */
|
||||
int ini_parse_file(FILE* file, ini_handler handler, void* user)
|
||||
{
|
||||
return ini_parse_stream((ini_reader)fgets, file, handler, user);
|
||||
}
|
||||
|
||||
/* See documentation in header file. */
|
||||
int ini_parse(const char* filename, ini_handler handler, void* user)
|
||||
{
|
||||
FILE* file;
|
||||
int error;
|
||||
|
||||
file = fopen(filename, "r");
|
||||
if (!file)
|
||||
return -1;
|
||||
error = ini_parse_file(file, handler, user);
|
||||
fclose(file);
|
||||
return error;
|
||||
}
|
||||
|
||||
/* An ini_reader function to read the next line from a string buffer. This
|
||||
is the fgets() equivalent used by ini_parse_string(). */
|
||||
static char* ini_reader_string(char* str, int num, void* stream) {
|
||||
ini_parse_string_ctx* ctx = (ini_parse_string_ctx*)stream;
|
||||
const char* ctx_ptr = ctx->ptr;
|
||||
size_t ctx_num_left = ctx->num_left;
|
||||
char* strp = str;
|
||||
char c;
|
||||
|
||||
if (ctx_num_left == 0 || num < 2)
|
||||
return NULL;
|
||||
|
||||
while (num > 1 && ctx_num_left != 0) {
|
||||
c = *ctx_ptr++;
|
||||
ctx_num_left--;
|
||||
*strp++ = c;
|
||||
if (c == '\n')
|
||||
break;
|
||||
num--;
|
||||
}
|
||||
|
||||
*strp = '\0';
|
||||
ctx->ptr = ctx_ptr;
|
||||
ctx->num_left = ctx_num_left;
|
||||
return str;
|
||||
}
|
||||
|
||||
/* See documentation in header file. */
|
||||
int ini_parse_string(const char* string, ini_handler handler, void* user) {
|
||||
ini_parse_string_ctx ctx;
|
||||
|
||||
ctx.ptr = string;
|
||||
ctx.num_left = strlen(string);
|
||||
return ini_parse_stream((ini_reader)ini_reader_string, &ctx, handler,
|
||||
user);
|
||||
}
|
||||
130
sept/sept-secondary/src/lib/ini.h
Normal file
130
sept/sept-secondary/src/lib/ini.h
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
/* inih -- simple .INI file parser
|
||||
|
||||
inih is released under the New BSD license (see LICENSE.txt). Go to the project
|
||||
home page for more info:
|
||||
|
||||
https://github.com/benhoyt/inih
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __INI_H__
|
||||
#define __INI_H__
|
||||
|
||||
/* Make this header file easier to include in C++ code */
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
/* Nonzero if ini_handler callback should accept lineno parameter. */
|
||||
#ifndef INI_HANDLER_LINENO
|
||||
#define INI_HANDLER_LINENO 0
|
||||
#endif
|
||||
|
||||
/* Typedef for prototype of handler function. */
|
||||
#if INI_HANDLER_LINENO
|
||||
typedef int (*ini_handler)(void* user, const char* section,
|
||||
const char* name, const char* value,
|
||||
int lineno);
|
||||
#else
|
||||
typedef int (*ini_handler)(void* user, const char* section,
|
||||
const char* name, const char* value);
|
||||
#endif
|
||||
|
||||
/* Typedef for prototype of fgets-style reader function. */
|
||||
typedef char* (*ini_reader)(char* str, int num, void* stream);
|
||||
|
||||
/* Parse given INI-style file. May have [section]s, name=value pairs
|
||||
(whitespace stripped), and comments starting with ';' (semicolon). Section
|
||||
is "" if name=value pair parsed before any section heading. name:value
|
||||
pairs are also supported as a concession to Python's configparser.
|
||||
|
||||
For each name=value pair parsed, call handler function with given user
|
||||
pointer as well as section, name, and value (data only valid for duration
|
||||
of handler call). Handler should return nonzero on success, zero on error.
|
||||
|
||||
Returns 0 on success, line number of first error on parse error (doesn't
|
||||
stop on first error), -1 on file open error, or -2 on memory allocation
|
||||
error (only when INI_USE_STACK is zero).
|
||||
*/
|
||||
int ini_parse(const char* filename, ini_handler handler, void* user);
|
||||
|
||||
/* Same as ini_parse(), but takes a FILE* instead of filename. This doesn't
|
||||
close the file when it's finished -- the caller must do that. */
|
||||
int ini_parse_file(FILE* file, ini_handler handler, void* user);
|
||||
|
||||
/* Same as ini_parse(), but takes an ini_reader function pointer instead of
|
||||
filename. Used for implementing custom or string-based I/O (see also
|
||||
ini_parse_string). */
|
||||
int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler,
|
||||
void* user);
|
||||
|
||||
/* Same as ini_parse(), but takes a zero-terminated string with the INI data
|
||||
instead of a file. Useful for parsing INI data from a network socket or
|
||||
already in memory. */
|
||||
int ini_parse_string(const char* string, ini_handler handler, void* user);
|
||||
|
||||
/* Nonzero to allow multi-line value parsing, in the style of Python's
|
||||
configparser. If allowed, ini_parse() will call the handler with the same
|
||||
name for each subsequent line parsed. */
|
||||
#ifndef INI_ALLOW_MULTILINE
|
||||
#define INI_ALLOW_MULTILINE 1
|
||||
#endif
|
||||
|
||||
/* Nonzero to allow a UTF-8 BOM sequence (0xEF 0xBB 0xBF) at the start of
|
||||
the file. See http://code.google.com/p/inih/issues/detail?id=21 */
|
||||
#ifndef INI_ALLOW_BOM
|
||||
#define INI_ALLOW_BOM 1
|
||||
#endif
|
||||
|
||||
/* Chars that begin a start-of-line comment. Per Python configparser, allow
|
||||
both ; and # comments at the start of a line by default. */
|
||||
#ifndef INI_START_COMMENT_PREFIXES
|
||||
#define INI_START_COMMENT_PREFIXES ";#"
|
||||
#endif
|
||||
|
||||
/* Nonzero to allow inline comments (with valid inline comment characters
|
||||
specified by INI_INLINE_COMMENT_PREFIXES). Set to 0 to turn off and match
|
||||
Python 3.2+ configparser behaviour. */
|
||||
#ifndef INI_ALLOW_INLINE_COMMENTS
|
||||
#define INI_ALLOW_INLINE_COMMENTS 1
|
||||
#endif
|
||||
#ifndef INI_INLINE_COMMENT_PREFIXES
|
||||
#define INI_INLINE_COMMENT_PREFIXES ";"
|
||||
#endif
|
||||
|
||||
/* Nonzero to use stack for line buffer, zero to use heap (malloc/free). */
|
||||
#ifndef INI_USE_STACK
|
||||
#define INI_USE_STACK 1
|
||||
#endif
|
||||
|
||||
/* Maximum line length for any line in INI file (stack or heap). Note that
|
||||
this must be 3 more than the longest line (due to '\r', '\n', and '\0'). */
|
||||
#ifndef INI_MAX_LINE
|
||||
#define INI_MAX_LINE 200
|
||||
#endif
|
||||
|
||||
/* Nonzero to allow heap line buffer to grow via realloc(), zero for a
|
||||
fixed-size buffer of INI_MAX_LINE bytes. Only applies if INI_USE_STACK is
|
||||
zero. */
|
||||
#ifndef INI_ALLOW_REALLOC
|
||||
#define INI_ALLOW_REALLOC 0
|
||||
#endif
|
||||
|
||||
/* Initial size in bytes for heap line buffer. Only applies if INI_USE_STACK
|
||||
is zero. */
|
||||
#ifndef INI_INITIAL_ALLOC
|
||||
#define INI_INITIAL_ALLOC 200
|
||||
#endif
|
||||
|
||||
/* Stop parsing on first error (default is to keep parsing). */
|
||||
#ifndef INI_STOP_ON_FIRST_ERROR
|
||||
#define INI_STOP_ON_FIRST_ERROR 0
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INI_H__ */
|
||||
127
sept/sept-secondary/src/lib/log.c
Normal file
127
sept/sept-secondary/src/lib/log.c
Normal file
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "log.h"
|
||||
|
||||
#include "../display/video_fb.h"
|
||||
#include "vsprintf.h"
|
||||
|
||||
/* default log level for screen output */
|
||||
ScreenLogLevel g_screen_log_level = SCREEN_LOG_LEVEL_NONE;
|
||||
|
||||
void log_set_log_level(ScreenLogLevel log_level) {
|
||||
g_screen_log_level = log_level;
|
||||
}
|
||||
|
||||
ScreenLogLevel log_get_log_level() {
|
||||
return g_screen_log_level;
|
||||
}
|
||||
|
||||
void log_to_uart(const char *message) {
|
||||
/* TODO: add UART logging */
|
||||
}
|
||||
|
||||
static void print_to_screen(ScreenLogLevel screen_log_level, char *message) {
|
||||
/* don't print to screen if below log level */
|
||||
if(screen_log_level > g_screen_log_level) return;
|
||||
|
||||
video_puts(message);
|
||||
}
|
||||
|
||||
/**
|
||||
* vprintk - logs a message and prints it to screen based on its screen_log_level
|
||||
*
|
||||
* If the level is below g_screen_log_level it will not be shown but logged to UART
|
||||
* This text will not be colored or prefixed
|
||||
* UART is TODO
|
||||
*/
|
||||
void vprint(ScreenLogLevel screen_log_level, const char *fmt, va_list args)
|
||||
{
|
||||
char buf[PRINT_MESSAGE_MAX_LENGTH];
|
||||
vsnprintf(buf, PRINT_MESSAGE_MAX_LENGTH, fmt, args);
|
||||
|
||||
/* we don't need that flag here, but if it gets used, strip it so we print correctly */
|
||||
screen_log_level &= ~SCREEN_LOG_LEVEL_NO_PREFIX;
|
||||
|
||||
/* log to UART */
|
||||
log_to_uart(buf);
|
||||
|
||||
print_to_screen(screen_log_level, buf);
|
||||
}
|
||||
|
||||
static void add_prefix(ScreenLogLevel screen_log_level, const char *fmt, char *buf) {
|
||||
char typebuf[] = "[%s] %s";
|
||||
|
||||
/* apply prefix and append message format */
|
||||
/* TODO: add coloring to the output */
|
||||
switch(screen_log_level)
|
||||
{
|
||||
case SCREEN_LOG_LEVEL_ERROR:
|
||||
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "ERROR", fmt);
|
||||
break;
|
||||
case SCREEN_LOG_LEVEL_WARNING:
|
||||
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "WARNING", fmt);
|
||||
break;
|
||||
case SCREEN_LOG_LEVEL_MANDATORY:
|
||||
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, "%s", fmt);
|
||||
break;
|
||||
case SCREEN_LOG_LEVEL_INFO:
|
||||
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "INFO", fmt);
|
||||
break;
|
||||
case SCREEN_LOG_LEVEL_DEBUG:
|
||||
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "DEBUG", fmt);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* print - logs a message and prints it to screen based on its screen_log_level
|
||||
*
|
||||
* If the level is below g_screen_log_level it will not be shown but logged to UART
|
||||
* Use SCREEN_LOG_LEVEL_NO_PREFIX if you don't want a prefix to be added
|
||||
* UART is TODO
|
||||
*/
|
||||
void print(ScreenLogLevel screen_log_level, const char * fmt, ...)
|
||||
{
|
||||
char buf[PRINT_MESSAGE_MAX_LENGTH] = {};
|
||||
char message[PRINT_MESSAGE_MAX_LENGTH] = {};
|
||||
|
||||
/* TODO: make splash disappear if level > MANDATORY */
|
||||
|
||||
/* make prefix free messages with log_level possible */
|
||||
if(screen_log_level & SCREEN_LOG_LEVEL_NO_PREFIX) {
|
||||
/* remove the NO_PREFIX flag so the enum can be recognized later on */
|
||||
screen_log_level &= ~SCREEN_LOG_LEVEL_NO_PREFIX;
|
||||
|
||||
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, "%s", fmt);
|
||||
}
|
||||
else {
|
||||
add_prefix(screen_log_level, fmt, buf);
|
||||
}
|
||||
|
||||
/* input arguments */
|
||||
va_list args;
|
||||
va_start(args, fmt);
|
||||
vsnprintf(message, PRINT_MESSAGE_MAX_LENGTH, buf, args);
|
||||
va_end(args);
|
||||
|
||||
/* log to UART */
|
||||
log_to_uart(message);
|
||||
|
||||
print_to_screen(screen_log_level, message);
|
||||
}
|
||||
43
sept/sept-secondary/src/lib/log.h
Normal file
43
sept/sept-secondary/src/lib/log.h
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_LOG_H
|
||||
#define FUSEE_LOG_H
|
||||
|
||||
#define PRINT_MESSAGE_MAX_LENGTH 512
|
||||
|
||||
#include <stdarg.h>
|
||||
|
||||
typedef enum {
|
||||
SCREEN_LOG_LEVEL_NONE = 0,
|
||||
SCREEN_LOG_LEVEL_ERROR = 1,
|
||||
SCREEN_LOG_LEVEL_WARNING = 2,
|
||||
SCREEN_LOG_LEVEL_MANDATORY = 3, /* no log prefix */
|
||||
SCREEN_LOG_LEVEL_INFO = 4,
|
||||
SCREEN_LOG_LEVEL_DEBUG = 5,
|
||||
|
||||
SCREEN_LOG_LEVEL_NO_PREFIX = 0x100 /* OR this to your LOG_LEVEL to prevent prefix creation */
|
||||
} ScreenLogLevel;
|
||||
|
||||
extern ScreenLogLevel g_screen_log_level;
|
||||
|
||||
void log_set_log_level(ScreenLogLevel screen_log_level);
|
||||
ScreenLogLevel log_get_log_level();
|
||||
void log_to_uart(const char *message);
|
||||
void vprint(ScreenLogLevel screen_log_level, const char *fmt, va_list args);
|
||||
void print(ScreenLogLevel screen_log_level, const char* fmt, ...);
|
||||
|
||||
#endif
|
||||
377
sept/sept-secondary/src/lib/lz.c
Normal file
377
sept/sept-secondary/src/lib/lz.c
Normal file
|
|
@ -0,0 +1,377 @@
|
|||
/*************************************************************************
|
||||
* Name: lz.c
|
||||
* Author: Marcus Geelnard
|
||||
* Description: LZ77 coder/decoder implementation.
|
||||
* Reentrant: Yes
|
||||
*
|
||||
* The LZ77 compression scheme is a substitutional compression scheme
|
||||
* proposed by Abraham Lempel and Jakob Ziv in 1977. It is very simple in
|
||||
* its design, and uses no fancy bit level compression.
|
||||
*
|
||||
* This is my first attempt at an implementation of a LZ77 code/decoder.
|
||||
*
|
||||
* The principle of the LZ77 compression algorithm is to store repeated
|
||||
* occurrences of strings as references to previous occurrences of the same
|
||||
* string. The point is that the reference consumes less space than the
|
||||
* string itself, provided that the string is long enough (in this
|
||||
* implementation, the string has to be at least 4 bytes long, since the
|
||||
* minimum coded reference is 3 bytes long). Also note that the term
|
||||
* "string" refers to any kind of byte sequence (it does not have to be
|
||||
* an ASCII string, for instance).
|
||||
*
|
||||
* The coder uses a brute force approach to finding string matches in the
|
||||
* history buffer (or "sliding window", if you wish), which is very, very
|
||||
* slow. I recon the complexity is somewhere between O(n^2) and O(n^3),
|
||||
* depending on the input data.
|
||||
*
|
||||
* There is also a faster implementation that uses a large working buffer
|
||||
* in which a "jump table" is stored, which is used to quickly find
|
||||
* possible string matches (see the source code for LZ_CompressFast() for
|
||||
* more information). The faster method is an order of magnitude faster,
|
||||
* but still quite slow compared to other compression methods.
|
||||
*
|
||||
* The upside is that decompression is very fast, and the compression ratio
|
||||
* is often very good.
|
||||
*
|
||||
* The reference to a string is coded as a (length,offset) pair, where the
|
||||
* length indicates the length of the string, and the offset gives the
|
||||
* offset from the current data position. To distinguish between string
|
||||
* references and literal strings (uncompressed bytes), a string reference
|
||||
* is preceded by a marker byte, which is chosen as the least common byte
|
||||
* symbol in the input data stream (this marker byte is stored in the
|
||||
* output stream as the first byte).
|
||||
*
|
||||
* Occurrences of the marker byte in the stream are encoded as the marker
|
||||
* byte followed by a zero byte, which means that occurrences of the marker
|
||||
* byte have to be coded with two bytes.
|
||||
*
|
||||
* The lengths and offsets are coded in a variable length fashion, allowing
|
||||
* values of any magnitude (up to 4294967295 in this implementation).
|
||||
*
|
||||
* With this compression scheme, the worst case compression result is
|
||||
* (257/256)*insize + 1.
|
||||
*
|
||||
*-------------------------------------------------------------------------
|
||||
* Copyright (c) 2003-2006 Marcus Geelnard
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would
|
||||
* be appreciated but is not required.
|
||||
*
|
||||
* 2. Altered source versions must be plainly marked as such, and must not
|
||||
* be misrepresented as being the original software.
|
||||
*
|
||||
* 3. This notice may not be removed or altered from any source
|
||||
* distribution.
|
||||
*
|
||||
* Marcus Geelnard
|
||||
* marcus.geelnard at home.se
|
||||
*************************************************************************/
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Constants used for LZ77 coding
|
||||
*************************************************************************/
|
||||
|
||||
/* Maximum offset (can be any size < 2^31). Lower values give faster
|
||||
compression, while higher values gives better compression. The default
|
||||
value of 100000 is quite high. Experiment to see what works best for
|
||||
you. */
|
||||
#define LZ_MAX_OFFSET 100000
|
||||
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* INTERNAL FUNCTIONS *
|
||||
*************************************************************************/
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* _LZ_StringCompare() - Return maximum length string match.
|
||||
*************************************************************************/
|
||||
|
||||
static unsigned int _LZ_StringCompare( const unsigned char * str1,
|
||||
const unsigned char * str2, unsigned int minlen, unsigned int maxlen )
|
||||
{
|
||||
unsigned int len;
|
||||
|
||||
for( len = minlen; (len < maxlen) && (str1[len] == str2[len]); ++ len );
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* _LZ_WriteVarSize() - Write unsigned integer with variable number of
|
||||
* bytes depending on value.
|
||||
*************************************************************************/
|
||||
|
||||
static int _LZ_WriteVarSize( unsigned int x, unsigned char * buf )
|
||||
{
|
||||
unsigned int y;
|
||||
int num_bytes, i, b;
|
||||
|
||||
/* Determine number of bytes needed to store the number x */
|
||||
y = x >> 3;
|
||||
for( num_bytes = 5; num_bytes >= 2; -- num_bytes )
|
||||
{
|
||||
if( y & 0xfe000000 ) break;
|
||||
y <<= 7;
|
||||
}
|
||||
|
||||
/* Write all bytes, seven bits in each, with 8:th bit set for all */
|
||||
/* but the last byte. */
|
||||
for( i = num_bytes-1; i >= 0; -- i )
|
||||
{
|
||||
b = (x >> (i*7)) & 0x0000007f;
|
||||
if( i > 0 )
|
||||
{
|
||||
b |= 0x00000080;
|
||||
}
|
||||
*buf ++ = (unsigned char) b;
|
||||
}
|
||||
|
||||
/* Return number of bytes written */
|
||||
return num_bytes;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* _LZ_ReadVarSize() - Read unsigned integer with variable number of
|
||||
* bytes depending on value.
|
||||
*************************************************************************/
|
||||
|
||||
static int _LZ_ReadVarSize( unsigned int * x, const unsigned char * buf )
|
||||
{
|
||||
unsigned int y, b, num_bytes;
|
||||
|
||||
/* Read complete value (stop when byte contains zero in 8:th bit) */
|
||||
y = 0;
|
||||
num_bytes = 0;
|
||||
do
|
||||
{
|
||||
b = (unsigned int) (*buf ++);
|
||||
y = (y << 7) | (b & 0x0000007f);
|
||||
++ num_bytes;
|
||||
}
|
||||
while( b & 0x00000080 );
|
||||
|
||||
/* Store value in x */
|
||||
*x = y;
|
||||
|
||||
/* Return number of bytes read */
|
||||
return num_bytes;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* PUBLIC FUNCTIONS *
|
||||
*************************************************************************/
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* LZ_Compress() - Compress a block of data using an LZ77 coder.
|
||||
* in - Input (uncompressed) buffer.
|
||||
* out - Output (compressed) buffer. This buffer must be 0.4% larger
|
||||
* than the input buffer, plus one byte.
|
||||
* insize - Number of input bytes.
|
||||
* The function returns the size of the compressed data.
|
||||
*************************************************************************/
|
||||
|
||||
int LZ_Compress( const unsigned char *in, unsigned char *out, unsigned int insize )
|
||||
{
|
||||
unsigned char marker, symbol;
|
||||
unsigned int inpos, outpos, bytesleft, i;
|
||||
unsigned int maxoffset, offset, bestoffset;
|
||||
unsigned int maxlength, length, bestlength;
|
||||
unsigned int histogram[ 256 ];
|
||||
const unsigned char *ptr1, *ptr2;
|
||||
|
||||
/* Do we have anything to compress? */
|
||||
if( insize < 1 )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Create histogram */
|
||||
for( i = 0; i < 256; ++ i )
|
||||
{
|
||||
histogram[ i ] = 0;
|
||||
}
|
||||
for( i = 0; i < insize; ++ i )
|
||||
{
|
||||
++ histogram[ in[ i ] ];
|
||||
}
|
||||
|
||||
/* Find the least common byte, and use it as the marker symbol */
|
||||
marker = 0;
|
||||
for( i = 1; i < 256; ++ i )
|
||||
{
|
||||
if( histogram[ i ] < histogram[ marker ] )
|
||||
{
|
||||
marker = (unsigned char) i;
|
||||
}
|
||||
}
|
||||
|
||||
/* Remember the marker symbol for the decoder */
|
||||
out[ 0 ] = marker;
|
||||
|
||||
/* Start of compression */
|
||||
inpos = 0;
|
||||
outpos = 1;
|
||||
|
||||
/* Main compression loop */
|
||||
bytesleft = insize;
|
||||
do
|
||||
{
|
||||
/* Determine most distant position */
|
||||
if( inpos > LZ_MAX_OFFSET ) maxoffset = LZ_MAX_OFFSET;
|
||||
else maxoffset = inpos;
|
||||
|
||||
/* Get pointer to current position */
|
||||
ptr1 = &in[ inpos ];
|
||||
|
||||
/* Search history window for maximum length string match */
|
||||
bestlength = 3;
|
||||
bestoffset = 0;
|
||||
for( offset = 3; offset <= maxoffset; ++ offset )
|
||||
{
|
||||
/* Get pointer to candidate string */
|
||||
ptr2 = &ptr1[ -(int)offset ];
|
||||
|
||||
/* Quickly determine if this is a candidate (for speed) */
|
||||
if( (ptr1[ 0 ] == ptr2[ 0 ]) &&
|
||||
(ptr1[ bestlength ] == ptr2[ bestlength ]) )
|
||||
{
|
||||
/* Determine maximum length for this offset */
|
||||
maxlength = (bytesleft < offset ? bytesleft : offset);
|
||||
|
||||
/* Count maximum length match at this offset */
|
||||
length = _LZ_StringCompare( ptr1, ptr2, 0, maxlength );
|
||||
|
||||
/* Better match than any previous match? */
|
||||
if( length > bestlength )
|
||||
{
|
||||
bestlength = length;
|
||||
bestoffset = offset;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Was there a good enough match? */
|
||||
if( (bestlength >= 8) ||
|
||||
((bestlength == 4) && (bestoffset <= 0x0000007f)) ||
|
||||
((bestlength == 5) && (bestoffset <= 0x00003fff)) ||
|
||||
((bestlength == 6) && (bestoffset <= 0x001fffff)) ||
|
||||
((bestlength == 7) && (bestoffset <= 0x0fffffff)) )
|
||||
{
|
||||
out[ outpos ++ ] = (unsigned char) marker;
|
||||
outpos += _LZ_WriteVarSize( bestlength, &out[ outpos ] );
|
||||
outpos += _LZ_WriteVarSize( bestoffset, &out[ outpos ] );
|
||||
inpos += bestlength;
|
||||
bytesleft -= bestlength;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Output single byte (or two bytes if marker byte) */
|
||||
symbol = in[ inpos ++ ];
|
||||
out[ outpos ++ ] = symbol;
|
||||
if( symbol == marker )
|
||||
{
|
||||
out[ outpos ++ ] = 0;
|
||||
}
|
||||
-- bytesleft;
|
||||
}
|
||||
}
|
||||
while( bytesleft > 3 );
|
||||
|
||||
/* Dump remaining bytes, if any */
|
||||
while( inpos < insize )
|
||||
{
|
||||
if( in[ inpos ] == marker )
|
||||
{
|
||||
out[ outpos ++ ] = marker;
|
||||
out[ outpos ++ ] = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
out[ outpos ++ ] = in[ inpos ];
|
||||
}
|
||||
++ inpos;
|
||||
}
|
||||
|
||||
return outpos;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* LZ_Uncompress() - Uncompress a block of data using an LZ77 decoder.
|
||||
* in - Input (compressed) buffer.
|
||||
* out - Output (uncompressed) buffer. This buffer must be large
|
||||
* enough to hold the uncompressed data.
|
||||
* insize - Number of input bytes.
|
||||
*************************************************************************/
|
||||
|
||||
int LZ_Uncompress( const unsigned char *in, unsigned char *out, unsigned int insize )
|
||||
{
|
||||
unsigned char marker, symbol;
|
||||
unsigned int i, inpos, outpos, length, offset;
|
||||
|
||||
/* Do we have anything to uncompress? */
|
||||
if( insize < 1 )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Get marker symbol from input stream */
|
||||
marker = in[ 0 ];
|
||||
inpos = 1;
|
||||
|
||||
/* Main decompression loop */
|
||||
outpos = 0;
|
||||
do
|
||||
{
|
||||
symbol = in[ inpos ++ ];
|
||||
if( symbol == marker )
|
||||
{
|
||||
/* We had a marker byte */
|
||||
if( in[ inpos ] == 0 )
|
||||
{
|
||||
/* It was a single occurrence of the marker byte */
|
||||
out[ outpos ++ ] = marker;
|
||||
++ inpos;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Extract true length and offset */
|
||||
inpos += _LZ_ReadVarSize( &length, &in[ inpos ] );
|
||||
inpos += _LZ_ReadVarSize( &offset, &in[ inpos ] );
|
||||
|
||||
/* Copy corresponding data from history window */
|
||||
for( i = 0; i < length; ++ i )
|
||||
{
|
||||
out[ outpos ] = out[ outpos - offset ];
|
||||
++ outpos;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No marker, plain copy */
|
||||
out[ outpos ++ ] = symbol;
|
||||
}
|
||||
}
|
||||
while( inpos < insize );
|
||||
|
||||
return outpos;
|
||||
}
|
||||
51
sept/sept-secondary/src/lib/lz.h
Normal file
51
sept/sept-secondary/src/lib/lz.h
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*************************************************************************
|
||||
* Name: lz.h
|
||||
* Author: Marcus Geelnard
|
||||
* Description: LZ77 coder/decoder interface.
|
||||
* Reentrant: Yes
|
||||
*-------------------------------------------------------------------------
|
||||
* Copyright (c) 2003-2006 Marcus Geelnard
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would
|
||||
* be appreciated but is not required.
|
||||
*
|
||||
* 2. Altered source versions must be plainly marked as such, and must not
|
||||
* be misrepresented as being the original software.
|
||||
*
|
||||
* 3. This notice may not be removed or altered from any source
|
||||
* distribution.
|
||||
*
|
||||
* Marcus Geelnard
|
||||
* marcus.geelnard at home.se
|
||||
*************************************************************************/
|
||||
|
||||
#ifndef _lz_h_
|
||||
#define _lz_h_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Function prototypes
|
||||
*************************************************************************/
|
||||
|
||||
int LZ_Compress(const unsigned char *in, unsigned char *out, unsigned int insize);
|
||||
int LZ_Uncompress(const unsigned char *in, unsigned char *out, unsigned int insize);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _lz_h_ */
|
||||
1676
sept/sept-secondary/src/lib/vsprintf.c
Normal file
1676
sept/sept-secondary/src/lib/vsprintf.c
Normal file
File diff suppressed because it is too large
Load diff
28
sept/sept-secondary/src/lib/vsprintf.h
Normal file
28
sept/sept-secondary/src/lib/vsprintf.h
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Andrei Warkentin <andrey.warkentin@gmail.com>
|
||||
*
|
||||
* This program is free software ; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#ifndef VSPRINTF_H
|
||||
#define VSPRINTF_H
|
||||
|
||||
struct va_format {
|
||||
const char *fmt;
|
||||
va_list *va;
|
||||
};
|
||||
|
||||
unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base);
|
||||
|
||||
int sprintf(char *buf, const char *fmt, ...);
|
||||
int scnprintf(char *buf, size_t size, const char *fmt, ...);
|
||||
int snprintf(char *buf, size_t size, const char *fmt, ...);
|
||||
int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
|
||||
int sscanf(const char *buf, const char *fmt, ...);
|
||||
|
||||
#endif /* VSPRINTF_H */
|
||||
105
sept/sept-secondary/src/main.c
Normal file
105
sept/sept-secondary/src/main.c
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "utils.h"
|
||||
#include "exception_handlers.h"
|
||||
#include "panic.h"
|
||||
#include "hwinit.h"
|
||||
#include "di.h"
|
||||
#include "timers.h"
|
||||
#include "fs_utils.h"
|
||||
#include "stage2.h"
|
||||
#include "chainloader.h"
|
||||
#include "sdmmc/sdmmc.h"
|
||||
#include "lib/fatfs/ff.h"
|
||||
#include "lib/log.h"
|
||||
#include "lib/vsprintf.h"
|
||||
#include "lib/ini.h"
|
||||
#include "display/video_fb.h"
|
||||
|
||||
extern void (*__program_exit_callback)(int rc);
|
||||
|
||||
static void *g_framebuffer;
|
||||
|
||||
static void setup_env(void) {
|
||||
g_framebuffer = (void *)0xC0000000;
|
||||
|
||||
/* Initialize hardware. */
|
||||
nx_hwinit();
|
||||
|
||||
/* Check for panics. */
|
||||
check_and_display_panic();
|
||||
|
||||
/* Zero-fill the framebuffer and register it as printk provider. */
|
||||
video_init(g_framebuffer);
|
||||
|
||||
/* Initialize the display. */
|
||||
display_init();
|
||||
|
||||
/* Set the framebuffer. */
|
||||
display_init_framebuffer(g_framebuffer);
|
||||
|
||||
/* Turn on the backlight after initializing the lfb */
|
||||
/* to avoid flickering. */
|
||||
display_backlight(true);
|
||||
|
||||
/* Set up the exception handlers. */
|
||||
setup_exception_handlers();
|
||||
|
||||
/* Mount the SD card. */
|
||||
mount_sd();
|
||||
}
|
||||
|
||||
static void cleanup_env(void) {
|
||||
/* Unmount the SD card. */
|
||||
unmount_sd();
|
||||
|
||||
display_backlight(false);
|
||||
display_end();
|
||||
}
|
||||
|
||||
static void exit_callback(int rc) {
|
||||
(void)rc;
|
||||
relocate_and_chainload();
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
ScreenLogLevel log_level = SCREEN_LOG_LEVEL_MANDATORY;
|
||||
|
||||
/* Override the global logging level. */
|
||||
log_set_log_level(log_level);
|
||||
|
||||
/* Initialize the display, console, etc. */
|
||||
setup_env();
|
||||
|
||||
/* Say hello. */
|
||||
print(SCREEN_LOG_LEVEL_MANDATORY, "Welcome to Atmosph\xe8re sept-secondary!\n");
|
||||
while (true) { }
|
||||
|
||||
/* TODO: Derive keys. */
|
||||
|
||||
/* TODO: Chainload to payload. */
|
||||
|
||||
/* Wait a while. */
|
||||
mdelay(1000);
|
||||
|
||||
/* Deinitialize the display, console, etc. */
|
||||
cleanup_env();
|
||||
|
||||
/* Finally, after the cleanup routines (__libc_fini_array, etc.) are called, jump to Stage2. */
|
||||
__program_exit_callback = exit_callback;
|
||||
return 0;
|
||||
}
|
||||
357
sept/sept-secondary/src/max77620.h
Normal file
357
sept/sept-secondary/src/max77620.h
Normal file
|
|
@ -0,0 +1,357 @@
|
|||
/*
|
||||
* Defining registers address and its bit definitions of MAX77620 and MAX20024
|
||||
*
|
||||
* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _MFD_MAX77620_H_
|
||||
#define _MFD_MAX77620_H_
|
||||
|
||||
/* RTC Registers */
|
||||
#define MAX77620_REG_RTCINT 0x00
|
||||
#define MAX77620_REG_RTCINTM 0x01
|
||||
#define MAX77620_REG_RTCCNTLM 0x02
|
||||
#define MAX77620_REG_RTCCNTL 0x03
|
||||
#define MAX77620_REG_RTCUPDATE0 0x04
|
||||
#define MAX77620_REG_RTCUPDATE1 0x05
|
||||
#define MAX77620_REG_RTCSMPL 0x06
|
||||
#define MAX77620_REG_RTCSEC 0x07
|
||||
#define MAX77620_REG_RTCMIN 0x08
|
||||
#define MAX77620_REG_RTCHOUR 0x09
|
||||
#define MAX77620_REG_RTCDOW 0x0A
|
||||
#define MAX77620_REG_RTCMONTH 0x0B
|
||||
#define MAX77620_REG_RTCYEAR 0x0C
|
||||
#define MAX77620_REG_RTCDOM 0x0D
|
||||
#define MAX77620_REG_RTCSECA1 0x0E
|
||||
#define MAX77620_REG_RTCMINA1 0x0F
|
||||
#define MAX77620_REG_RTCHOURA1 0x10
|
||||
#define MAX77620_REG_RTCDOWA1 0x11
|
||||
#define MAX77620_REG_RTCMONTHA1 0x12
|
||||
#define MAX77620_REG_RTCYEARA1 0x13
|
||||
#define MAX77620_REG_RTCDOMA1 0x14
|
||||
#define MAX77620_REG_RTCSECA2 0x15
|
||||
#define MAX77620_REG_RTCMINA2 0x16
|
||||
#define MAX77620_REG_RTCHOURA2 0x17
|
||||
#define MAX77620_REG_RTCDOWA2 0x18
|
||||
#define MAX77620_REG_RTCMONTHA2 0x19
|
||||
#define MAX77620_REG_RTCYEARA2 0x1A
|
||||
#define MAX77620_REG_RTCDOMA2 0x1B
|
||||
|
||||
/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
|
||||
#define MAX77620_REG_CNFGGLBL1 0x00
|
||||
#define MAX77620_REG_CNFGGLBL2 0x01
|
||||
#define MAX77620_REG_CNFGGLBL3 0x02
|
||||
#define MAX77620_REG_CNFG1_32K 0x03
|
||||
#define MAX77620_REG_CNFGBBC 0x04
|
||||
#define MAX77620_REG_IRQTOP 0x05
|
||||
#define MAX77620_REG_INTLBT 0x06
|
||||
#define MAX77620_REG_IRQSD 0x07
|
||||
#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
|
||||
#define MAX77620_REG_IRQ_LVL2_L8 0x09
|
||||
#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
|
||||
#define MAX77620_REG_ONOFFIRQ 0x0B
|
||||
#define MAX77620_REG_NVERC 0x0C
|
||||
#define MAX77620_REG_IRQTOPM 0x0D
|
||||
#define MAX77620_REG_INTENLBT 0x0E
|
||||
#define MAX77620_REG_IRQMASKSD 0x0F
|
||||
#define MAX77620_REG_IRQ_MSK_L0_7 0x10
|
||||
#define MAX77620_REG_IRQ_MSK_L8 0x11
|
||||
#define MAX77620_REG_ONOFFIRQM 0x12
|
||||
#define MAX77620_REG_STATLBT 0x13
|
||||
#define MAX77620_REG_STATSD 0x14
|
||||
#define MAX77620_REG_ONOFFSTAT 0x15
|
||||
|
||||
/* SD and LDO Registers */
|
||||
#define MAX77620_REG_SD0 0x16
|
||||
#define MAX77620_REG_SD1 0x17
|
||||
#define MAX77620_REG_SD2 0x18
|
||||
#define MAX77620_REG_SD3 0x19
|
||||
#define MAX77620_REG_SD4 0x1A
|
||||
#define MAX77620_REG_DVSSD0 0x1B
|
||||
#define MAX77620_REG_DVSSD1 0x1C
|
||||
#define MAX77620_REG_SD0_CFG 0x1D
|
||||
#define MAX77620_REG_SD1_CFG 0x1E
|
||||
#define MAX77620_REG_SD2_CFG 0x1F
|
||||
#define MAX77620_REG_SD3_CFG 0x20
|
||||
#define MAX77620_REG_SD4_CFG 0x21
|
||||
#define MAX77620_REG_SD_CFG2 0x22
|
||||
#define MAX77620_REG_LDO0_CFG 0x23
|
||||
#define MAX77620_REG_LDO0_CFG2 0x24
|
||||
#define MAX77620_REG_LDO1_CFG 0x25
|
||||
#define MAX77620_REG_LDO1_CFG2 0x26
|
||||
#define MAX77620_REG_LDO2_CFG 0x27
|
||||
#define MAX77620_REG_LDO2_CFG2 0x28
|
||||
#define MAX77620_REG_LDO3_CFG 0x29
|
||||
#define MAX77620_REG_LDO3_CFG2 0x2A
|
||||
#define MAX77620_REG_LDO4_CFG 0x2B
|
||||
#define MAX77620_REG_LDO4_CFG2 0x2C
|
||||
#define MAX77620_REG_LDO5_CFG 0x2D
|
||||
#define MAX77620_REG_LDO5_CFG2 0x2E
|
||||
#define MAX77620_REG_LDO6_CFG 0x2F
|
||||
#define MAX77620_REG_LDO6_CFG2 0x30
|
||||
#define MAX77620_REG_LDO7_CFG 0x31
|
||||
#define MAX77620_REG_LDO7_CFG2 0x32
|
||||
#define MAX77620_REG_LDO8_CFG 0x33
|
||||
#define MAX77620_REG_LDO8_CFG2 0x34
|
||||
#define MAX77620_REG_LDO_CFG3 0x35
|
||||
|
||||
#define MAX77620_LDO_SLEW_RATE_MASK 0x1
|
||||
|
||||
/* LDO Configuration 3 */
|
||||
#define MAX77620_TRACK4_MASK (1 << 5)
|
||||
#define MAX77620_TRACK4_SHIFT 5
|
||||
|
||||
/* Voltage */
|
||||
#define MAX77620_SDX_VOLT_MASK 0xFF
|
||||
#define MAX77620_SD0_VOLT_MASK 0x3F
|
||||
#define MAX77620_SD1_VOLT_MASK 0x7F
|
||||
#define MAX77620_LDO_VOLT_MASK 0x3F
|
||||
|
||||
#define MAX77620_REG_GPIO0 0x36
|
||||
#define MAX77620_REG_GPIO1 0x37
|
||||
#define MAX77620_REG_GPIO2 0x38
|
||||
#define MAX77620_REG_GPIO3 0x39
|
||||
#define MAX77620_REG_GPIO4 0x3A
|
||||
#define MAX77620_REG_GPIO5 0x3B
|
||||
#define MAX77620_REG_GPIO6 0x3C
|
||||
#define MAX77620_REG_GPIO7 0x3D
|
||||
#define MAX77620_REG_PUE_GPIO 0x3E
|
||||
#define MAX77620_REG_PDE_GPIO 0x3F
|
||||
#define MAX77620_REG_AME_GPIO 0x40
|
||||
#define MAX77620_REG_ONOFFCNFG1 0x41
|
||||
#define MAX77620_REG_ONOFFCNFG2 0x42
|
||||
|
||||
/* FPS Registers */
|
||||
#define MAX77620_REG_FPS_CFG0 0x43
|
||||
#define MAX77620_REG_FPS_CFG1 0x44
|
||||
#define MAX77620_REG_FPS_CFG2 0x45
|
||||
#define MAX77620_REG_FPS_LDO0 0x46
|
||||
#define MAX77620_REG_FPS_LDO1 0x47
|
||||
#define MAX77620_REG_FPS_LDO2 0x48
|
||||
#define MAX77620_REG_FPS_LDO3 0x49
|
||||
#define MAX77620_REG_FPS_LDO4 0x4A
|
||||
#define MAX77620_REG_FPS_LDO5 0x4B
|
||||
#define MAX77620_REG_FPS_LDO6 0x4C
|
||||
#define MAX77620_REG_FPS_LDO7 0x4D
|
||||
#define MAX77620_REG_FPS_LDO8 0x4E
|
||||
#define MAX77620_REG_FPS_SD0 0x4F
|
||||
#define MAX77620_REG_FPS_SD1 0x50
|
||||
#define MAX77620_REG_FPS_SD2 0x51
|
||||
#define MAX77620_REG_FPS_SD3 0x52
|
||||
#define MAX77620_REG_FPS_SD4 0x53
|
||||
#define MAX77620_REG_FPS_NONE 0
|
||||
|
||||
#define MAX77620_FPS_SRC_MASK 0xC0
|
||||
#define MAX77620_FPS_SRC_SHIFT 6
|
||||
#define MAX77620_FPS_PU_PERIOD_MASK 0x38
|
||||
#define MAX77620_FPS_PU_PERIOD_SHIFT 3
|
||||
#define MAX77620_FPS_PD_PERIOD_MASK 0x07
|
||||
#define MAX77620_FPS_PD_PERIOD_SHIFT 0
|
||||
#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
|
||||
#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
|
||||
#define MAX77620_FPS_EN_SRC_MASK 0x06
|
||||
#define MAX77620_FPS_EN_SRC_SHIFT 1
|
||||
#define MAX77620_FPS_ENFPS_SW_MASK 0x01
|
||||
#define MAX77620_FPS_ENFPS_SW 0x01
|
||||
|
||||
/* Minimum and maximum FPS period time (in microseconds) are
|
||||
* different for MAX77620 and Max20024.
|
||||
*/
|
||||
#define MAX77620_FPS_PERIOD_MIN_US 40
|
||||
#define MAX20024_FPS_PERIOD_MIN_US 20
|
||||
|
||||
#define MAX77620_FPS_PERIOD_MAX_US 2560
|
||||
#define MAX20024_FPS_PERIOD_MAX_US 5120
|
||||
|
||||
#define MAX77620_REG_FPS_GPIO1 0x54
|
||||
#define MAX77620_REG_FPS_GPIO2 0x55
|
||||
#define MAX77620_REG_FPS_GPIO3 0x56
|
||||
#define MAX77620_REG_FPS_RSO 0x57
|
||||
#define MAX77620_REG_CID0 0x58
|
||||
#define MAX77620_REG_CID1 0x59
|
||||
#define MAX77620_REG_CID2 0x5A
|
||||
#define MAX77620_REG_CID3 0x5B
|
||||
#define MAX77620_REG_CID4 0x5C
|
||||
#define MAX77620_REG_CID5 0x5D
|
||||
|
||||
#define MAX77620_REG_DVSSD4 0x5E
|
||||
#define MAX20024_REG_MAX_ADD 0x70
|
||||
|
||||
#define MAX77620_CID_DIDM_MASK 0xF0
|
||||
#define MAX77620_CID_DIDM_SHIFT 4
|
||||
|
||||
/* CNCG2SD */
|
||||
#define MAX77620_SD_CNF2_ROVS_EN_SD1 (1 << 1)
|
||||
#define MAX77620_SD_CNF2_ROVS_EN_SD0 (1 << 2)
|
||||
|
||||
/* Device Identification Metal */
|
||||
#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
|
||||
/* Device Indentification OTP */
|
||||
#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
|
||||
|
||||
/* SD CNFG1 */
|
||||
#define MAX77620_SD_SR_MASK 0xC0
|
||||
#define MAX77620_SD_SR_SHIFT 6
|
||||
#define MAX77620_SD_POWER_MODE_MASK 0x30
|
||||
#define MAX77620_SD_POWER_MODE_SHIFT 4
|
||||
#define MAX77620_SD_CFG1_ADE_MASK (1 << 3)
|
||||
#define MAX77620_SD_CFG1_ADE_DISABLE 0
|
||||
#define MAX77620_SD_CFG1_ADE_ENABLE (1 << 3)
|
||||
#define MAX77620_SD_FPWM_MASK 0x04
|
||||
#define MAX77620_SD_FPWM_SHIFT 2
|
||||
#define MAX77620_SD_FSRADE_MASK 0x01
|
||||
#define MAX77620_SD_FSRADE_SHIFT 0
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_MASK (1 << 2)
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_FPWM (1 << 2)
|
||||
#define MAX20024_SD_CFG1_MPOK_MASK (1 << 1)
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_MASK (1 << 0)
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0)
|
||||
|
||||
/* LDO_CNFG2 */
|
||||
#define MAX77620_LDO_POWER_MODE_MASK 0xC0
|
||||
#define MAX77620_LDO_POWER_MODE_SHIFT 6
|
||||
#define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2)
|
||||
#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1)
|
||||
#define MAX77620_LDO_CFG2_ADE_DISABLE 0
|
||||
#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1)
|
||||
#define MAX77620_LDO_CFG2_SS_MASK (1 << 0)
|
||||
#define MAX77620_LDO_CFG2_SS_FAST (1 << 0)
|
||||
#define MAX77620_LDO_CFG2_SS_SLOW 0
|
||||
|
||||
#define MAX77620_IRQ_TOP_GLBL_MASK (1 << 7)
|
||||
#define MAX77620_IRQ_TOP_SD_MASK (1 << 6)
|
||||
#define MAX77620_IRQ_TOP_LDO_MASK (1 << 5)
|
||||
#define MAX77620_IRQ_TOP_GPIO_MASK (1 << 4)
|
||||
#define MAX77620_IRQ_TOP_RTC_MASK (1 << 3)
|
||||
#define MAX77620_IRQ_TOP_32K_MASK (1 << 2)
|
||||
#define MAX77620_IRQ_TOP_ONOFF_MASK (1 << 1)
|
||||
|
||||
#define MAX77620_IRQ_LBM_MASK (1 << 3)
|
||||
#define MAX77620_IRQ_TJALRM1_MASK (1 << 2)
|
||||
#define MAX77620_IRQ_TJALRM2_MASK (1 << 1)
|
||||
|
||||
#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0)
|
||||
#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0)
|
||||
#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
|
||||
#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1)
|
||||
#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1)
|
||||
#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
|
||||
#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2)
|
||||
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3)
|
||||
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3)
|
||||
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
|
||||
#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
|
||||
#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4)
|
||||
#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5)
|
||||
#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
|
||||
#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
|
||||
#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
|
||||
#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
|
||||
#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
|
||||
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE3 (1 << 3)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE4 (1 << 4)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE5 (1 << 5)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE6 (1 << 6)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE7 (1 << 7)
|
||||
|
||||
#define MAX77620_CNFG1_32K_OUT0_EN (1 << 2)
|
||||
|
||||
#define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7)
|
||||
#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
|
||||
#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
|
||||
#define MAX77620_ONOFFCNFG1_SLPEN (1 << 2)
|
||||
#define MAX77620_ONOFFCNFG1_PWR_OFF (1 << 1)
|
||||
#define MAX20024_ONOFFCNFG1_CLRSE 0x18
|
||||
|
||||
#define MAX77620_ONOFFCNFG2_SFT_RST_WK (1 << 7)
|
||||
#define MAX77620_ONOFFCNFG2_WD_RST_WK (1 << 6)
|
||||
#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK (1 << 5)
|
||||
#define MAX77620_ONOFFCNFG2_WK_ALARM1 (1 << 2)
|
||||
#define MAX77620_ONOFFCNFG2_WK_EN0 (1 << 0)
|
||||
|
||||
#define MAX77620_GLBLM_MASK (1 << 0)
|
||||
|
||||
#define MAX77620_WDTC_MASK 0x3
|
||||
#define MAX77620_WDTOFFC (1 << 4)
|
||||
#define MAX77620_WDTSLPC (1 << 3)
|
||||
#define MAX77620_WDTEN (1 << 2)
|
||||
|
||||
#define MAX77620_TWD_MASK 0x3
|
||||
#define MAX77620_TWD_2s 0x0
|
||||
#define MAX77620_TWD_16s 0x1
|
||||
#define MAX77620_TWD_64s 0x2
|
||||
#define MAX77620_TWD_128s 0x3
|
||||
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_EN (1 << 7)
|
||||
#define MAX77620_CNFGGLBL1_MPPLD (1 << 6)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST ((1 << 5) | (1 << 4))
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_N (1 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC 0x0E
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_N (1 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBRSTEN (1 << 0)
|
||||
|
||||
/* CNFG BBC registers */
|
||||
#define MAX77620_CNFGBBC_ENABLE (1 << 0)
|
||||
#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
|
||||
#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
|
||||
#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
|
||||
#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
|
||||
#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5)
|
||||
#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
|
||||
#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
|
||||
|
||||
#define MAX77620_FPS_COUNT 3
|
||||
|
||||
/* Interrupts */
|
||||
enum {
|
||||
MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
|
||||
MAX77620_IRQ_TOP_SD, /* SD power fail */
|
||||
MAX77620_IRQ_TOP_LDO, /* LDO power fail */
|
||||
MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
|
||||
MAX77620_IRQ_TOP_RTC, /* RTC */
|
||||
MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
|
||||
MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
|
||||
MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
|
||||
MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
|
||||
MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
|
||||
};
|
||||
|
||||
/* GPIOs */
|
||||
enum {
|
||||
MAX77620_GPIO0,
|
||||
MAX77620_GPIO1,
|
||||
MAX77620_GPIO2,
|
||||
MAX77620_GPIO3,
|
||||
MAX77620_GPIO4,
|
||||
MAX77620_GPIO5,
|
||||
MAX77620_GPIO6,
|
||||
MAX77620_GPIO7,
|
||||
MAX77620_GPIO_NR,
|
||||
};
|
||||
|
||||
/* FPS Source */
|
||||
enum max77620_fps_src {
|
||||
MAX77620_FPS_SRC_0,
|
||||
MAX77620_FPS_SRC_1,
|
||||
MAX77620_FPS_SRC_2,
|
||||
MAX77620_FPS_SRC_NONE,
|
||||
MAX77620_FPS_SRC_DEF,
|
||||
};
|
||||
|
||||
enum max77620_chip_id {
|
||||
MAX77620,
|
||||
MAX20024,
|
||||
};
|
||||
|
||||
#endif /* _MFD_MAX77620_H_ */
|
||||
178
sept/sept-secondary/src/max7762x.c
Normal file
178
sept/sept-secondary/src/max7762x.c
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "max7762x.h"
|
||||
#include "max77620.h"
|
||||
#include "i2c.h"
|
||||
#include "timers.h"
|
||||
|
||||
#define REGULATOR_SD 0
|
||||
#define REGULATOR_LDO 1
|
||||
|
||||
typedef struct _max77620_regulator_t
|
||||
{
|
||||
uint8_t type;
|
||||
const char *name;
|
||||
uint8_t reg_sd;
|
||||
uint32_t mv_step;
|
||||
uint32_t mv_min;
|
||||
uint32_t mv_default;
|
||||
uint32_t mv_max;
|
||||
uint8_t volt_addr;
|
||||
uint8_t cfg_addr;
|
||||
uint8_t volt_mask;
|
||||
uint8_t enable_mask;
|
||||
uint8_t enable_shift;
|
||||
uint8_t status_mask;
|
||||
|
||||
uint8_t fps_addr;
|
||||
uint8_t fps_src;
|
||||
uint8_t pd_period;
|
||||
uint8_t pu_period;
|
||||
} max77620_regulator_t;
|
||||
|
||||
static const max77620_regulator_t _pmic_regulators[] = {
|
||||
{ REGULATOR_SD, "sd0", 0x16, 12500, 600000, 625000, 1400000, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, 0x3F, 0x30, 4, 0x80, 0x4F, 1, 7, 1 },
|
||||
{ REGULATOR_SD, "sd1", 0x17, 12500, 600000, 1125000, 1125000, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, 0x3F, 0x30, 4, 0x40, 0x50, 0, 1, 5 },
|
||||
{ REGULATOR_SD, "sd2", 0x18, 12500, 600000, 1325000, 1350000, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, 0xFF, 0x30, 4, 0x20, 0x51, 1, 5, 2 },
|
||||
{ REGULATOR_SD, "sd3", 0x19, 12500, 600000, 1800000, 1800000, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, 0xFF, 0x30, 4, 0x10, 0x52, 0, 3, 3 },
|
||||
{ REGULATOR_LDO, "ldo0", 0x00, 25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, 0x3F, 0xC0, 6, 0x00, 0x46, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo1", 0x00, 25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, 0x3F, 0xC0, 6, 0x00, 0x47, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo2", 0x00, 50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, 0x3F, 0xC0, 6, 0x00, 0x48, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo3", 0x00, 50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, 0x3F, 0xC0, 6, 0x00, 0x49, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo4", 0x00, 12500, 800000, 850000, 850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4A, 0, 7, 1 },
|
||||
{ REGULATOR_LDO, "ldo5", 0x00, 50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4B, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo6", 0x00, 50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4C, 3, 7, 0 },
|
||||
{ REGULATOR_LDO, "ldo7", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4D, 1, 4, 3 },
|
||||
{ REGULATOR_LDO, "ldo8", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4E, 3, 7, 0 }
|
||||
};
|
||||
|
||||
int max77620_regulator_get_status(uint32_t id)
|
||||
{
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
uint8_t val = 0;
|
||||
|
||||
if (reg->type == REGULATOR_SD) {
|
||||
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_STATSD, &val, 1))
|
||||
return (val & reg->status_mask) ? 0 : 1;
|
||||
}
|
||||
|
||||
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->cfg_addr, &val, 1))
|
||||
return (val & 8) ? 1 : 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int max77620_regulator_config_fps(uint32_t id)
|
||||
{
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
uint8_t val = ((reg->fps_src << 6) | (reg->pu_period << 3) | (reg->pd_period));
|
||||
|
||||
if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, reg->fps_addr, &val, 1)) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int max77620_regulator_set_voltage(uint32_t id, uint32_t mv)
|
||||
{
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
if ((mv < reg->mv_default) || (mv > reg->mv_max))
|
||||
return 0;
|
||||
|
||||
uint32_t mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
|
||||
uint8_t val = 0;
|
||||
|
||||
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->volt_addr, &val, 1))
|
||||
{
|
||||
val = ((val & ~reg->volt_mask) | (mult & reg->volt_mask));
|
||||
|
||||
if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, reg->volt_addr, &val, 1))
|
||||
{
|
||||
udelay(1000);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int max77620_regulator_enable(uint32_t id, int enable)
|
||||
{
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
uint32_t addr = (reg->type == REGULATOR_SD) ? reg->cfg_addr : reg->volt_addr;
|
||||
uint8_t val = 0;
|
||||
|
||||
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, addr, &val, 1))
|
||||
{
|
||||
if (enable)
|
||||
val = ((val & ~reg->enable_mask) | ((3 << reg->enable_shift) & reg->enable_mask));
|
||||
else
|
||||
val &= ~reg->enable_mask;
|
||||
|
||||
if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, addr, &val, 1))
|
||||
{
|
||||
udelay(1000);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void max77620_config_default()
|
||||
{
|
||||
for (uint32_t i = 1; i <= REGULATOR_MAX; i++)
|
||||
{
|
||||
uint8_t val = 0;
|
||||
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CID4, &val, 1))
|
||||
{
|
||||
max77620_regulator_config_fps(i);
|
||||
max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default);
|
||||
|
||||
if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE) {
|
||||
max77620_regulator_enable(i, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t val = 4;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1);
|
||||
}
|
||||
|
||||
void max77620_low_battery_monitor_config()
|
||||
{
|
||||
uint8_t val = (MAX77620_CNFGGLBL1_LBDAC_EN | MAX77620_CNFGGLBL1_LBHYST_N | MAX77620_CNFGGLBL1_LBDAC_N);
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
|
||||
}
|
||||
68
sept/sept-secondary/src/max7762x.h
Normal file
68
sept/sept-secondary/src/max7762x.h
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_MAX7762X_H_
|
||||
#define FUSEE_MAX7762X_H_
|
||||
|
||||
/*
|
||||
* Switch Power domains (max77620):
|
||||
* Name | Usage | uV step | uV min | uV default | uV max | Init
|
||||
*-------+---------------+---------+--------+------------+---------+------------------
|
||||
* sd0 | core | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1)
|
||||
* sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1)
|
||||
* sd2 | ldo{0-1, 7-8} | 12500 | 600000 | 1325000 | 1350000 | 1.325V (pcv)
|
||||
* sd3 | 1.8V general | 12500 | 600000 | 1800000 | 1800000 |
|
||||
* ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1)
|
||||
* ldo1 | XUSB, PCIE | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv)
|
||||
* ldo2 | SDMMC1 | 50000 | 800000 | 1800000 | 3300000 |
|
||||
* ldo3 | | 50000 | 800000 | 3100000 | 3100000 |
|
||||
* ldo4 | RTC | 12500 | 800000 | 850000 | 850000 |
|
||||
* ldo5 | | 50000 | 800000 | 1800000 | 1800000 |
|
||||
* ldo6 | | 50000 | 800000 | 2900000 | 2900000 |
|
||||
* ldo7 | XUSB | 50000 | 800000 | 1050000 | 1050000 |
|
||||
* ldo8 | XUSB, DC | 50000 | 800000 | 1050000 | 1050000 |
|
||||
*/
|
||||
|
||||
/*
|
||||
* MAX77620_AME_GPIO: control GPIO modes (bits 0 - 7 correspond to GPIO0 - GPIO7); 0 -> GPIO, 1 -> alt-mode
|
||||
* MAX77620_REG_GPIOx: 0x9 sets output and enable
|
||||
*/
|
||||
|
||||
/*! MAX77620 partitions. */
|
||||
#define REGULATOR_SD0 0
|
||||
#define REGULATOR_SD1 1
|
||||
#define REGULATOR_SD2 2
|
||||
#define REGULATOR_SD3 3
|
||||
#define REGULATOR_LDO0 4
|
||||
#define REGULATOR_LDO1 5
|
||||
#define REGULATOR_LDO2 6
|
||||
#define REGULATOR_LDO3 7
|
||||
#define REGULATOR_LDO4 8
|
||||
#define REGULATOR_LDO5 9
|
||||
#define REGULATOR_LDO6 10
|
||||
#define REGULATOR_LDO7 11
|
||||
#define REGULATOR_LDO8 12
|
||||
#define REGULATOR_MAX 12
|
||||
|
||||
int max77620_regulator_get_status(uint32_t id);
|
||||
int max77620_regulator_config_fps(uint32_t id);
|
||||
int max77620_regulator_set_voltage(uint32_t id, uint32_t mv);
|
||||
int max77620_regulator_enable(uint32_t id, int enable);
|
||||
void max77620_config_default();
|
||||
void max77620_low_battery_monitor_config();
|
||||
|
||||
#endif
|
||||
169
sept/sept-secondary/src/mc.c
Normal file
169
sept/sept-secondary/src/mc.c
Normal file
|
|
@ -0,0 +1,169 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "mc.h"
|
||||
#include "car.h"
|
||||
#include "timers.h"
|
||||
|
||||
void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock)
|
||||
{
|
||||
MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = bom;
|
||||
MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = size1mb;
|
||||
|
||||
if (lock)
|
||||
MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = 1;
|
||||
}
|
||||
|
||||
void mc_config_carveout()
|
||||
{
|
||||
*(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC;
|
||||
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1;
|
||||
|
||||
mc_config_tsec_carveout(0, 0, true);
|
||||
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0;
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0;
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1;
|
||||
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006;
|
||||
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM_HI) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
|
||||
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
|
||||
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
|
||||
}
|
||||
|
||||
void mc_config_carveout_finalize()
|
||||
{
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM_HI) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
|
||||
MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E;
|
||||
}
|
||||
|
||||
void mc_enable_ahb_redirect()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
car->lvl2_clk_gate_ovrd = ((car->lvl2_clk_gate_ovrd & 0xFFF7FFFF) | 0x80000);
|
||||
|
||||
MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000;
|
||||
MAKE_MC_REG(MC_IRAM_TOM) = 0x4003F000;
|
||||
}
|
||||
|
||||
void mc_disable_ahb_redirect()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
|
||||
MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000;
|
||||
MAKE_MC_REG(MC_IRAM_TOM) = 0;
|
||||
|
||||
car->lvl2_clk_gate_ovrd &= 0xFFF7FFFF;
|
||||
}
|
||||
|
||||
void mc_enable()
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
|
||||
/* Set EMC clock source. */
|
||||
car->clk_source_emc = ((car->clk_source_emc & 0x1FFFFFFF) | 0x40000000);
|
||||
|
||||
/* Enable MIPI CAL clock. */
|
||||
car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFDFFFFFF) | 0x2000000);
|
||||
|
||||
/* Enable MC clock. */
|
||||
car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFFFFFFFE) | 1);
|
||||
|
||||
/* Enable EMC DLL clock. */
|
||||
car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000);
|
||||
|
||||
/* Clear EMC and MC reset. */
|
||||
/* NOTE: [4.0.0+] This was changed to use the right register. */
|
||||
/* car->rst_dev_h_set = 0x2000001; */
|
||||
car->rst_dev_h_clr = 0x2000001;
|
||||
udelay(5);
|
||||
|
||||
mc_disable_ahb_redirect();
|
||||
}
|
||||
598
sept/sept-secondary/src/mc.h
Normal file
598
sept/sept-secondary/src/mc.h
Normal file
|
|
@ -0,0 +1,598 @@
|
|||
/*
|
||||
* Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_MC_H_
|
||||
#define FUSEE_MC_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define MC_BASE 0x70019000
|
||||
#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n)
|
||||
|
||||
#define MC_INTSTATUS 0x0
|
||||
#define MC_INTMASK 0x4
|
||||
#define MC_ERR_STATUS 0x8
|
||||
#define MC_ERR_ADR 0xc
|
||||
#define MC_SMMU_CONFIG 0x10
|
||||
#define MC_SMMU_TLB_CONFIG 0x14
|
||||
#define MC_SMMU_PTC_CONFIG 0x18
|
||||
#define MC_SMMU_PTB_ASID 0x1c
|
||||
#define MC_SMMU_PTB_DATA 0x20
|
||||
#define MC_SMMU_TLB_FLUSH 0x30
|
||||
#define MC_SMMU_PTC_FLUSH 0x34
|
||||
#define MC_SMMU_ASID_SECURITY 0x38
|
||||
#define MC_SMMU_AFI_ASID 0x238
|
||||
#define MC_SMMU_AVPC_ASID 0x23c
|
||||
#define MC_SMMU_TSEC_ASID 0x294
|
||||
#define MC_SMMU_PPCS1_ASID 0x298
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
|
||||
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3 0xddc
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0
|
||||
#define MC_EMEM_CFG 0x50
|
||||
#define MC_EMEM_ADR_CFG 0x54
|
||||
#define MC_EMEM_ADR_CFG_DEV0 0x58
|
||||
#define MC_EMEM_ADR_CFG_DEV1 0x5c
|
||||
#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60
|
||||
#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64
|
||||
#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68
|
||||
#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c
|
||||
#define MC_SECURITY_CFG0 0x70
|
||||
#define MC_SECURITY_CFG1 0x74
|
||||
#define MC_SECURITY_CFG3 0x9bc
|
||||
#define MC_SECURITY_RSV 0x7c
|
||||
#define MC_EMEM_ARB_CFG 0x90
|
||||
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
|
||||
#define MC_EMEM_ARB_TIMING_RCD 0x98
|
||||
#define MC_EMEM_ARB_TIMING_RP 0x9c
|
||||
#define MC_EMEM_ARB_TIMING_RC 0xa0
|
||||
#define MC_EMEM_ARB_TIMING_RAS 0xa4
|
||||
#define MC_EMEM_ARB_TIMING_FAW 0xa8
|
||||
#define MC_EMEM_ARB_TIMING_RRD 0xac
|
||||
#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
|
||||
#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
|
||||
#define MC_EMEM_ARB_TIMING_R2R 0xb8
|
||||
#define MC_EMEM_ARB_TIMING_W2W 0xbc
|
||||
#define MC_EMEM_ARB_TIMING_R2W 0xc0
|
||||
#define MC_EMEM_ARB_TIMING_W2R 0xc4
|
||||
#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0
|
||||
#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4
|
||||
#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0
|
||||
#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4
|
||||
#define MC_EMEM_ARB_DA_TURNS 0xd0
|
||||
#define MC_EMEM_ARB_DA_COVERS 0xd4
|
||||
#define MC_EMEM_ARB_MISC0 0xd8
|
||||
#define MC_EMEM_ARB_MISC1 0xdc
|
||||
#define MC_EMEM_ARB_MISC2 0xc8
|
||||
#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
|
||||
#define MC_EMEM_ARB_RING3_THROTTLE 0xe4
|
||||
#define MC_EMEM_ARB_NISO_THROTTLE 0x6b0
|
||||
#define MC_EMEM_ARB_OVERRIDE 0xe8
|
||||
#define MC_EMEM_ARB_RSV 0xec
|
||||
#define MC_CLKEN_OVERRIDE 0xf4
|
||||
#define MC_TIMING_CONTROL_DBG 0xf8
|
||||
#define MC_TIMING_CONTROL 0xfc
|
||||
#define MC_STAT_CONTROL 0x100
|
||||
#define MC_STAT_STATUS 0x104
|
||||
#define MC_STAT_EMC_CLOCK_LIMIT 0x108
|
||||
#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c
|
||||
#define MC_STAT_EMC_CLOCKS 0x110
|
||||
#define MC_STAT_EMC_CLOCKS_MSBS 0x114
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24
|
||||
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198
|
||||
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8
|
||||
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c
|
||||
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac
|
||||
#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28
|
||||
#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c
|
||||
#define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0
|
||||
#define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0
|
||||
#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120
|
||||
#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c
|
||||
#define MC_STAT_EMC_SET0_COUNT 0x138
|
||||
#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c
|
||||
#define MC_STAT_EMC_SET1_COUNT 0x178
|
||||
#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c
|
||||
#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140
|
||||
#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144
|
||||
#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180
|
||||
#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184
|
||||
#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148
|
||||
#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c
|
||||
#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188
|
||||
#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c
|
||||
#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150
|
||||
#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190
|
||||
#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8
|
||||
#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc
|
||||
#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8
|
||||
#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc
|
||||
#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0
|
||||
#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0
|
||||
#define MC_CLIENT_HOTRESET_CTRL 0x200
|
||||
#define MC_CLIENT_HOTRESET_CTRL_1 0x970
|
||||
#define MC_CLIENT_HOTRESET_STATUS 0x204
|
||||
#define MC_CLIENT_HOTRESET_STATUS_1 0x974
|
||||
#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208
|
||||
#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c
|
||||
#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210
|
||||
#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214
|
||||
#define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94
|
||||
#define MC_EMEM_ARB_HYSTERESIS_0 0x218
|
||||
#define MC_EMEM_ARB_HYSTERESIS_1 0x21c
|
||||
#define MC_EMEM_ARB_HYSTERESIS_2 0x220
|
||||
#define MC_EMEM_ARB_HYSTERESIS_3 0x224
|
||||
#define MC_EMEM_ARB_HYSTERESIS_4 0xb84
|
||||
#define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0
|
||||
#define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4
|
||||
#define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8
|
||||
#define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc
|
||||
#define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0
|
||||
#define MC_EMEM_ARB_DHYST_CTRL 0xbcc
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec
|
||||
#define MC_RESERVED_RSV 0x3fc
|
||||
#define MC_DISB_EXTRA_SNAP_LEVELS 0x408
|
||||
#define MC_APB_EXTRA_SNAP_LEVELS 0x2a4
|
||||
#define MC_AHB_EXTRA_SNAP_LEVELS 0x2a0
|
||||
#define MC_USBD_EXTRA_SNAP_LEVELS 0xa18
|
||||
#define MC_ISP_EXTRA_SNAP_LEVELS 0xa08
|
||||
#define MC_AUD_EXTRA_SNAP_LEVELS 0xa10
|
||||
#define MC_MSE_EXTRA_SNAP_LEVELS 0x40c
|
||||
#define MC_GK2_EXTRA_SNAP_LEVELS 0xa40
|
||||
#define MC_A9AVPPC_EXTRA_SNAP_LEVELS 0x414
|
||||
#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc
|
||||
#define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c
|
||||
#define MC_HOST_EXTRA_SNAP_LEVELS 0xa14
|
||||
#define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0
|
||||
#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac
|
||||
#define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c
|
||||
#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48
|
||||
#define MC_AVP_EXTRA_SNAP_LEVELS 0x2a8
|
||||
#define MC_USBX_EXTRA_SNAP_LEVELS 0x404
|
||||
#define MC_PCX_EXTRA_SNAP_LEVELS 0x2b8
|
||||
#define MC_SD_EXTRA_SNAP_LEVELS 0xa04
|
||||
#define MC_DFD_EXTRA_SNAP_LEVELS 0xa4c
|
||||
#define MC_VE_EXTRA_SNAP_LEVELS 0x2d8
|
||||
#define MC_GK_EXTRA_SNAP_LEVELS 0xa00
|
||||
#define MC_VE2_EXTRA_SNAP_LEVELS 0x410
|
||||
#define MC_SDM_EXTRA_SNAP_LEVELS 0xa44
|
||||
#define MC_VIDEO_PROTECT_BOM 0x648
|
||||
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
|
||||
#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978
|
||||
#define MC_VIDEO_PROTECT_REG_CTRL 0x650
|
||||
#define MC_ERR_VPR_STATUS 0x654
|
||||
#define MC_ERR_VPR_ADR 0x658
|
||||
#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418
|
||||
#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590
|
||||
#define MC_IRAM_BOM 0x65c
|
||||
#define MC_IRAM_TOM 0x660
|
||||
#define MC_IRAM_ADR_HI 0x980
|
||||
#define MC_IRAM_REG_CTRL 0x964
|
||||
#define MC_EMEM_CFG_ACCESS_CTRL 0x664
|
||||
#define MC_TZ_SECURITY_CTRL 0x668
|
||||
#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c
|
||||
#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4
|
||||
#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc
|
||||
#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8
|
||||
#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80
|
||||
#define MC_SEC_CARVEOUT_BOM 0x670
|
||||
#define MC_SEC_CARVEOUT_SIZE_MB 0x674
|
||||
#define MC_SEC_CARVEOUT_ADR_HI 0x9d4
|
||||
#define MC_SEC_CARVEOUT_REG_CTRL 0x678
|
||||
#define MC_ERR_SEC_STATUS 0x67c
|
||||
#define MC_ERR_SEC_ADR 0x680
|
||||
#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684
|
||||
#define MC_STUTTER_CONTROL 0x688
|
||||
#define MC_RESERVED_RSV_1 0x958
|
||||
#define MC_DVFS_PIPE_SELECT 0x95c
|
||||
#define MC_AHB_PTSA_MIN 0x4e0
|
||||
#define MC_AUD_PTSA_MIN 0x54c
|
||||
#define MC_MLL_MPCORER_PTSA_RATE 0x44c
|
||||
#define MC_RING2_PTSA_RATE 0x440
|
||||
#define MC_USBD_PTSA_RATE 0x530
|
||||
#define MC_USBX_PTSA_MIN 0x528
|
||||
#define MC_USBD_PTSA_MIN 0x534
|
||||
#define MC_APB_PTSA_MAX 0x4f0
|
||||
#define MC_JPG_PTSA_RATE 0x584
|
||||
#define MC_DIS_PTSA_MIN 0x420
|
||||
#define MC_AVP_PTSA_MAX 0x4fc
|
||||
#define MC_AVP_PTSA_RATE 0x4f4
|
||||
#define MC_RING1_PTSA_MIN 0x480
|
||||
#define MC_DIS_PTSA_MAX 0x424
|
||||
#define MC_SD_PTSA_MAX 0x4d8
|
||||
#define MC_MSE_PTSA_RATE 0x4c4
|
||||
#define MC_VICPC_PTSA_MIN 0x558
|
||||
#define MC_PCX_PTSA_MAX 0x4b4
|
||||
#define MC_ISP_PTSA_RATE 0x4a0
|
||||
#define MC_A9AVPPC_PTSA_MIN 0x48c
|
||||
#define MC_RING2_PTSA_MAX 0x448
|
||||
#define MC_AUD_PTSA_RATE 0x548
|
||||
#define MC_HOST_PTSA_MIN 0x51c
|
||||
#define MC_MLL_MPCORER_PTSA_MAX 0x454
|
||||
#define MC_SD_PTSA_MIN 0x4d4
|
||||
#define MC_RING1_PTSA_RATE 0x47c
|
||||
#define MC_JPG_PTSA_MIN 0x588
|
||||
#define MC_HDAPC_PTSA_MIN 0x62c
|
||||
#define MC_AVP_PTSA_MIN 0x4f8
|
||||
#define MC_JPG_PTSA_MAX 0x58c
|
||||
#define MC_VE_PTSA_MAX 0x43c
|
||||
#define MC_DFD_PTSA_MAX 0x63c
|
||||
#define MC_VICPC_PTSA_RATE 0x554
|
||||
#define MC_GK_PTSA_MAX 0x544
|
||||
#define MC_VICPC_PTSA_MAX 0x55c
|
||||
#define MC_SDM_PTSA_MAX 0x624
|
||||
#define MC_SAX_PTSA_RATE 0x4b8
|
||||
#define MC_PCX_PTSA_MIN 0x4b0
|
||||
#define MC_APB_PTSA_MIN 0x4ec
|
||||
#define MC_GK2_PTSA_MIN 0x614
|
||||
#define MC_PCX_PTSA_RATE 0x4ac
|
||||
#define MC_RING1_PTSA_MAX 0x484
|
||||
#define MC_HDAPC_PTSA_RATE 0x628
|
||||
#define MC_MLL_MPCORER_PTSA_MIN 0x450
|
||||
#define MC_GK2_PTSA_MAX 0x618
|
||||
#define MC_AUD_PTSA_MAX 0x550
|
||||
#define MC_GK2_PTSA_RATE 0x610
|
||||
#define MC_ISP_PTSA_MAX 0x4a8
|
||||
#define MC_DISB_PTSA_RATE 0x428
|
||||
#define MC_VE2_PTSA_MAX 0x49c
|
||||
#define MC_DFD_PTSA_MIN 0x638
|
||||
#define MC_FTOP_PTSA_RATE 0x50c
|
||||
#define MC_A9AVPPC_PTSA_RATE 0x488
|
||||
#define MC_VE2_PTSA_MIN 0x498
|
||||
#define MC_USBX_PTSA_MAX 0x52c
|
||||
#define MC_DIS_PTSA_RATE 0x41c
|
||||
#define MC_USBD_PTSA_MAX 0x538
|
||||
#define MC_A9AVPPC_PTSA_MAX 0x490
|
||||
#define MC_USBX_PTSA_RATE 0x524
|
||||
#define MC_FTOP_PTSA_MAX 0x514
|
||||
#define MC_HDAPC_PTSA_MAX 0x630
|
||||
#define MC_SD_PTSA_RATE 0x4d0
|
||||
#define MC_DFD_PTSA_RATE 0x634
|
||||
#define MC_FTOP_PTSA_MIN 0x510
|
||||
#define MC_SDM_PTSA_RATE 0x61c
|
||||
#define MC_AHB_PTSA_RATE 0x4dc
|
||||
#define MC_SMMU_SMMU_PTSA_MAX 0x460
|
||||
#define MC_RING2_PTSA_MIN 0x444
|
||||
#define MC_SDM_PTSA_MIN 0x620
|
||||
#define MC_APB_PTSA_RATE 0x4e8
|
||||
#define MC_MSE_PTSA_MIN 0x4c8
|
||||
#define MC_HOST_PTSA_RATE 0x518
|
||||
#define MC_VE_PTSA_RATE 0x434
|
||||
#define MC_AHB_PTSA_MAX 0x4e4
|
||||
#define MC_SAX_PTSA_MIN 0x4bc
|
||||
#define MC_SMMU_SMMU_PTSA_MIN 0x45c
|
||||
#define MC_ISP_PTSA_MIN 0x4a4
|
||||
#define MC_HOST_PTSA_MAX 0x520
|
||||
#define MC_SAX_PTSA_MAX 0x4c0
|
||||
#define MC_VE_PTSA_MIN 0x438
|
||||
#define MC_GK_PTSA_MIN 0x540
|
||||
#define MC_MSE_PTSA_MAX 0x4cc
|
||||
#define MC_DISB_PTSA_MAX 0x430
|
||||
#define MC_DISB_PTSA_MIN 0x42c
|
||||
#define MC_SMMU_SMMU_PTSA_RATE 0x458
|
||||
#define MC_VE2_PTSA_RATE 0x494
|
||||
#define MC_GK_PTSA_RATE 0x53c
|
||||
#define MC_PTSA_GRANT_DECREMENT 0x960
|
||||
#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
|
||||
#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0
|
||||
#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
|
||||
#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
|
||||
#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8
|
||||
#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8
|
||||
#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc
|
||||
#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
|
||||
#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694
|
||||
#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
|
||||
#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
|
||||
#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
|
||||
#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0
|
||||
#define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698
|
||||
#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec
|
||||
#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0
|
||||
#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4
|
||||
#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4
|
||||
#define MC_LATENCY_ALLOWANCE_HC_1 0x314
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0
|
||||
#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4
|
||||
#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c
|
||||
#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec
|
||||
#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
|
||||
#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4
|
||||
#define MC_LATENCY_ALLOWANCE_SATA_0 0x350
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690
|
||||
#define MC_LATENCY_ALLOWANCE_HC_0 0x310
|
||||
#define MC_LATENCY_ALLOWANCE_DC_3 0x3c8
|
||||
#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388
|
||||
#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
|
||||
#define MC_LATENCY_ALLOWANCE_HDA_0 0x318
|
||||
#define MC_MIN_LENGTH_APE_0 0xb34
|
||||
#define MC_MIN_LENGTH_DCB_2 0x8a8
|
||||
#define MC_MIN_LENGTH_A9AVP_0 0x950
|
||||
#define MC_MIN_LENGTH_TSEC_0 0x93c
|
||||
#define MC_MIN_LENGTH_DC_1 0x898
|
||||
#define MC_MIN_LENGTH_AXIAP_0 0x94c
|
||||
#define MC_MIN_LENGTH_ISP2B_0 0x930
|
||||
#define MC_MIN_LENGTH_VI2_0 0x944
|
||||
#define MC_MIN_LENGTH_DCB_0 0x8a0
|
||||
#define MC_MIN_LENGTH_DCB_1 0x8a4
|
||||
#define MC_MIN_LENGTH_PPCS_1 0x8f4
|
||||
#define MC_MIN_LENGTH_NVJPG_0 0xb3c
|
||||
#define MC_MIN_LENGTH_HDA_0 0x8c4
|
||||
#define MC_MIN_LENGTH_NVENC_0 0x8d4
|
||||
#define MC_MIN_LENGTH_SDMMC_0 0xb18
|
||||
#define MC_MIN_LENGTH_ISP2B_1 0x934
|
||||
#define MC_MIN_LENGTH_HC_1 0x8c0
|
||||
#define MC_MIN_LENGTH_DC_3 0xb20
|
||||
#define MC_MIN_LENGTH_AVPC_0 0x890
|
||||
#define MC_MIN_LENGTH_VIC_0 0x940
|
||||
#define MC_MIN_LENGTH_ISP2_0 0x91c
|
||||
#define MC_MIN_LENGTH_HC_0 0x8bc
|
||||
#define MC_MIN_LENGTH_SE_0 0xb38
|
||||
#define MC_MIN_LENGTH_NVDEC_0 0xb30
|
||||
#define MC_MIN_LENGTH_SATA_0 0x8fc
|
||||
#define MC_MIN_LENGTH_DC_0 0x894
|
||||
#define MC_MIN_LENGTH_XUSB_1 0x92c
|
||||
#define MC_MIN_LENGTH_DC_2 0x89c
|
||||
#define MC_MIN_LENGTH_SDMMCAA_0 0xb14
|
||||
#define MC_MIN_LENGTH_GPU_0 0xb04
|
||||
#define MC_MIN_LENGTH_ETR_0 0xb44
|
||||
#define MC_MIN_LENGTH_AFI_0 0x88c
|
||||
#define MC_MIN_LENGTH_PPCS_0 0x8f0
|
||||
#define MC_MIN_LENGTH_ISP2_1 0x920
|
||||
#define MC_MIN_LENGTH_XUSB_0 0x928
|
||||
#define MC_MIN_LENGTH_MPCORE_0 0x8cc
|
||||
#define MC_MIN_LENGTH_TSECB_0 0xb48
|
||||
#define MC_MIN_LENGTH_SDMMCA_0 0xb10
|
||||
#define MC_MIN_LENGTH_GPU2_0 0xb40
|
||||
#define MC_MIN_LENGTH_SDMMCAB_0 0xb1c
|
||||
#define MC_MIN_LENGTH_PTC_0 0x8f8
|
||||
#define MC_EMEM_ARB_OVERRIDE_1 0x968
|
||||
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984
|
||||
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988
|
||||
#define MC_EMEM_ARB_STATS_0 0x990
|
||||
#define MC_EMEM_ARB_STATS_1 0x994
|
||||
#define MC_MTS_CARVEOUT_BOM 0x9a0
|
||||
#define MC_MTS_CARVEOUT_SIZE_MB 0x9a4
|
||||
#define MC_MTS_CARVEOUT_ADR_HI 0x9a8
|
||||
#define MC_MTS_CARVEOUT_REG_CTRL 0x9ac
|
||||
#define MC_ERR_MTS_STATUS 0x9b0
|
||||
#define MC_ERR_MTS_ADR 0x9b4
|
||||
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00
|
||||
#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd74
|
||||
#define MC_SECURITY_CARVEOUT4_CFG0 0xcf8
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10
|
||||
#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc30
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc8c
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd1c
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd70
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc2c
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd7c
|
||||
#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4
|
||||
#define MC_SECURITY_CARVEOUT2_CFG0 0xc58
|
||||
#define MC_SECURITY_CARVEOUT1_CFG0 0xc08
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc84
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68
|
||||
#define MC_SECURITY_CARVEOUT3_BOM 0xcac
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd78
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc7c
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc38
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc34
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60
|
||||
#define MC_SECURITY_CARVEOUT3_CFG0 0xca8
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc88
|
||||
#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64
|
||||
#define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50
|
||||
#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14
|
||||
#define MC_SECURITY_CARVEOUT1_BOM 0xc0c
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd2c
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd24
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd28
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c
|
||||
#define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcd8
|
||||
#define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60
|
||||
#define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xcdc
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc80
|
||||
#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd20
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd4
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xccc
|
||||
#define MC_SECURITY_CARVEOUT4_BOM 0xcfc
|
||||
#define MC_SECURITY_CARVEOUT5_CFG0 0xd48
|
||||
#define MC_SECURITY_CARVEOUT2_BOM 0xc5c
|
||||
#define MC_SECURITY_CARVEOUT5_BOM 0xd4c
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd6c
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd0
|
||||
#define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc3c
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
|
||||
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
|
||||
#define MC_DA_CONFIG0 0x9dc
|
||||
|
||||
/* Memory Controller clients */
|
||||
#define CLIENT_ACCESS_NUM_CLIENTS 32
|
||||
typedef enum {
|
||||
/* _ACCESS0 */
|
||||
CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
|
||||
|
||||
/* _ACCESS1 */
|
||||
CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
|
||||
|
||||
/* _ACCESS2 */
|
||||
CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
|
||||
|
||||
/* _ACCESS3 */
|
||||
CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
|
||||
|
||||
/* _ACCESS4 */
|
||||
CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
|
||||
CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4))
|
||||
} McClient;
|
||||
|
||||
void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock);
|
||||
void mc_config_carveout();
|
||||
void mc_config_carveout_finalize();
|
||||
void mc_enable_ahb_redirect();
|
||||
void mc_disable_ahb_redirect();
|
||||
void mc_enable();
|
||||
|
||||
#endif
|
||||
98
sept/sept-secondary/src/panic.c
Normal file
98
sept/sept-secondary/src/panic.c
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "panic.h"
|
||||
#include "di.h"
|
||||
#include "pmc.h"
|
||||
#include "fuse.h"
|
||||
#include "utils.h"
|
||||
|
||||
static uint32_t g_panic_code = 0;
|
||||
|
||||
void check_and_display_panic(void) {
|
||||
/* We also handle our own panics. */
|
||||
/* In the case of our own panics, we assume that the display has already been initialized. */
|
||||
bool has_panic = APBDEV_PMC_RST_STATUS_0 != 0 || g_panic_code != 0;
|
||||
uint32_t code = g_panic_code == 0 ? APBDEV_PMC_SCRATCH200_0 : g_panic_code;
|
||||
|
||||
has_panic = has_panic && !(APBDEV_PMC_RST_STATUS_0 != 1 && code == PANIC_CODE_SAFEMODE);
|
||||
|
||||
if (has_panic) {
|
||||
uint32_t color;
|
||||
|
||||
/* Check for predefined codes: */
|
||||
switch (code & MASK(20)) {
|
||||
case 0x01: /* Package2 signature verification failed. */
|
||||
case 0x02: /* Package2 meta verification failed. */
|
||||
case 0x03: /* Package2 version check failed. */
|
||||
case 0x04: /* Package2 payload verification failed. */
|
||||
color = PANIC_COLOR_KERNEL;
|
||||
break;
|
||||
case 0x05: /* Unknown SMC. */
|
||||
case 0x06: /* Unknown Abort. */
|
||||
color = PANIC_COLOR_SECMON_GENERIC;
|
||||
break;
|
||||
case 0x07: /* Invalid CPU context. */
|
||||
case 0x08: /* Invalid SE state. */
|
||||
case 0x09: /* CPU is already awake (2.0.0+). */
|
||||
color = PANIC_COLOR_SECMON_DEEPSLEEP;
|
||||
break;
|
||||
case 0x10: /* Unknown exception. */
|
||||
color = PANIC_COLOR_SECMON_EXCEPTION;
|
||||
break;
|
||||
case 0x30: /* General bootloader error. */
|
||||
case 0x31: /* Invalid DRAM ID. */
|
||||
case 0x32: /* Invalid size. */
|
||||
case 0x33: /* Invalid arguement. */
|
||||
case 0x34: /* Bad GPT. */
|
||||
case 0x35: /* Failed to boot SafeMode. */
|
||||
case 0x36: /* Activity monitor fired (4.0.0+). */
|
||||
color = PANIC_COLOR_BOOTLOADER_GENERIC;
|
||||
break;
|
||||
case 0x40: /* Kernel panic. */
|
||||
color = PANIC_COLOR_KERNEL;
|
||||
break;
|
||||
default:
|
||||
color = code >> 20;
|
||||
color |= color << 4;
|
||||
break;
|
||||
}
|
||||
|
||||
if (g_panic_code == 0) {
|
||||
display_init();
|
||||
}
|
||||
|
||||
display_color_screen(color);
|
||||
wait_for_button_and_reboot();
|
||||
} else {
|
||||
g_panic_code = 0;
|
||||
APBDEV_PMC_SCRATCH200_0 = 0;
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__ ((noreturn)) void panic(uint32_t code) {
|
||||
/* Set panic code. */
|
||||
if (g_panic_code == 0) {
|
||||
g_panic_code = code;
|
||||
APBDEV_PMC_SCRATCH200_0 = code;
|
||||
}
|
||||
|
||||
fuse_disable_programming();
|
||||
APBDEV_PMC_CRYPTO_OP_0 = 1; /* Disable all SE operations. */
|
||||
|
||||
check_and_display_panic();
|
||||
while(true);
|
||||
}
|
||||
34
sept/sept-secondary/src/panic.h
Normal file
34
sept/sept-secondary/src/panic.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_PANIC_H
|
||||
#define FUSEE_PANIC_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define PANIC_COLOR_KERNEL 0x0000FF
|
||||
#define PANIC_COLOR_SECMON_EXCEPTION 0xFF7700
|
||||
#define PANIC_COLOR_SECMON_GENERIC 0x00FFFF
|
||||
#define PANIC_COLOR_SECMON_DEEPSLEEP 0xFF77FF /* 4.0+ color */
|
||||
#define PANIC_COLOR_BOOTLOADER_GENERIC 0xAA00FF
|
||||
#define PANIC_COLOR_BOOTLOADER_SAFEMODE 0xFFFFAA /* Removed */
|
||||
|
||||
#define PANIC_CODE_SAFEMODE 0x00000020
|
||||
|
||||
void check_and_display_panic(void);
|
||||
__attribute__ ((noreturn)) void panic(uint32_t code);
|
||||
|
||||
#endif
|
||||
39
sept/sept-secondary/src/panic_color.h
Normal file
39
sept/sept-secondary/src/panic_color.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_PANIC_COLOR_H
|
||||
#define FUSEE_PANIC_COLOR_H
|
||||
|
||||
#define COLOR_0 0x00F00003
|
||||
#define COLOR_1 0x0F000003
|
||||
#define COLOR_2 0xF0000003
|
||||
#define COLOR_3 0x0FF00003
|
||||
#define COLOR_4 0xF0F00003
|
||||
#define COLOR_5 0xFF000003
|
||||
#define COLOR_6 0xFFF00003
|
||||
#define COLOR_7 0xAAF00003
|
||||
#define COLOR_8 0xAFA00003
|
||||
#define COLOR_9 0xFAA00003
|
||||
#define COLOR_A 0x33300003
|
||||
#define COLOR_B 0x06F00003
|
||||
#define COLOR_C 0x14800003
|
||||
#define COLOR_D 0x00300003
|
||||
#define COLOR_E 0x03000003
|
||||
#define COLOR_F 0xB6000003
|
||||
|
||||
#define PANIC_REBOOT 0x20
|
||||
|
||||
#endif
|
||||
211
sept/sept-secondary/src/pinmux.h
Normal file
211
sept/sept-secondary/src/pinmux.h
Normal file
|
|
@ -0,0 +1,211 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_PINMUX_H
|
||||
#define FUSEE_PINMUX_H
|
||||
|
||||
#define PINMUX_BASE 0x70003000
|
||||
#define MAKE_PINMUX_REG(n) MAKE_REG32(PINMUX_BASE + n)
|
||||
|
||||
#define PINMUX_TRISTATE (1 << 4)
|
||||
#define PINMUX_PARKED (1 << 5)
|
||||
#define PINMUX_INPUT (1 << 6)
|
||||
#define PINMUX_PULL_NONE (0 << 2)
|
||||
#define PINMUX_PULL_DOWN (1 << 2)
|
||||
#define PINMUX_PULL_UP (2 << 2)
|
||||
#define PINMUX_SELECT_FUNCTION0 0
|
||||
#define PINMUX_SELECT_FUNCTION1 1
|
||||
#define PINMUX_SELECT_FUNCTION2 2
|
||||
#define PINMUX_SELECT_FUNCTION3 3
|
||||
#define PINMUX_DRIVE_1X (0 << 13)
|
||||
#define PINMUX_DRIVE_2X (1 << 13)
|
||||
#define PINMUX_DRIVE_3X (2 << 13)
|
||||
#define PINMUX_DRIVE_4X (3 << 13)
|
||||
|
||||
typedef struct {
|
||||
uint32_t sdmmc1_clk;
|
||||
uint32_t sdmmc1_cmd;
|
||||
uint32_t sdmmc1_dat3;
|
||||
uint32_t sdmmc1_dat2;
|
||||
uint32_t sdmmc1_dat1;
|
||||
uint32_t sdmmc1_dat0;
|
||||
uint32_t _r18;
|
||||
uint32_t sdmmc3_clk;
|
||||
uint32_t sdmmc3_cmd;
|
||||
uint32_t sdmmc3_dat0;
|
||||
uint32_t sdmmc3_dat1;
|
||||
uint32_t sdmmc3_dat2;
|
||||
uint32_t sdmmc3_dat3;
|
||||
uint32_t _r34;
|
||||
uint32_t pex_l0_rst_n;
|
||||
uint32_t pex_l0_clkreq_n;
|
||||
uint32_t pex_wake_n;
|
||||
uint32_t pex_l1_rst_n;
|
||||
uint32_t pex_l1_clkreq_n;
|
||||
uint32_t sata_led_active;
|
||||
uint32_t spi1_mosi;
|
||||
uint32_t spi1_miso;
|
||||
uint32_t spi1_sck;
|
||||
uint32_t spi1_cs0;
|
||||
uint32_t spi1_cs1;
|
||||
uint32_t spi2_mosi;
|
||||
uint32_t spi2_miso;
|
||||
uint32_t spi2_sck;
|
||||
uint32_t spi2_cs0;
|
||||
uint32_t spi2_cs1;
|
||||
uint32_t spi4_mosi;
|
||||
uint32_t spi4_miso;
|
||||
uint32_t spi4_sck;
|
||||
uint32_t spi4_cs0;
|
||||
uint32_t qspi_sck;
|
||||
uint32_t qspi_cs_n;
|
||||
uint32_t qspi_io0;
|
||||
uint32_t qspi_io1;
|
||||
uint32_t qspi_io2;
|
||||
uint32_t qspi_io3;
|
||||
uint32_t _ra0;
|
||||
uint32_t dmic1_clk;
|
||||
uint32_t dmic1_dat;
|
||||
uint32_t dmic2_clk;
|
||||
uint32_t dmic2_dat;
|
||||
uint32_t dmic3_clk;
|
||||
uint32_t dmic3_dat;
|
||||
uint32_t gen1_i2c_scl;
|
||||
uint32_t gen1_i2c_sda;
|
||||
uint32_t gen2_i2c_scl;
|
||||
uint32_t gen2_i2c_sda;
|
||||
uint32_t gen3_i2c_scl;
|
||||
uint32_t gen3_i2c_sda;
|
||||
uint32_t cam_i2c_scl;
|
||||
uint32_t cam_i2c_sda;
|
||||
uint32_t pwr_i2c_scl;
|
||||
uint32_t pwr_i2c_sda;
|
||||
uint32_t uart1_tx;
|
||||
uint32_t uart1_rx;
|
||||
uint32_t uart1_rts;
|
||||
uint32_t uart1_cts;
|
||||
uint32_t uart2_tx;
|
||||
uint32_t uart2_rx;
|
||||
uint32_t uart2_rts;
|
||||
uint32_t uart2_cts;
|
||||
uint32_t uart3_tx;
|
||||
uint32_t uart3_rx;
|
||||
uint32_t uart3_rts;
|
||||
uint32_t uart3_cts;
|
||||
uint32_t uart4_tx;
|
||||
uint32_t uart4_rx;
|
||||
uint32_t uart4_rts;
|
||||
uint32_t uart4_cts;
|
||||
uint32_t dap1_fs;
|
||||
uint32_t dap1_din;
|
||||
uint32_t dap1_dout;
|
||||
uint32_t dap1_sclk;
|
||||
uint32_t dap2_fs;
|
||||
uint32_t dap2_din;
|
||||
uint32_t dap2_dout;
|
||||
uint32_t dap2_sclk;
|
||||
uint32_t dap4_fs;
|
||||
uint32_t dap4_din;
|
||||
uint32_t dap4_dout;
|
||||
uint32_t dap4_sclk;
|
||||
uint32_t cam1_mclk;
|
||||
uint32_t cam2_mclk;
|
||||
uint32_t jtag_rtck;
|
||||
uint32_t clk_32k_in;
|
||||
uint32_t clk_32k_out;
|
||||
uint32_t batt_bcl;
|
||||
uint32_t clk_req;
|
||||
uint32_t cpu_pwr_req;
|
||||
uint32_t pwr_int_n;
|
||||
uint32_t shutdown;
|
||||
uint32_t core_pwr_req;
|
||||
uint32_t aud_mclk;
|
||||
uint32_t dvfs_pwm;
|
||||
uint32_t dvfs_clk;
|
||||
uint32_t gpio_x1_aud;
|
||||
uint32_t gpio_x3_aud;
|
||||
uint32_t pcc7;
|
||||
uint32_t hdmi_cec;
|
||||
uint32_t hdmi_int_dp_hpd;
|
||||
uint32_t spdif_out;
|
||||
uint32_t spdif_in;
|
||||
uint32_t usb_vbus_en0;
|
||||
uint32_t usb_vbus_en1;
|
||||
uint32_t dp_hpd0;
|
||||
uint32_t wifi_en;
|
||||
uint32_t wifi_rst;
|
||||
uint32_t wifi_wake_ap;
|
||||
uint32_t ap_wake_bt;
|
||||
uint32_t bt_rst;
|
||||
uint32_t bt_wake_ap;
|
||||
uint32_t ap_wake_nfc;
|
||||
uint32_t nfc_en;
|
||||
uint32_t nfc_int;
|
||||
uint32_t gps_en;
|
||||
uint32_t gps_rst;
|
||||
uint32_t cam_rst;
|
||||
uint32_t cam_af_en;
|
||||
uint32_t cam_flash_en;
|
||||
uint32_t cam1_pwdn;
|
||||
uint32_t cam2_pwdn;
|
||||
uint32_t cam1_strobe;
|
||||
uint32_t lcd_te;
|
||||
uint32_t lcd_bl_pwm;
|
||||
uint32_t lcd_bl_en;
|
||||
uint32_t lcd_rst;
|
||||
uint32_t lcd_gpio1;
|
||||
uint32_t lcd_gpio2;
|
||||
uint32_t ap_ready;
|
||||
uint32_t touch_rst;
|
||||
uint32_t touch_clk;
|
||||
uint32_t modem_wake_ap;
|
||||
uint32_t touch_int;
|
||||
uint32_t motion_int;
|
||||
uint32_t als_prox_int;
|
||||
uint32_t temp_alert;
|
||||
uint32_t button_power_on;
|
||||
uint32_t button_vol_up;
|
||||
uint32_t button_vol_down;
|
||||
uint32_t button_slide_sw;
|
||||
uint32_t button_home;
|
||||
uint32_t pa6;
|
||||
uint32_t pe6;
|
||||
uint32_t pe7;
|
||||
uint32_t ph6;
|
||||
uint32_t pk0;
|
||||
uint32_t pk1;
|
||||
uint32_t pk2;
|
||||
uint32_t pk3;
|
||||
uint32_t pk4;
|
||||
uint32_t pk5;
|
||||
uint32_t pk6;
|
||||
uint32_t pk7;
|
||||
uint32_t pl0;
|
||||
uint32_t pl1;
|
||||
uint32_t pz0;
|
||||
uint32_t pz1;
|
||||
uint32_t pz2;
|
||||
uint32_t pz3;
|
||||
uint32_t pz4;
|
||||
uint32_t pz5;
|
||||
} tegra_pinmux_t;
|
||||
|
||||
static inline volatile tegra_pinmux_t *pinmux_get_regs(void)
|
||||
{
|
||||
return (volatile tegra_pinmux_t *)PINMUX_BASE;
|
||||
}
|
||||
|
||||
#endif
|
||||
626
sept/sept-secondary/src/pmc.h
Normal file
626
sept/sept-secondary/src/pmc.h
Normal file
|
|
@ -0,0 +1,626 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_PMC_H
|
||||
#define FUSEE_PMC_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define PMC_BASE 0x7000E400
|
||||
#define MAKE_PMC_REG(n) MAKE_REG32(PMC_BASE + n)
|
||||
|
||||
#define PMC_CONTROL_SDMMC1 (1 << 12)
|
||||
#define PMC_CONTROL_SDMMC3 (1 << 13)
|
||||
#define PMC_CONTROL_SDMMC4 (1 << 14)
|
||||
|
||||
#define APBDEV_PMC_CONTROL MAKE_PMC_REG(0x00)
|
||||
#define APBDEV_PM_0 MAKE_PMC_REG(0x14)
|
||||
#define APBDEV_PMC_DPD_ENABLE_0 MAKE_PMC_REG(0x24)
|
||||
#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x30)
|
||||
#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x38)
|
||||
#define APBDEV_PMC_NO_IOPOWER_0 MAKE_PMC_REG(0x44)
|
||||
#define APBDEV_PMC_SCRATCH0_0 MAKE_PMC_REG(0x50)
|
||||
#define APBDEV_PMC_SCRATCH1_0 MAKE_PMC_REG(0x54)
|
||||
#define APBDEV_PMC_SCRATCH20_0 MAKE_PMC_REG(0xA0)
|
||||
#define APBDEV_PMC_PWR_DET_VAL_0 MAKE_PMC_REG(0xE4)
|
||||
#define APBDEV_PMC_DDR_PWR_0 MAKE_PMC_REG(0xE8)
|
||||
#define APBDEV_PMC_CRYPTO_OP_0 MAKE_PMC_REG(0xF4)
|
||||
#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_PMC_REG(0x168)
|
||||
#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4)
|
||||
#define APBDEV_PMC_RST_STATUS_0 MAKE_PMC_REG(0x1B4)
|
||||
#define APBDEV_PMC_IO_DPD_REQ_0 MAKE_PMC_REG(0x1B8)
|
||||
#define APBDEV_PMC_IO_DPD2_REQ_0 MAKE_PMC_REG(0x1C0)
|
||||
#define APBDEV_PMC_VDDP_SEL_0 MAKE_PMC_REG(0x1CC)
|
||||
#define APBDEV_PMC_SCRATCH49_0 MAKE_PMC_REG(0x244)
|
||||
#define APBDEV_PMC_TSC_MULT_0 MAKE_PMC_REG(0x2B4)
|
||||
#define APBDEV_PMC_REG_SHORT_0 MAKE_PMC_REG(0x2CC)
|
||||
#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH21_0 MAKE_PMC_REG(0x334)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH32_0 MAKE_PMC_REG(0x360)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH49_0 MAKE_PMC_REG(0x3A4)
|
||||
#define APBDEV_PMC_CNTRL2_0 MAKE_PMC_REG(0x440)
|
||||
#define APBDEV_PMC_IO_DPD4_REQ_0 MAKE_PMC_REG(0x464)
|
||||
#define APBDEV_PMC_UTMIP_PAD_CFG1_0 MAKE_PMC_REG(0x4C4)
|
||||
#define APBDEV_PMC_UTMIP_PAD_CFG3_0 MAKE_PMC_REG(0x4CC)
|
||||
#define APBDEV_PMC_DDR_CNTRL_0 MAKE_PMC_REG(0x4E4)
|
||||
#define APBDEV_PMC_SCRATCH43_0 MAKE_PMC_REG(0x22C)
|
||||
#define APBDEV_PMC_SCRATCH188_0 MAKE_PMC_REG(0x810)
|
||||
#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818)
|
||||
#define APBDEV_PMC_SCRATCH200_0 MAKE_PMC_REG(0x840)
|
||||
|
||||
#define APBDEV_PMC_SCRATCH45_0 MAKE_PMC_REG(0x234)
|
||||
#define APBDEV_PMC_SCRATCH46_0 MAKE_PMC_REG(0x238)
|
||||
#define APBDEV_PMC_SCRATCH33_0 MAKE_PMC_REG(0x120)
|
||||
#define APBDEV_PMC_SCRATCH40_0 MAKE_PMC_REG(0x13C)
|
||||
|
||||
typedef struct {
|
||||
uint32_t cntrl;
|
||||
uint32_t sec_disable;
|
||||
uint32_t pmc_swrst;
|
||||
uint32_t wake_mask;
|
||||
uint32_t wake_lvl;
|
||||
uint32_t wake_status;
|
||||
uint32_t sw_wake_status;
|
||||
uint32_t dpd_pads_oride;
|
||||
uint32_t dpd_sample;
|
||||
uint32_t dpd_enable;
|
||||
uint32_t pwrgate_timer_off;
|
||||
uint32_t clamp_status;
|
||||
uint32_t pwrgate_toggle;
|
||||
uint32_t remove_clamping;
|
||||
uint32_t pwrgate_status;
|
||||
uint32_t pwrgood_timer;
|
||||
uint32_t blink_timer;
|
||||
uint32_t no_iopower;
|
||||
uint32_t pwr_det;
|
||||
uint32_t pwr_det_latch;
|
||||
uint32_t scratch0;
|
||||
uint32_t scratch1;
|
||||
uint32_t scratch2;
|
||||
uint32_t scratch3;
|
||||
uint32_t scratch4;
|
||||
uint32_t scratch5;
|
||||
uint32_t scratch6;
|
||||
uint32_t scratch7;
|
||||
uint32_t scratch8;
|
||||
uint32_t scratch9;
|
||||
uint32_t scratch10;
|
||||
uint32_t scratch11;
|
||||
uint32_t scratch12;
|
||||
uint32_t scratch13;
|
||||
uint32_t scratch14;
|
||||
uint32_t scratch15;
|
||||
uint32_t scratch16;
|
||||
uint32_t scratch17;
|
||||
uint32_t scratch18;
|
||||
uint32_t scratch19;
|
||||
uint32_t scratch20;
|
||||
uint32_t scratch21;
|
||||
uint32_t scratch22;
|
||||
uint32_t scratch23;
|
||||
uint32_t secure_scratch0;
|
||||
uint32_t secure_scratch1;
|
||||
uint32_t secure_scratch2;
|
||||
uint32_t secure_scratch3;
|
||||
uint32_t secure_scratch4;
|
||||
uint32_t secure_scratch5;
|
||||
uint32_t cpupwrgood_timer;
|
||||
uint32_t cpupwroff_timer;
|
||||
uint32_t pg_mask;
|
||||
uint32_t pg_mask_1;
|
||||
uint32_t auto_wake_lvl;
|
||||
uint32_t auto_wake_lvl_mask;
|
||||
uint32_t wake_delay;
|
||||
uint32_t pwr_det_val;
|
||||
uint32_t ddr_pwr;
|
||||
uint32_t usb_debounce_del;
|
||||
uint32_t usb_ao;
|
||||
uint32_t crypto_op;
|
||||
uint32_t pllp_wb0_override;
|
||||
uint32_t scratch24;
|
||||
uint32_t scratch25;
|
||||
uint32_t scratch26;
|
||||
uint32_t scratch27;
|
||||
uint32_t scratch28;
|
||||
uint32_t scratch29;
|
||||
uint32_t scratch30;
|
||||
uint32_t scratch31;
|
||||
uint32_t scratch32;
|
||||
uint32_t scratch33;
|
||||
uint32_t scratch34;
|
||||
uint32_t scratch35;
|
||||
uint32_t scratch36;
|
||||
uint32_t scratch37;
|
||||
uint32_t scratch38;
|
||||
uint32_t scratch39;
|
||||
uint32_t scratch40;
|
||||
uint32_t scratch41;
|
||||
uint32_t scratch42;
|
||||
uint32_t bo_mirror0;
|
||||
uint32_t bo_mirror1;
|
||||
uint32_t bo_mirror2;
|
||||
uint32_t sys_33v_en;
|
||||
uint32_t bo_mirror_access;
|
||||
uint32_t gate;
|
||||
uint32_t wake2_mask;
|
||||
uint32_t wake2_lvl;
|
||||
uint32_t wake2_stat;
|
||||
uint32_t sw_wake2_stat;
|
||||
uint32_t auto_wake2_lvl_mask;
|
||||
uint32_t pg_mask2;
|
||||
uint32_t pg_mask_ce1;
|
||||
uint32_t pg_mask_ce2;
|
||||
uint32_t pg_mask_ce3;
|
||||
uint32_t pwrgate_timer_ce0;
|
||||
uint32_t pwrgate_timer_ce1;
|
||||
uint32_t pwrgate_timer_ce2;
|
||||
uint32_t pwrgate_timer_ce3;
|
||||
uint32_t pwrgate_timer_ce4;
|
||||
uint32_t pwrgate_timer_ce5;
|
||||
uint32_t pwrgate_timer_ce6;
|
||||
uint32_t pcx_edpd_cntrl;
|
||||
uint32_t osc_edpd_over;
|
||||
uint32_t clk_out_cntrl;
|
||||
uint32_t sata_pwrgate;
|
||||
uint32_t sensor_ctrl;
|
||||
uint32_t reset_status;
|
||||
uint32_t io_dpd_req;
|
||||
uint32_t io_dpd_stat;
|
||||
uint32_t io_dpd2_req;
|
||||
uint32_t io_dpd2_stat;
|
||||
uint32_t sel_dpd_tim;
|
||||
uint32_t vddp_sel;
|
||||
uint32_t ddr_cfg;
|
||||
uint32_t e_no_vttgen;
|
||||
uint32_t _reserved0;
|
||||
uint32_t pllm_wb0_ovrride_frq;
|
||||
uint32_t test_pwrgate;
|
||||
uint32_t pwrgate_timer_mult;
|
||||
uint32_t dsi_sel_dpd;
|
||||
uint32_t utmip_uhsic_triggers;
|
||||
uint32_t utmip_uhsic_saved_st;
|
||||
uint32_t utmip_pad_cfg;
|
||||
uint32_t utmip_term_pad_cfg;
|
||||
uint32_t utmip_uhsic_sleep_cfg;
|
||||
uint32_t utmip_uhsic_sleepwalk_cfg;
|
||||
uint32_t utmip_sleepwalk_p[3];
|
||||
uint32_t uhsic_sleepwalk_p0;
|
||||
uint32_t utmip_uhsic_status;
|
||||
uint32_t utmip_uhsic_fake;
|
||||
uint32_t bo_mirror3[2];
|
||||
uint32_t secure_scratch6;
|
||||
uint32_t secure_scratch7;
|
||||
uint32_t scratch43;
|
||||
uint32_t scratch44;
|
||||
uint32_t scratch45;
|
||||
uint32_t scratch46;
|
||||
uint32_t scratch47;
|
||||
uint32_t scratch48;
|
||||
uint32_t scratch49;
|
||||
uint32_t scratch50;
|
||||
uint32_t scratch51;
|
||||
uint32_t scratch52;
|
||||
uint32_t scratch53;
|
||||
uint32_t scratch54;
|
||||
uint32_t scratch55;
|
||||
uint32_t scratch0_eco;
|
||||
uint32_t por_dpd_ctrl;
|
||||
uint32_t scratch2_eco;
|
||||
uint32_t utmip_uhsic_line_wakeup;
|
||||
uint32_t utmip_bias_master_cntrl;
|
||||
uint32_t utmip_master_config;
|
||||
uint32_t td_pwrgate_inter_part_timer;
|
||||
uint32_t utmip_uhsic2_triggers;
|
||||
uint32_t utmip_uhsic2_saved_state;
|
||||
uint32_t utmip_uhsic2_sleep_cfg;
|
||||
uint32_t utmip_uhsic2_sleepwalk_cfg;
|
||||
uint32_t uhsic2_sleepwalk_p1;
|
||||
uint32_t utmip_uhsic2_status;
|
||||
uint32_t utmip_uhsic2_fake;
|
||||
uint32_t utmip_uhsic2_line_wakeup;
|
||||
uint32_t utmip_master2_config;
|
||||
uint32_t utmip_uhsic_rpd_cfg;
|
||||
uint32_t pg_mask_ce0;
|
||||
uint32_t pg_mask3[2];
|
||||
uint32_t pllm_wb0_override2;
|
||||
uint32_t tsc_mult;
|
||||
uint32_t cpu_vsense_override;
|
||||
uint32_t glb_amap_cfg;
|
||||
uint32_t sticky_bits;
|
||||
uint32_t sec_disable2;
|
||||
uint32_t weak_bias;
|
||||
uint32_t reg_short;
|
||||
uint32_t pg_mask_andor;
|
||||
uint32_t _reserved1[11];
|
||||
uint32_t secure_scratch8;
|
||||
uint32_t secure_scratch9;
|
||||
uint32_t secure_scratch10;
|
||||
uint32_t secure_scratch11;
|
||||
uint32_t secure_scratch12;
|
||||
uint32_t secure_scratch13;
|
||||
uint32_t secure_scratch14;
|
||||
uint32_t secure_scratch15;
|
||||
uint32_t secure_scratch16;
|
||||
uint32_t secure_scratch17;
|
||||
uint32_t secure_scratch18;
|
||||
uint32_t secure_scratch19;
|
||||
uint32_t secure_scratch20;
|
||||
uint32_t secure_scratch21;
|
||||
uint32_t secure_scratch22;
|
||||
uint32_t secure_scratch23;
|
||||
uint32_t secure_scratch24;
|
||||
uint32_t secure_scratch25;
|
||||
uint32_t secure_scratch26;
|
||||
uint32_t secure_scratch27;
|
||||
uint32_t secure_scratch28;
|
||||
uint32_t secure_scratch29;
|
||||
uint32_t secure_scratch30;
|
||||
uint32_t secure_scratch31;
|
||||
uint32_t secure_scratch32;
|
||||
uint32_t secure_scratch33;
|
||||
uint32_t secure_scratch34;
|
||||
uint32_t secure_scratch35;
|
||||
uint32_t secure_scratch36;
|
||||
uint32_t secure_scratch37;
|
||||
uint32_t secure_scratch38;
|
||||
uint32_t secure_scratch39;
|
||||
uint32_t secure_scratch40;
|
||||
uint32_t secure_scratch41;
|
||||
uint32_t secure_scratch42;
|
||||
uint32_t secure_scratch43;
|
||||
uint32_t secure_scratch44;
|
||||
uint32_t secure_scratch45;
|
||||
uint32_t secure_scratch46;
|
||||
uint32_t secure_scratch47;
|
||||
uint32_t secure_scratch48;
|
||||
uint32_t secure_scratch49;
|
||||
uint32_t secure_scratch50;
|
||||
uint32_t secure_scratch51;
|
||||
uint32_t secure_scratch52;
|
||||
uint32_t secure_scratch53;
|
||||
uint32_t secure_scratch54;
|
||||
uint32_t secure_scratch55;
|
||||
uint32_t secure_scratch56;
|
||||
uint32_t secure_scratch57;
|
||||
uint32_t secure_scratch58;
|
||||
uint32_t secure_scratch59;
|
||||
uint32_t secure_scratch60;
|
||||
uint32_t secure_scratch61;
|
||||
uint32_t secure_scratch62;
|
||||
uint32_t secure_scratch63;
|
||||
uint32_t secure_scratch64;
|
||||
uint32_t secure_scratch65;
|
||||
uint32_t secure_scratch66;
|
||||
uint32_t secure_scratch67;
|
||||
uint32_t secure_scratch68;
|
||||
uint32_t secure_scratch69;
|
||||
uint32_t secure_scratch70;
|
||||
uint32_t secure_scratch71;
|
||||
uint32_t secure_scratch72;
|
||||
uint32_t secure_scratch73;
|
||||
uint32_t secure_scratch74;
|
||||
uint32_t secure_scratch75;
|
||||
uint32_t secure_scratch76;
|
||||
uint32_t secure_scratch77;
|
||||
uint32_t secure_scratch78;
|
||||
uint32_t secure_scratch79;
|
||||
uint32_t _reserved2[8];
|
||||
uint32_t cntrl2;
|
||||
uint32_t _reserved3[2];
|
||||
uint32_t event_counter;
|
||||
uint32_t fuse_control;
|
||||
uint32_t scratch1_eco;
|
||||
uint32_t _reserved4;
|
||||
uint32_t io_dpd3_req;
|
||||
uint32_t io_dpd3_status;
|
||||
uint32_t io_dpd4_req;
|
||||
uint32_t io_dpd4_status;
|
||||
uint32_t _reserved5[30];
|
||||
uint32_t ddr_cntrl;
|
||||
uint32_t _reserved6[70];
|
||||
uint32_t scratch56;
|
||||
uint32_t scratch57;
|
||||
uint32_t scratch58;
|
||||
uint32_t scratch59;
|
||||
uint32_t scratch60;
|
||||
uint32_t scratch61;
|
||||
uint32_t scratch62;
|
||||
uint32_t scratch63;
|
||||
uint32_t scratch64;
|
||||
uint32_t scratch65;
|
||||
uint32_t scratch66;
|
||||
uint32_t scratch67;
|
||||
uint32_t scratch68;
|
||||
uint32_t scratch69;
|
||||
uint32_t scratch70;
|
||||
uint32_t scratch71;
|
||||
uint32_t scratch72;
|
||||
uint32_t scratch73;
|
||||
uint32_t scratch74;
|
||||
uint32_t scratch75;
|
||||
uint32_t scratch76;
|
||||
uint32_t scratch77;
|
||||
uint32_t scratch78;
|
||||
uint32_t scratch79;
|
||||
uint32_t scratch80;
|
||||
uint32_t scratch81;
|
||||
uint32_t scratch82;
|
||||
uint32_t scratch83;
|
||||
uint32_t scratch84;
|
||||
uint32_t scratch85;
|
||||
uint32_t scratch86;
|
||||
uint32_t scratch87;
|
||||
uint32_t scratch88;
|
||||
uint32_t scratch89;
|
||||
uint32_t scratch90;
|
||||
uint32_t scratch91;
|
||||
uint32_t scratch92;
|
||||
uint32_t scratch93;
|
||||
uint32_t scratch94;
|
||||
uint32_t scratch95;
|
||||
uint32_t scratch96;
|
||||
uint32_t scratch97;
|
||||
uint32_t scratch98;
|
||||
uint32_t scratch99;
|
||||
uint32_t scratch100;
|
||||
uint32_t scratch101;
|
||||
uint32_t scratch102;
|
||||
uint32_t scratch103;
|
||||
uint32_t scratch104;
|
||||
uint32_t scratch105;
|
||||
uint32_t scratch106;
|
||||
uint32_t scratch107;
|
||||
uint32_t scratch108;
|
||||
uint32_t scratch109;
|
||||
uint32_t scratch110;
|
||||
uint32_t scratch111;
|
||||
uint32_t scratch112;
|
||||
uint32_t scratch113;
|
||||
uint32_t scratch114;
|
||||
uint32_t scratch115;
|
||||
uint32_t scratch116;
|
||||
uint32_t scratch117;
|
||||
uint32_t scratch118;
|
||||
uint32_t scratch119;
|
||||
uint32_t scratch120;
|
||||
uint32_t scratch121;
|
||||
uint32_t scratch122;
|
||||
uint32_t scratch123;
|
||||
uint32_t scratch124;
|
||||
uint32_t scratch125;
|
||||
uint32_t scratch126;
|
||||
uint32_t scratch127;
|
||||
uint32_t scratch128;
|
||||
uint32_t scratch129;
|
||||
uint32_t scratch130;
|
||||
uint32_t scratch131;
|
||||
uint32_t scratch132;
|
||||
uint32_t scratch133;
|
||||
uint32_t scratch134;
|
||||
uint32_t scratch135;
|
||||
uint32_t scratch136;
|
||||
uint32_t scratch137;
|
||||
uint32_t scratch138;
|
||||
uint32_t scratch139;
|
||||
uint32_t scratch140;
|
||||
uint32_t scratch141;
|
||||
uint32_t scratch142;
|
||||
uint32_t scratch143;
|
||||
uint32_t scratch144;
|
||||
uint32_t scratch145;
|
||||
uint32_t scratch146;
|
||||
uint32_t scratch147;
|
||||
uint32_t scratch148;
|
||||
uint32_t scratch149;
|
||||
uint32_t scratch150;
|
||||
uint32_t scratch151;
|
||||
uint32_t scratch152;
|
||||
uint32_t scratch153;
|
||||
uint32_t scratch154;
|
||||
uint32_t scratch155;
|
||||
uint32_t scratch156;
|
||||
uint32_t scratch157;
|
||||
uint32_t scratch158;
|
||||
uint32_t scratch159;
|
||||
uint32_t scratch160;
|
||||
uint32_t scratch161;
|
||||
uint32_t scratch162;
|
||||
uint32_t scratch163;
|
||||
uint32_t scratch164;
|
||||
uint32_t scratch165;
|
||||
uint32_t scratch166;
|
||||
uint32_t scratch167;
|
||||
uint32_t scratch168;
|
||||
uint32_t scratch169;
|
||||
uint32_t scratch170;
|
||||
uint32_t scratch171;
|
||||
uint32_t scratch172;
|
||||
uint32_t scratch173;
|
||||
uint32_t scratch174;
|
||||
uint32_t scratch175;
|
||||
uint32_t scratch176;
|
||||
uint32_t scratch177;
|
||||
uint32_t scratch178;
|
||||
uint32_t scratch179;
|
||||
uint32_t scratch180;
|
||||
uint32_t scratch181;
|
||||
uint32_t scratch182;
|
||||
uint32_t scratch183;
|
||||
uint32_t scratch184;
|
||||
uint32_t scratch185;
|
||||
uint32_t scratch186;
|
||||
uint32_t scratch187;
|
||||
uint32_t scratch188;
|
||||
uint32_t scratch189;
|
||||
uint32_t scratch190;
|
||||
uint32_t scratch191;
|
||||
uint32_t scratch192;
|
||||
uint32_t scratch193;
|
||||
uint32_t scratch194;
|
||||
uint32_t scratch195;
|
||||
uint32_t scratch196;
|
||||
uint32_t scratch197;
|
||||
uint32_t scratch198;
|
||||
uint32_t scratch199;
|
||||
uint32_t scratch200;
|
||||
uint32_t scratch201;
|
||||
uint32_t scratch202;
|
||||
uint32_t scratch203;
|
||||
uint32_t scratch204;
|
||||
uint32_t scratch205;
|
||||
uint32_t scratch206;
|
||||
uint32_t scratch207;
|
||||
uint32_t scratch208;
|
||||
uint32_t scratch209;
|
||||
uint32_t scratch210;
|
||||
uint32_t scratch211;
|
||||
uint32_t scratch212;
|
||||
uint32_t scratch213;
|
||||
uint32_t scratch214;
|
||||
uint32_t scratch215;
|
||||
uint32_t scratch216;
|
||||
uint32_t scratch217;
|
||||
uint32_t scratch218;
|
||||
uint32_t scratch219;
|
||||
uint32_t scratch220;
|
||||
uint32_t scratch221;
|
||||
uint32_t scratch222;
|
||||
uint32_t scratch223;
|
||||
uint32_t scratch224;
|
||||
uint32_t scratch225;
|
||||
uint32_t scratch226;
|
||||
uint32_t scratch227;
|
||||
uint32_t scratch228;
|
||||
uint32_t scratch229;
|
||||
uint32_t scratch230;
|
||||
uint32_t scratch231;
|
||||
uint32_t scratch232;
|
||||
uint32_t scratch233;
|
||||
uint32_t scratch234;
|
||||
uint32_t scratch235;
|
||||
uint32_t scratch236;
|
||||
uint32_t scratch237;
|
||||
uint32_t scratch238;
|
||||
uint32_t scratch239;
|
||||
uint32_t scratch240;
|
||||
uint32_t scratch241;
|
||||
uint32_t scratch242;
|
||||
uint32_t scratch243;
|
||||
uint32_t scratch244;
|
||||
uint32_t scratch245;
|
||||
uint32_t scratch246;
|
||||
uint32_t scratch247;
|
||||
uint32_t scratch248;
|
||||
uint32_t scratch249;
|
||||
uint32_t scratch250;
|
||||
uint32_t scratch251;
|
||||
uint32_t scratch252;
|
||||
uint32_t scratch253;
|
||||
uint32_t scratch254;
|
||||
uint32_t scratch255;
|
||||
uint32_t scratch256;
|
||||
uint32_t scratch257;
|
||||
uint32_t scratch258;
|
||||
uint32_t scratch259;
|
||||
uint32_t scratch260;
|
||||
uint32_t scratch261;
|
||||
uint32_t scratch262;
|
||||
uint32_t scratch263;
|
||||
uint32_t scratch264;
|
||||
uint32_t scratch265;
|
||||
uint32_t scratch266;
|
||||
uint32_t scratch267;
|
||||
uint32_t scratch268;
|
||||
uint32_t scratch269;
|
||||
uint32_t scratch270;
|
||||
uint32_t scratch271;
|
||||
uint32_t scratch272;
|
||||
uint32_t scratch273;
|
||||
uint32_t scratch274;
|
||||
uint32_t scratch275;
|
||||
uint32_t scratch276;
|
||||
uint32_t scratch277;
|
||||
uint32_t scratch278;
|
||||
uint32_t scratch279;
|
||||
uint32_t scratch280;
|
||||
uint32_t scratch281;
|
||||
uint32_t scratch282;
|
||||
uint32_t scratch283;
|
||||
uint32_t scratch284;
|
||||
uint32_t scratch285;
|
||||
uint32_t scratch286;
|
||||
uint32_t scratch287;
|
||||
uint32_t scratch288;
|
||||
uint32_t scratch289;
|
||||
uint32_t scratch290;
|
||||
uint32_t scratch291;
|
||||
uint32_t scratch292;
|
||||
uint32_t scratch293;
|
||||
uint32_t scratch294;
|
||||
uint32_t scratch295;
|
||||
uint32_t scratch296;
|
||||
uint32_t scratch297;
|
||||
uint32_t scratch298;
|
||||
uint32_t scratch299;
|
||||
uint32_t _reserved7[50];
|
||||
uint32_t secure_scratch80;
|
||||
uint32_t secure_scratch81;
|
||||
uint32_t secure_scratch82;
|
||||
uint32_t secure_scratch83;
|
||||
uint32_t secure_scratch84;
|
||||
uint32_t secure_scratch85;
|
||||
uint32_t secure_scratch86;
|
||||
uint32_t secure_scratch87;
|
||||
uint32_t secure_scratch88;
|
||||
uint32_t secure_scratch89;
|
||||
uint32_t secure_scratch90;
|
||||
uint32_t secure_scratch91;
|
||||
uint32_t secure_scratch92;
|
||||
uint32_t secure_scratch93;
|
||||
uint32_t secure_scratch94;
|
||||
uint32_t secure_scratch95;
|
||||
uint32_t secure_scratch96;
|
||||
uint32_t secure_scratch97;
|
||||
uint32_t secure_scratch98;
|
||||
uint32_t secure_scratch99;
|
||||
uint32_t secure_scratch100;
|
||||
uint32_t secure_scratch101;
|
||||
uint32_t secure_scratch102;
|
||||
uint32_t secure_scratch103;
|
||||
uint32_t secure_scratch104;
|
||||
uint32_t secure_scratch105;
|
||||
uint32_t secure_scratch106;
|
||||
uint32_t secure_scratch107;
|
||||
uint32_t secure_scratch108;
|
||||
uint32_t secure_scratch109;
|
||||
uint32_t secure_scratch110;
|
||||
uint32_t secure_scratch111;
|
||||
uint32_t secure_scratch112;
|
||||
uint32_t secure_scratch113;
|
||||
uint32_t secure_scratch114;
|
||||
uint32_t secure_scratch115;
|
||||
uint32_t secure_scratch116;
|
||||
uint32_t secure_scratch117;
|
||||
uint32_t secure_scratch118;
|
||||
uint32_t secure_scratch119;
|
||||
} tegra_pmc_t;
|
||||
|
||||
static inline volatile tegra_pmc_t *pmc_get_regs(void)
|
||||
{
|
||||
return (volatile tegra_pmc_t *)PMC_BASE;
|
||||
}
|
||||
|
||||
#endif
|
||||
207
sept/sept-secondary/src/preprocessor.h
Normal file
207
sept/sept-secondary/src/preprocessor.h
Normal file
|
|
@ -0,0 +1,207 @@
|
|||
/* TuxSH: I added INC/DEC_10 to INC/DEC_32; tuples */
|
||||
|
||||
#ifndef FUSEE_PREPROCESSOR_H
|
||||
#define FUSEE_PREPROCESSOR_H
|
||||
|
||||
/*=============================================================================
|
||||
Copyright (c) 2015 Paul Fultz II
|
||||
cloak.h
|
||||
Distributed under the Boost Software License, Version 1.0. (See accompanying
|
||||
file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
|
||||
==============================================================================*/
|
||||
|
||||
/*#ifndef CLOAK_GUARD_H
|
||||
#define CLOAK_GUARD_H*/
|
||||
|
||||
#define CAT(a, ...) PRIMITIVE_CAT(a, __VA_ARGS__)
|
||||
#define PRIMITIVE_CAT(a, ...) a ## __VA_ARGS__
|
||||
|
||||
#define COMPL(b) PRIMITIVE_CAT(COMPL_, b)
|
||||
#define COMPL_0 1
|
||||
#define COMPL_1 0
|
||||
|
||||
#define BITAND(x) PRIMITIVE_CAT(BITAND_, x)
|
||||
#define BITAND_0(y) 0
|
||||
#define BITAND_1(y) y
|
||||
|
||||
#define INC(x) PRIMITIVE_CAT(INC_, x)
|
||||
#define INC_0 1
|
||||
#define INC_1 2
|
||||
#define INC_2 3
|
||||
#define INC_3 4
|
||||
#define INC_4 5
|
||||
#define INC_5 6
|
||||
#define INC_6 7
|
||||
#define INC_7 8
|
||||
#define INC_8 9
|
||||
#define INC_9 10
|
||||
#define INC_10 11
|
||||
#define INC_11 12
|
||||
#define INC_12 13
|
||||
#define INC_13 14
|
||||
#define INC_14 15
|
||||
#define INC_15 16
|
||||
#define INC_16 17
|
||||
#define INC_17 18
|
||||
#define INC_18 19
|
||||
#define INC_19 20
|
||||
#define INC_20 21
|
||||
#define INC_21 22
|
||||
#define INC_22 23
|
||||
#define INC_23 24
|
||||
#define INC_24 25
|
||||
#define INC_25 26
|
||||
#define INC_26 27
|
||||
#define INC_27 28
|
||||
#define INC_28 29
|
||||
#define INC_29 30
|
||||
#define INC_30 31
|
||||
#define INC_31 32
|
||||
#define INC_32 32
|
||||
#define INC_33 33
|
||||
|
||||
#define DEC(x) PRIMITIVE_CAT(DEC_, x)
|
||||
#define DEC_0 0
|
||||
#define DEC_1 0
|
||||
#define DEC_2 1
|
||||
#define DEC_3 2
|
||||
#define DEC_4 3
|
||||
#define DEC_5 4
|
||||
#define DEC_6 5
|
||||
#define DEC_7 6
|
||||
#define DEC_8 7
|
||||
#define DEC_9 8
|
||||
#define DEC_10 9
|
||||
#define DEC_11 10
|
||||
#define DEC_12 11
|
||||
#define DEC_13 12
|
||||
#define DEC_14 13
|
||||
#define DEC_15 14
|
||||
#define DEC_16 15
|
||||
#define DEC_17 16
|
||||
#define DEC_18 17
|
||||
#define DEC_19 18
|
||||
#define DEC_20 19
|
||||
#define DEC_21 20
|
||||
#define DEC_22 21
|
||||
#define DEC_23 22
|
||||
#define DEC_24 23
|
||||
#define DEC_25 24
|
||||
#define DEC_26 25
|
||||
#define DEC_27 26
|
||||
#define DEC_28 27
|
||||
#define DEC_29 28
|
||||
#define DEC_30 29
|
||||
#define DEC_31 30
|
||||
#define DEC_32 31
|
||||
#define DEC_33 32
|
||||
|
||||
#define CHECK_N(x, n, ...) n
|
||||
#define CHECK(...) CHECK_N(__VA_ARGS__, 0,)
|
||||
#define PROBE(x) x, 1,
|
||||
|
||||
#define IS_PAREN(x) CHECK(IS_PAREN_PROBE x)
|
||||
#define IS_PAREN_PROBE(...) PROBE(~)
|
||||
|
||||
#define NOT(x) CHECK(PRIMITIVE_CAT(NOT_, x))
|
||||
#define NOT_0 PROBE(~)
|
||||
|
||||
#define COMPL(b) PRIMITIVE_CAT(COMPL_, b)
|
||||
#define COMPL_0 1
|
||||
#define COMPL_1 0
|
||||
|
||||
#define BOOL(x) COMPL(NOT(x))
|
||||
|
||||
#define IIF(c) PRIMITIVE_CAT(IIF_, c)
|
||||
#define IIF_0(t, ...) __VA_ARGS__
|
||||
#define IIF_1(t, ...) t
|
||||
|
||||
#define IF(c) IIF(BOOL(c))
|
||||
|
||||
#define EAT(...)
|
||||
#define EXPAND(...) __VA_ARGS__
|
||||
#define WHEN(c) IF(c)(EXPAND, EAT)
|
||||
|
||||
#define EMPTY()
|
||||
#define DEFER(id) id EMPTY()
|
||||
#define OBSTRUCT(id) id DEFER(EMPTY)()
|
||||
|
||||
#define EVAL(...) EVAL1(EVAL1(EVAL1(__VA_ARGS__)))
|
||||
#define EVAL1(...) EVAL2(EVAL2(EVAL2(__VA_ARGS__)))
|
||||
#define EVAL2(...) EVAL3(EVAL3(EVAL3(__VA_ARGS__)))
|
||||
#define EVAL3(...) EVAL4(EVAL4(EVAL4(__VA_ARGS__)))
|
||||
#define EVAL4(...) EVAL5(EVAL5(EVAL5(__VA_ARGS__)))
|
||||
#define EVAL5(...) __VA_ARGS__
|
||||
|
||||
#define REPEAT(count, macro, ...) \
|
||||
WHEN(count) \
|
||||
( \
|
||||
OBSTRUCT(REPEAT_INDIRECT) () \
|
||||
( \
|
||||
DEC(count), macro, __VA_ARGS__ \
|
||||
) \
|
||||
OBSTRUCT(macro) \
|
||||
( \
|
||||
DEC(count), __VA_ARGS__ \
|
||||
) \
|
||||
)
|
||||
#define REPEAT_INDIRECT() REPEAT
|
||||
|
||||
#define WHILE(pred, op, ...) \
|
||||
IF(pred(__VA_ARGS__)) \
|
||||
( \
|
||||
OBSTRUCT(WHILE_INDIRECT) () \
|
||||
( \
|
||||
pred, op, op(__VA_ARGS__) \
|
||||
), \
|
||||
__VA_ARGS__ \
|
||||
)
|
||||
#define WHILE_INDIRECT() WHILE
|
||||
|
||||
#define PRIMITIVE_COMPARE(x, y) IS_PAREN \
|
||||
( \
|
||||
COMPARE_ ## x ( COMPARE_ ## y) (()) \
|
||||
)
|
||||
|
||||
#define IS_COMPARABLE(x) IS_PAREN( CAT(COMPARE_, x) (()) )
|
||||
|
||||
#define NOT_EQUAL(x, y) \
|
||||
IIF(BITAND(IS_COMPARABLE(x))(IS_COMPARABLE(y)) ) \
|
||||
( \
|
||||
PRIMITIVE_COMPARE, \
|
||||
1 EAT \
|
||||
)(x, y)
|
||||
|
||||
#define EQUAL(x, y) COMPL(NOT_EQUAL(x, y))
|
||||
|
||||
#define COMMA() ,
|
||||
|
||||
#define COMMA_IF(n) IF(n)(COMMA, EAT)()
|
||||
|
||||
#define PLUS() +
|
||||
|
||||
#define _TUPLE_ELEM_0(a, ...) a
|
||||
#define _TUPLE_ELEM_1(a, b, ...) b
|
||||
#define _TUPLE_ELEM_2(a, b, c, ...) c
|
||||
#define _TUPLE_ELEM_3(a, b, c, d, ...) d
|
||||
#define _TUPLE_ELEM_4(a, b, c, d, e, ...) e
|
||||
|
||||
#define TUPLE_ELEM_0(T) EVAL(_TUPLE_ELEM_0 T)
|
||||
#define TUPLE_ELEM_1(T) EVAL(_TUPLE_ELEM_1 T)
|
||||
#define TUPLE_ELEM_2(T) EVAL(_TUPLE_ELEM_2 T)
|
||||
#define TUPLE_ELEM_3(T) EVAL(_TUPLE_ELEM_3 T)
|
||||
#define TUPLE_ELEM_4(T) EVAL(_TUPLE_ELEM_4 T)
|
||||
|
||||
#define _TUPLE_FOLD_LEFT_0(i, T, op) (_TUPLE_ELEM_0 CAT(T,i)) op()
|
||||
#define _TUPLE_FOLD_LEFT_1(i, T, op) (_TUPLE_ELEM_1 CAT(T,i)) op()
|
||||
#define _TUPLE_FOLD_LEFT_2(i, T, op) (_TUPLE_ELEM_2 CAT(T,i)) op()
|
||||
#define _TUPLE_FOLD_LEFT_3(i, T, op) (_TUPLE_ELEM_3 CAT(T,i)) op()
|
||||
#define _TUPLE_FOLD_LEFT_4(i, T, op) (_TUPLE_ELEM_4 CAT(T,i)) op()
|
||||
|
||||
#define TUPLE_FOLD_LEFT_0(len, T, op) EVAL(REPEAT(len, _TUPLE_FOLD_LEFT_0, T, op))
|
||||
#define TUPLE_FOLD_LEFT_1(len, T, op) EVAL(REPEAT(len, _TUPLE_FOLD_LEFT_1, T, op))
|
||||
#define TUPLE_FOLD_LEFT_2(len, T, op) EVAL(REPEAT(len, _TUPLE_FOLD_LEFT_2, T, op))
|
||||
#define TUPLE_FOLD_LEFT_3(len, T, op) EVAL(REPEAT(len, _TUPLE_FOLD_LEFT_3, T, op))
|
||||
#define TUPLE_FOLD_LEFT_4(len, T, op) EVAL(REPEAT(len, _TUPLE_FOLD_LEFT_4, T, op))
|
||||
|
||||
#endif
|
||||
449
sept/sept-secondary/src/sdmmc/mmc.h
Normal file
449
sept/sept-secondary/src/sdmmc/mmc.h
Normal file
|
|
@ -0,0 +1,449 @@
|
|||
/*
|
||||
* Header for MultiMediaCard (MMC)
|
||||
*
|
||||
* Copyright 2002 Hewlett-Packard Company
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* Use consistent with the GNU GPL is permitted,
|
||||
* provided that this copyright notice is
|
||||
* preserved in its entirety in all copies and derived works.
|
||||
*
|
||||
* HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
|
||||
* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
|
||||
* FITNESS FOR ANY PARTICULAR PURPOSE.
|
||||
*
|
||||
* Many thanks to Alessandro Rubini and Jonathan Corbet!
|
||||
*
|
||||
* Based strongly on code by:
|
||||
*
|
||||
* Author: Yong-iL Joh <tolkien@mizi.com>
|
||||
*
|
||||
* Author: Andrew Christian
|
||||
* 15 May 2002
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_MMC_H
|
||||
#define LINUX_MMC_MMC_H
|
||||
|
||||
/* Standard MMC commands (4.1) type argument response */
|
||||
/* class 1 */
|
||||
#define MMC_GO_IDLE_STATE 0 /* bc */
|
||||
#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
|
||||
#define MMC_ALL_SEND_CID 2 /* bcr R2 */
|
||||
#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
|
||||
#define MMC_SET_DSR 4 /* bc [31:16] RCA */
|
||||
#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
|
||||
#define MMC_SWITCH 6 /* ac [31:0] See below R1b */
|
||||
#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
|
||||
#define MMC_SEND_EXT_CSD 8 /* adtc R1 */
|
||||
#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
|
||||
#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
|
||||
#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
|
||||
#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
|
||||
#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
|
||||
#define MMC_BUS_TEST_R 14 /* adtc R1 */
|
||||
#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
|
||||
#define MMC_BUS_TEST_W 19 /* adtc R1 */
|
||||
#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
|
||||
#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
|
||||
|
||||
/* class 2 */
|
||||
#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
|
||||
#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
|
||||
#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
|
||||
|
||||
/* class 3 */
|
||||
#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
|
||||
|
||||
/* class 4 */
|
||||
#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
|
||||
#define MMC_PROGRAM_CID 26 /* adtc R1 */
|
||||
#define MMC_PROGRAM_CSD 27 /* adtc R1 */
|
||||
|
||||
/* class 6 */
|
||||
#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
|
||||
#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
|
||||
#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
|
||||
|
||||
/* class 5 */
|
||||
#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
|
||||
#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
|
||||
#define MMC_ERASE 38 /* ac R1b */
|
||||
|
||||
/* class 9 */
|
||||
#define MMC_FAST_IO 39 /* ac <Complex> R4 */
|
||||
#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
|
||||
|
||||
/* class 7 */
|
||||
#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
|
||||
|
||||
/* class 8 */
|
||||
#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
|
||||
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
|
||||
|
||||
/* class 11 */
|
||||
#define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */
|
||||
#define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */
|
||||
#define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */
|
||||
#define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */
|
||||
#define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */
|
||||
|
||||
/*
|
||||
* MMC_SWITCH argument format:
|
||||
*
|
||||
* [31:26] Always 0
|
||||
* [25:24] Access Mode
|
||||
* [23:16] Location of target Byte in EXT_CSD
|
||||
* [15:08] Value Byte
|
||||
* [07:03] Always 0
|
||||
* [02:00] Command Set
|
||||
*/
|
||||
|
||||
/*
|
||||
MMC status in R1, for native mode (SPI bits are different)
|
||||
Type
|
||||
e : error bit
|
||||
s : status bit
|
||||
r : detected and set for the actual command response
|
||||
x : detected and set during command execution. the host must poll
|
||||
the card by sending status command in order to read these bits.
|
||||
Clear condition
|
||||
a : according to the card state
|
||||
b : always related to the previous command. Reception of
|
||||
a valid command will clear it (with a delay of one command)
|
||||
c : clear by read
|
||||
*/
|
||||
|
||||
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
|
||||
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
|
||||
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
|
||||
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
|
||||
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
|
||||
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
|
||||
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
|
||||
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
|
||||
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
|
||||
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
|
||||
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
|
||||
#define R1_CC_ERROR (1 << 20) /* erx, c */
|
||||
#define R1_ERROR (1 << 19) /* erx, c */
|
||||
#define R1_UNDERRUN (1 << 18) /* ex, c */
|
||||
#define R1_OVERRUN (1 << 17) /* ex, c */
|
||||
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
|
||||
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
|
||||
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
|
||||
#define R1_ERASE_RESET (1 << 13) /* sr, c */
|
||||
#define R1_STATUS(x) (x & 0xFFFFE000)
|
||||
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
|
||||
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
|
||||
#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
|
||||
#define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */
|
||||
#define R1_APP_CMD (1 << 5) /* sr, c */
|
||||
|
||||
#define R1_STATE_IDLE 0
|
||||
#define R1_STATE_READY 1
|
||||
#define R1_STATE_IDENT 2
|
||||
#define R1_STATE_STBY 3
|
||||
#define R1_STATE_TRAN 4
|
||||
#define R1_STATE_DATA 5
|
||||
#define R1_STATE_RCV 6
|
||||
#define R1_STATE_PRG 7
|
||||
#define R1_STATE_DIS 8
|
||||
|
||||
/*
|
||||
* MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
|
||||
* R1 is the low order byte; R2 is the next highest byte, when present.
|
||||
*/
|
||||
#define R1_SPI_IDLE (1 << 0)
|
||||
#define R1_SPI_ERASE_RESET (1 << 1)
|
||||
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
|
||||
#define R1_SPI_COM_CRC (1 << 3)
|
||||
#define R1_SPI_ERASE_SEQ (1 << 4)
|
||||
#define R1_SPI_ADDRESS (1 << 5)
|
||||
#define R1_SPI_PARAMETER (1 << 6)
|
||||
/* R1 bit 7 is always zero */
|
||||
#define R2_SPI_CARD_LOCKED (1 << 8)
|
||||
#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
|
||||
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
|
||||
#define R2_SPI_ERROR (1 << 10)
|
||||
#define R2_SPI_CC_ERROR (1 << 11)
|
||||
#define R2_SPI_CARD_ECC_ERROR (1 << 12)
|
||||
#define R2_SPI_WP_VIOLATION (1 << 13)
|
||||
#define R2_SPI_ERASE_PARAM (1 << 14)
|
||||
#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
|
||||
#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
|
||||
|
||||
/*
|
||||
* OCR bits are mostly in host.h
|
||||
*/
|
||||
#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
|
||||
#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
|
||||
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
|
||||
#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
|
||||
#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
|
||||
#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
|
||||
#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
|
||||
#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
|
||||
#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
|
||||
#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
|
||||
#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
|
||||
#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
|
||||
#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
|
||||
#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
|
||||
#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
|
||||
#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
|
||||
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
|
||||
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
|
||||
|
||||
/*
|
||||
* Card Command Classes (CCC)
|
||||
*/
|
||||
#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
|
||||
/* (CMD0,1,2,3,4,7,9,10,12,13,15) */
|
||||
/* (and for SPI, CMD58,59) */
|
||||
#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
|
||||
/* (CMD11) */
|
||||
#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
|
||||
/* (CMD16,17,18) */
|
||||
#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
|
||||
/* (CMD20) */
|
||||
#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
|
||||
/* (CMD16,24,25,26,27) */
|
||||
#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
|
||||
/* (CMD32,33,34,35,36,37,38,39) */
|
||||
#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
|
||||
/* (CMD28,29,30) */
|
||||
#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
|
||||
/* (CMD16,CMD42) */
|
||||
#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
|
||||
/* (CMD55,56,57,ACMD*) */
|
||||
#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
|
||||
/* (CMD5,39,40,52,53) */
|
||||
#define CCC_SWITCH (1<<10) /* (10) High speed switch */
|
||||
/* (CMD6,34,35,36,37,50) */
|
||||
/* (11) Reserved */
|
||||
/* (CMD?) */
|
||||
|
||||
/*
|
||||
* CSD field definitions
|
||||
*/
|
||||
|
||||
#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
|
||||
#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
|
||||
#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
|
||||
#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
|
||||
|
||||
#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
|
||||
#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
|
||||
#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
|
||||
#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
|
||||
#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
|
||||
|
||||
/*
|
||||
* EXT_CSD fields
|
||||
*/
|
||||
|
||||
#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
|
||||
#define EXT_CSD_FLUSH_CACHE 32 /* W */
|
||||
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
|
||||
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
|
||||
#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
|
||||
#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
|
||||
#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
|
||||
#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
|
||||
#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
|
||||
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
|
||||
#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
|
||||
#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
|
||||
#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
|
||||
#define EXT_CSD_HPI_MGMT 161 /* R/W */
|
||||
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
|
||||
#define EXT_CSD_BKOPS_EN 163 /* R/W */
|
||||
#define EXT_CSD_BKOPS_START 164 /* W */
|
||||
#define EXT_CSD_SANITIZE_START 165 /* W */
|
||||
#define EXT_CSD_WR_REL_PARAM 166 /* RO */
|
||||
#define EXT_CSD_RPMB_MULT 168 /* RO */
|
||||
#define EXT_CSD_FW_CONFIG 169 /* R/W */
|
||||
#define EXT_CSD_BOOT_WP 173 /* R/W */
|
||||
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
|
||||
#define EXT_CSD_PART_CONFIG 179 /* R/W */
|
||||
#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
|
||||
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
|
||||
#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
|
||||
#define EXT_CSD_HS_TIMING 185 /* R/W */
|
||||
#define EXT_CSD_POWER_CLASS 187 /* R/W */
|
||||
#define EXT_CSD_REV 192 /* RO */
|
||||
#define EXT_CSD_STRUCTURE 194 /* RO */
|
||||
#define EXT_CSD_CARD_TYPE 196 /* RO */
|
||||
#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
|
||||
#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
|
||||
#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
|
||||
#define EXT_CSD_PWR_CL_52_195 200 /* RO */
|
||||
#define EXT_CSD_PWR_CL_26_195 201 /* RO */
|
||||
#define EXT_CSD_PWR_CL_52_360 202 /* RO */
|
||||
#define EXT_CSD_PWR_CL_26_360 203 /* RO */
|
||||
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
|
||||
#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
|
||||
#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
|
||||
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
|
||||
#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
|
||||
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
|
||||
#define EXT_CSD_BOOT_MULT 226 /* RO */
|
||||
#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
|
||||
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
|
||||
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
|
||||
#define EXT_CSD_TRIM_MULT 232 /* RO */
|
||||
#define EXT_CSD_PWR_CL_200_195 236 /* RO */
|
||||
#define EXT_CSD_PWR_CL_200_360 237 /* RO */
|
||||
#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
|
||||
#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
|
||||
#define EXT_CSD_BKOPS_STATUS 246 /* RO */
|
||||
#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
|
||||
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
|
||||
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
|
||||
#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
|
||||
#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */
|
||||
#define EXT_CSD_PRE_EOL_INFO 267 /* RO */
|
||||
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */
|
||||
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */
|
||||
#define EXT_CSD_CMDQ_DEPTH 307 /* RO */
|
||||
#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */
|
||||
#define EXT_CSD_SUPPORTED_MODE 493 /* RO */
|
||||
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
|
||||
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
|
||||
#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
|
||||
#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
|
||||
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
|
||||
#define EXT_CSD_HPI_FEATURES 503 /* RO */
|
||||
|
||||
/*
|
||||
* EXT_CSD field definitions
|
||||
*/
|
||||
|
||||
#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
|
||||
|
||||
#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
|
||||
#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
|
||||
#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
|
||||
#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
|
||||
|
||||
#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
|
||||
|
||||
#define EXT_CSD_PART_SETTING_COMPLETED (0x1)
|
||||
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
|
||||
|
||||
#define EXT_CSD_CMD_SET_NORMAL (1<<0)
|
||||
#define EXT_CSD_CMD_SET_SECURE (1<<1)
|
||||
#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
|
||||
|
||||
#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \
|
||||
EXT_CSD_CARD_TYPE_HS_52)
|
||||
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
|
||||
/* DDR mode @1.8V or 3V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
|
||||
/* DDR mode @1.2V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
|
||||
| EXT_CSD_CARD_TYPE_DDR_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
|
||||
/* SDR mode @1.2V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
|
||||
EXT_CSD_CARD_TYPE_HS200_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
|
||||
#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
|
||||
#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
|
||||
EXT_CSD_CARD_TYPE_HS400_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */
|
||||
|
||||
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
|
||||
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
|
||||
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
|
||||
#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
|
||||
|
||||
#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
|
||||
#define EXT_CSD_TIMING_HS 1 /* High speed */
|
||||
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
|
||||
#define EXT_CSD_TIMING_HS400 3 /* HS400 */
|
||||
#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
|
||||
|
||||
#define EXT_CSD_SEC_ER_EN BIT(0)
|
||||
#define EXT_CSD_SEC_BD_BLK_EN BIT(2)
|
||||
#define EXT_CSD_SEC_GB_CL_EN BIT(4)
|
||||
#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
|
||||
|
||||
#define EXT_CSD_RST_N_EN_MASK 0x3
|
||||
#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
|
||||
|
||||
#define EXT_CSD_NO_POWER_NOTIFICATION 0
|
||||
#define EXT_CSD_POWER_ON 1
|
||||
#define EXT_CSD_POWER_OFF_SHORT 2
|
||||
#define EXT_CSD_POWER_OFF_LONG 3
|
||||
|
||||
#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
|
||||
#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
|
||||
#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
|
||||
#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
|
||||
|
||||
#define EXT_CSD_PACKED_EVENT_EN BIT(3)
|
||||
|
||||
/*
|
||||
* EXCEPTION_EVENT_STATUS field
|
||||
*/
|
||||
#define EXT_CSD_URGENT_BKOPS BIT(0)
|
||||
#define EXT_CSD_DYNCAP_NEEDED BIT(1)
|
||||
#define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2)
|
||||
#define EXT_CSD_PACKED_FAILURE BIT(3)
|
||||
|
||||
#define EXT_CSD_PACKED_GENERIC_ERROR BIT(0)
|
||||
#define EXT_CSD_PACKED_INDEXED_ERROR BIT(1)
|
||||
|
||||
/*
|
||||
* BKOPS status level
|
||||
*/
|
||||
#define EXT_CSD_BKOPS_LEVEL_2 0x2
|
||||
|
||||
/*
|
||||
* BKOPS modes
|
||||
*/
|
||||
#define EXT_CSD_MANUAL_BKOPS_MASK 0x01
|
||||
#define EXT_CSD_AUTO_BKOPS_MASK 0x02
|
||||
|
||||
/*
|
||||
* Command Queue
|
||||
*/
|
||||
#define EXT_CSD_CMDQ_MODE_ENABLED BIT(0)
|
||||
#define EXT_CSD_CMDQ_DEPTH_MASK GENMASK(4, 0)
|
||||
#define EXT_CSD_CMDQ_SUPPORTED BIT(0)
|
||||
|
||||
/*
|
||||
* MMC_SWITCH access modes
|
||||
*/
|
||||
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
|
||||
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
|
||||
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
|
||||
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
|
||||
|
||||
/*
|
||||
* Erase/trim/discard
|
||||
*/
|
||||
#define MMC_ERASE_ARG 0x00000000
|
||||
#define MMC_SECURE_ERASE_ARG 0x80000000
|
||||
#define MMC_TRIM_ARG 0x00000001
|
||||
#define MMC_DISCARD_ARG 0x00000003
|
||||
#define MMC_SECURE_TRIM1_ARG 0x80000001
|
||||
#define MMC_SECURE_TRIM2_ARG 0x80008000
|
||||
#define MMC_SECURE_ARGS 0x80000000
|
||||
#define MMC_TRIM_ARGS 0x00008001
|
||||
|
||||
#endif /* LINUX_MMC_MMC_H */
|
||||
155
sept/sept-secondary/src/sdmmc/sd.h
Normal file
155
sept/sept-secondary/src/sdmmc/sd.h
Normal file
|
|
@ -0,0 +1,155 @@
|
|||
/*
|
||||
* include/linux/mmc/sd.h
|
||||
*
|
||||
* Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
|
||||
* Copyright (C) 2018 CTCaer
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or (at
|
||||
* your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_SD_H
|
||||
#define LINUX_MMC_SD_H
|
||||
|
||||
/* SD commands type argument response */
|
||||
/* class 0 */
|
||||
/* This is basically the same command as for MMC with some quirks. */
|
||||
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
|
||||
#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
|
||||
#define SD_SWITCH_VOLTAGE 11 /* ac R1 */
|
||||
|
||||
/* class 10 */
|
||||
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
|
||||
|
||||
/* class 5 */
|
||||
#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */
|
||||
#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */
|
||||
|
||||
/* Application commands */
|
||||
#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
|
||||
#define SD_APP_SD_STATUS 13 /* adtc R1 */
|
||||
#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
|
||||
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
|
||||
#define SD_APP_SET_CLR_CARD_DETECT 42 /* ac [0] set cd R1 */
|
||||
#define SD_APP_SEND_SCR 51 /* adtc R1 */
|
||||
|
||||
/* OCR bit definitions */
|
||||
#define SD_OCR_S18R (1 << 24) /* 1.8V switching request */
|
||||
#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
|
||||
#define SD_OCR_XPC (1 << 28) /* SDXC power control */
|
||||
#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */
|
||||
#define SD_OCR_VDD_LOW (1 << 7) /* SD: Reserved for Low Voltage Range */
|
||||
#define SD_OCR_VDD_20_21 (1 << 8)
|
||||
#define SD_OCR_VDD_21_22 (1 << 9)
|
||||
#define SD_OCR_VDD_22_23 (1 << 10)
|
||||
#define SD_OCR_VDD_23_24 (1 << 11)
|
||||
#define SD_OCR_VDD_24_25 (1 << 12)
|
||||
#define SD_OCR_VDD_25_26 (1 << 13)
|
||||
#define SD_OCR_VDD_26_27 (1 << 14)
|
||||
#define SD_OCR_VDD_27_28 (1 << 15)
|
||||
#define SD_OCR_VDD_28_29 (1 << 16)
|
||||
#define SD_OCR_VDD_29_30 (1 << 17)
|
||||
#define SD_OCR_VDD_30_31 (1 << 18)
|
||||
#define SD_OCR_VDD_31_32 (1 << 19)
|
||||
#define SD_OCR_VDD_32_33 (1 << 20)
|
||||
#define SD_OCR_VDD_33_34 (1 << 21)
|
||||
#define SD_OCR_VDD_34_35 (1 << 22)
|
||||
#define SD_OCR_VDD_35_36 (1 << 23)
|
||||
|
||||
/*
|
||||
* SD_SWITCH argument format:
|
||||
*
|
||||
* [31] Check (0) or switch (1)
|
||||
* [30:24] Reserved (0)
|
||||
* [23:20] Function group 6
|
||||
* [19:16] Function group 5
|
||||
* [15:12] Function group 4
|
||||
* [11:8] Function group 3
|
||||
* [7:4] Function group 2
|
||||
* [3:0] Function group 1
|
||||
*/
|
||||
|
||||
/*
|
||||
* SD_SEND_IF_COND argument format:
|
||||
*
|
||||
* [31:12] Reserved (0)
|
||||
* [11:8] Host Voltage Supply Flags
|
||||
* [7:0] Check Pattern (0xAA)
|
||||
*/
|
||||
|
||||
/*
|
||||
* SCR field definitions
|
||||
*/
|
||||
|
||||
#define SD_SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
|
||||
#define SD_SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
|
||||
#define SD_SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */
|
||||
#define SD_SCR_BUS_WIDTH_1 1
|
||||
#define SD_SCR_BUS_WIDTH_4 4
|
||||
#define SD_SCR_CMD20_SUPPORT 1
|
||||
#define SD_SCR_CMD23_SUPPORT 2
|
||||
|
||||
/*
|
||||
* SD bus widths
|
||||
*/
|
||||
#define SD_BUS_WIDTH_1 0
|
||||
#define SD_BUS_WIDTH_4 2
|
||||
|
||||
/*
|
||||
* SD bus speed modes
|
||||
*/
|
||||
#define UHS_SDR12_BUS_SPEED 0
|
||||
#define HIGH_SPEED_BUS_SPEED 1
|
||||
#define UHS_SDR25_BUS_SPEED 1
|
||||
#define UHS_SDR50_BUS_SPEED 2
|
||||
#define UHS_SDR104_BUS_SPEED 3
|
||||
#define UHS_DDR50_BUS_SPEED 4
|
||||
#define SD_MODE_HIGH_SPEED (1 << HIGH_SPEED_BUS_SPEED)
|
||||
#define SD_MODE_UHS_SDR12 (1 << UHS_SDR12_BUS_SPEED)
|
||||
#define SD_MODE_UHS_SDR25 (1 << UHS_SDR25_BUS_SPEED)
|
||||
#define SD_MODE_UHS_SDR50 (1 << UHS_SDR50_BUS_SPEED)
|
||||
#define SD_MODE_UHS_SDR104 (1 << UHS_SDR104_BUS_SPEED)
|
||||
#define SD_MODE_UHS_DDR50 (1 << UHS_DDR50_BUS_SPEED)
|
||||
|
||||
/*
|
||||
* SD bus driver types
|
||||
*/
|
||||
#define SD_DRIVER_TYPE_B 0x01
|
||||
#define SD_DRIVER_TYPE_A 0x02
|
||||
#define SD_DRIVER_TYPE_C 0x04
|
||||
#define SD_DRIVER_TYPE_D 0x08
|
||||
|
||||
/*
|
||||
* SD bus current limits
|
||||
*/
|
||||
#define SD_SET_CURRENT_LIMIT_200 0
|
||||
#define SD_SET_CURRENT_LIMIT_400 1
|
||||
#define SD_SET_CURRENT_LIMIT_600 2
|
||||
#define SD_SET_CURRENT_LIMIT_800 3
|
||||
#define SD_SET_CURRENT_NO_CHANGE (-1)
|
||||
#define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200)
|
||||
#define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400)
|
||||
#define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600)
|
||||
#define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800)
|
||||
|
||||
/*
|
||||
* SD_SWITCH mode
|
||||
*/
|
||||
#define SD_SWITCH_CHECK 0
|
||||
#define SD_SWITCH_SET 1
|
||||
|
||||
/*
|
||||
* SD_SWITCH function groups
|
||||
*/
|
||||
#define SD_SWITCH_GRP_ACCESS 0
|
||||
|
||||
/*
|
||||
* SD_SWITCH access modes
|
||||
*/
|
||||
#define SD_SWITCH_ACCESS_DEF 0
|
||||
#define SD_SWITCH_ACCESS_HS 1
|
||||
|
||||
#endif /* LINUX_MMC_SD_H */
|
||||
1543
sept/sept-secondary/src/sdmmc/sdmmc.c
Normal file
1543
sept/sept-secondary/src/sdmmc/sdmmc.c
Normal file
File diff suppressed because it is too large
Load diff
179
sept/sept-secondary/src/sdmmc/sdmmc.h
Normal file
179
sept/sept-secondary/src/sdmmc/sdmmc.h
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 CTCaer
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_SDMMC_H
|
||||
#define FUSEE_SDMMC_H
|
||||
|
||||
#include "sdmmc_core.h"
|
||||
|
||||
/* Structure for storing the MMC CID (adapted from Linux headers) */
|
||||
typedef struct {
|
||||
uint32_t manfid;
|
||||
uint8_t prod_name[8];
|
||||
uint8_t prv;
|
||||
uint32_t serial;
|
||||
uint16_t oemid;
|
||||
uint16_t year;
|
||||
uint8_t hwrev;
|
||||
uint8_t fwrev;
|
||||
uint8_t month;
|
||||
} mmc_cid_t;
|
||||
|
||||
/* Structure for storing the MMC CSD (adapted from Linux headers) */
|
||||
typedef struct {
|
||||
uint8_t structure;
|
||||
uint8_t mmca_vsn;
|
||||
uint16_t cmdclass;
|
||||
uint16_t taac_clks;
|
||||
uint32_t taac_ns;
|
||||
uint32_t c_size;
|
||||
uint32_t r2w_factor;
|
||||
uint32_t max_dtr;
|
||||
uint32_t erase_size; /* In sectors */
|
||||
uint32_t read_blkbits;
|
||||
uint32_t write_blkbits;
|
||||
uint32_t capacity;
|
||||
uint32_t read_partial:1,
|
||||
read_misalign:1,
|
||||
write_partial:1,
|
||||
write_misalign:1,
|
||||
dsr_imp:1;
|
||||
} mmc_csd_t;
|
||||
|
||||
/* Structure for storing the MMC extended CSD (adapted from Linux headers) */
|
||||
typedef struct {
|
||||
uint8_t rev;
|
||||
uint8_t erase_group_def;
|
||||
uint8_t sec_feature_support;
|
||||
uint8_t rel_sectors;
|
||||
uint8_t rel_param;
|
||||
uint8_t part_config;
|
||||
uint8_t cache_ctrl;
|
||||
uint8_t rst_n_function;
|
||||
uint8_t max_packed_writes;
|
||||
uint8_t max_packed_reads;
|
||||
uint8_t packed_event_en;
|
||||
uint32_t part_time; /* Units: ms */
|
||||
uint32_t sa_timeout; /* Units: 100ns */
|
||||
uint32_t generic_cmd6_time; /* Units: 10ms */
|
||||
uint32_t power_off_longtime; /* Units: ms */
|
||||
uint8_t power_off_notification; /* state */
|
||||
uint32_t hs_max_dtr;
|
||||
uint32_t hs200_max_dtr;
|
||||
uint32_t sectors;
|
||||
uint32_t hc_erase_size; /* In sectors */
|
||||
uint32_t hc_erase_timeout; /* In milliseconds */
|
||||
uint32_t sec_trim_mult; /* Secure trim multiplier */
|
||||
uint32_t sec_erase_mult; /* Secure erase multiplier */
|
||||
uint32_t trim_timeout; /* In milliseconds */
|
||||
uint32_t partition_setting_completed; /* enable bit */
|
||||
uint64_t enhanced_area_offset; /* Units: Byte */
|
||||
uint32_t enhanced_area_size; /* Units: KB */
|
||||
uint32_t cache_size; /* Units: KB */
|
||||
uint32_t hpi_en; /* HPI enablebit */
|
||||
uint32_t hpi; /* HPI support bit */
|
||||
uint32_t hpi_cmd; /* cmd used as HPI */
|
||||
uint32_t bkops; /* background support bit */
|
||||
uint32_t man_bkops_en; /* manual bkops enable bit */
|
||||
uint32_t auto_bkops_en; /* auto bkops enable bit */
|
||||
uint32_t data_sector_size; /* 512 bytes or 4KB */
|
||||
uint32_t data_tag_unit_size; /* DATA TAG UNIT size */
|
||||
uint32_t boot_ro_lock; /* ro lock support */
|
||||
uint32_t boot_ro_lockable;
|
||||
uint32_t ffu_capable; /* Firmware upgrade support */
|
||||
uint32_t cmdq_en; /* Command Queue enabled */
|
||||
uint32_t cmdq_support; /* Command Queue supported */
|
||||
uint32_t cmdq_depth; /* Command Queue depth */
|
||||
uint8_t fwrev[8]; /* FW version */
|
||||
uint8_t raw_exception_status; /* 54 */
|
||||
uint8_t raw_partition_support; /* 160 */
|
||||
uint8_t raw_rpmb_size_mult; /* 168 */
|
||||
uint8_t raw_erased_mem_count; /* 181 */
|
||||
uint8_t strobe_support; /* 184 */
|
||||
uint8_t raw_ext_csd_structure; /* 194 */
|
||||
uint8_t raw_card_type; /* 196 */
|
||||
uint8_t raw_driver_strength; /* 197 */
|
||||
uint8_t out_of_int_time; /* 198 */
|
||||
uint8_t raw_pwr_cl_52_195; /* 200 */
|
||||
uint8_t raw_pwr_cl_26_195; /* 201 */
|
||||
uint8_t raw_pwr_cl_52_360; /* 202 */
|
||||
uint8_t raw_pwr_cl_26_360; /* 203 */
|
||||
uint8_t raw_s_a_timeout; /* 217 */
|
||||
uint8_t raw_hc_erase_gap_size; /* 221 */
|
||||
uint8_t raw_erase_timeout_mult; /* 223 */
|
||||
uint8_t raw_hc_erase_grp_size; /* 224 */
|
||||
uint8_t raw_sec_trim_mult; /* 229 */
|
||||
uint8_t raw_sec_erase_mult; /* 230 */
|
||||
uint8_t raw_sec_feature_support; /* 231 */
|
||||
uint8_t raw_trim_mult; /* 232 */
|
||||
uint8_t raw_pwr_cl_200_195; /* 236 */
|
||||
uint8_t raw_pwr_cl_200_360; /* 237 */
|
||||
uint8_t raw_pwr_cl_ddr_52_195; /* 238 */
|
||||
uint8_t raw_pwr_cl_ddr_52_360; /* 239 */
|
||||
uint8_t raw_pwr_cl_ddr_200_360; /* 253 */
|
||||
uint8_t raw_bkops_status; /* 246 */
|
||||
uint8_t raw_sectors[4]; /* 212 - 4 bytes */
|
||||
uint8_t pre_eol_info; /* 267 */
|
||||
uint8_t device_life_time_est_typ_a; /* 268 */
|
||||
uint8_t device_life_time_est_typ_b; /* 269 */
|
||||
uint32_t feature_support;
|
||||
} mmc_ext_csd_t;
|
||||
|
||||
/* Structure for storing the SD SCR (adapted from Linux headers) */
|
||||
typedef struct {
|
||||
uint8_t sda_vsn;
|
||||
uint8_t sda_spec3;
|
||||
uint8_t bus_widths;
|
||||
uint8_t cmds;
|
||||
} sd_scr_t;
|
||||
|
||||
/* Structure for storing the SD SSR (adapted from Linux headers) */
|
||||
typedef struct {
|
||||
uint8_t dat_bus_width;
|
||||
uint8_t secured_mode;
|
||||
uint16_t sd_card_type;
|
||||
uint8_t speed_class;
|
||||
uint8_t uhs_speed_grade;
|
||||
uint8_t uhs_au_size;
|
||||
uint8_t video_speed_class;
|
||||
uint8_t app_perf_class;
|
||||
} sd_ssr_t;
|
||||
|
||||
/* Structure describing a SDMMC device's context. */
|
||||
typedef struct {
|
||||
/* Underlying driver context. */
|
||||
sdmmc_t *sdmmc;
|
||||
|
||||
bool is_180v;
|
||||
bool is_block_sdhc;
|
||||
uint32_t rca;
|
||||
mmc_cid_t cid;
|
||||
mmc_csd_t csd;
|
||||
mmc_ext_csd_t ext_csd;
|
||||
sd_scr_t scr;
|
||||
sd_ssr_t ssr;
|
||||
} sdmmc_device_t;
|
||||
|
||||
int sdmmc_device_sd_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth bus_width, SdmmcBusSpeed bus_speed);
|
||||
int sdmmc_device_mmc_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth bus_width, SdmmcBusSpeed bus_speed);
|
||||
int sdmmc_device_read(sdmmc_device_t *device, uint32_t sector, uint32_t num_sectors, void *data);
|
||||
int sdmmc_device_write(sdmmc_device_t *device, uint32_t sector, uint32_t num_sectors, void *data);
|
||||
int sdmmc_device_finish(sdmmc_device_t *device);
|
||||
int sdmmc_mmc_select_partition(sdmmc_device_t *device, SdmmcPartitionNum partition);
|
||||
|
||||
#endif
|
||||
1979
sept/sept-secondary/src/sdmmc/sdmmc_core.c
Normal file
1979
sept/sept-secondary/src/sdmmc/sdmmc_core.c
Normal file
File diff suppressed because it is too large
Load diff
306
sept/sept-secondary/src/sdmmc/sdmmc_core.h
Normal file
306
sept/sept-secondary/src/sdmmc/sdmmc_core.h
Normal file
|
|
@ -0,0 +1,306 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 CTCaer
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_SDMMC_CORE_H
|
||||
#define FUSEE_SDMMC_CORE_H
|
||||
|
||||
#include "sdmmc_tegra.h"
|
||||
|
||||
/* Bounce buffer */
|
||||
#define SDMMC_BOUNCE_BUFFER_ADDRESS 0x90000000
|
||||
|
||||
/* Present state */
|
||||
#define SDHCI_CMD_INHIBIT 0x00000001
|
||||
#define SDHCI_DATA_INHIBIT 0x00000002
|
||||
#define SDHCI_DOING_WRITE 0x00000100
|
||||
#define SDHCI_DOING_READ 0x00000200
|
||||
#define SDHCI_SPACE_AVAILABLE 0x00000400
|
||||
#define SDHCI_DATA_AVAILABLE 0x00000800
|
||||
#define SDHCI_CARD_PRESENT 0x00010000
|
||||
#define SDHCI_WRITE_PROTECT 0x00080000
|
||||
#define SDHCI_DATA_LVL_MASK 0x00F00000
|
||||
#define SDHCI_DATA_LVL_SHIFT 20
|
||||
#define SDHCI_DATA_0_LVL_MASK 0x00100000
|
||||
#define SDHCI_CMD_LVL 0x01000000
|
||||
|
||||
/* SDHCI clock control */
|
||||
#define SDHCI_DIVIDER_SHIFT 8
|
||||
#define SDHCI_DIVIDER_HI_SHIFT 6
|
||||
#define SDHCI_DIV_MASK 0xFF
|
||||
#define SDHCI_DIV_MASK_LEN 8
|
||||
#define SDHCI_DIV_HI_MASK 0x300
|
||||
#define SDHCI_PROG_CLOCK_MODE 0x0020
|
||||
#define SDHCI_CLOCK_CARD_EN 0x0004
|
||||
#define SDHCI_CLOCK_INT_STABLE 0x0002
|
||||
#define SDHCI_CLOCK_INT_EN 0x0001
|
||||
|
||||
/* SDHCI host control */
|
||||
#define SDHCI_CTRL_LED 0x01
|
||||
#define SDHCI_CTRL_4BITBUS 0x02
|
||||
#define SDHCI_CTRL_HISPD 0x04
|
||||
#define SDHCI_CTRL_DMA_MASK 0x18
|
||||
#define SDHCI_CTRL_SDMA 0x00
|
||||
#define SDHCI_CTRL_ADMA1 0x08
|
||||
#define SDHCI_CTRL_ADMA32 0x10
|
||||
#define SDHCI_CTRL_ADMA64 0x18
|
||||
#define SDHCI_CTRL_8BITBUS 0x20
|
||||
#define SDHCI_CTRL_CDTEST_INS 0x40
|
||||
#define SDHCI_CTRL_CDTEST_EN 0x80
|
||||
|
||||
/* SDHCI host control 2 */
|
||||
#define SDHCI_CTRL_UHS_MASK 0x0007
|
||||
#define SDHCI_CTRL_UHS_SDR12 0x0000
|
||||
#define SDHCI_CTRL_UHS_SDR25 0x0001
|
||||
#define SDHCI_CTRL_UHS_SDR50 0x0002
|
||||
#define SDHCI_CTRL_UHS_SDR104 0x0003
|
||||
#define SDHCI_CTRL_UHS_DDR50 0x0004
|
||||
#define SDHCI_CTRL_HS400 0x0005
|
||||
#define SDHCI_CTRL_VDD_180 0x0008
|
||||
#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
|
||||
#define SDHCI_CTRL_DRV_TYPE_B 0x0000
|
||||
#define SDHCI_CTRL_DRV_TYPE_A 0x0010
|
||||
#define SDHCI_CTRL_DRV_TYPE_C 0x0020
|
||||
#define SDHCI_CTRL_DRV_TYPE_D 0x0030
|
||||
#define SDHCI_CTRL_EXEC_TUNING 0x0040
|
||||
#define SDHCI_CTRL_TUNED_CLK 0x0080
|
||||
#define SDHCI_UHS2_IF_EN 0x0100
|
||||
#define SDHCI_HOST_VERSION_4_EN 0x1000
|
||||
#define SDHCI_ADDRESSING_64BIT_EN 0x2000
|
||||
#define SDHCI_ASYNC_INTR_EN 0x4000
|
||||
#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
|
||||
|
||||
/* SDHCI capabilities */
|
||||
#define SDHCI_CAN_DO_8BIT 0x00040000
|
||||
#define SDHCI_CAN_DO_ADMA2 0x00080000
|
||||
#define SDHCI_CAN_DO_ADMA1 0x00100000
|
||||
#define SDHCI_CAN_DO_HISPD 0x00200000
|
||||
#define SDHCI_CAN_DO_SDMA 0x00400000
|
||||
#define SDHCI_CAN_VDD_330 0x01000000
|
||||
#define SDHCI_CAN_VDD_300 0x02000000
|
||||
#define SDHCI_CAN_VDD_180 0x04000000
|
||||
#define SDHCI_CAN_64BIT 0x10000000
|
||||
#define SDHCI_ASYNC_INTR 0x20000000
|
||||
|
||||
/* Vendor clock control */
|
||||
#define SDMMC_CLOCK_TAP_MASK (0xFF << 16)
|
||||
#define SDMMC_CLOCK_TAP_SDMMC1 (0x04 << 16)
|
||||
#define SDMMC_CLOCK_TAP_SDMMC2 (0x00 << 16)
|
||||
#define SDMMC_CLOCK_TAP_SDMMC3 (0x03 << 16)
|
||||
#define SDMMC_CLOCK_TAP_SDMMC4 (0x00 << 16)
|
||||
#define SDMMC_CLOCK_TRIM_MASK (0xFF << 24)
|
||||
#define SDMMC_CLOCK_TRIM_SDMMC1 (0x02 << 24)
|
||||
#define SDMMC_CLOCK_TRIM_SDMMC2 (0x08 << 24)
|
||||
#define SDMMC_CLOCK_TRIM_SDMMC3 (0x03 << 24)
|
||||
#define SDMMC_CLOCK_TRIM_SDMMC4 (0x08 << 24)
|
||||
#define SDMMC_CLOCK_PADPIPE_CLKEN_OVERRIDE (1 << 3)
|
||||
|
||||
/* Autocal configuration */
|
||||
#define SDMMC_AUTOCAL_PDPU_CONFIG_MASK 0x7F7F
|
||||
#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8 0x7B7B
|
||||
#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3 0x7D00
|
||||
#define SDMMC_AUTOCAL_PDPU_SDMMC4_1V8 0x0505
|
||||
#define SDMMC_AUTOCAL_START (1 << 31)
|
||||
#define SDMMC_AUTOCAL_ENABLE (1 << 29)
|
||||
|
||||
/* Autocal status */
|
||||
#define SDMMC_AUTOCAL_ACTIVE (1 << 31)
|
||||
|
||||
/* Vendor tuning control 0*/
|
||||
#define SDMMC_VENDOR_TUNING_TRIES_MASK (0x7 << 13)
|
||||
#define SDMMC_VENDOR_TUNING_TRIES_SHIFT 13
|
||||
#define SDMMC_VENDOR_TUNING_MULTIPLIER_MASK (0x7F << 6)
|
||||
#define SDMMC_VENDOR_TUNING_MULTIPLIER_UNITY (1 << 6)
|
||||
#define SDMMC_VENDOR_TUNING_DIVIDER_MASK (0x7 << 3)
|
||||
#define SDMMC_VENDOR_TUNING_SET_BY_HW (1 << 17)
|
||||
|
||||
/* Vendor tuning control 1*/
|
||||
#define SDMMC_VENDOR_TUNING_STEP_SIZE_SDR50_DEFAULT (0 << 0)
|
||||
#define SDMMC_VENDOR_TUNING_STEP_SIZE_SDR104_DEFAULT (0 << 4)
|
||||
|
||||
/* Vendor capability overrides */
|
||||
#define SDMMC_VENDOR_CAPABILITY_DQS_TRIM_MASK (0x3F << 8)
|
||||
#define SDMMC_VENDOR_CAPABILITY_DQS_TRIM_HS400 (0x11 << 8)
|
||||
|
||||
/* Timeouts */
|
||||
#define SDMMC_AUTOCAL_TIMEOUT (10 * 1000)
|
||||
#define SDMMC_TUNING_TIMEOUT (150 * 1000)
|
||||
|
||||
/* Command response flags */
|
||||
#define SDMMC_RSP_PRESENT (1 << 0)
|
||||
#define SDMMC_RSP_136 (1 << 1)
|
||||
#define SDMMC_RSP_CRC (1 << 2)
|
||||
#define SDMMC_RSP_BUSY (1 << 3)
|
||||
#define SDMMC_RSP_OPCODE (1 << 4)
|
||||
|
||||
/* Command types */
|
||||
#define SDMMC_CMD_MASK (3 << 5)
|
||||
#define SDMMC_CMD_AC (0 << 5)
|
||||
#define SDMMC_CMD_ADTC (1 << 5)
|
||||
#define SDMMC_CMD_BC (2 << 5)
|
||||
#define SDMMC_CMD_BCR (3 << 5)
|
||||
|
||||
/* SPI command response flags */
|
||||
#define SDMMC_RSP_SPI_S1 (1 << 7)
|
||||
#define SDMMC_RSP_SPI_S2 (1 << 8)
|
||||
#define SDMMC_RSP_SPI_B4 (1 << 9)
|
||||
#define SDMMC_RSP_SPI_BUSY (1 << 10)
|
||||
|
||||
/* Native response types for commands */
|
||||
#define SDMMC_RSP_NONE (0)
|
||||
#define SDMMC_RSP_R1 (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
|
||||
#define SDMMC_RSP_R1B (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE|SDMMC_RSP_BUSY)
|
||||
#define SDMMC_RSP_R2 (SDMMC_RSP_PRESENT|SDMMC_RSP_136|SDMMC_RSP_CRC)
|
||||
#define SDMMC_RSP_R3 (SDMMC_RSP_PRESENT)
|
||||
#define SDMMC_RSP_R4 (SDMMC_RSP_PRESENT)
|
||||
#define SDMMC_RSP_R5 (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
|
||||
#define SDMMC_RSP_R6 (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
|
||||
#define SDMMC_RSP_R7 (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
|
||||
#define SDMMC_RSP_R1_NO_CRC (SDMMC_RSP_PRESENT|SDMMC_RSP_OPCODE)
|
||||
|
||||
/* SPI response types for commands */
|
||||
#define SDMMC_RSP_SPI_R1 (SDMMC_RSP_SPI_S1)
|
||||
#define SDMMC_RSP_SPI_R1B (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_BUSY)
|
||||
#define SDMMC_RSP_SPI_R2 (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_S2)
|
||||
#define SDMMC_RSP_SPI_R3 (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_B4)
|
||||
#define SDMMC_RSP_SPI_R4 (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_B4)
|
||||
#define SDMMC_RSP_SPI_R5 (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_S2)
|
||||
#define SDMMC_RSP_SPI_R7 (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_B4)
|
||||
|
||||
/* SDMMC controllers */
|
||||
typedef enum {
|
||||
SDMMC_1 = 0,
|
||||
SDMMC_2 = 1,
|
||||
SDMMC_3 = 2,
|
||||
SDMMC_4 = 3
|
||||
} SdmmcControllerNum;
|
||||
|
||||
typedef enum {
|
||||
SDMMC_PARTITION_INVALID = -1,
|
||||
SDMMC_PARTITION_USER = 0,
|
||||
SDMMC_PARTITION_BOOT0 = 1,
|
||||
SDMMC_PARTITION_BOOT1 = 2,
|
||||
SDMMC_PARTITION_RPMB = 3
|
||||
} SdmmcPartitionNum;
|
||||
|
||||
typedef enum {
|
||||
SDMMC_VOLTAGE_NONE = 0,
|
||||
SDMMC_VOLTAGE_1V8 = 1,
|
||||
SDMMC_VOLTAGE_3V3 = 2
|
||||
} SdmmcBusVoltage;
|
||||
|
||||
typedef enum {
|
||||
SDMMC_BUS_WIDTH_1BIT = 0,
|
||||
SDMMC_BUS_WIDTH_4BIT = 1,
|
||||
SDMMC_BUS_WIDTH_8BIT = 2
|
||||
} SdmmcBusWidth;
|
||||
|
||||
typedef enum {
|
||||
SDMMC_SPEED_INIT_HS = 0,
|
||||
SDMMC_SPEED_HS26 = 1,
|
||||
SDMMC_SPEED_HS52 = 2,
|
||||
SDMMC_SPEED_HS200 = 3,
|
||||
SDMMC_SPEED_HS400 = 4,
|
||||
SDMMC_SPEED_INIT_SDR = 5,
|
||||
SDMMC_SPEED_UNK6 = 6,
|
||||
SDMMC_SPEED_SDR25 = 7,
|
||||
SDMMC_SPEED_SDR12 = 8,
|
||||
SDMMC_SPEED_UNK9 = 9,
|
||||
SDMMC_SPEED_SDR50 = 10,
|
||||
SDMMC_SPEED_SDR104 = 11,
|
||||
SDMMC_SPEED_UNK12 = 12,
|
||||
SDMMC_SPEED_DDR50 = 13,
|
||||
SDMMC_SPEED_UNK14 = 14,
|
||||
} SdmmcBusSpeed;
|
||||
|
||||
typedef enum {
|
||||
SDMMC_CAR_DIVIDER_SDR12 = 31, // (16.5 * 2) - 2
|
||||
SDMMC_CAR_DIVIDER_SDR25 = 15, // (8.5 * 2) - 2
|
||||
SDMMC_CAR_DIVIDER_SDR50 = 7, // (4.5 * 2) - 2
|
||||
SDMMC_CAR_DIVIDER_SDR104 = 2, // (2 * 2) - 2
|
||||
SDMMC_CAR_DIVIDER_DDR50 = 18, // (5 * 2 * 2) - 2
|
||||
SDMMC_CAR_DIVIDER_HS26 = 30, // (16 * 2) - 2
|
||||
SDMMC_CAR_DIVIDER_HS52 = 14, // (8 * 2) - 2
|
||||
SDMMC_CAR_DIVIDER_HS200 = 3, // (2.5 * 2) - 2 (for PLLP_OUT0)
|
||||
SDMMC_CAR_DIVIDER_HS400 = 3, // (2.5 * 2) - 2 (for PLLP_OUT0)
|
||||
} SdmmcCarDivider;
|
||||
|
||||
/* Structure for describing a SDMMC device. */
|
||||
typedef struct {
|
||||
/* Controller number */
|
||||
SdmmcControllerNum controller;
|
||||
|
||||
/* Backing register space */
|
||||
volatile tegra_sdmmc_t *regs;
|
||||
|
||||
/* Controller properties */
|
||||
const char *name;
|
||||
bool has_sd;
|
||||
bool is_clk_running;
|
||||
bool is_sd_clk_enabled;
|
||||
bool is_tuning_tap_val_set;
|
||||
bool use_adma;
|
||||
uint32_t tap_val;
|
||||
uint32_t internal_divider;
|
||||
uint32_t resp[4];
|
||||
uint32_t resp_auto_cmd12;
|
||||
uint32_t next_dma_addr;
|
||||
uint8_t* dma_bounce_buf;
|
||||
SdmmcBusVoltage bus_voltage;
|
||||
SdmmcBusWidth bus_width;
|
||||
|
||||
/* Per-controller operations. */
|
||||
int (*sdmmc_config)();
|
||||
} sdmmc_t;
|
||||
|
||||
/* Structure for describing a SDMMC command. */
|
||||
typedef struct {
|
||||
uint32_t opcode;
|
||||
uint32_t arg;
|
||||
uint32_t resp[4];
|
||||
uint32_t flags; /* expected response type */
|
||||
} sdmmc_command_t;
|
||||
|
||||
/* Structure for describing a SDMMC request. */
|
||||
typedef struct {
|
||||
void* data;
|
||||
uint32_t blksz;
|
||||
uint32_t num_blocks;
|
||||
bool is_multi_block;
|
||||
bool is_read;
|
||||
bool is_auto_cmd12;
|
||||
} sdmmc_request_t;
|
||||
|
||||
int sdmmc_init(sdmmc_t *sdmmc, SdmmcControllerNum controller, SdmmcBusVoltage bus_voltage, SdmmcBusWidth bus_width, SdmmcBusSpeed bus_speed);
|
||||
void sdmmc_finish(sdmmc_t *sdmmc);
|
||||
int sdmmc_select_speed(sdmmc_t *sdmmc, SdmmcBusSpeed bus_speed);
|
||||
void sdmmc_select_bus_width(sdmmc_t *sdmmc, SdmmcBusWidth width);
|
||||
void sdmmc_select_voltage(sdmmc_t *sdmmc, SdmmcBusVoltage voltage);
|
||||
void sdmmc_adjust_sd_clock(sdmmc_t *sdmmc);
|
||||
int sdmmc_switch_voltage(sdmmc_t *sdmmc);
|
||||
void sdmmc_set_tuning_tap_val(sdmmc_t *sdmmc);
|
||||
int sdmmc_execute_tuning(sdmmc_t *sdmmc, SdmmcBusSpeed bus_speed, uint32_t opcode);
|
||||
int sdmmc_send_cmd(sdmmc_t *sdmmc, sdmmc_command_t *cmd, sdmmc_request_t *req, uint32_t *num_blocks_out);
|
||||
int sdmmc_load_response(sdmmc_t *sdmmc, uint32_t flags, uint32_t *resp);
|
||||
int sdmmc_abort(sdmmc_t *sdmmc, uint32_t opcode);
|
||||
void sdmmc_error(sdmmc_t *sdmmc, char *fmt, ...);
|
||||
void sdmmc_warn(sdmmc_t *sdmmc, char *fmt, ...);
|
||||
void sdmmc_info(sdmmc_t *sdmmc, char *fmt, ...);
|
||||
void sdmmc_debug(sdmmc_t *sdmmc, char *fmt, ...);
|
||||
void sdmmc_dump_regs(sdmmc_t *sdmmc);
|
||||
|
||||
#endif
|
||||
172
sept/sept-secondary/src/sdmmc/sdmmc_tegra.h
Normal file
172
sept/sept-secondary/src/sdmmc/sdmmc_tegra.h
Normal file
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 CTCaer
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_SDMMC_TEGRA_H
|
||||
#define FUSEE_SDMMC_TEGRA_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0)
|
||||
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1)
|
||||
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1)
|
||||
#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1)
|
||||
|
||||
#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
|
||||
#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
|
||||
#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
|
||||
#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
|
||||
|
||||
#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
|
||||
#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
|
||||
#define TEGRA_MMC_TRNMOD_AUTO_CMD12 (1 << 2)
|
||||
#define TEGRA_MMC_TRNMOD_AUTO_CMD23 (1 << 3)
|
||||
#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
|
||||
#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
|
||||
#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
|
||||
|
||||
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
|
||||
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
|
||||
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
|
||||
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
|
||||
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
|
||||
|
||||
#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
|
||||
#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
|
||||
#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
|
||||
|
||||
#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
|
||||
#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
|
||||
|
||||
#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
|
||||
#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
|
||||
#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
|
||||
#define TEGRA_MMC_CLKCON_PROG_CLOCK_MODE (1 << 5)
|
||||
|
||||
#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
|
||||
#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
|
||||
|
||||
#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
|
||||
#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
|
||||
#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
|
||||
|
||||
#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
|
||||
#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
|
||||
#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
|
||||
#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
|
||||
#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
|
||||
|
||||
#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
|
||||
#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
|
||||
#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
|
||||
#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
|
||||
#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
|
||||
|
||||
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
|
||||
|
||||
typedef struct {
|
||||
/* SDHCI standard registers */
|
||||
uint32_t dma_address;
|
||||
uint16_t block_size;
|
||||
uint16_t block_count;
|
||||
uint32_t argument;
|
||||
uint16_t transfer_mode;
|
||||
uint16_t command;
|
||||
uint32_t response[0x4];
|
||||
uint32_t buffer;
|
||||
uint32_t present_state;
|
||||
uint8_t host_control;
|
||||
uint8_t power_control;
|
||||
uint8_t block_gap_control;
|
||||
uint8_t wake_up_control;
|
||||
uint16_t clock_control;
|
||||
uint8_t timeout_control;
|
||||
uint8_t software_reset;
|
||||
uint32_t int_status;
|
||||
uint32_t int_enable;
|
||||
uint32_t signal_enable;
|
||||
uint16_t acmd12_err;
|
||||
uint16_t host_control2;
|
||||
uint32_t capabilities;
|
||||
uint32_t capabilities_1;
|
||||
uint32_t max_current;
|
||||
uint32_t _0x4c;
|
||||
uint16_t set_acmd12_error;
|
||||
uint16_t set_int_error;
|
||||
uint8_t adma_error;
|
||||
uint8_t _0x56[0x3];
|
||||
uint32_t adma_address;
|
||||
uint32_t upper_adma_address;
|
||||
uint16_t preset_for_init;
|
||||
uint16_t preset_for_default;
|
||||
uint16_t preset_for_high;
|
||||
uint16_t preset_for_sdr12;
|
||||
uint16_t preset_for_sdr25;
|
||||
uint16_t preset_for_sdr50;
|
||||
uint16_t preset_for_sdr104;
|
||||
uint16_t preset_for_ddr50;
|
||||
uint32_t _0x70[0x23];
|
||||
uint16_t slot_int_status;
|
||||
uint16_t host_version;
|
||||
|
||||
/* Vendor specific registers */
|
||||
uint32_t vendor_clock_cntrl;
|
||||
uint32_t vendor_sys_sw_cntrl;
|
||||
uint32_t vendor_err_intr_status;
|
||||
uint32_t vendor_cap_overrides;
|
||||
uint32_t vendor_boot_cntrl;
|
||||
uint32_t vendor_boot_ack_timeout;
|
||||
uint32_t vendor_boot_dat_timeout;
|
||||
uint32_t vendor_debounce_count;
|
||||
uint32_t vendor_misc_cntrl;
|
||||
uint32_t max_current_override;
|
||||
uint32_t max_current_override_hi;
|
||||
uint32_t _0x12c[0x20];
|
||||
uint32_t vendor_io_trim_cntrl;
|
||||
|
||||
/* Start of sdmmc2/sdmmc4 only */
|
||||
uint32_t vendor_dllcal_cfg;
|
||||
uint32_t vendor_dll_ctrl0;
|
||||
uint32_t vendor_dll_ctrl1;
|
||||
uint32_t vendor_dllcal_cfg_sta;
|
||||
/* End of sdmmc2/sdmmc4 only */
|
||||
|
||||
uint32_t vendor_tuning_cntrl0;
|
||||
uint32_t vendor_tuning_cntrl1;
|
||||
uint32_t vendor_tuning_status0;
|
||||
uint32_t vendor_tuning_status1;
|
||||
uint32_t vendor_clk_gate_hysteresis_count;
|
||||
uint32_t vendor_preset_val0;
|
||||
uint32_t vendor_preset_val1;
|
||||
uint32_t vendor_preset_val2;
|
||||
uint32_t sdmemcomppadctrl;
|
||||
uint32_t auto_cal_config;
|
||||
uint32_t auto_cal_interval;
|
||||
uint32_t auto_cal_status;
|
||||
uint32_t io_spare;
|
||||
uint32_t sdmmca_mccif_fifoctrl;
|
||||
uint32_t timeout_wcoal_sdmmca;
|
||||
uint32_t _0x1fc;
|
||||
} tegra_sdmmc_t;
|
||||
|
||||
static inline volatile tegra_sdmmc_t *sdmmc_get_regs(uint32_t idx)
|
||||
{
|
||||
return (volatile tegra_sdmmc_t *)(0x700B0000 + (idx * 0x200));
|
||||
}
|
||||
|
||||
#endif
|
||||
578
sept/sept-secondary/src/sdram.c
Normal file
578
sept/sept-secondary/src/sdram.c
Normal file
|
|
@ -0,0 +1,578 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "i2c.h"
|
||||
#include "mc.h"
|
||||
#include "emc.h"
|
||||
#include "pmc.h"
|
||||
#include "timers.h"
|
||||
#include "sysreg.h"
|
||||
#include "fuse.h"
|
||||
#include "max77620.h"
|
||||
#include "sdram_param_t210.h"
|
||||
#include "car.h"
|
||||
|
||||
#define CONFIG_SDRAM_COMPRESS_CFG
|
||||
|
||||
#ifdef CONFIG_SDRAM_COMPRESS_CFG
|
||||
#include "lib/lz.h"
|
||||
#include "sdram_lz.inl"
|
||||
#else
|
||||
#include "sdram.inl"
|
||||
#endif
|
||||
|
||||
static uint32_t _get_sdram_id()
|
||||
{
|
||||
return ((fuse_get_reserved_odm(4) & 0x38) >> 3);
|
||||
}
|
||||
|
||||
static void _sdram_config(const sdram_params_t *params)
|
||||
{
|
||||
volatile tegra_car_t *car = car_get_regs();
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
|
||||
pmc->io_dpd3_req = (((4 * params->emc_pmc_scratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF;
|
||||
udelay(params->pmc_io_dpd3_req_wait);
|
||||
|
||||
uint32_t req = (4 * params->emc_pmc_scratch2 >> 2) + 0x80000000;
|
||||
pmc->io_dpd4_req = (req >> 16 << 16) ^ 0x3FFF0000;
|
||||
|
||||
udelay(params->pmc_io_dpd4_req_wait);
|
||||
pmc->io_dpd4_req = (req ^ 0xFFFF) & 0xC000FFFF;
|
||||
udelay(params->pmc_io_dpd4_req_wait);
|
||||
|
||||
pmc->weak_bias = 0;
|
||||
udelay(1);
|
||||
|
||||
car->pllm_misc1 = params->pllm_setup_control;
|
||||
car->pllm_misc2 = 0;
|
||||
car->pllm_base = ((params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20));
|
||||
|
||||
bool timeout = false;
|
||||
uint32_t wait_end = get_time_us() + 300;
|
||||
|
||||
while (!(car->pllm_base & 0x8000000) && !timeout)
|
||||
{
|
||||
if (get_time_us() >= wait_end)
|
||||
timeout = true;
|
||||
}
|
||||
|
||||
if (!timeout) {
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
car->clk_source_emc = (((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF));
|
||||
|
||||
if (params->emc_clock_source_dll)
|
||||
car->clk_source_emc_dll = params->emc_clock_source_dll;
|
||||
|
||||
if (params->clear_clock2_mc1)
|
||||
car->clk_enb_w_clr = 0x40000000;
|
||||
|
||||
car->clk_enb_h_set = 0x2000001;
|
||||
car->clk_enb_x_set = 0x4000;
|
||||
car->rst_dev_h_clr = 0x2000001;
|
||||
|
||||
MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_0) = params->emc_pmacro_vttgen_ctrl0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_1) = params->emc_pmacro_vttgen_ctrl1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_2) = params->emc_pmacro_vttgen_ctrl2;
|
||||
MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1;
|
||||
udelay(1);
|
||||
|
||||
MAKE_EMC_REG(EMC_DBG) = (params->emc_dbg_write_mux << 1) | params->emc_dbg;
|
||||
|
||||
if (params->emc_bct_spare2)
|
||||
*(volatile uint32_t *)params->emc_bct_spare2 = params->emc_bct_spare3;
|
||||
|
||||
MAKE_EMC_REG(EMC_FBIO_CFG7) = params->emc_fbio_cfg7;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_0) = params->emc_cmd_mapping_cmd1_0;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_1) = params->emc_cmd_mapping_cmd1_1;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_2) = params->emc_cmd_mapping_cmd1_2;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_0) = params->emc_cmd_mapping_cmd2_0;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_1) = params->emc_cmd_mapping_cmd2_1;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_2) = params->emc_cmd_mapping_cmd2_2;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2;
|
||||
MAKE_EMC_REG(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte;
|
||||
MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_1) = params->emc_pmacro_brick_mapping1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_2) = params->emc_pmacro_brick_mapping2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->emc_pmacro_brick_ctrl_rfu1 & 0x1120112) | 0x1EED1EED);
|
||||
MAKE_EMC_REG(EMC_CONFIG_SAMPLE_DELAY) = params->emc_config_sample_delay;
|
||||
MAKE_EMC_REG(EMC_FBIO_CFG8) = params->emc_fbio_cfg8;
|
||||
MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE0) = params->emc_swizzle_rank0_byte0;
|
||||
MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE1) = params->emc_swizzle_rank0_byte1;
|
||||
MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE2) = params->emc_swizzle_rank0_byte2;
|
||||
MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE3) = params->emc_swizzle_rank0_byte3;
|
||||
MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE0) = params->emc_swizzle_rank1_byte0;
|
||||
MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE1) = params->emc_swizzle_rank1_byte1;
|
||||
MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE2) = params->emc_swizzle_rank1_byte2;
|
||||
MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE3) = params->emc_swizzle_rank1_byte3;
|
||||
|
||||
if (params->emc_bct_spare6)
|
||||
*(volatile uint32_t *)params->emc_bct_spare6 = params->emc_bct_spare7;
|
||||
|
||||
MAKE_EMC_REG(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl;
|
||||
MAKE_EMC_REG(EMC_XM2COMPPADCTRL2) = params->emc_xm2_comp_pad_ctrl2;
|
||||
MAKE_EMC_REG(EMC_XM2COMPPADCTRL3) = params->emc_xm2_comp_pad_ctrl3;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG2) = params->emc_auto_cal_config2;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG3) = params->emc_auto_cal_config3;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG4) = params->emc_auto_cal_config4;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG5) = params->emc_auto_cal_config5;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG6) = params->emc_auto_cal_config6;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8;
|
||||
MAKE_EMC_REG(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive;
|
||||
MAKE_EMC_REG(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive;
|
||||
MAKE_EMC_REG(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive;
|
||||
MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel;
|
||||
MAKE_EMC_REG(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl;
|
||||
MAKE_EMC_REG(EMC_DLL_CFG_0) = params->emc_dll_cfg0;
|
||||
MAKE_EMC_REG(EMC_DLL_CFG_1) = params->emc_dll_cfg1;
|
||||
MAKE_EMC_REG(EMC_CFG_DIG_DLL_1) = params->emc_cfg_dig_dll_1;
|
||||
MAKE_EMC_REG(EMC_DATA_BRLSHFT_0) = params->emc_data_brlshft0;
|
||||
MAKE_EMC_REG(EMC_DATA_BRLSHFT_1) = params->emc_data_brlshft1;
|
||||
MAKE_EMC_REG(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0;
|
||||
MAKE_EMC_REG(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1;
|
||||
MAKE_EMC_REG(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0;
|
||||
MAKE_EMC_REG(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1;
|
||||
MAKE_EMC_REG(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2;
|
||||
MAKE_EMC_REG(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3;
|
||||
MAKE_EMC_REG(EMC_QUSE_BRLSHFT_0) = params->emc_quse_brlshft0;
|
||||
MAKE_EMC_REG(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1;
|
||||
MAKE_EMC_REG(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2;
|
||||
MAKE_EMC_REG(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->emc_pmacro_brick_ctrl_rfu1 & 0x1BF01BF) | 0x1E401E40);
|
||||
MAKE_EMC_REG(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl;
|
||||
MAKE_EMC_REG(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd;
|
||||
MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = (params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F);
|
||||
MAKE_EMC_REG(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd;
|
||||
MAKE_EMC_REG(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl;
|
||||
MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode;
|
||||
MAKE_EMC_REG(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode;
|
||||
MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl;
|
||||
MAKE_EMC_REG(EMC_CFG_3) = params->emc_cfg3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->emc_pmacro_tx_sel_clk_src0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->emc_pmacro_tx_sel_clk_src1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->emc_pmacro_tx_sel_clk_src2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->emc_pmacro_tx_sel_clk_src3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->emc_pmacro_tx_sel_clk_src4;
|
||||
MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->emc_pmacro_tx_sel_clk_src5;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->emc_pmacro_quse_ddll_rank0_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->emc_pmacro_quse_ddll_rank0_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->emc_pmacro_quse_ddll_rank0_2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->emc_pmacro_quse_ddll_rank0_3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->emc_pmacro_quse_ddll_rank0_4;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->emc_pmacro_quse_ddll_rank0_5;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->emc_pmacro_quse_ddll_rank1_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->emc_pmacro_quse_ddll_rank1_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->emc_pmacro_quse_ddll_rank1_2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->emc_pmacro_quse_ddll_rank1_3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->emc_pmacro_quse_ddll_rank1_4;
|
||||
MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->emc_pmacro_quse_ddll_rank1_5;
|
||||
MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->emc_pmacro_ob_ddll_long_dq_rank0_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->emc_pmacro_ob_ddll_long_dq_rank0_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->emc_pmacro_ob_ddll_long_dq_rank0_2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->emc_pmacro_ob_ddll_long_dq_rank0_3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->emc_pmacro_ob_ddll_long_dq_rank0_4;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->emc_pmacro_ob_ddll_long_dq_rank0_5;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->emc_pmacro_ob_ddll_long_dq_rank1_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->emc_pmacro_ob_ddll_long_dq_rank1_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->emc_pmacro_ob_ddll_long_dq_rank1_2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->emc_pmacro_ob_ddll_long_dq_rank1_3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->emc_pmacro_ob_ddll_long_dq_rank1_4;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->emc_pmacro_ob_ddll_long_dq_rank1_5;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ob_ddll_long_dqs_rank0_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ob_ddll_long_dqs_rank0_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ob_ddll_long_dqs_rank0_2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ob_ddll_long_dqs_rank0_3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->emc_pmacro_ob_ddll_long_dqs_rank0_4;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->emc_pmacro_ob_ddll_long_dqs_rank0_5;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ob_ddll_long_dqs_rank1_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ob_ddll_long_dqs_rank1_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ob_ddll_long_dqs_rank1_2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ob_ddll_long_dqs_rank1_3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->emc_pmacro_ob_ddll_long_dqs_rank1_4;
|
||||
MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->emc_pmacro_ob_ddll_long_dqs_rank1_5;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ib_ddll_long_dqs_rank0_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ib_ddll_long_dqs_rank0_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ib_ddll_long_dqs_rank0_2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ib_ddll_long_dqs_rank0_3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ib_ddll_long_dqs_rank1_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ib_ddll_long_dqs_rank1_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ib_ddll_long_dqs_rank1_2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ib_ddll_long_dqs_rank1_3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2;
|
||||
MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = ((params->emc_pmacro_common_pad_tx_ctrl & 1) | 0xE);
|
||||
|
||||
if (params->emc_bct_spare4)
|
||||
*(volatile uint32_t *)params->emc_bct_spare4 = params->emc_bct_spare5;
|
||||
|
||||
MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1;
|
||||
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->mc_video_protect_gpu_override0;
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->mc_video_protect_gpu_override1;
|
||||
MAKE_MC_REG(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg;
|
||||
MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0;
|
||||
MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1;
|
||||
MAKE_MC_REG(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->mc_emem_adr_cfg_channel_mask;
|
||||
MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->mc_emem_adr_cfg_bank_mask0;
|
||||
MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->mc_emem_adr_cfg_bank_mask1;
|
||||
MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->mc_emem_adr_cfg_bank_mask2;
|
||||
MAKE_MC_REG(MC_EMEM_CFG) = params->mc_emem_cfg;
|
||||
MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom;
|
||||
MAKE_MC_REG(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi;
|
||||
MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = params->mc_sec_carveout_size_mb;
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom;
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi;
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = params->mc_mts_carveout_size_mb;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_OUTSTANDING_REQ) = params->mc_emem_arb_outstanding_req;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->emc_emem_arb_refpb_bank_ctrl;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1;
|
||||
MAKE_MC_REG(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv;
|
||||
MAKE_MC_REG(MC_DA_CONFIG0) = params->mc_da_cfg0;
|
||||
MAKE_MC_REG(MC_TIMING_CONTROL) = 1;
|
||||
MAKE_MC_REG(MC_CLKEN_OVERRIDE) = params->mc_clken_override;
|
||||
MAKE_MC_REG(MC_STAT_CONTROL) = params->mc_stat_control;
|
||||
|
||||
MAKE_EMC_REG(EMC_ADR_CFG) = params->emc_adr_cfg;
|
||||
MAKE_EMC_REG(EMC_CLKEN_OVERRIDE) = params->emc_clken_override;
|
||||
MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_0) = params->emc_pmacro_auto_cal_cfg0;
|
||||
MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_1) = params->emc_pmacro_auto_cal_cfg1;
|
||||
MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_2) = params->emc_pmacro_auto_cal_cfg2;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_0) = params->emc_auto_cal_vref_sel0;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval;
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config;
|
||||
udelay(params->emc_auto_cal_wait);
|
||||
|
||||
if (params->emc_bct_spare8)
|
||||
*(volatile uint32_t *)params->emc_bct_spare8 = params->emc_bct_spare9;
|
||||
|
||||
MAKE_EMC_REG(EMC_CFG_2) = params->emc_cfg2;
|
||||
MAKE_EMC_REG(EMC_CFG_PIPE) = params->emc_cfg_pipe;
|
||||
MAKE_EMC_REG(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1;
|
||||
MAKE_EMC_REG(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2;
|
||||
MAKE_EMC_REG(EMC_CMDQ) = params->emc_cmd_q;
|
||||
MAKE_EMC_REG(EMC_MC2EMCQ) = params->emc_mc2emc_q;
|
||||
MAKE_EMC_REG(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt;
|
||||
MAKE_EMC_REG(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2;
|
||||
MAKE_EMC_REG(EMC_FBIO_CFG5) = params->emc_fbio_cfg5;
|
||||
MAKE_EMC_REG(EMC_RC) = params->emc_rc;
|
||||
MAKE_EMC_REG(EMC_RFC) = params->emc_rfc;
|
||||
MAKE_EMC_REG(EMC_RFCPB) = params->emc_rfc_pb;
|
||||
MAKE_EMC_REG(EMC_REFCTRL2) = params->emc_ref_ctrl2;
|
||||
MAKE_EMC_REG(EMC_RFC_SLR) = params->emc_rfc_slr;
|
||||
MAKE_EMC_REG(EMC_RAS) = params->emc_ras;
|
||||
MAKE_EMC_REG(EMC_RP) = params->emc_rp;
|
||||
MAKE_EMC_REG(EMC_TPPD) = params->emc_tppd;
|
||||
MAKE_EMC_REG(EMC_R2R) = params->emc_r2r;
|
||||
MAKE_EMC_REG(EMC_W2W) = params->emc_w2w;
|
||||
MAKE_EMC_REG(EMC_R2W) = params->emc_r2w;
|
||||
MAKE_EMC_REG(EMC_W2R) = params->emc_w2r;
|
||||
MAKE_EMC_REG(EMC_R2P) = params->emc_r2p;
|
||||
MAKE_EMC_REG(EMC_W2P) = params->emc_w2p;
|
||||
MAKE_EMC_REG(EMC_CCDMW) = params->emc_ccdmw;
|
||||
MAKE_EMC_REG(EMC_RD_RCD) = params->emc_rd_rcd;
|
||||
MAKE_EMC_REG(EMC_WR_RCD) = params->emc_wr_rcd;
|
||||
MAKE_EMC_REG(EMC_RRD) = params->emc_rrd;
|
||||
MAKE_EMC_REG(EMC_REXT) = params->emc_rext;
|
||||
MAKE_EMC_REG(EMC_WEXT) = params->emc_wext;
|
||||
MAKE_EMC_REG(EMC_WDV) = params->emc_wdv;
|
||||
MAKE_EMC_REG(EMC_WDV_CHK) = params->emc_wdv_chk;
|
||||
MAKE_EMC_REG(EMC_WSV) = params->emc_wsv;
|
||||
MAKE_EMC_REG(EMC_WEV) = params->emc_wev;
|
||||
MAKE_EMC_REG(EMC_WDV_MASK) = params->emc_wdv_mask;
|
||||
MAKE_EMC_REG(EMC_WS_DURATION) = params->emc_ws_duration;
|
||||
MAKE_EMC_REG(EMC_WE_DURATION) = params->emc_we_duration;
|
||||
MAKE_EMC_REG(EMC_QUSE) = params->emc_quse;
|
||||
MAKE_EMC_REG(EMC_QUSE_WIDTH) = params->emc_quse_width;
|
||||
MAKE_EMC_REG(EMC_IBDLY) = params->emc_ibdly;
|
||||
MAKE_EMC_REG(EMC_OBDLY) = params->emc_obdly;
|
||||
MAKE_EMC_REG(EMC_EINPUT) = params->emc_einput;
|
||||
MAKE_EMC_REG(EMC_EINPUT_DURATION) = params->emc_einput_duration;
|
||||
MAKE_EMC_REG(EMC_PUTERM_EXTRA) = params->emc_puterm_extra;
|
||||
MAKE_EMC_REG(EMC_PUTERM_WIDTH) = params->emc_puterm_width;
|
||||
MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->emc_pmacro_common_pad_tx_ctrl;
|
||||
MAKE_EMC_REG(EMC_DBG) = params->emc_dbg;
|
||||
MAKE_EMC_REG(EMC_QRST) = params->emc_qrst;
|
||||
MAKE_EMC_REG(EMC_ISSUE_QRST) = 0;
|
||||
MAKE_EMC_REG(EMC_QSAFE) = params->emc_qsafe;
|
||||
MAKE_EMC_REG(EMC_RDV) = params->emc_rdv;
|
||||
MAKE_EMC_REG(EMC_RDV_MASK) = params->emc_rdv_mask;
|
||||
MAKE_EMC_REG(EMC_RDV_EARLY) = params->emc_rdv_early;
|
||||
MAKE_EMC_REG(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask;
|
||||
MAKE_EMC_REG(EMC_QPOP) = params->emc_qpop;
|
||||
MAKE_EMC_REG(EMC_REFRESH) = params->emc_refresh;
|
||||
MAKE_EMC_REG(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num;
|
||||
MAKE_EMC_REG(EMC_PRE_REFRESH_REQ_CNT) = params->emc_prerefresh_req_cnt;
|
||||
MAKE_EMC_REG(EMC_PDEX2WR) = params->emc_pdex2wr;
|
||||
MAKE_EMC_REG(EMC_PDEX2RD) = params->emc_pdex2rd;
|
||||
MAKE_EMC_REG(EMC_PCHG2PDEN) = params->emc_pchg2pden;
|
||||
MAKE_EMC_REG(EMC_ACT2PDEN) = params->emc_act2pden;
|
||||
MAKE_EMC_REG(EMC_AR2PDEN) = params->emc_ar2pden;
|
||||
MAKE_EMC_REG(EMC_RW2PDEN) = params->emc_rw2pden;
|
||||
MAKE_EMC_REG(EMC_CKE2PDEN) = params->emc_cke2pden;
|
||||
MAKE_EMC_REG(EMC_PDEX2CKE) = params->emc_pdex2che;
|
||||
MAKE_EMC_REG(EMC_PDEX2MRR) = params->emc_pdex2mrr;
|
||||
MAKE_EMC_REG(EMC_TXSR) = params->emc_txsr;
|
||||
MAKE_EMC_REG(EMC_TXSRDLL) = params->emc_txsr_dll;
|
||||
MAKE_EMC_REG(EMC_TCKE) = params->emc_tcke;
|
||||
MAKE_EMC_REG(EMC_TCKESR) = params->emc_tckesr;
|
||||
MAKE_EMC_REG(EMC_TPD) = params->emc_tpd;
|
||||
MAKE_EMC_REG(EMC_TFAW) = params->emc_tfaw;
|
||||
MAKE_EMC_REG(EMC_TRPAB) = params->emc_trpab;
|
||||
MAKE_EMC_REG(EMC_TCLKSTABLE) = params->emc_tclkstable;
|
||||
MAKE_EMC_REG(EMC_TCLKSTOP) = params->emc_tclkstop;
|
||||
MAKE_EMC_REG(EMC_TREFBW) = params->emc_trefbw;
|
||||
MAKE_EMC_REG(EMC_ODT_WRITE) = params->emc_odt_write;
|
||||
MAKE_EMC_REG(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll;
|
||||
MAKE_EMC_REG(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period;
|
||||
MAKE_EMC_REG(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD;
|
||||
MAKE_EMC_REG(EMC_CFG_RSV) = params->emc_cfg_rsv;
|
||||
MAKE_EMC_REG(EMC_PMC_SCRATCH1) = params->emc_pmc_scratch1;
|
||||
MAKE_EMC_REG(EMC_PMC_SCRATCH2) = params->emc_pmc_scratch2;
|
||||
MAKE_EMC_REG(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3;
|
||||
MAKE_EMC_REG(EMC_ACPD_CONTROL) = params->emc_acpd_control;
|
||||
MAKE_EMC_REG(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen;
|
||||
MAKE_EMC_REG(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000;
|
||||
|
||||
if (params->boot_rom_patch_control & 0x80000000)
|
||||
{
|
||||
*(volatile uint32_t *)(4 * (params->boot_rom_patch_control + 0x1C000000)) = params->boot_rom_patch_data;
|
||||
MAKE_MC_REG(MC_TIMING_CONTROL) = 1;
|
||||
}
|
||||
|
||||
pmc->io_dpd3_req = (((4 * params->emc_pmc_scratch1 >> 2) + 0x40000000) & 0xCFFF0000);
|
||||
udelay(params->pmc_io_dpd3_req_wait);
|
||||
|
||||
if (!params->emc_auto_cal_interval)
|
||||
MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = (params->emc_auto_cal_config | 0x200);
|
||||
|
||||
MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2;
|
||||
|
||||
if (params->emc_zcal_warm_cold_boot_enables & 1)
|
||||
{
|
||||
if (params->memory_type == 2)
|
||||
MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = (8 * params->emc_zcal_wait_cnt);
|
||||
|
||||
if (params->memory_type == 3)
|
||||
{
|
||||
MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt;
|
||||
MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd;
|
||||
}
|
||||
}
|
||||
|
||||
MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1;
|
||||
udelay(params->emc_timing_control_wait);
|
||||
|
||||
pmc->ddr_cntrl &= 0xFFF8007F;
|
||||
udelay(params->pmc_ddr_ctrl_wait);
|
||||
|
||||
if (params->memory_type == 2)
|
||||
{
|
||||
MAKE_EMC_REG(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12));
|
||||
udelay(params->emc_pin_extra_wait + 200);
|
||||
MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256);
|
||||
udelay(params->emc_pin_extra_wait + 500);
|
||||
}
|
||||
|
||||
if (params->memory_type == 3)
|
||||
{
|
||||
MAKE_EMC_REG(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12));
|
||||
udelay(params->emc_pin_extra_wait + 200);
|
||||
MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256);
|
||||
udelay(params->emc_pin_extra_wait + 2000);
|
||||
}
|
||||
|
||||
MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 0x101);
|
||||
udelay(params->emc_pin_program_wait);
|
||||
|
||||
if (params->memory_type != 3)
|
||||
MAKE_EMC_REG(EMC_NOP) = ((params->emc_dev_select << 30) + 1);
|
||||
|
||||
if (params->memory_type == 1)
|
||||
udelay(params->emc_pin_extra_wait + 200);
|
||||
|
||||
if (params->memory_type == 3)
|
||||
{
|
||||
if (params->emc_bct_spare10)
|
||||
*(volatile uint32_t *)params->emc_bct_spare10 = params->emc_bct_spare11;
|
||||
|
||||
MAKE_EMC_REG(EMC_MRW2) = params->emc_mrw2;
|
||||
MAKE_EMC_REG(EMC_MRW) = params->emc_mrw1;
|
||||
MAKE_EMC_REG(EMC_MRW3) = params->emc_mrw3;
|
||||
MAKE_EMC_REG(EMC_MRW4) = params->emc_mrw4;
|
||||
MAKE_EMC_REG(EMC_MRW6) = params->emc_mrw6;
|
||||
MAKE_EMC_REG(EMC_MRW14) = params->emc_mrw14;
|
||||
MAKE_EMC_REG(EMC_MRW8) = params->emc_mrw8;
|
||||
MAKE_EMC_REG(EMC_MRW12) = params->emc_mrw12;
|
||||
MAKE_EMC_REG(EMC_MRW9) = params->emc_mrw9;
|
||||
MAKE_EMC_REG(EMC_MRW13) = params->emc_mrw13;
|
||||
|
||||
if (params->emc_zcal_warm_cold_boot_enables & 1)
|
||||
{
|
||||
MAKE_EMC_REG(EMC_ZQ_CAL) = params->emc_zcal_init_dev0;
|
||||
udelay(params->emc_zcal_init_wait);
|
||||
MAKE_EMC_REG(EMC_ZQ_CAL) = (params->emc_zcal_init_dev0 ^ 3);
|
||||
|
||||
if (!(params->emc_dev_select & 2))
|
||||
{
|
||||
MAKE_EMC_REG(EMC_ZQ_CAL) = params->emc_zcal_init_dev1;
|
||||
udelay(params->emc_zcal_init_wait);
|
||||
MAKE_EMC_REG(EMC_ZQ_CAL) = (params->emc_zcal_init_dev1 ^ 3);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pmc->ddr_cfg = params->pmc_ddr_cfg;
|
||||
if ((params->memory_type - 1) <= 2)
|
||||
{
|
||||
MAKE_EMC_REG(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval;
|
||||
MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt;
|
||||
MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd;
|
||||
}
|
||||
|
||||
if (params->emc_bct_spare12)
|
||||
*(volatile uint32_t *)params->emc_bct_spare12 = params->emc_bct_spare13;
|
||||
|
||||
MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1;
|
||||
|
||||
if (params->emc_extra_refresh_num)
|
||||
MAKE_EMC_REG(EMC_REF) = (((1 << params->emc_extra_refresh_num << 8) - 0xFD) | (params->emc_pin_gpio << 30));
|
||||
|
||||
MAKE_EMC_REG(EMC_REFCTRL) = (params->emc_dev_select | 0x80000000);
|
||||
MAKE_EMC_REG(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control;
|
||||
MAKE_EMC_REG(EMC_CFG_UPDATE) = params->emc_cfg_update;
|
||||
MAKE_EMC_REG(EMC_CFG) = params->emc_cfg;
|
||||
MAKE_EMC_REG(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq;
|
||||
MAKE_EMC_REG(EMC_FDPD_CTRL_CMD) = params->emc_fdpd_ctrl_cmd;
|
||||
MAKE_EMC_REG(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl;
|
||||
MAKE_EMC_REG(EMC_FBIO_SPARE) = (params->emc_fbio_spare | 2);
|
||||
MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1;
|
||||
MAKE_EMC_REG(EMC_CFG_PIPE_CLK) = params->emc_cfg_pipe_clk;
|
||||
MAKE_EMC_REG(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->emc_fdpd_ctrl_cmd_no_ramp;
|
||||
|
||||
AHB_ARBITRATION_XBAR_CTRL_0 = ((AHB_ARBITRATION_XBAR_CTRL_0 & 0xFFFEFFFF) | ((params->ahb_arbitration_xbar_ctrl_meminit_done & 0xFFFF) << 16));
|
||||
|
||||
MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access;
|
||||
MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access;
|
||||
MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl;
|
||||
MAKE_MC_REG(MC_EMEM_CFG_ACCESS_CTRL) = 1; /* Disable write access to a bunch of MC registers. */
|
||||
}
|
||||
|
||||
const void *sdram_get_params()
|
||||
{
|
||||
/* TODO: sdram_id should be in [0, 7]. */
|
||||
|
||||
#ifdef CONFIG_SDRAM_COMPRESS_CFG
|
||||
uint8_t *buf = (uint8_t *)0x40030000;
|
||||
LZ_Uncompress(_dram_cfg_lz, buf, sizeof(_dram_cfg_lz));
|
||||
return (const void *)&buf[sizeof(sdram_params_t) * _get_sdram_id()];
|
||||
#else
|
||||
return _dram_cfgs[_get_sdram_id()];
|
||||
#endif
|
||||
}
|
||||
|
||||
void sdram_init()
|
||||
{
|
||||
volatile tegra_pmc_t *pmc = pmc_get_regs();
|
||||
|
||||
/* TODO: sdram_id should be in [0,4]. */
|
||||
const sdram_params_t *params = (const sdram_params_t *)sdram_get_params();
|
||||
|
||||
uint8_t val = 5;
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1);
|
||||
val = 40; /* 40 = (1000 * 1100 - 600000) / 12500 -> 1.1V */
|
||||
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD1, &val, 1);
|
||||
|
||||
pmc->vddp_sel = params->pmc_vddp_sel;
|
||||
udelay(params->pmc_vddp_sel_wait);
|
||||
|
||||
pmc->ddr_pwr = pmc->ddr_pwr;
|
||||
pmc->no_iopower = params->pmc_no_io_power;
|
||||
pmc->reg_short = params->pmc_reg_short;
|
||||
pmc->ddr_cntrl = params->pmc_ddr_ctrl;
|
||||
|
||||
if (params->emc_bct_spare0)
|
||||
*(volatile uint32_t *)params->emc_bct_spare0 = params->emc_bct_spare1;
|
||||
|
||||
_sdram_config(params);
|
||||
}
|
||||
25
sept/sept-secondary/src/sdram.h
Normal file
25
sept/sept-secondary/src/sdram.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_SDRAM_H_
|
||||
#define FUSEE_SDRAM_H_
|
||||
|
||||
void sdram_init();
|
||||
const void *sdram_get_params();
|
||||
void sdram_lp0_save_params(const void *params);
|
||||
|
||||
#endif
|
||||
1152
sept/sept-secondary/src/sdram.inl
Normal file
1152
sept/sept-secondary/src/sdram.inl
Normal file
File diff suppressed because it is too large
Load diff
1125
sept/sept-secondary/src/sdram_lp0.c
Normal file
1125
sept/sept-secondary/src/sdram_lp0.c
Normal file
File diff suppressed because it is too large
Load diff
124
sept/sept-secondary/src/sdram_lz.inl
Normal file
124
sept/sept-secondary/src/sdram_lz.inl
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
static const uint8_t _dram_cfg_lz[1262] = {
|
||||
0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
|
||||
0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08,
|
||||
0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00,
|
||||
0x00, 0x04, 0xB4, 0x01, 0x70, 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00,
|
||||
0x70, 0x17, 0x10, 0x24, 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40,
|
||||
0x00, 0x00, 0x00, 0x17, 0x04, 0x04, 0x17, 0x09, 0x18, 0xFF, 0xFF, 0x1F,
|
||||
0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, 0x77,
|
||||
0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, 0x17, 0x08, 0x08, 0xA6, 0xA6,
|
||||
0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, 0x04, 0x04,
|
||||
0x04, 0x04, 0x17, 0x04, 0x04, 0x17, 0x04, 0x3C, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
0x17, 0x04, 0x04, 0x17, 0x06, 0x06, 0x00, 0x00, 0x04, 0x08, 0x17, 0x06,
|
||||
0x46, 0xA1, 0x01, 0x00, 0x00, 0x32, 0x17, 0x0B, 0x64, 0x01, 0x17, 0x04,
|
||||
0x7C, 0x17, 0x07, 0x0C, 0x03, 0x17, 0x04, 0x04, 0x00, 0x00, 0x00, 0x1E,
|
||||
0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x13,
|
||||
0x17, 0x0B, 0x2C, 0x09, 0x00, 0x00, 0x00, 0x17, 0x05, 0x5D, 0x17, 0x07,
|
||||
0x10, 0x0B, 0x17, 0x07, 0x28, 0x08, 0x17, 0x07, 0x0C, 0x17, 0x04, 0x1C,
|
||||
0x20, 0x00, 0x00, 0x00, 0x06, 0x17, 0x04, 0x04, 0x17, 0x07, 0x08, 0x17,
|
||||
0x04, 0x50, 0x17, 0x04, 0x2C, 0x17, 0x04, 0x1C, 0x17, 0x04, 0x10, 0x17,
|
||||
0x08, 0x6C, 0x17, 0x04, 0x10, 0x17, 0x04, 0x38, 0x17, 0x04, 0x40, 0x05,
|
||||
0x17, 0x07, 0x1C, 0x17, 0x08, 0x58, 0x17, 0x04, 0x24, 0x17, 0x04, 0x18,
|
||||
0x17, 0x08, 0x64, 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14,
|
||||
0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x17, 0x09, 0x0C, 0x17, 0x05, 0x82,
|
||||
0x58, 0x17, 0x07, 0x61, 0xC1, 0x17, 0x07, 0x50, 0x17, 0x04, 0x04, 0x17,
|
||||
0x08, 0x81, 0x48, 0x17, 0x04, 0x04, 0x17, 0x04, 0x28, 0x17, 0x04, 0x60,
|
||||
0x17, 0x08, 0x54, 0x27, 0x17, 0x04, 0x04, 0x17, 0x07, 0x14, 0x17, 0x04,
|
||||
0x04, 0x04, 0x17, 0x07, 0x81, 0x58, 0x17, 0x0C, 0x0C, 0x1C, 0x03, 0x00,
|
||||
0x00, 0x0D, 0xA0, 0x60, 0x91, 0xBF, 0x3B, 0x17, 0x04, 0x5A, 0xF3, 0x0C,
|
||||
0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05,
|
||||
0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03,
|
||||
0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02,
|
||||
0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08,
|
||||
0x24, 0x06, 0x07, 0x9A, 0x12, 0x17, 0x05, 0x83, 0x41, 0x00, 0xFF, 0x17,
|
||||
0x10, 0x83, 0x6C, 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00,
|
||||
0x00, 0x0D, 0x08, 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00,
|
||||
0x00, 0x0B, 0x08, 0x72, 0x72, 0x0E, 0x0C, 0x17, 0x04, 0x20, 0x08, 0x08,
|
||||
0x0D, 0x0C, 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x17, 0x06,
|
||||
0x2C, 0x11, 0x08, 0x17, 0x10, 0x84, 0x67, 0x15, 0x00, 0xCC, 0x00, 0x0A,
|
||||
0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, 0xFF,
|
||||
0x0F, 0xFF, 0x0F, 0x17, 0x08, 0x83, 0x4C, 0x01, 0x03, 0x00, 0x70, 0x00,
|
||||
0x0C, 0x00, 0x01, 0x17, 0x04, 0x0C, 0x08, 0x44, 0x00, 0x10, 0x04, 0x04,
|
||||
0x00, 0x06, 0x13, 0x07, 0x00, 0x80, 0x17, 0x04, 0x10, 0xA0, 0x00, 0x2C,
|
||||
0x00, 0x01, 0x37, 0x00, 0x00, 0x00, 0x80, 0x17, 0x06, 0x48, 0x08, 0x00,
|
||||
0x04, 0x00, 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28,
|
||||
0x28, 0x28, 0x17, 0x04, 0x04, 0x11, 0x11, 0x11, 0x11, 0x17, 0x04, 0x04,
|
||||
0xBE, 0x00, 0x00, 0x17, 0x05, 0x58, 0x17, 0x08, 0x5C, 0x17, 0x22, 0x85,
|
||||
0x6A, 0x17, 0x1A, 0x1A, 0x14, 0x00, 0x12, 0x00, 0x10, 0x17, 0x05, 0x83,
|
||||
0x0A, 0x17, 0x16, 0x18, 0x30, 0x00, 0x2E, 0x00, 0x33, 0x00, 0x30, 0x00,
|
||||
0x33, 0x00, 0x35, 0x00, 0x30, 0x00, 0x32, 0x17, 0x05, 0x83, 0x0C, 0x17,
|
||||
0x04, 0x20, 0x17, 0x18, 0x18, 0x28, 0x00, 0x28, 0x17, 0x04, 0x04, 0x17,
|
||||
0x08, 0x08, 0x17, 0x10, 0x10, 0x00, 0x14, 0x17, 0x05, 0x5A, 0x17, 0x04,
|
||||
0x5C, 0x17, 0x04, 0x5E, 0x17, 0x04, 0x0E, 0x17, 0x0E, 0x78, 0x17, 0x09,
|
||||
0x82, 0x50, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, 0x00, 0x51,
|
||||
0x17, 0x08, 0x18, 0x80, 0x01, 0x00, 0x00, 0x40, 0x17, 0x04, 0x20, 0x03,
|
||||
0x00, 0x00, 0x00, 0xAB, 0x00, 0x0A, 0x04, 0x11, 0x17, 0x08, 0x82, 0x58,
|
||||
0x17, 0x0C, 0x38, 0x17, 0x1B, 0x81, 0x6C, 0x17, 0x08, 0x85, 0x60, 0x17,
|
||||
0x08, 0x86, 0x50, 0x17, 0x08, 0x86, 0x60, 0x17, 0x06, 0x83, 0x21, 0x22,
|
||||
0x04, 0xFF, 0xFF, 0xAF, 0x4F, 0x17, 0x0C, 0x86, 0x74, 0x17, 0x08, 0x2C,
|
||||
0x8B, 0xFF, 0x07, 0x17, 0x06, 0x81, 0x04, 0x32, 0x54, 0x76, 0x10, 0x47,
|
||||
0x32, 0x65, 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75,
|
||||
0x64, 0x32, 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45,
|
||||
0x32, 0x67, 0x17, 0x04, 0x24, 0x49, 0x92, 0x24, 0x17, 0x04, 0x04, 0x17,
|
||||
0x11, 0x7C, 0x1B, 0x17, 0x04, 0x04, 0x17, 0x13, 0x81, 0x14, 0x2F, 0x41,
|
||||
0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, 0x17, 0x04, 0x7C, 0xFF, 0xFF, 0xFF,
|
||||
0x7F, 0x0B, 0xD7, 0x06, 0x40, 0x00, 0x00, 0x02, 0x00, 0x08, 0x08, 0x03,
|
||||
0x00, 0x00, 0x5C, 0x01, 0x00, 0x10, 0x10, 0x10, 0x17, 0x06, 0x86, 0x59,
|
||||
0x17, 0x0F, 0x89, 0x14, 0x37, 0x17, 0x07, 0x82, 0x72, 0x10, 0x17, 0x06,
|
||||
0x83, 0x0D, 0x00, 0x11, 0x01, 0x17, 0x05, 0x85, 0x39, 0x17, 0x04, 0x0E,
|
||||
0x0A, 0x17, 0x07, 0x89, 0x29, 0x17, 0x04, 0x1B, 0x17, 0x08, 0x86, 0x77,
|
||||
0x17, 0x09, 0x12, 0x20, 0x00, 0x00, 0x00, 0x81, 0x10, 0x09, 0x28, 0x93,
|
||||
0x32, 0xA5, 0x44, 0x5B, 0x8A, 0x67, 0x76, 0x17, 0x18, 0x82, 0x2C, 0xFF,
|
||||
0xEF, 0xFF, 0xEF, 0xC0, 0xC0, 0xC0, 0xC0, 0x17, 0x04, 0x04, 0xDC, 0xDC,
|
||||
0xDC, 0xDC, 0x0A, 0x0A, 0x0A, 0x0A, 0x17, 0x04, 0x04, 0x17, 0x04, 0x04,
|
||||
0x17, 0x05, 0x82, 0x24, 0x03, 0x07, 0x17, 0x04, 0x04, 0x00, 0x00, 0x24,
|
||||
0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39, 0x00, 0x10,
|
||||
0x9C, 0x4B, 0x17, 0x04, 0x64, 0x01, 0x00, 0x00, 0x08, 0x4C, 0x00, 0x00,
|
||||
0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x17, 0x06, 0x85, 0x60, 0x17,
|
||||
0x10, 0x82, 0x74, 0x17, 0x08, 0x08, 0x17, 0x08, 0x88, 0x00, 0x17, 0x04,
|
||||
0x10, 0x04, 0x17, 0x0B, 0x87, 0x6C, 0x01, 0x00, 0x02, 0x02, 0x01, 0x02,
|
||||
0x03, 0x00, 0x04, 0x05, 0xC3, 0x71, 0x0F, 0x0F, 0x17, 0x08, 0x8B, 0x18,
|
||||
0x1F, 0x17, 0x09, 0x81, 0x73, 0x00, 0xFF, 0x00, 0xFF, 0x17, 0x05, 0x86,
|
||||
0x48, 0x17, 0x04, 0x0C, 0x17, 0x07, 0x86, 0x34, 0x00, 0x00, 0xF0, 0x17,
|
||||
0x09, 0x87, 0x54, 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x17, 0x0C, 0x81,
|
||||
0x52, 0x17, 0x0A, 0x1C, 0x17, 0x10, 0x81, 0x6C, 0x17, 0x0A, 0x82, 0x21,
|
||||
0x17, 0x07, 0x82, 0x4D, 0x17, 0x0A, 0x8A, 0x1B, 0x17, 0x11, 0x2C, 0x76,
|
||||
0x0C, 0x17, 0x0A, 0x8A, 0x67, 0x17, 0x0F, 0x84, 0x28, 0x17, 0x06, 0x34,
|
||||
0x17, 0x17, 0x3A, 0x7E, 0x16, 0x40, 0x17, 0x0C, 0x8B, 0x1F, 0x17, 0x2A,
|
||||
0x38, 0x1E, 0x17, 0x0A, 0x38, 0x17, 0x13, 0x81, 0x28, 0x00, 0xC0, 0x17,
|
||||
0x17, 0x55, 0x46, 0x24, 0x17, 0x0A, 0x81, 0x28, 0x17, 0x14, 0x38, 0x17,
|
||||
0x18, 0x81, 0x60, 0x46, 0x2C, 0x17, 0x06, 0x38, 0xEC, 0x17, 0x0D, 0x16,
|
||||
0x17, 0x0E, 0x82, 0x3C, 0x17, 0x82, 0x0C, 0x8E, 0x68, 0x17, 0x04, 0x24,
|
||||
0x17, 0x5C, 0x8E, 0x68, 0x17, 0x07, 0x82, 0x5F, 0x80, 0x17, 0x87, 0x01,
|
||||
0x8E, 0x68, 0x02, 0x17, 0x81, 0x4A, 0x8E, 0x68, 0x17, 0x0C, 0x87, 0x78,
|
||||
0x17, 0x85, 0x28, 0x8E, 0x68, 0x17, 0x8E, 0x68, 0x9D, 0x50, 0x17, 0x81,
|
||||
0x24, 0x8E, 0x68, 0x17, 0x04, 0x2C, 0x17, 0x28, 0x8E, 0x68, 0x17, 0x04,
|
||||
0x30, 0x17, 0x85, 0x3C, 0x8E, 0x68, 0x12, 0x17, 0x07, 0x85, 0x70, 0x17,
|
||||
0x88, 0x74, 0x8E, 0x68, 0x17, 0x87, 0x3E, 0x9D, 0x50, 0x0C, 0x17, 0x04,
|
||||
0x04, 0x17, 0x12, 0x8E, 0x68, 0x18, 0x17, 0x87, 0x12, 0xBB, 0x20, 0x17,
|
||||
0x83, 0x04, 0x9D, 0x50, 0x15, 0x17, 0x05, 0x8D, 0x76, 0x17, 0x0F, 0x8B,
|
||||
0x49, 0x17, 0x0B, 0x18, 0x32, 0x00, 0x2F, 0x00, 0x32, 0x00, 0x31, 0x00,
|
||||
0x34, 0x00, 0x36, 0x00, 0x2F, 0x00, 0x33, 0x17, 0x09, 0x84, 0x0C, 0x17,
|
||||
0x18, 0x18, 0x17, 0x20, 0x8E, 0x68, 0x15, 0x17, 0x07, 0x5A, 0x17, 0x06,
|
||||
0x5E, 0x16, 0x00, 0x15, 0x17, 0x82, 0x40, 0x9D, 0x50, 0x17, 0x86, 0x5F,
|
||||
0xBB, 0x20, 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x17, 0x81, 0x4F, 0xAC, 0x38,
|
||||
0x3B, 0x17, 0x04, 0x04, 0x17, 0x86, 0x30, 0x8E, 0x68, 0x17, 0x81, 0x53,
|
||||
0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10,
|
||||
0x8E, 0x68
|
||||
};
|
||||
933
sept/sept-secondary/src/sdram_param_t210.h
Normal file
933
sept/sept-secondary/src/sdram_param_t210.h
Normal file
|
|
@ -0,0 +1,933 @@
|
|||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Defines the SDRAM parameter structure.
|
||||
*
|
||||
* Note that PLLM is used by EMC.
|
||||
*/
|
||||
|
||||
#ifndef _SDRAM_PARAM_T210_H_
|
||||
#define _SDRAM_PARAM_T210_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define MEMORY_TYPE_NONE 0
|
||||
#define MEMORY_TYPE_DDR 0
|
||||
#define MEMORY_TYPE_LPDDR 0
|
||||
#define MEMORY_TYPE_DDR2 0
|
||||
#define MEMORY_TYPE_LPDDR2 1
|
||||
#define MEMORY_TYPE_DDR3 2
|
||||
#define MEMORY_TYPE_LPDDR4 3
|
||||
|
||||
/**
|
||||
* Defines the SDRAM parameter structure
|
||||
*/
|
||||
typedef struct _sdram_params
|
||||
{
|
||||
/* Specifies the type of memory device */
|
||||
uint32_t memory_type;
|
||||
|
||||
/* MC/EMC clock source configuration */
|
||||
|
||||
/* Specifies the M value for PllM */
|
||||
uint32_t pllm_input_divider;
|
||||
/* Specifies the N value for PllM */
|
||||
uint32_t pllm_feedback_divider;
|
||||
/* Specifies the time to wait for PLLM to lock (in microseconds) */
|
||||
uint32_t pllm_stable_time;
|
||||
/* Specifies misc. control bits */
|
||||
uint32_t pllm_setup_control;
|
||||
/* Specifies the P value for PLLM */
|
||||
uint32_t pllm_post_divider;
|
||||
/* Specifies value for Charge Pump Gain Control */
|
||||
uint32_t pllm_kcp;
|
||||
/* Specifies VCO gain */
|
||||
uint32_t pllm_kvco;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare0;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare1;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare2;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare3;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare4;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare5;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare6;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare7;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare8;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare9;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare10;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare11;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare12;
|
||||
/* Spare BCT param */
|
||||
uint32_t emc_bct_spare13;
|
||||
|
||||
/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
|
||||
uint32_t emc_clock_source;
|
||||
uint32_t emc_clock_source_dll;
|
||||
|
||||
/* Defines possible override for PLLLM_MISC2 */
|
||||
uint32_t clk_rst_pllm_misc20_override;
|
||||
/* enables override for PLLLM_MISC2 */
|
||||
uint32_t clk_rst_pllm_misc20_override_enable;
|
||||
/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
|
||||
uint32_t clear_clock2_mc1;
|
||||
|
||||
/* Auto-calibration of EMC pads */
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
|
||||
uint32_t emc_auto_cal_interval;
|
||||
/*
|
||||
* Specifies the value for EMC_AUTO_CAL_CONFIG
|
||||
* Note: Trigger bits are set by the SDRAM code.
|
||||
*/
|
||||
uint32_t emc_auto_cal_config;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
|
||||
uint32_t emc_auto_cal_config2;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
|
||||
uint32_t emc_auto_cal_config3;
|
||||
|
||||
uint32_t emc_auto_cal_config4;
|
||||
uint32_t emc_auto_cal_config5;
|
||||
uint32_t emc_auto_cal_config6;
|
||||
uint32_t emc_auto_cal_config7;
|
||||
uint32_t emc_auto_cal_config8;
|
||||
/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
|
||||
uint32_t emc_auto_cal_vref_sel0;
|
||||
uint32_t emc_auto_cal_vref_sel1;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
|
||||
uint32_t emc_auto_cal_channel;
|
||||
|
||||
/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
|
||||
uint32_t emc_pmacro_auto_cal_cfg0;
|
||||
uint32_t emc_pmacro_auto_cal_cfg1;
|
||||
uint32_t emc_pmacro_auto_cal_cfg2;
|
||||
|
||||
uint32_t emc_pmacro_rx_term;
|
||||
uint32_t emc_pmacro_dq_tx_drive;
|
||||
uint32_t emc_pmacro_ca_tx_drive;
|
||||
uint32_t emc_pmacro_cmd_tx_drive;
|
||||
uint32_t emc_pmacro_auto_cal_common;
|
||||
uint32_t emc_pmacro_zcrtl;
|
||||
|
||||
/*
|
||||
* Specifies the time for the calibration
|
||||
* to stabilize (in microseconds)
|
||||
*/
|
||||
uint32_t emc_auto_cal_wait;
|
||||
|
||||
uint32_t emc_xm2_comp_pad_ctrl;
|
||||
uint32_t emc_xm2_comp_pad_ctrl2;
|
||||
uint32_t emc_xm2_comp_pad_ctrl3;
|
||||
|
||||
/*
|
||||
* DRAM size information
|
||||
* Specifies the value for EMC_ADR_CFG
|
||||
*/
|
||||
uint32_t emc_adr_cfg;
|
||||
|
||||
/*
|
||||
* Specifies the time to wait after asserting pin
|
||||
* CKE (in microseconds)
|
||||
*/
|
||||
uint32_t emc_pin_program_wait;
|
||||
/* Specifies the extra delay before/after pin RESET/CKE command */
|
||||
uint32_t emc_pin_extra_wait;
|
||||
|
||||
uint32_t emc_pin_gpio_enable;
|
||||
uint32_t emc_pin_gpio;
|
||||
|
||||
/*
|
||||
* Specifies the extra delay after the first writing
|
||||
* of EMC_TIMING_CONTROL
|
||||
*/
|
||||
uint32_t emc_timing_control_wait;
|
||||
|
||||
/* Timing parameters required for the SDRAM */
|
||||
|
||||
/* Specifies the value for EMC_RC */
|
||||
uint32_t emc_rc;
|
||||
/* Specifies the value for EMC_RFC */
|
||||
uint32_t emc_rfc;
|
||||
|
||||
uint32_t emc_rfc_pb;
|
||||
uint32_t emc_ref_ctrl2;
|
||||
|
||||
/* Specifies the value for EMC_RFC_SLR */
|
||||
uint32_t emc_rfc_slr;
|
||||
/* Specifies the value for EMC_RAS */
|
||||
uint32_t emc_ras;
|
||||
/* Specifies the value for EMC_RP */
|
||||
uint32_t emc_rp;
|
||||
/* Specifies the value for EMC_R2R */
|
||||
uint32_t emc_r2r;
|
||||
/* Specifies the value for EMC_W2W */
|
||||
uint32_t emc_w2w;
|
||||
/* Specifies the value for EMC_R2W */
|
||||
uint32_t emc_r2w;
|
||||
/* Specifies the value for EMC_W2R */
|
||||
uint32_t emc_w2r;
|
||||
/* Specifies the value for EMC_R2P */
|
||||
uint32_t emc_r2p;
|
||||
/* Specifies the value for EMC_W2P */
|
||||
uint32_t emc_w2p;
|
||||
/* Specifies the value for EMC_RD_RCD */
|
||||
|
||||
uint32_t emc_tppd;
|
||||
uint32_t emc_ccdmw;
|
||||
|
||||
uint32_t emc_rd_rcd;
|
||||
/* Specifies the value for EMC_WR_RCD */
|
||||
uint32_t emc_wr_rcd;
|
||||
/* Specifies the value for EMC_RRD */
|
||||
uint32_t emc_rrd;
|
||||
/* Specifies the value for EMC_REXT */
|
||||
uint32_t emc_rext;
|
||||
/* Specifies the value for EMC_WEXT */
|
||||
uint32_t emc_wext;
|
||||
/* Specifies the value for EMC_WDV */
|
||||
uint32_t emc_wdv;
|
||||
|
||||
uint32_t emc_wdv_chk;
|
||||
uint32_t emc_wsv;
|
||||
uint32_t emc_wev;
|
||||
|
||||
/* Specifies the value for EMC_WDV_MASK */
|
||||
uint32_t emc_wdv_mask;
|
||||
|
||||
uint32_t emc_ws_duration;
|
||||
uint32_t emc_we_duration;
|
||||
|
||||
/* Specifies the value for EMC_QUSE */
|
||||
uint32_t emc_quse;
|
||||
/* Specifies the value for EMC_QUSE_WIDTH */
|
||||
uint32_t emc_quse_width;
|
||||
/* Specifies the value for EMC_IBDLY */
|
||||
uint32_t emc_ibdly;
|
||||
|
||||
uint32_t emc_obdly;
|
||||
|
||||
/* Specifies the value for EMC_EINPUT */
|
||||
uint32_t emc_einput;
|
||||
/* Specifies the value for EMC_EINPUT_DURATION */
|
||||
uint32_t emc_einput_duration;
|
||||
/* Specifies the value for EMC_PUTERM_EXTRA */
|
||||
uint32_t emc_puterm_extra;
|
||||
/* Specifies the value for EMC_PUTERM_WIDTH */
|
||||
uint32_t emc_puterm_width;
|
||||
|
||||
uint32_t emc_qrst;
|
||||
uint32_t emc_qsafe;
|
||||
uint32_t emc_rdv;
|
||||
uint32_t emc_rdv_mask;
|
||||
|
||||
uint32_t emc_rdv_early;
|
||||
uint32_t emc_rdv_early_mask;
|
||||
|
||||
/* Specifies the value for EMC_QPOP */
|
||||
uint32_t emc_qpop;
|
||||
|
||||
/* Specifies the value for EMC_REFRESH */
|
||||
uint32_t emc_refresh;
|
||||
/* Specifies the value for EMC_BURST_REFRESH_NUM */
|
||||
uint32_t emc_burst_refresh_num;
|
||||
/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
|
||||
uint32_t emc_prerefresh_req_cnt;
|
||||
/* Specifies the value for EMC_PDEX2WR */
|
||||
uint32_t emc_pdex2wr;
|
||||
/* Specifies the value for EMC_PDEX2RD */
|
||||
uint32_t emc_pdex2rd;
|
||||
/* Specifies the value for EMC_PCHG2PDEN */
|
||||
uint32_t emc_pchg2pden;
|
||||
/* Specifies the value for EMC_ACT2PDEN */
|
||||
uint32_t emc_act2pden;
|
||||
/* Specifies the value for EMC_AR2PDEN */
|
||||
uint32_t emc_ar2pden;
|
||||
/* Specifies the value for EMC_RW2PDEN */
|
||||
uint32_t emc_rw2pden;
|
||||
|
||||
uint32_t emc_cke2pden;
|
||||
uint32_t emc_pdex2che;
|
||||
uint32_t emc_pdex2mrr;
|
||||
|
||||
/* Specifies the value for EMC_TXSR */
|
||||
uint32_t emc_txsr;
|
||||
/* Specifies the value for EMC_TXSRDLL */
|
||||
uint32_t emc_txsr_dll;
|
||||
/* Specifies the value for EMC_TCKE */
|
||||
uint32_t emc_tcke;
|
||||
/* Specifies the value for EMC_TCKESR */
|
||||
uint32_t emc_tckesr;
|
||||
/* Specifies the value for EMC_TPD */
|
||||
uint32_t emc_tpd;
|
||||
/* Specifies the value for EMC_TFAW */
|
||||
uint32_t emc_tfaw;
|
||||
/* Specifies the value for EMC_TRPAB */
|
||||
uint32_t emc_trpab;
|
||||
/* Specifies the value for EMC_TCLKSTABLE */
|
||||
uint32_t emc_tclkstable;
|
||||
/* Specifies the value for EMC_TCLKSTOP */
|
||||
uint32_t emc_tclkstop;
|
||||
/* Specifies the value for EMC_TREFBW */
|
||||
uint32_t emc_trefbw;
|
||||
|
||||
/* FBIO configuration values */
|
||||
|
||||
/* Specifies the value for EMC_FBIO_CFG5 */
|
||||
uint32_t emc_fbio_cfg5;
|
||||
/* Specifies the value for EMC_FBIO_CFG7 */
|
||||
uint32_t emc_fbio_cfg7;
|
||||
uint32_t emc_fbio_cfg8;
|
||||
|
||||
/* Command mapping for CMD brick 0 */
|
||||
uint32_t emc_cmd_mapping_cmd0_0;
|
||||
uint32_t emc_cmd_mapping_cmd0_1;
|
||||
uint32_t emc_cmd_mapping_cmd0_2;
|
||||
uint32_t emc_cmd_mapping_cmd1_0;
|
||||
uint32_t emc_cmd_mapping_cmd1_1;
|
||||
uint32_t emc_cmd_mapping_cmd1_2;
|
||||
uint32_t emc_cmd_mapping_cmd2_0;
|
||||
uint32_t emc_cmd_mapping_cmd2_1;
|
||||
uint32_t emc_cmd_mapping_cmd2_2;
|
||||
uint32_t emc_cmd_mapping_cmd3_0;
|
||||
uint32_t emc_cmd_mapping_cmd3_1;
|
||||
uint32_t emc_cmd_mapping_cmd3_2;
|
||||
uint32_t emc_cmd_mapping_byte;
|
||||
|
||||
/* Specifies the value for EMC_FBIO_SPARE */
|
||||
uint32_t emc_fbio_spare;
|
||||
|
||||
/* Specifies the value for EMC_CFG_RSV */
|
||||
uint32_t emc_cfg_rsv;
|
||||
|
||||
/* MRS command values */
|
||||
|
||||
/* Specifies the value for EMC_MRS */
|
||||
uint32_t emc_mrs;
|
||||
/* Specifies the MP0 command to initialize mode registers */
|
||||
uint32_t emc_emrs;
|
||||
/* Specifies the MP2 command to initialize mode registers */
|
||||
uint32_t emc_emrs2;
|
||||
/* Specifies the MP3 command to initialize mode registers */
|
||||
uint32_t emc_emrs3;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
|
||||
uint32_t emc_mrw1;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
|
||||
uint32_t emc_mrw2;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
|
||||
uint32_t emc_mrw3;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
|
||||
uint32_t emc_mrw4;
|
||||
|
||||
/* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */
|
||||
uint32_t emc_mrw6;
|
||||
/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
|
||||
uint32_t emc_mrw8;
|
||||
/* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */
|
||||
uint32_t emc_mrw9;
|
||||
/* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */
|
||||
uint32_t emc_mrw10;
|
||||
/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
|
||||
uint32_t emc_mrw12;
|
||||
/* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */
|
||||
uint32_t emc_mrw13;
|
||||
/* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */
|
||||
uint32_t emc_mrw14;
|
||||
|
||||
/*
|
||||
* Specifies the programming to extra LPDDR2 Mode Register
|
||||
* at cold boot
|
||||
*/
|
||||
uint32_t emc_mrw_extra;
|
||||
/*
|
||||
* Specifies the programming to extra LPDDR2 Mode Register
|
||||
* at warm boot
|
||||
*/
|
||||
uint32_t emc_warm_boot_mrw_extra;
|
||||
/*
|
||||
* Specify the enable of extra Mode Register programming at
|
||||
* warm boot
|
||||
*/
|
||||
uint32_t emc_warm_boot_extramode_reg_write_enable;
|
||||
/*
|
||||
* Specify the enable of extra Mode Register programming at
|
||||
* cold boot
|
||||
*/
|
||||
uint32_t emc_extramode_reg_write_enable;
|
||||
|
||||
/* Specifies the EMC_MRW reset command value */
|
||||
uint32_t emc_mrw_reset_command;
|
||||
/* Specifies the EMC Reset wait time (in microseconds) */
|
||||
uint32_t emc_mrw_reset_ninit_wait;
|
||||
/* Specifies the value for EMC_MRS_WAIT_CNT */
|
||||
uint32_t emc_mrs_wait_cnt;
|
||||
/* Specifies the value for EMC_MRS_WAIT_CNT2 */
|
||||
uint32_t emc_mrs_wait_cnt2;
|
||||
|
||||
/* EMC miscellaneous configurations */
|
||||
|
||||
/* Specifies the value for EMC_CFG */
|
||||
uint32_t emc_cfg;
|
||||
/* Specifies the value for EMC_CFG_2 */
|
||||
uint32_t emc_cfg2;
|
||||
/* Specifies the pipe bypass controls */
|
||||
uint32_t emc_cfg_pipe;
|
||||
|
||||
uint32_t emc_cfg_pipe_clk;
|
||||
uint32_t emc_fdpd_ctrl_cmd_no_ramp;
|
||||
uint32_t emc_cfg_update;
|
||||
|
||||
/* Specifies the value for EMC_DBG */
|
||||
uint32_t emc_dbg;
|
||||
|
||||
uint32_t emc_dbg_write_mux;
|
||||
|
||||
/* Specifies the value for EMC_CMDQ */
|
||||
uint32_t emc_cmd_q;
|
||||
/* Specifies the value for EMC_MC2EMCQ */
|
||||
uint32_t emc_mc2emc_q;
|
||||
/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
|
||||
uint32_t emc_dyn_self_ref_control;
|
||||
|
||||
/* Specifies the value for MEM_INIT_DONE */
|
||||
uint32_t ahb_arbitration_xbar_ctrl_meminit_done;
|
||||
|
||||
/* Specifies the value for EMC_CFG_DIG_DLL */
|
||||
uint32_t emc_cfg_dig_dll;
|
||||
uint32_t emc_cfg_dig_dll_1;
|
||||
|
||||
/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
|
||||
uint32_t emc_cfg_dig_dll_period;
|
||||
/* Specifies the value of *DEV_SELECTN of various EMC registers */
|
||||
uint32_t emc_dev_select;
|
||||
|
||||
/* Specifies the value for EMC_SEL_DPD_CTRL */
|
||||
uint32_t emc_sel_dpd_ctrl;
|
||||
|
||||
/* Pads trimmer delays */
|
||||
uint32_t emc_fdpd_ctrl_dq;
|
||||
uint32_t emc_fdpd_ctrl_cmd;
|
||||
uint32_t emc_pmacro_ib_vref_dq_0;
|
||||
uint32_t emc_pmacro_ib_vref_dq_1;
|
||||
uint32_t emc_pmacro_ib_vref_dqs_0;
|
||||
uint32_t emc_pmacro_ib_vref_dqs_1;
|
||||
uint32_t emc_pmacro_ib_rxrt;
|
||||
uint32_t emc_cfg_pipe1;
|
||||
uint32_t emc_cfg_pipe2;
|
||||
|
||||
/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
|
||||
uint32_t emc_pmacro_quse_ddll_rank0_0;
|
||||
uint32_t emc_pmacro_quse_ddll_rank0_1;
|
||||
uint32_t emc_pmacro_quse_ddll_rank0_2;
|
||||
uint32_t emc_pmacro_quse_ddll_rank0_3;
|
||||
uint32_t emc_pmacro_quse_ddll_rank0_4;
|
||||
uint32_t emc_pmacro_quse_ddll_rank0_5;
|
||||
uint32_t emc_pmacro_quse_ddll_rank1_0;
|
||||
uint32_t emc_pmacro_quse_ddll_rank1_1;
|
||||
uint32_t emc_pmacro_quse_ddll_rank1_2;
|
||||
uint32_t emc_pmacro_quse_ddll_rank1_3;
|
||||
uint32_t emc_pmacro_quse_ddll_rank1_4;
|
||||
uint32_t emc_pmacro_quse_ddll_rank1_5;
|
||||
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
|
||||
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
|
||||
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
|
||||
|
||||
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0;
|
||||
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1;
|
||||
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2;
|
||||
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3;
|
||||
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0;
|
||||
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1;
|
||||
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2;
|
||||
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3;
|
||||
|
||||
uint32_t emc_pmacro_ddll_long_cmd_0;
|
||||
uint32_t emc_pmacro_ddll_long_cmd_1;
|
||||
uint32_t emc_pmacro_ddll_long_cmd_2;
|
||||
uint32_t emc_pmacro_ddll_long_cmd_3;
|
||||
uint32_t emc_pmacro_ddll_long_cmd_4;
|
||||
uint32_t emc_pmacro_ddll_short_cmd_0;
|
||||
uint32_t emc_pmacro_ddll_short_cmd_1;
|
||||
uint32_t emc_pmacro_ddll_short_cmd_2;
|
||||
|
||||
/*
|
||||
* Specifies the delay after asserting CKE pin during a WarmBoot0
|
||||
* sequence (in microseconds)
|
||||
*/
|
||||
uint32_t warm_boot_wait;
|
||||
|
||||
/* Specifies the value for EMC_ODT_WRITE */
|
||||
uint32_t emc_odt_write;
|
||||
|
||||
/* Periodic ZQ calibration */
|
||||
|
||||
/*
|
||||
* Specifies the value for EMC_ZCAL_INTERVAL
|
||||
* Value 0 disables ZQ calibration
|
||||
*/
|
||||
uint32_t emc_zcal_interval;
|
||||
/* Specifies the value for EMC_ZCAL_WAIT_CNT */
|
||||
uint32_t emc_zcal_wait_cnt;
|
||||
/* Specifies the value for EMC_ZCAL_MRW_CMD */
|
||||
uint32_t emc_zcal_mrw_cmd;
|
||||
|
||||
/* DRAM initialization sequence flow control */
|
||||
|
||||
/* Specifies the MRS command value for resetting DLL */
|
||||
uint32_t emc_mrs_reset_dll;
|
||||
/* Specifies the command for ZQ initialization of device 0 */
|
||||
uint32_t emc_zcal_init_dev0;
|
||||
/* Specifies the command for ZQ initialization of device 1 */
|
||||
uint32_t emc_zcal_init_dev1;
|
||||
/*
|
||||
* Specifies the wait time after programming a ZQ initialization
|
||||
* command (in microseconds)
|
||||
*/
|
||||
uint32_t emc_zcal_init_wait;
|
||||
/*
|
||||
* Specifies the enable for ZQ calibration at cold boot [bit 0]
|
||||
* and warm boot [bit 1]
|
||||
*/
|
||||
uint32_t emc_zcal_warm_cold_boot_enables;
|
||||
|
||||
/*
|
||||
* Specifies the MRW command to LPDDR2 for ZQ calibration
|
||||
* on warmboot
|
||||
*/
|
||||
/* Is issued to both devices separately */
|
||||
uint32_t emc_mrw_lpddr2zcal_warm_boot;
|
||||
/*
|
||||
* Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
|
||||
* Is issued to both devices separately
|
||||
*/
|
||||
uint32_t emc_zqcal_ddr3_warm_boot;
|
||||
|
||||
uint32_t emc_zqcal_lpddr4_warm_boot;
|
||||
|
||||
/*
|
||||
* Specifies the wait time for ZQ calibration on warmboot
|
||||
* (in microseconds)
|
||||
*/
|
||||
uint32_t emc_zcal_warm_boot_wait;
|
||||
/*
|
||||
* Specifies the enable for DRAM Mode Register programming
|
||||
* at warm boot
|
||||
*/
|
||||
uint32_t emc_mrs_warm_boot_enable;
|
||||
/*
|
||||
* Specifies the wait time after sending an MRS DLL reset command
|
||||
* in microseconds)
|
||||
*/
|
||||
uint32_t emc_mrs_reset_dll_wait;
|
||||
/* Specifies the extra MRS command to initialize mode registers */
|
||||
uint32_t emc_mrs_extra;
|
||||
/* Specifies the extra MRS command at warm boot */
|
||||
uint32_t emc_warm_boot_mrs_extra;
|
||||
/* Specifies the EMRS command to enable the DDR2 DLL */
|
||||
uint32_t emc_emrs_ddr2_dll_enable;
|
||||
/* Specifies the MRS command to reset the DDR2 DLL */
|
||||
uint32_t emc_mrs_ddr2_dll_reset;
|
||||
/* Specifies the EMRS command to set OCD calibration */
|
||||
uint32_t emc_emrs_ddr2_ocd_calib;
|
||||
/*
|
||||
* Specifies the wait between initializing DDR and setting OCD
|
||||
* calibration (in microseconds)
|
||||
*/
|
||||
uint32_t emc_ddr2_wait;
|
||||
/* Specifies the value for EMC_CLKEN_OVERRIDE */
|
||||
uint32_t emc_clken_override;
|
||||
/*
|
||||
* Specifies LOG2 of the extra refresh numbers after booting
|
||||
* Program 0 to disable
|
||||
*/
|
||||
uint32_t emc_extra_refresh_num;
|
||||
/* Specifies the master override for all EMC clocks */
|
||||
uint32_t emc_clken_override_allwarm_boot;
|
||||
/* Specifies the master override for all MC clocks */
|
||||
uint32_t mc_clken_override_allwarm_boot;
|
||||
/* Specifies digital dll period, choosing between 4 to 64 ms */
|
||||
uint32_t emc_cfg_dig_dll_period_warm_boot;
|
||||
|
||||
/* Pad controls */
|
||||
|
||||
/* Specifies the value for PMC_VDDP_SEL */
|
||||
uint32_t pmc_vddp_sel;
|
||||
/* Specifies the wait time after programming PMC_VDDP_SEL */
|
||||
uint32_t pmc_vddp_sel_wait;
|
||||
/* Specifies the value for PMC_DDR_PWR */
|
||||
uint32_t pmc_ddr_pwr;
|
||||
/* Specifies the value for PMC_DDR_CFG */
|
||||
uint32_t pmc_ddr_cfg;
|
||||
/* Specifies the value for PMC_IO_DPD3_REQ */
|
||||
uint32_t pmc_io_dpd3_req;
|
||||
/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
|
||||
uint32_t pmc_io_dpd3_req_wait;
|
||||
|
||||
uint32_t pmc_io_dpd4_req_wait;
|
||||
|
||||
/* Specifies the value for PMC_REG_SHORT */
|
||||
uint32_t pmc_reg_short;
|
||||
/* Specifies the value for PMC_NO_IOPOWER */
|
||||
uint32_t pmc_no_io_power;
|
||||
|
||||
uint32_t pmc_ddr_ctrl_wait;
|
||||
uint32_t pmc_ddr_ctrl;
|
||||
|
||||
/* Specifies the value for EMC_ACPD_CONTROL */
|
||||
uint32_t emc_acpd_control;
|
||||
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
|
||||
uint32_t emc_swizzle_rank0_byte0;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
|
||||
uint32_t emc_swizzle_rank0_byte1;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
|
||||
uint32_t emc_swizzle_rank0_byte2;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
|
||||
uint32_t emc_swizzle_rank0_byte3;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
|
||||
uint32_t emc_swizzle_rank1_byte0;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
|
||||
uint32_t emc_swizzle_rank1_byte1;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
|
||||
uint32_t emc_swizzle_rank1_byte2;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
|
||||
uint32_t emc_swizzle_rank1_byte3;
|
||||
|
||||
/* Specifies the value for EMC_TXDSRVTTGEN */
|
||||
uint32_t emc_txdsrvttgen;
|
||||
|
||||
/* Specifies the value for EMC_DATA_BRLSHFT_0 */
|
||||
uint32_t emc_data_brlshft0;
|
||||
uint32_t emc_data_brlshft1;
|
||||
|
||||
uint32_t emc_dqs_brlshft0;
|
||||
uint32_t emc_dqs_brlshft1;
|
||||
|
||||
uint32_t emc_cmd_brlshft0;
|
||||
uint32_t emc_cmd_brlshft1;
|
||||
uint32_t emc_cmd_brlshft2;
|
||||
uint32_t emc_cmd_brlshft3;
|
||||
|
||||
uint32_t emc_quse_brlshft0;
|
||||
uint32_t emc_quse_brlshft1;
|
||||
uint32_t emc_quse_brlshft2;
|
||||
uint32_t emc_quse_brlshft3;
|
||||
|
||||
uint32_t emc_dll_cfg0;
|
||||
uint32_t emc_dll_cfg1;
|
||||
|
||||
uint32_t emc_pmc_scratch1;
|
||||
uint32_t emc_pmc_scratch2;
|
||||
uint32_t emc_pmc_scratch3;
|
||||
|
||||
uint32_t emc_pmacro_pad_cfg_ctrl;
|
||||
|
||||
uint32_t emc_pmacro_vttgen_ctrl0;
|
||||
uint32_t emc_pmacro_vttgen_ctrl1;
|
||||
uint32_t emc_pmacro_vttgen_ctrl2;
|
||||
|
||||
uint32_t emc_pmacro_brick_ctrl_rfu1;
|
||||
uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
|
||||
uint32_t emc_pmacro_brick_ctrl_rfu2;
|
||||
uint32_t emc_pmacro_data_brick_ctrl_fdpd;
|
||||
uint32_t emc_pmacro_bg_bias_ctrl0;
|
||||
uint32_t emc_pmacro_data_pad_rx_ctrl;
|
||||
uint32_t emc_pmacro_cmd_pad_rx_ctrl;
|
||||
uint32_t emc_pmacro_data_rx_term_mode;
|
||||
uint32_t emc_pmacro_cmd_rx_term_mode;
|
||||
uint32_t emc_pmacro_data_pad_tx_ctrl;
|
||||
uint32_t emc_pmacro_common_pad_tx_ctrl;
|
||||
uint32_t emc_pmacro_cmd_pad_tx_ctrl;
|
||||
uint32_t emc_cfg3;
|
||||
|
||||
uint32_t emc_pmacro_tx_pwrd0;
|
||||
uint32_t emc_pmacro_tx_pwrd1;
|
||||
uint32_t emc_pmacro_tx_pwrd2;
|
||||
uint32_t emc_pmacro_tx_pwrd3;
|
||||
uint32_t emc_pmacro_tx_pwrd4;
|
||||
uint32_t emc_pmacro_tx_pwrd5;
|
||||
|
||||
uint32_t emc_config_sample_delay;
|
||||
|
||||
uint32_t emc_pmacro_brick_mapping0;
|
||||
uint32_t emc_pmacro_brick_mapping1;
|
||||
uint32_t emc_pmacro_brick_mapping2;
|
||||
|
||||
uint32_t emc_pmacro_tx_sel_clk_src0;
|
||||
uint32_t emc_pmacro_tx_sel_clk_src1;
|
||||
uint32_t emc_pmacro_tx_sel_clk_src2;
|
||||
uint32_t emc_pmacro_tx_sel_clk_src3;
|
||||
uint32_t emc_pmacro_tx_sel_clk_src4;
|
||||
uint32_t emc_pmacro_tx_sel_clk_src5;
|
||||
|
||||
uint32_t emc_pmacro_ddll_bypass;
|
||||
|
||||
uint32_t emc_pmacro_ddll_pwrd0;
|
||||
uint32_t emc_pmacro_ddll_pwrd1;
|
||||
uint32_t emc_pmacro_ddll_pwrd2;
|
||||
|
||||
uint32_t emc_pmacro_cmd_ctrl0;
|
||||
uint32_t emc_pmacro_cmd_ctrl1;
|
||||
uint32_t emc_pmacro_cmd_ctrl2;
|
||||
|
||||
/* DRAM size information */
|
||||
|
||||
/* Specifies the value for MC_EMEM_ADR_CFG */
|
||||
uint32_t mc_emem_adr_cfg;
|
||||
/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
|
||||
uint32_t mc_emem_adr_cfg_dev0;
|
||||
/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
|
||||
uint32_t mc_emem_adr_cfg_dev1;
|
||||
|
||||
uint32_t mc_emem_adr_cfg_channel_mask;
|
||||
|
||||
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */
|
||||
uint32_t mc_emem_adr_cfg_bank_mask0;
|
||||
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
|
||||
uint32_t mc_emem_adr_cfg_bank_mask1;
|
||||
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
|
||||
uint32_t mc_emem_adr_cfg_bank_mask2;
|
||||
|
||||
/*
|
||||
* Specifies the value for MC_EMEM_CFG which holds the external memory
|
||||
* size (in KBytes)
|
||||
*/
|
||||
uint32_t mc_emem_cfg;
|
||||
|
||||
/* MC arbitration configuration */
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_CFG */
|
||||
uint32_t mc_emem_arb_cfg;
|
||||
/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
|
||||
uint32_t mc_emem_arb_outstanding_req;
|
||||
|
||||
uint32_t emc_emem_arb_refpb_hp_ctrl;
|
||||
uint32_t emc_emem_arb_refpb_bank_ctrl;
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
|
||||
uint32_t mc_emem_arb_timing_rcd;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
|
||||
uint32_t mc_emem_arb_timing_rp;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
|
||||
uint32_t mc_emem_arb_timing_rc;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
|
||||
uint32_t mc_emem_arb_timing_ras;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
|
||||
uint32_t mc_emem_arb_timing_faw;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
|
||||
uint32_t mc_emem_arb_timing_rrd;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
|
||||
uint32_t mc_emem_arb_timing_rap2pre;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
|
||||
uint32_t mc_emem_arb_timing_wap2pre;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
|
||||
uint32_t mc_emem_arb_timing_r2r;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
|
||||
uint32_t mc_emem_arb_timing_w2w;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
|
||||
uint32_t mc_emem_arb_timing_r2w;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
|
||||
uint32_t mc_emem_arb_timing_w2r;
|
||||
|
||||
uint32_t mc_emem_arb_timing_rfcpb;
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
|
||||
uint32_t mc_emem_arb_da_turns;
|
||||
/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
|
||||
uint32_t mc_emem_arb_da_covers;
|
||||
/* Specifies the value for MC_EMEM_ARB_MISC0 */
|
||||
uint32_t mc_emem_arb_misc0;
|
||||
/* Specifies the value for MC_EMEM_ARB_MISC1 */
|
||||
uint32_t mc_emem_arb_misc1;
|
||||
uint32_t mc_emem_arb_misc2;
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
|
||||
uint32_t mc_emem_arb_ring1_throttle;
|
||||
/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
|
||||
uint32_t mc_emem_arb_override;
|
||||
/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
|
||||
uint32_t mc_emem_arb_override1;
|
||||
/* Specifies the value for MC_EMEM_ARB_RSV */
|
||||
uint32_t mc_emem_arb_rsv;
|
||||
|
||||
uint32_t mc_da_cfg0;
|
||||
uint32_t mc_emem_arb_timing_ccdmw;
|
||||
|
||||
/* Specifies the value for MC_CLKEN_OVERRIDE */
|
||||
uint32_t mc_clken_override;
|
||||
|
||||
/* Specifies the value for MC_STAT_CONTROL */
|
||||
uint32_t mc_stat_control;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_BOM */
|
||||
uint32_t mc_video_protect_bom;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
|
||||
uint32_t mc_video_protect_bom_adr_hi;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
|
||||
uint32_t mc_video_protect_size_mb;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
|
||||
uint32_t mc_video_protect_vpr_override;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
|
||||
uint32_t mc_video_protect_vpr_override1;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
|
||||
uint32_t mc_video_protect_gpu_override0;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
|
||||
uint32_t mc_video_protect_gpu_override1;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_BOM */
|
||||
uint32_t mc_sec_carveout_bom;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
|
||||
uint32_t mc_sec_carveout_adr_hi;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
|
||||
uint32_t mc_sec_carveout_size_mb;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */
|
||||
uint32_t mc_video_protect_write_access;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */
|
||||
uint32_t mc_sec_carveout_protect_write_access;
|
||||
|
||||
uint32_t mc_generalized_carveout1_bom;
|
||||
uint32_t mc_generalized_carveout1_bom_hi;
|
||||
uint32_t mc_generalized_carveout1_size_128kb;
|
||||
uint32_t mc_generalized_carveout1_access0;
|
||||
uint32_t mc_generalized_carveout1_access1;
|
||||
uint32_t mc_generalized_carveout1_access2;
|
||||
uint32_t mc_generalized_carveout1_access3;
|
||||
uint32_t mc_generalized_carveout1_access4;
|
||||
uint32_t mc_generalized_carveout1_force_internal_access0;
|
||||
uint32_t mc_generalized_carveout1_force_internal_access1;
|
||||
uint32_t mc_generalized_carveout1_force_internal_access2;
|
||||
uint32_t mc_generalized_carveout1_force_internal_access3;
|
||||
uint32_t mc_generalized_carveout1_force_internal_access4;
|
||||
uint32_t mc_generalized_carveout1_cfg0;
|
||||
|
||||
uint32_t mc_generalized_carveout2_bom;
|
||||
uint32_t mc_generalized_carveout2_bom_hi;
|
||||
uint32_t mc_generalized_carveout2_size_128kb;
|
||||
uint32_t mc_generalized_carveout2_access0;
|
||||
uint32_t mc_generalized_carveout2_access1;
|
||||
uint32_t mc_generalized_carveout2_access2;
|
||||
uint32_t mc_generalized_carveout2_access3;
|
||||
uint32_t mc_generalized_carveout2_access4;
|
||||
uint32_t mc_generalized_carveout2_force_internal_access0;
|
||||
uint32_t mc_generalized_carveout2_force_internal_access1;
|
||||
uint32_t mc_generalized_carveout2_force_internal_access2;
|
||||
uint32_t mc_generalized_carveout2_force_internal_access3;
|
||||
uint32_t mc_generalized_carveout2_force_internal_access4;
|
||||
uint32_t mc_generalized_carveout2_cfg0;
|
||||
|
||||
uint32_t mc_generalized_carveout3_bom;
|
||||
uint32_t mc_generalized_carveout3_bom_hi;
|
||||
uint32_t mc_generalized_carveout3_size_128kb;
|
||||
uint32_t mc_generalized_carveout3_access0;
|
||||
uint32_t mc_generalized_carveout3_access1;
|
||||
uint32_t mc_generalized_carveout3_access2;
|
||||
uint32_t mc_generalized_carveout3_access3;
|
||||
uint32_t mc_generalized_carveout3_access4;
|
||||
uint32_t mc_generalized_carveout3_force_internal_access0;
|
||||
uint32_t mc_generalized_carveout3_force_internal_access1;
|
||||
uint32_t mc_generalized_carveout3_force_internal_access2;
|
||||
uint32_t mc_generalized_carveout3_force_internal_access3;
|
||||
uint32_t mc_generalized_carveout3_force_internal_access4;
|
||||
uint32_t mc_generalized_carveout3_cfg0;
|
||||
|
||||
uint32_t mc_generalized_carveout4_bom;
|
||||
uint32_t mc_generalized_carveout4_bom_hi;
|
||||
uint32_t mc_generalized_carveout4_size_128kb;
|
||||
uint32_t mc_generalized_carveout4_access0;
|
||||
uint32_t mc_generalized_carveout4_access1;
|
||||
uint32_t mc_generalized_carveout4_access2;
|
||||
uint32_t mc_generalized_carveout4_access3;
|
||||
uint32_t mc_generalized_carveout4_access4;
|
||||
uint32_t mc_generalized_carveout4_force_internal_access0;
|
||||
uint32_t mc_generalized_carveout4_force_internal_access1;
|
||||
uint32_t mc_generalized_carveout4_force_internal_access2;
|
||||
uint32_t mc_generalized_carveout4_force_internal_access3;
|
||||
uint32_t mc_generalized_carveout4_force_internal_access4;
|
||||
uint32_t mc_generalized_carveout4_cfg0;
|
||||
|
||||
uint32_t mc_generalized_carveout5_bom;
|
||||
uint32_t mc_generalized_carveout5_bom_hi;
|
||||
uint32_t mc_generalized_carveout5_size_128kb;
|
||||
uint32_t mc_generalized_carveout5_access0;
|
||||
uint32_t mc_generalized_carveout5_access1;
|
||||
uint32_t mc_generalized_carveout5_access2;
|
||||
uint32_t mc_generalized_carveout5_access3;
|
||||
uint32_t mc_generalized_carveout5_access4;
|
||||
uint32_t mc_generalized_carveout5_force_internal_access0;
|
||||
uint32_t mc_generalized_carveout5_force_internal_access1;
|
||||
uint32_t mc_generalized_carveout5_force_internal_access2;
|
||||
uint32_t mc_generalized_carveout5_force_internal_access3;
|
||||
uint32_t mc_generalized_carveout5_force_internal_access4;
|
||||
uint32_t mc_generalized_carveout5_cfg0;
|
||||
|
||||
/* Specifies enable for CA training */
|
||||
uint32_t emc_ca_training_enable;
|
||||
/* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */
|
||||
uint32_t swizzle_rank_byte_encode;
|
||||
/* Specifies enable and offset for patched boot rom write */
|
||||
uint32_t boot_rom_patch_control;
|
||||
/* Specifies data for patched boot rom write */
|
||||
uint32_t boot_rom_patch_data;
|
||||
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
|
||||
uint32_t mc_mts_carveout_bom;
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
|
||||
uint32_t mc_mts_carveout_adr_hi;
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
|
||||
uint32_t mc_mts_carveout_size_mb;
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
|
||||
uint32_t mc_mts_carveout_reg_ctrl;
|
||||
} sdram_params_t;
|
||||
|
||||
#endif
|
||||
964
sept/sept-secondary/src/sdram_param_t210_lp0.h
Normal file
964
sept/sept-secondary/src/sdram_param_t210_lp0.h
Normal file
|
|
@ -0,0 +1,964 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright 2014 Google Inc.
|
||||
* Copyright (c) 2018 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Defines the SDRAM parameter structure.
|
||||
*
|
||||
* Note that PLLM is used by EMC. The field names are in camel case to ease
|
||||
* directly converting BCT config files (*.cfg) into C structure.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
|
||||
#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
enum
|
||||
{
|
||||
/* Specifies the memory type to be undefined */
|
||||
NvBootMemoryType_None = 0,
|
||||
|
||||
/* Specifies the memory type to be DDR SDRAM */
|
||||
NvBootMemoryType_Ddr = 0,
|
||||
|
||||
/* Specifies the memory type to be LPDDR SDRAM */
|
||||
NvBootMemoryType_LpDdr = 0,
|
||||
|
||||
/* Specifies the memory type to be DDR2 SDRAM */
|
||||
NvBootMemoryType_Ddr2 = 0,
|
||||
|
||||
/* Specifies the memory type to be LPDDR2 SDRAM */
|
||||
NvBootMemoryType_LpDdr2,
|
||||
|
||||
/* Specifies the memory type to be DDR3 SDRAM */
|
||||
NvBootMemoryType_Ddr3,
|
||||
|
||||
/* Specifies the memory type to be LPDDR4 SDRAM */
|
||||
NvBootMemoryType_LpDdr4,
|
||||
|
||||
NvBootMemoryType_Num,
|
||||
|
||||
/* Specifies an entry in the ram_code table that's not in use */
|
||||
NvBootMemoryType_Unused = 0X7FFFFFF,
|
||||
};
|
||||
|
||||
/**
|
||||
* Defines the SDRAM parameter structure
|
||||
*/
|
||||
struct sdram_params
|
||||
{
|
||||
|
||||
/* Specifies the type of memory device */
|
||||
uint32_t MemoryType;
|
||||
|
||||
/* MC/EMC clock source configuration */
|
||||
|
||||
/* Specifies the M value for PllM */
|
||||
uint32_t PllMInputDivider;
|
||||
/* Specifies the N value for PllM */
|
||||
uint32_t PllMFeedbackDivider;
|
||||
/* Specifies the time to wait for PLLM to lock (in microseconds) */
|
||||
uint32_t PllMStableTime;
|
||||
/* Specifies misc. control bits */
|
||||
uint32_t PllMSetupControl;
|
||||
/* Specifies the P value for PLLM */
|
||||
uint32_t PllMPostDivider;
|
||||
/* Specifies value for Charge Pump Gain Control */
|
||||
uint32_t PllMKCP;
|
||||
/* Specifies VCO gain */
|
||||
uint32_t PllMKVCO;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare0;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare1;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare2;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare3;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare4;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare5;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare6;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare7;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare8;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare9;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare10;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare11;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare12;
|
||||
/* Spare BCT param */
|
||||
uint32_t EmcBctSpare13;
|
||||
|
||||
/* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */
|
||||
uint32_t EmcClockSource;
|
||||
uint32_t EmcClockSourceDll;
|
||||
|
||||
/* Defines possible override for PLLLM_MISC2 */
|
||||
uint32_t ClkRstControllerPllmMisc2Override;
|
||||
/* enables override for PLLLM_MISC2 */
|
||||
uint32_t ClkRstControllerPllmMisc2OverrideEnable;
|
||||
/* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */
|
||||
uint32_t ClearClk2Mc1;
|
||||
|
||||
/* Auto-calibration of EMC pads */
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
|
||||
uint32_t EmcAutoCalInterval;
|
||||
/*
|
||||
* Specifies the value for EMC_AUTO_CAL_CONFIG
|
||||
* Note: Trigger bits are set by the SDRAM code.
|
||||
*/
|
||||
uint32_t EmcAutoCalConfig;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_CONFIG2 */
|
||||
uint32_t EmcAutoCalConfig2;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_CONFIG3 */
|
||||
uint32_t EmcAutoCalConfig3;
|
||||
|
||||
/* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */
|
||||
uint32_t EmcAutoCalConfig4;
|
||||
uint32_t EmcAutoCalConfig5;
|
||||
uint32_t EmcAutoCalConfig6;
|
||||
uint32_t EmcAutoCalConfig7;
|
||||
uint32_t EmcAutoCalConfig8;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */
|
||||
uint32_t EmcAutoCalVrefSel0;
|
||||
uint32_t EmcAutoCalVrefSel1;
|
||||
|
||||
/* Specifies the value for EMC_AUTO_CAL_CHANNEL */
|
||||
uint32_t EmcAutoCalChannel;
|
||||
|
||||
/* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */
|
||||
uint32_t EmcPmacroAutocalCfg0;
|
||||
uint32_t EmcPmacroAutocalCfg1;
|
||||
uint32_t EmcPmacroAutocalCfg2;
|
||||
uint32_t EmcPmacroRxTerm;
|
||||
uint32_t EmcPmacroDqTxDrv;
|
||||
uint32_t EmcPmacroCaTxDrv;
|
||||
uint32_t EmcPmacroCmdTxDrv;
|
||||
uint32_t EmcPmacroAutocalCfgCommon;
|
||||
uint32_t EmcPmacroZctrl;
|
||||
|
||||
/*
|
||||
* Specifies the time for the calibration
|
||||
* to stabilize (in microseconds)
|
||||
*/
|
||||
uint32_t EmcAutoCalWait;
|
||||
|
||||
uint32_t EmcXm2CompPadCtrl;
|
||||
uint32_t EmcXm2CompPadCtrl2;
|
||||
uint32_t EmcXm2CompPadCtrl3;
|
||||
|
||||
/*
|
||||
* DRAM size information
|
||||
* Specifies the value for EMC_ADR_CFG
|
||||
*/
|
||||
uint32_t EmcAdrCfg;
|
||||
|
||||
/*
|
||||
* Specifies the time to wait after asserting pin
|
||||
* CKE (in microseconds)
|
||||
*/
|
||||
uint32_t EmcPinProgramWait;
|
||||
/* Specifies the extra delay before/after pin RESET/CKE command */
|
||||
uint32_t EmcPinExtraWait;
|
||||
|
||||
uint32_t EmcPinGpioEn;
|
||||
uint32_t EmcPinGpio;
|
||||
|
||||
/*
|
||||
* Specifies the extra delay after the first writing
|
||||
* of EMC_TIMING_CONTROL
|
||||
*/
|
||||
uint32_t EmcTimingControlWait;
|
||||
|
||||
/* Timing parameters required for the SDRAM */
|
||||
|
||||
/* Specifies the value for EMC_RC */
|
||||
uint32_t EmcRc;
|
||||
/* Specifies the value for EMC_RFC */
|
||||
uint32_t EmcRfc;
|
||||
/* Specifies the value for EMC_RFC_PB */
|
||||
uint32_t EmcRfcPb;
|
||||
/* Specifies the value for EMC_RFC_CTRL2 */
|
||||
uint32_t EmcRefctrl2;
|
||||
/* Specifies the value for EMC_RFC_SLR */
|
||||
uint32_t EmcRfcSlr;
|
||||
/* Specifies the value for EMC_RAS */
|
||||
uint32_t EmcRas;
|
||||
/* Specifies the value for EMC_RP */
|
||||
uint32_t EmcRp;
|
||||
/* Specifies the value for EMC_R2R */
|
||||
uint32_t EmcR2r;
|
||||
/* Specifies the value for EMC_W2W */
|
||||
uint32_t EmcW2w;
|
||||
/* Specifies the value for EMC_R2W */
|
||||
uint32_t EmcR2w;
|
||||
/* Specifies the value for EMC_W2R */
|
||||
uint32_t EmcW2r;
|
||||
/* Specifies the value for EMC_R2P */
|
||||
uint32_t EmcR2p;
|
||||
/* Specifies the value for EMC_W2P */
|
||||
uint32_t EmcW2p;
|
||||
|
||||
uint32_t EmcTppd;
|
||||
uint32_t EmcCcdmw;
|
||||
|
||||
/* Specifies the value for EMC_RD_RCD */
|
||||
uint32_t EmcRdRcd;
|
||||
/* Specifies the value for EMC_WR_RCD */
|
||||
uint32_t EmcWrRcd;
|
||||
/* Specifies the value for EMC_RRD */
|
||||
uint32_t EmcRrd;
|
||||
/* Specifies the value for EMC_REXT */
|
||||
uint32_t EmcRext;
|
||||
/* Specifies the value for EMC_WEXT */
|
||||
uint32_t EmcWext;
|
||||
/* Specifies the value for EMC_WDV */
|
||||
uint32_t EmcWdv;
|
||||
|
||||
uint32_t EmcWdvChk;
|
||||
uint32_t EmcWsv;
|
||||
uint32_t EmcWev;
|
||||
|
||||
/* Specifies the value for EMC_WDV_MASK */
|
||||
uint32_t EmcWdvMask;
|
||||
|
||||
uint32_t EmcWsDuration;
|
||||
uint32_t EmcWeDuration;
|
||||
|
||||
/* Specifies the value for EMC_QUSE */
|
||||
uint32_t EmcQUse;
|
||||
/* Specifies the value for EMC_QUSE_WIDTH */
|
||||
uint32_t EmcQuseWidth;
|
||||
/* Specifies the value for EMC_IBDLY */
|
||||
uint32_t EmcIbdly;
|
||||
/* Specifies the value for EMC_OBDLY */
|
||||
uint32_t EmcObdly;
|
||||
/* Specifies the value for EMC_EINPUT */
|
||||
uint32_t EmcEInput;
|
||||
/* Specifies the value for EMC_EINPUT_DURATION */
|
||||
uint32_t EmcEInputDuration;
|
||||
/* Specifies the value for EMC_PUTERM_EXTRA */
|
||||
uint32_t EmcPutermExtra;
|
||||
/* Specifies the value for EMC_PUTERM_WIDTH */
|
||||
uint32_t EmcPutermWidth;
|
||||
/* Specifies the value for EMC_PUTERM_ADJ */
|
||||
////uint32_t EmcPutermAdj;
|
||||
|
||||
/* Specifies the value for EMC_QRST */
|
||||
uint32_t EmcQRst;
|
||||
/* Specifies the value for EMC_QSAFE */
|
||||
uint32_t EmcQSafe;
|
||||
/* Specifies the value for EMC_RDV */
|
||||
uint32_t EmcRdv;
|
||||
/* Specifies the value for EMC_RDV_MASK */
|
||||
uint32_t EmcRdvMask;
|
||||
/* Specifies the value for EMC_RDV_EARLY */
|
||||
uint32_t EmcRdvEarly;
|
||||
/* Specifies the value for EMC_RDV_EARLY_MASK */
|
||||
uint32_t EmcRdvEarlyMask;
|
||||
/* Specifies the value for EMC_QPOP */
|
||||
uint32_t EmcQpop;
|
||||
|
||||
/* Specifies the value for EMC_REFRESH */
|
||||
uint32_t EmcRefresh;
|
||||
/* Specifies the value for EMC_BURST_REFRESH_NUM */
|
||||
uint32_t EmcBurstRefreshNum;
|
||||
/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
|
||||
uint32_t EmcPreRefreshReqCnt;
|
||||
/* Specifies the value for EMC_PDEX2WR */
|
||||
uint32_t EmcPdEx2Wr;
|
||||
/* Specifies the value for EMC_PDEX2RD */
|
||||
uint32_t EmcPdEx2Rd;
|
||||
/* Specifies the value for EMC_PCHG2PDEN */
|
||||
uint32_t EmcPChg2Pden;
|
||||
/* Specifies the value for EMC_ACT2PDEN */
|
||||
uint32_t EmcAct2Pden;
|
||||
/* Specifies the value for EMC_AR2PDEN */
|
||||
uint32_t EmcAr2Pden;
|
||||
/* Specifies the value for EMC_RW2PDEN */
|
||||
uint32_t EmcRw2Pden;
|
||||
/* Specifies the value for EMC_CKE2PDEN */
|
||||
uint32_t EmcCke2Pden;
|
||||
/* Specifies the value for EMC_PDEX2CKE */
|
||||
uint32_t EmcPdex2Cke;
|
||||
/* Specifies the value for EMC_PDEX2MRR */
|
||||
uint32_t EmcPdex2Mrr;
|
||||
/* Specifies the value for EMC_TXSR */
|
||||
uint32_t EmcTxsr;
|
||||
/* Specifies the value for EMC_TXSRDLL */
|
||||
uint32_t EmcTxsrDll;
|
||||
/* Specifies the value for EMC_TCKE */
|
||||
uint32_t EmcTcke;
|
||||
/* Specifies the value for EMC_TCKESR */
|
||||
uint32_t EmcTckesr;
|
||||
/* Specifies the value for EMC_TPD */
|
||||
uint32_t EmcTpd;
|
||||
/* Specifies the value for EMC_TFAW */
|
||||
uint32_t EmcTfaw;
|
||||
/* Specifies the value for EMC_TRPAB */
|
||||
uint32_t EmcTrpab;
|
||||
/* Specifies the value for EMC_TCLKSTABLE */
|
||||
uint32_t EmcTClkStable;
|
||||
/* Specifies the value for EMC_TCLKSTOP */
|
||||
uint32_t EmcTClkStop;
|
||||
/* Specifies the value for EMC_TREFBW */
|
||||
uint32_t EmcTRefBw;
|
||||
|
||||
/* FBIO configuration values */
|
||||
|
||||
/* Specifies the value for EMC_FBIO_CFG5 */
|
||||
uint32_t EmcFbioCfg5;
|
||||
/* Specifies the value for EMC_FBIO_CFG7 */
|
||||
uint32_t EmcFbioCfg7;
|
||||
/* Specifies the value for EMC_FBIO_CFG8 */
|
||||
uint32_t EmcFbioCfg8;
|
||||
|
||||
/* Command mapping for CMD brick 0 */
|
||||
uint32_t EmcCmdMappingCmd0_0;
|
||||
uint32_t EmcCmdMappingCmd0_1;
|
||||
uint32_t EmcCmdMappingCmd0_2;
|
||||
uint32_t EmcCmdMappingCmd1_0;
|
||||
uint32_t EmcCmdMappingCmd1_1;
|
||||
uint32_t EmcCmdMappingCmd1_2;
|
||||
uint32_t EmcCmdMappingCmd2_0;
|
||||
uint32_t EmcCmdMappingCmd2_1;
|
||||
uint32_t EmcCmdMappingCmd2_2;
|
||||
uint32_t EmcCmdMappingCmd3_0;
|
||||
uint32_t EmcCmdMappingCmd3_1;
|
||||
uint32_t EmcCmdMappingCmd3_2;
|
||||
uint32_t EmcCmdMappingByte;
|
||||
|
||||
/* Specifies the value for EMC_FBIO_SPARE */
|
||||
uint32_t EmcFbioSpare;
|
||||
|
||||
/* Specifies the value for EMC_CFG_RSV */
|
||||
uint32_t EmcCfgRsv;
|
||||
|
||||
/* MRS command values */
|
||||
|
||||
/* Specifies the value for EMC_MRS */
|
||||
uint32_t EmcMrs;
|
||||
/* Specifies the MP0 command to initialize mode registers */
|
||||
uint32_t EmcEmrs;
|
||||
/* Specifies the MP2 command to initialize mode registers */
|
||||
uint32_t EmcEmrs2;
|
||||
/* Specifies the MP3 command to initialize mode registers */
|
||||
uint32_t EmcEmrs3;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
|
||||
uint32_t EmcMrw1;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
|
||||
uint32_t EmcMrw2;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
|
||||
uint32_t EmcMrw3;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
|
||||
uint32_t EmcMrw4;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */
|
||||
uint32_t EmcMrw6;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */
|
||||
uint32_t EmcMrw8;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */
|
||||
uint32_t EmcMrw9;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */
|
||||
uint32_t EmcMrw10;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */
|
||||
uint32_t EmcMrw12;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */
|
||||
uint32_t EmcMrw13;
|
||||
/* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */
|
||||
uint32_t EmcMrw14;
|
||||
/*
|
||||
* Specifies the programming to extra LPDDR2 Mode Register
|
||||
* at cold boot
|
||||
*/
|
||||
uint32_t EmcMrwExtra;
|
||||
/*
|
||||
* Specifies the programming to extra LPDDR2 Mode Register
|
||||
* at warm boot
|
||||
*/
|
||||
uint32_t EmcWarmBootMrwExtra;
|
||||
/*
|
||||
* Specify the enable of extra Mode Register programming at
|
||||
* warm boot
|
||||
*/
|
||||
uint32_t EmcWarmBootExtraModeRegWriteEnable;
|
||||
/*
|
||||
* Specify the enable of extra Mode Register programming at
|
||||
* cold boot
|
||||
*/
|
||||
uint32_t EmcExtraModeRegWriteEnable;
|
||||
|
||||
/* Specifies the EMC_MRW reset command value */
|
||||
uint32_t EmcMrwResetCommand;
|
||||
/* Specifies the EMC Reset wait time (in microseconds) */
|
||||
uint32_t EmcMrwResetNInitWait;
|
||||
/* Specifies the value for EMC_MRS_WAIT_CNT */
|
||||
uint32_t EmcMrsWaitCnt;
|
||||
/* Specifies the value for EMC_MRS_WAIT_CNT2 */
|
||||
uint32_t EmcMrsWaitCnt2;
|
||||
|
||||
/* EMC miscellaneous configurations */
|
||||
|
||||
/* Specifies the value for EMC_CFG */
|
||||
uint32_t EmcCfg;
|
||||
/* Specifies the value for EMC_CFG_2 */
|
||||
uint32_t EmcCfg2;
|
||||
/* Specifies the pipe bypass controls */
|
||||
uint32_t EmcCfgPipe;
|
||||
uint32_t EmcCfgPipeClk;
|
||||
uint32_t EmcFdpdCtrlCmdNoRamp;
|
||||
uint32_t EmcCfgUpdate;
|
||||
|
||||
/* Specifies the value for EMC_DBG */
|
||||
uint32_t EmcDbg;
|
||||
uint32_t EmcDbgWriteMux;
|
||||
|
||||
/* Specifies the value for EMC_CMDQ */
|
||||
uint32_t EmcCmdQ;
|
||||
/* Specifies the value for EMC_MC2EMCQ */
|
||||
uint32_t EmcMc2EmcQ;
|
||||
/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
|
||||
uint32_t EmcDynSelfRefControl;
|
||||
|
||||
/* Specifies the value for MEM_INIT_DONE */
|
||||
uint32_t AhbArbitrationXbarCtrlMemInitDone;
|
||||
|
||||
/* Specifies the value for EMC_CFG_DIG_DLL */
|
||||
uint32_t EmcCfgDigDll;
|
||||
uint32_t EmcCfgDigDll_1;
|
||||
/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
|
||||
uint32_t EmcCfgDigDllPeriod;
|
||||
/* Specifies the value of *DEV_SELECTN of various EMC registers */
|
||||
uint32_t EmcDevSelect;
|
||||
|
||||
/* Specifies the value for EMC_SEL_DPD_CTRL */
|
||||
uint32_t EmcSelDpdCtrl;
|
||||
|
||||
/* Pads trimmer delays */
|
||||
uint32_t EmcFdpdCtrlDq;
|
||||
uint32_t EmcFdpdCtrlCmd;
|
||||
uint32_t EmcPmacroIbVrefDq_0;
|
||||
uint32_t EmcPmacroIbVrefDq_1;
|
||||
uint32_t EmcPmacroIbVrefDqs_0;
|
||||
uint32_t EmcPmacroIbVrefDqs_1;
|
||||
uint32_t EmcPmacroIbRxrt;
|
||||
uint32_t EmcCfgPipe1;
|
||||
uint32_t EmcCfgPipe2;
|
||||
|
||||
/* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */
|
||||
uint32_t EmcPmacroQuseDdllRank0_0;
|
||||
uint32_t EmcPmacroQuseDdllRank0_1;
|
||||
uint32_t EmcPmacroQuseDdllRank0_2;
|
||||
uint32_t EmcPmacroQuseDdllRank0_3;
|
||||
uint32_t EmcPmacroQuseDdllRank0_4;
|
||||
uint32_t EmcPmacroQuseDdllRank0_5;
|
||||
uint32_t EmcPmacroQuseDdllRank1_0;
|
||||
uint32_t EmcPmacroQuseDdllRank1_1;
|
||||
uint32_t EmcPmacroQuseDdllRank1_2;
|
||||
uint32_t EmcPmacroQuseDdllRank1_3;
|
||||
uint32_t EmcPmacroQuseDdllRank1_4;
|
||||
uint32_t EmcPmacroQuseDdllRank1_5;
|
||||
|
||||
uint32_t EmcPmacroObDdllLongDqRank0_0;
|
||||
uint32_t EmcPmacroObDdllLongDqRank0_1;
|
||||
uint32_t EmcPmacroObDdllLongDqRank0_2;
|
||||
uint32_t EmcPmacroObDdllLongDqRank0_3;
|
||||
uint32_t EmcPmacroObDdllLongDqRank0_4;
|
||||
uint32_t EmcPmacroObDdllLongDqRank0_5;
|
||||
uint32_t EmcPmacroObDdllLongDqRank1_0;
|
||||
uint32_t EmcPmacroObDdllLongDqRank1_1;
|
||||
uint32_t EmcPmacroObDdllLongDqRank1_2;
|
||||
uint32_t EmcPmacroObDdllLongDqRank1_3;
|
||||
uint32_t EmcPmacroObDdllLongDqRank1_4;
|
||||
uint32_t EmcPmacroObDdllLongDqRank1_5;
|
||||
|
||||
uint32_t EmcPmacroObDdllLongDqsRank0_0;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank0_1;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank0_2;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank0_3;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank0_4;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank0_5;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank1_0;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank1_1;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank1_2;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank1_3;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank1_4;
|
||||
uint32_t EmcPmacroObDdllLongDqsRank1_5;
|
||||
|
||||
uint32_t EmcPmacroIbDdllLongDqsRank0_0;
|
||||
uint32_t EmcPmacroIbDdllLongDqsRank0_1;
|
||||
uint32_t EmcPmacroIbDdllLongDqsRank0_2;
|
||||
uint32_t EmcPmacroIbDdllLongDqsRank0_3;
|
||||
uint32_t EmcPmacroIbDdllLongDqsRank1_0;
|
||||
uint32_t EmcPmacroIbDdllLongDqsRank1_1;
|
||||
uint32_t EmcPmacroIbDdllLongDqsRank1_2;
|
||||
uint32_t EmcPmacroIbDdllLongDqsRank1_3;
|
||||
|
||||
uint32_t EmcPmacroDdllLongCmd_0;
|
||||
uint32_t EmcPmacroDdllLongCmd_1;
|
||||
uint32_t EmcPmacroDdllLongCmd_2;
|
||||
uint32_t EmcPmacroDdllLongCmd_3;
|
||||
uint32_t EmcPmacroDdllLongCmd_4;
|
||||
uint32_t EmcPmacroDdllShortCmd_0;
|
||||
uint32_t EmcPmacroDdllShortCmd_1;
|
||||
uint32_t EmcPmacroDdllShortCmd_2;
|
||||
|
||||
/*
|
||||
* Specifies the delay after asserting CKE pin during a WarmBoot0
|
||||
* sequence (in microseconds)
|
||||
*/
|
||||
uint32_t WarmBootWait;
|
||||
|
||||
/* Specifies the value for EMC_ODT_WRITE */
|
||||
uint32_t EmcOdtWrite;
|
||||
|
||||
/* Periodic ZQ calibration */
|
||||
|
||||
/*
|
||||
* Specifies the value for EMC_ZCAL_INTERVAL
|
||||
* Value 0 disables ZQ calibration
|
||||
*/
|
||||
uint32_t EmcZcalInterval;
|
||||
/* Specifies the value for EMC_ZCAL_WAIT_CNT */
|
||||
uint32_t EmcZcalWaitCnt;
|
||||
/* Specifies the value for EMC_ZCAL_MRW_CMD */
|
||||
uint32_t EmcZcalMrwCmd;
|
||||
|
||||
/* DRAM initialization sequence flow control */
|
||||
|
||||
/* Specifies the MRS command value for resetting DLL */
|
||||
uint32_t EmcMrsResetDll;
|
||||
/* Specifies the command for ZQ initialization of device 0 */
|
||||
uint32_t EmcZcalInitDev0;
|
||||
/* Specifies the command for ZQ initialization of device 1 */
|
||||
uint32_t EmcZcalInitDev1;
|
||||
/*
|
||||
* Specifies the wait time after programming a ZQ initialization
|
||||
* command (in microseconds)
|
||||
*/
|
||||
uint32_t EmcZcalInitWait;
|
||||
/*
|
||||
* Specifies the enable for ZQ calibration at cold boot [bit 0]
|
||||
* and warm boot [bit 1]
|
||||
*/
|
||||
uint32_t EmcZcalWarmColdBootEnables;
|
||||
|
||||
/*
|
||||
* Specifies the MRW command to LPDDR2 for ZQ calibration
|
||||
* on warmboot
|
||||
*/
|
||||
/* Is issued to both devices separately */
|
||||
uint32_t EmcMrwLpddr2ZcalWarmBoot;
|
||||
/*
|
||||
* Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
|
||||
* Is issued to both devices separately
|
||||
*/
|
||||
uint32_t EmcZqCalDdr3WarmBoot;
|
||||
uint32_t EmcZqCalLpDdr4WarmBoot;
|
||||
/*
|
||||
* Specifies the wait time for ZQ calibration on warmboot
|
||||
* (in microseconds)
|
||||
*/
|
||||
uint32_t EmcZcalWarmBootWait;
|
||||
/*
|
||||
* Specifies the enable for DRAM Mode Register programming
|
||||
* at warm boot
|
||||
*/
|
||||
uint32_t EmcMrsWarmBootEnable;
|
||||
/*
|
||||
* Specifies the wait time after sending an MRS DLL reset command
|
||||
* in microseconds)
|
||||
*/
|
||||
uint32_t EmcMrsResetDllWait;
|
||||
/* Specifies the extra MRS command to initialize mode registers */
|
||||
uint32_t EmcMrsExtra;
|
||||
/* Specifies the extra MRS command at warm boot */
|
||||
uint32_t EmcWarmBootMrsExtra;
|
||||
/* Specifies the EMRS command to enable the DDR2 DLL */
|
||||
uint32_t EmcEmrsDdr2DllEnable;
|
||||
/* Specifies the MRS command to reset the DDR2 DLL */
|
||||
uint32_t EmcMrsDdr2DllReset;
|
||||
/* Specifies the EMRS command to set OCD calibration */
|
||||
uint32_t EmcEmrsDdr2OcdCalib;
|
||||
/*
|
||||
* Specifies the wait between initializing DDR and setting OCD
|
||||
* calibration (in microseconds)
|
||||
*/
|
||||
uint32_t EmcDdr2Wait;
|
||||
/* Specifies the value for EMC_CLKEN_OVERRIDE */
|
||||
uint32_t EmcClkenOverride;
|
||||
|
||||
/*
|
||||
* Specifies LOG2 of the extra refresh numbers after booting
|
||||
* Program 0 to disable
|
||||
*/
|
||||
uint32_t EmcExtraRefreshNum;
|
||||
/* Specifies the master override for all EMC clocks */
|
||||
uint32_t EmcClkenOverrideAllWarmBoot;
|
||||
/* Specifies the master override for all MC clocks */
|
||||
uint32_t McClkenOverrideAllWarmBoot;
|
||||
/* Specifies digital dll period, choosing between 4 to 64 ms */
|
||||
uint32_t EmcCfgDigDllPeriodWarmBoot;
|
||||
|
||||
/* Pad controls */
|
||||
|
||||
/* Specifies the value for PMC_VDDP_SEL */
|
||||
uint32_t PmcVddpSel;
|
||||
/* Specifies the wait time after programming PMC_VDDP_SEL */
|
||||
uint32_t PmcVddpSelWait;
|
||||
/* Specifies the value for PMC_DDR_PWR */
|
||||
uint32_t PmcDdrPwr;
|
||||
/* Specifies the value for PMC_DDR_CFG */
|
||||
uint32_t PmcDdrCfg;
|
||||
/* Specifies the value for PMC_IO_DPD3_REQ */
|
||||
uint32_t PmcIoDpd3Req;
|
||||
/* Specifies the wait time after programming PMC_IO_DPD3_REQ */
|
||||
uint32_t PmcIoDpd3ReqWait;
|
||||
uint32_t PmcIoDpd4ReqWait;
|
||||
|
||||
/* Specifies the value for PMC_REG_SHORT */
|
||||
uint32_t PmcRegShort;
|
||||
/* Specifies the value for PMC_NO_IOPOWER */
|
||||
uint32_t PmcNoIoPower;
|
||||
|
||||
uint32_t PmcDdrCntrlWait;
|
||||
uint32_t PmcDdrCntrl;
|
||||
|
||||
/* Specifies the value for EMC_ACPD_CONTROL */
|
||||
uint32_t EmcAcpdControl;
|
||||
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */
|
||||
////uint32_t EmcSwizzleRank0ByteCfg;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */
|
||||
uint32_t EmcSwizzleRank0Byte0;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */
|
||||
uint32_t EmcSwizzleRank0Byte1;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */
|
||||
uint32_t EmcSwizzleRank0Byte2;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */
|
||||
uint32_t EmcSwizzleRank0Byte3;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */
|
||||
////uint32_t EmcSwizzleRank1ByteCfg;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */
|
||||
uint32_t EmcSwizzleRank1Byte0;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */
|
||||
uint32_t EmcSwizzleRank1Byte1;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */
|
||||
uint32_t EmcSwizzleRank1Byte2;
|
||||
/* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */
|
||||
uint32_t EmcSwizzleRank1Byte3;
|
||||
|
||||
/* Specifies the value for EMC_TXDSRVTTGEN */
|
||||
uint32_t EmcTxdsrvttgen;
|
||||
|
||||
/* Specifies the value for EMC_DATA_BRLSHFT_0 */
|
||||
uint32_t EmcDataBrlshft0;
|
||||
uint32_t EmcDataBrlshft1;
|
||||
|
||||
uint32_t EmcDqsBrlshft0;
|
||||
uint32_t EmcDqsBrlshft1;
|
||||
|
||||
uint32_t EmcCmdBrlshft0;
|
||||
uint32_t EmcCmdBrlshft1;
|
||||
uint32_t EmcCmdBrlshft2;
|
||||
uint32_t EmcCmdBrlshft3;
|
||||
|
||||
uint32_t EmcQuseBrlshft0;
|
||||
uint32_t EmcQuseBrlshft1;
|
||||
uint32_t EmcQuseBrlshft2;
|
||||
uint32_t EmcQuseBrlshft3;
|
||||
|
||||
uint32_t EmcDllCfg0;
|
||||
uint32_t EmcDllCfg1;
|
||||
|
||||
uint32_t EmcPmcScratch1;
|
||||
uint32_t EmcPmcScratch2;
|
||||
uint32_t EmcPmcScratch3;
|
||||
|
||||
uint32_t EmcPmacroPadCfgCtrl;
|
||||
|
||||
uint32_t EmcPmacroVttgenCtrl0;
|
||||
uint32_t EmcPmacroVttgenCtrl1;
|
||||
uint32_t EmcPmacroVttgenCtrl2;
|
||||
|
||||
uint32_t EmcPmacroBrickCtrlRfu1;
|
||||
uint32_t EmcPmacroCmdBrickCtrlFdpd;
|
||||
uint32_t EmcPmacroBrickCtrlRfu2;
|
||||
uint32_t EmcPmacroDataBrickCtrlFdpd;
|
||||
uint32_t EmcPmacroBgBiasCtrl0;
|
||||
uint32_t EmcPmacroDataPadRxCtrl;
|
||||
uint32_t EmcPmacroCmdPadRxCtrl;
|
||||
uint32_t EmcPmacroDataRxTermMode;
|
||||
uint32_t EmcPmacroCmdRxTermMode;
|
||||
uint32_t EmcPmacroDataPadTxCtrl;
|
||||
uint32_t EmcPmacroCommonPadTxCtrl;
|
||||
uint32_t EmcPmacroCmdPadTxCtrl;
|
||||
uint32_t EmcCfg3;
|
||||
|
||||
uint32_t EmcPmacroTxPwrd0;
|
||||
uint32_t EmcPmacroTxPwrd1;
|
||||
uint32_t EmcPmacroTxPwrd2;
|
||||
uint32_t EmcPmacroTxPwrd3;
|
||||
uint32_t EmcPmacroTxPwrd4;
|
||||
uint32_t EmcPmacroTxPwrd5;
|
||||
|
||||
uint32_t EmcConfigSampleDelay;
|
||||
|
||||
uint32_t EmcPmacroBrickMapping0;
|
||||
uint32_t EmcPmacroBrickMapping1;
|
||||
uint32_t EmcPmacroBrickMapping2;
|
||||
|
||||
uint32_t EmcPmacroTxSelClkSrc0;
|
||||
uint32_t EmcPmacroTxSelClkSrc1;
|
||||
uint32_t EmcPmacroTxSelClkSrc2;
|
||||
uint32_t EmcPmacroTxSelClkSrc3;
|
||||
uint32_t EmcPmacroTxSelClkSrc4;
|
||||
uint32_t EmcPmacroTxSelClkSrc5;
|
||||
|
||||
uint32_t EmcPmacroDdllBypass;
|
||||
|
||||
uint32_t EmcPmacroDdllPwrd0;
|
||||
uint32_t EmcPmacroDdllPwrd1;
|
||||
uint32_t EmcPmacroDdllPwrd2;
|
||||
|
||||
uint32_t EmcPmacroCmdCtrl0;
|
||||
uint32_t EmcPmacroCmdCtrl1;
|
||||
uint32_t EmcPmacroCmdCtrl2;
|
||||
|
||||
/* DRAM size information */
|
||||
|
||||
/* Specifies the value for MC_EMEM_ADR_CFG */
|
||||
uint32_t McEmemAdrCfg;
|
||||
/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
|
||||
uint32_t McEmemAdrCfgDev0;
|
||||
/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
|
||||
uint32_t McEmemAdrCfgDev1;
|
||||
uint32_t McEmemAdrCfgChannelMask;
|
||||
|
||||
/* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */
|
||||
uint32_t McEmemAdrCfgBankMask0;
|
||||
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */
|
||||
uint32_t McEmemAdrCfgBankMask1;
|
||||
/* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */
|
||||
uint32_t McEmemAdrCfgBankMask2;
|
||||
|
||||
/*
|
||||
* Specifies the value for MC_EMEM_CFG which holds the external memory
|
||||
* size (in KBytes)
|
||||
*/
|
||||
uint32_t McEmemCfg;
|
||||
|
||||
/* MC arbitration configuration */
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_CFG */
|
||||
uint32_t McEmemArbCfg;
|
||||
/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
|
||||
uint32_t McEmemArbOutstandingReq;
|
||||
|
||||
uint32_t McEmemArbRefpbHpCtrl;
|
||||
uint32_t McEmemArbRefpbBankCtrl;
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
|
||||
uint32_t McEmemArbTimingRcd;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
|
||||
uint32_t McEmemArbTimingRp;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
|
||||
uint32_t McEmemArbTimingRc;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
|
||||
uint32_t McEmemArbTimingRas;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
|
||||
uint32_t McEmemArbTimingFaw;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
|
||||
uint32_t McEmemArbTimingRrd;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
|
||||
uint32_t McEmemArbTimingRap2Pre;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
|
||||
uint32_t McEmemArbTimingWap2Pre;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
|
||||
uint32_t McEmemArbTimingR2R;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
|
||||
uint32_t McEmemArbTimingW2W;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
|
||||
uint32_t McEmemArbTimingR2W;
|
||||
/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
|
||||
uint32_t McEmemArbTimingW2R;
|
||||
|
||||
uint32_t McEmemArbTimingRFCPB;
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
|
||||
uint32_t McEmemArbDaTurns;
|
||||
/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
|
||||
uint32_t McEmemArbDaCovers;
|
||||
/* Specifies the value for MC_EMEM_ARB_MISC0 */
|
||||
uint32_t McEmemArbMisc0;
|
||||
/* Specifies the value for MC_EMEM_ARB_MISC1 */
|
||||
uint32_t McEmemArbMisc1;
|
||||
uint32_t McEmemArbMisc2;
|
||||
|
||||
/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
|
||||
uint32_t McEmemArbRing1Throttle;
|
||||
/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
|
||||
uint32_t McEmemArbOverride;
|
||||
/* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */
|
||||
uint32_t McEmemArbOverride1;
|
||||
/* Specifies the value for MC_EMEM_ARB_RSV */
|
||||
uint32_t McEmemArbRsv;
|
||||
|
||||
uint32_t McDaCfg0;
|
||||
uint32_t McEmemArbTimingCcdmw;
|
||||
|
||||
/* Specifies the value for MC_CLKEN_OVERRIDE */
|
||||
uint32_t McClkenOverride;
|
||||
|
||||
/* Specifies the value for MC_STAT_CONTROL */
|
||||
uint32_t McStatControl;
|
||||
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_BOM */
|
||||
uint32_t McVideoProtectBom;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */
|
||||
uint32_t McVideoProtectBomAdrHi;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */
|
||||
uint32_t McVideoProtectSizeMb;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */
|
||||
uint32_t McVideoProtectVprOverride;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */
|
||||
uint32_t McVideoProtectVprOverride1;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */
|
||||
uint32_t McVideoProtectGpuOverride0;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */
|
||||
uint32_t McVideoProtectGpuOverride1;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_BOM */
|
||||
uint32_t McSecCarveoutBom;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */
|
||||
uint32_t McSecCarveoutAdrHi;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */
|
||||
uint32_t McSecCarveoutSizeMb;
|
||||
/* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.
|
||||
VIDEO_PROTECT_WRITEAccess */
|
||||
uint32_t McVideoProtectWriteAccess;
|
||||
/* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.
|
||||
SEC_CARVEOUT_WRITEAccess */
|
||||
uint32_t McSecCarveoutProtectWriteAccess;
|
||||
|
||||
/* Write-Protect Regions (WPR) */
|
||||
uint32_t McGeneralizedCarveout1Bom;
|
||||
uint32_t McGeneralizedCarveout1BomHi;
|
||||
uint32_t McGeneralizedCarveout1Size128kb;
|
||||
uint32_t McGeneralizedCarveout1Access0;
|
||||
uint32_t McGeneralizedCarveout1Access1;
|
||||
uint32_t McGeneralizedCarveout1Access2;
|
||||
uint32_t McGeneralizedCarveout1Access3;
|
||||
uint32_t McGeneralizedCarveout1Access4;
|
||||
uint32_t McGeneralizedCarveout1ForceInternalAccess0;
|
||||
uint32_t McGeneralizedCarveout1ForceInternalAccess1;
|
||||
uint32_t McGeneralizedCarveout1ForceInternalAccess2;
|
||||
uint32_t McGeneralizedCarveout1ForceInternalAccess3;
|
||||
uint32_t McGeneralizedCarveout1ForceInternalAccess4;
|
||||
uint32_t McGeneralizedCarveout1Cfg0;
|
||||
|
||||
uint32_t McGeneralizedCarveout2Bom;
|
||||
uint32_t McGeneralizedCarveout2BomHi;
|
||||
uint32_t McGeneralizedCarveout2Size128kb;
|
||||
uint32_t McGeneralizedCarveout2Access0;
|
||||
uint32_t McGeneralizedCarveout2Access1;
|
||||
uint32_t McGeneralizedCarveout2Access2;
|
||||
uint32_t McGeneralizedCarveout2Access3;
|
||||
uint32_t McGeneralizedCarveout2Access4;
|
||||
uint32_t McGeneralizedCarveout2ForceInternalAccess0;
|
||||
uint32_t McGeneralizedCarveout2ForceInternalAccess1;
|
||||
uint32_t McGeneralizedCarveout2ForceInternalAccess2;
|
||||
uint32_t McGeneralizedCarveout2ForceInternalAccess3;
|
||||
uint32_t McGeneralizedCarveout2ForceInternalAccess4;
|
||||
uint32_t McGeneralizedCarveout2Cfg0;
|
||||
|
||||
uint32_t McGeneralizedCarveout3Bom;
|
||||
uint32_t McGeneralizedCarveout3BomHi;
|
||||
uint32_t McGeneralizedCarveout3Size128kb;
|
||||
uint32_t McGeneralizedCarveout3Access0;
|
||||
uint32_t McGeneralizedCarveout3Access1;
|
||||
uint32_t McGeneralizedCarveout3Access2;
|
||||
uint32_t McGeneralizedCarveout3Access3;
|
||||
uint32_t McGeneralizedCarveout3Access4;
|
||||
uint32_t McGeneralizedCarveout3ForceInternalAccess0;
|
||||
uint32_t McGeneralizedCarveout3ForceInternalAccess1;
|
||||
uint32_t McGeneralizedCarveout3ForceInternalAccess2;
|
||||
uint32_t McGeneralizedCarveout3ForceInternalAccess3;
|
||||
uint32_t McGeneralizedCarveout3ForceInternalAccess4;
|
||||
uint32_t McGeneralizedCarveout3Cfg0;
|
||||
|
||||
uint32_t McGeneralizedCarveout4Bom;
|
||||
uint32_t McGeneralizedCarveout4BomHi;
|
||||
uint32_t McGeneralizedCarveout4Size128kb;
|
||||
uint32_t McGeneralizedCarveout4Access0;
|
||||
uint32_t McGeneralizedCarveout4Access1;
|
||||
uint32_t McGeneralizedCarveout4Access2;
|
||||
uint32_t McGeneralizedCarveout4Access3;
|
||||
uint32_t McGeneralizedCarveout4Access4;
|
||||
uint32_t McGeneralizedCarveout4ForceInternalAccess0;
|
||||
uint32_t McGeneralizedCarveout4ForceInternalAccess1;
|
||||
uint32_t McGeneralizedCarveout4ForceInternalAccess2;
|
||||
uint32_t McGeneralizedCarveout4ForceInternalAccess3;
|
||||
uint32_t McGeneralizedCarveout4ForceInternalAccess4;
|
||||
uint32_t McGeneralizedCarveout4Cfg0;
|
||||
|
||||
uint32_t McGeneralizedCarveout5Bom;
|
||||
uint32_t McGeneralizedCarveout5BomHi;
|
||||
uint32_t McGeneralizedCarveout5Size128kb;
|
||||
uint32_t McGeneralizedCarveout5Access0;
|
||||
uint32_t McGeneralizedCarveout5Access1;
|
||||
uint32_t McGeneralizedCarveout5Access2;
|
||||
uint32_t McGeneralizedCarveout5Access3;
|
||||
uint32_t McGeneralizedCarveout5Access4;
|
||||
uint32_t McGeneralizedCarveout5ForceInternalAccess0;
|
||||
uint32_t McGeneralizedCarveout5ForceInternalAccess1;
|
||||
uint32_t McGeneralizedCarveout5ForceInternalAccess2;
|
||||
uint32_t McGeneralizedCarveout5ForceInternalAccess3;
|
||||
uint32_t McGeneralizedCarveout5ForceInternalAccess4;
|
||||
uint32_t McGeneralizedCarveout5Cfg0;
|
||||
|
||||
/* Specifies enable for CA training */
|
||||
uint32_t EmcCaTrainingEnable;
|
||||
|
||||
/* Set if bit 6 select is greater than bit 7 select; uses aremc.
|
||||
spec packet SWIZZLE_BIT6_GT_BIT7 */
|
||||
uint32_t SwizzleRankByteEncode;
|
||||
/* Specifies enable and offset for patched boot ROM write */
|
||||
uint32_t BootRomPatchControl;
|
||||
/* Specifies data for patched boot ROM write */
|
||||
uint32_t BootRomPatchData;
|
||||
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_BOM */
|
||||
uint32_t McMtsCarveoutBom;
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */
|
||||
uint32_t McMtsCarveoutAdrHi;
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */
|
||||
uint32_t McMtsCarveoutSizeMb;
|
||||
/* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */
|
||||
uint32_t McMtsCarveoutRegCtrl;
|
||||
|
||||
/* End */
|
||||
};
|
||||
|
||||
#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */
|
||||
649
sept/sept-secondary/src/se.c
Normal file
649
sept/sept-secondary/src/se.c
Normal file
|
|
@ -0,0 +1,649 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "utils.h"
|
||||
#include "se.h"
|
||||
|
||||
void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size);
|
||||
|
||||
/* Globals for driver. */
|
||||
static unsigned int g_se_modulus_sizes[KEYSLOT_RSA_MAX];
|
||||
static unsigned int g_se_exp_sizes[KEYSLOT_RSA_MAX];
|
||||
|
||||
/* Initialize a SE linked list. */
|
||||
void NOINLINE ll_init(volatile se_ll_t *ll, void *buffer, size_t size) {
|
||||
ll->num_entries = 0; /* 1 Entry. */
|
||||
|
||||
if (buffer != NULL) {
|
||||
ll->addr_info.address = (uint32_t) get_physical_address(buffer);
|
||||
ll->addr_info.size = (uint32_t) size;
|
||||
} else {
|
||||
ll->addr_info.address = 0;
|
||||
ll->addr_info.size = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void se_check_error_status_reg(void) {
|
||||
if (se_get_regs()->ERR_STATUS_REG) {
|
||||
generic_panic();
|
||||
}
|
||||
}
|
||||
|
||||
void se_check_for_error(void) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
if (se->INT_STATUS_REG & 0x10000 || se->FLAGS_REG & 3 || se->ERR_STATUS_REG) {
|
||||
generic_panic();
|
||||
}
|
||||
}
|
||||
|
||||
void se_verify_flags_cleared(void) {
|
||||
if (se_get_regs()->FLAGS_REG & 3) {
|
||||
generic_panic();
|
||||
}
|
||||
}
|
||||
|
||||
/* Set the flags for an AES keyslot. */
|
||||
void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
/* Misc flags. */
|
||||
if (flags & ~0x80) {
|
||||
se->AES_KEYSLOT_FLAGS[keyslot] = ~flags;
|
||||
}
|
||||
|
||||
/* Disable keyslot reads. */
|
||||
if (flags & 0x80) {
|
||||
se->AES_KEY_READ_DISABLE_REG &= ~(1 << keyslot);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set the flags for an RSA keyslot. */
|
||||
void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_RSA_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
/* Misc flags. */
|
||||
if (flags & ~0x80) {
|
||||
/* TODO: Why are flags assigned this way? */
|
||||
se->RSA_KEYSLOT_FLAGS[keyslot] = (((flags >> 4) & 4) | (flags & 3)) ^ 7;
|
||||
}
|
||||
|
||||
/* Disable keyslot reads. */
|
||||
if (flags & 0x80) {
|
||||
se->RSA_KEY_READ_DISABLE_REG &= ~(1 << keyslot);
|
||||
}
|
||||
}
|
||||
|
||||
void clear_aes_keyslot(unsigned int keyslot) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
/* Zero out the whole keyslot and IV. */
|
||||
for (unsigned int i = 0; i < 0x10; i++) {
|
||||
se->AES_KEYTABLE_ADDR = (keyslot << 4) | i;
|
||||
se->AES_KEYTABLE_DATA = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void clear_rsa_keyslot(unsigned int keyslot) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_RSA_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
/* Zero out the whole keyslot. */
|
||||
for (unsigned int i = 0; i < 0x40; i++) {
|
||||
/* Select Keyslot Modulus[i] */
|
||||
se->RSA_KEYTABLE_ADDR = (keyslot << 7) | i | 0x40;
|
||||
se->RSA_KEYTABLE_DATA = 0;
|
||||
}
|
||||
for (unsigned int i = 0; i < 0x40; i++) {
|
||||
/* Select Keyslot Expontent[i] */
|
||||
se->RSA_KEYTABLE_ADDR = (keyslot << 7) | i;
|
||||
se->RSA_KEYTABLE_DATA = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX || key_size > KEYSIZE_AES_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < (key_size >> 2); i++) {
|
||||
se->AES_KEYTABLE_ADDR = (keyslot << 4) | i;
|
||||
se->AES_KEYTABLE_DATA = read32le(key, 4 * i);
|
||||
}
|
||||
}
|
||||
|
||||
void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_RSA_MAX || modulus_size > KEYSIZE_RSA_MAX || exp_size > KEYSIZE_RSA_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < (modulus_size >> 2); i++) {
|
||||
se->RSA_KEYTABLE_ADDR = (keyslot << 7) | 0x40 | i;
|
||||
se->RSA_KEYTABLE_DATA = read32be(modulus, (4 * (modulus_size >> 2)) - (4 * i) - 4);
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < (exp_size >> 2); i++) {
|
||||
se->RSA_KEYTABLE_ADDR = (keyslot << 7) | i;
|
||||
se->RSA_KEYTABLE_DATA = read32be(exponent, (4 * (exp_size >> 2)) - (4 * i) - 4);
|
||||
}
|
||||
|
||||
g_se_modulus_sizes[keyslot] = modulus_size;
|
||||
g_se_exp_sizes[keyslot] = exp_size;
|
||||
}
|
||||
|
||||
void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX || iv_size > 0x10) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < (iv_size >> 2); i++) {
|
||||
se->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i;
|
||||
se->AES_KEYTABLE_DATA = read32le(iv, 4 * i);
|
||||
}
|
||||
}
|
||||
|
||||
void clear_aes_keyslot_iv(unsigned int keyslot) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < (0x10 >> 2); i++) {
|
||||
se->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i;
|
||||
se->AES_KEYTABLE_DATA = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void set_se_ctr(const void *ctr) {
|
||||
for (unsigned int i = 0; i < 4; i++) {
|
||||
se_get_regs()->CRYPTO_CTR_REG[i] = read32le(ctr, i * 4);
|
||||
}
|
||||
}
|
||||
|
||||
void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot_dst >= KEYSLOT_AES_MAX || keyslot_src >= KEYSLOT_AES_MAX || wrapped_key_size > KEYSIZE_AES_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
se->CONFIG_REG = (ALG_AES_DEC | DST_KEYTAB);
|
||||
se->CRYPTO_REG = keyslot_src << 24;
|
||||
se->BLOCK_COUNT_REG = 0;
|
||||
se->CRYPTO_KEYTABLE_DST_REG = keyslot_dst << 8;
|
||||
|
||||
trigger_se_blocking_op(OP_START, NULL, 0, wrapped_key, wrapped_key_size);
|
||||
}
|
||||
|
||||
void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
uint8_t ALIGN(16) stack_buf[KEYSIZE_RSA_MAX];
|
||||
|
||||
if (keyslot >= KEYSLOT_RSA_MAX || src_size > KEYSIZE_RSA_MAX || dst_size > KEYSIZE_RSA_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
/* Endian swap the input. */
|
||||
for (size_t i = 0; i < src_size; i++) {
|
||||
stack_buf[i] = *((uint8_t *)src + src_size - i - 1);
|
||||
}
|
||||
|
||||
se->CONFIG_REG = (ALG_RSA | DST_RSAREG);
|
||||
se->RSA_CONFIG = keyslot << 24;
|
||||
se->RSA_KEY_SIZE_REG = (g_se_modulus_sizes[keyslot] >> 6) - 1;
|
||||
se->RSA_EXP_SIZE_REG = g_se_exp_sizes[keyslot] >> 2;
|
||||
|
||||
trigger_se_blocking_op(OP_START, NULL, 0, stack_buf, src_size);
|
||||
se_get_exp_mod_output(dst, dst_size);
|
||||
}
|
||||
|
||||
void se_get_exp_mod_output(void *buf, size_t size) {
|
||||
size_t num_dwords = (size >> 2);
|
||||
|
||||
if (num_dwords < 1) {
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t *p_out = ((uint32_t *)buf) + num_dwords - 1;
|
||||
uint32_t offset = 0;
|
||||
|
||||
/* Copy endian swapped output. */
|
||||
while (num_dwords) {
|
||||
*p_out = read32be(se_get_regs()->RSA_OUTPUT, offset);
|
||||
offset += 4;
|
||||
p_out--;
|
||||
num_dwords--;
|
||||
}
|
||||
}
|
||||
|
||||
bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const void *modulus, size_t modulus_size, const void *data, size_t data_size) {
|
||||
uint8_t message[RSA_2048_BYTES];
|
||||
uint8_t h_buf[0x24];
|
||||
|
||||
/* Hardcode RSA with keyslot 0. */
|
||||
const uint8_t public_exponent[4] = {0x00, 0x01, 0x00, 0x01};
|
||||
set_rsa_keyslot(0, modulus, modulus_size, public_exponent, sizeof(public_exponent));
|
||||
se_synchronous_exp_mod(0, message, sizeof(message), signature, signature_size);
|
||||
|
||||
/* Validate sanity byte. */
|
||||
if (message[RSA_2048_BYTES - 1] != 0xBC) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Copy Salt into MGF1 Hash Buffer. */
|
||||
memset(h_buf, 0, sizeof(h_buf));
|
||||
memcpy(h_buf, message + RSA_2048_BYTES - 0x20 - 0x1, 0x20);
|
||||
|
||||
/* Decrypt maskedDB (via inline MGF1). */
|
||||
uint8_t seed = 0;
|
||||
uint8_t mgf1_buf[0x20];
|
||||
for (unsigned int ofs = 0; ofs < RSA_2048_BYTES - 0x20 - 1; ofs += 0x20) {
|
||||
h_buf[sizeof(h_buf) - 1] = seed++;
|
||||
se_calculate_sha256(mgf1_buf, h_buf, sizeof(h_buf));
|
||||
for (unsigned int i = ofs; i < ofs + 0x20 && i < RSA_2048_BYTES - 0x20 - 1; i++) {
|
||||
message[i] ^= mgf1_buf[i - ofs];
|
||||
}
|
||||
}
|
||||
|
||||
/* Constant lmask for rsa-2048-pss. */
|
||||
message[0] &= 0x7F;
|
||||
|
||||
/* Validate DB is of the form 0000...0001. */
|
||||
for (unsigned int i = 0; i < RSA_2048_BYTES - 0x20 - 0x20 - 1 - 1; i++) {
|
||||
if (message[i] != 0) {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
if (message[RSA_2048_BYTES - 0x20 - 0x20 - 1 - 1] != 1) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Check hash correctness. */
|
||||
uint8_t validate_buf[8 + 0x20 + 0x20];
|
||||
uint8_t validate_hash[0x20];
|
||||
|
||||
memset(validate_buf, 0, sizeof(validate_buf));
|
||||
se_calculate_sha256(&validate_buf[8], data, data_size);
|
||||
memcpy(&validate_buf[0x28], &message[RSA_2048_BYTES - 0x20 - 0x20 - 1], 0x20);
|
||||
se_calculate_sha256(validate_hash, validate_buf, sizeof(validate_buf));
|
||||
return memcmp(h_buf, validate_hash, 0x20) == 0;
|
||||
}
|
||||
|
||||
void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
se_ll_t in_ll;
|
||||
se_ll_t out_ll;
|
||||
|
||||
ll_init(&in_ll, (void *)src, src_size);
|
||||
ll_init(&out_ll, dst, dst_size);
|
||||
|
||||
/* Set the LLs. */
|
||||
se->IN_LL_ADDR_REG = (uint32_t) get_physical_address(&in_ll);
|
||||
se->OUT_LL_ADDR_REG = (uint32_t) get_physical_address(&out_ll);
|
||||
|
||||
/* Set registers for operation. */
|
||||
se->ERR_STATUS_REG = se->ERR_STATUS_REG;
|
||||
se->INT_STATUS_REG = se->INT_STATUS_REG;
|
||||
se->OPERATION_REG = op;
|
||||
|
||||
while (!(se->INT_STATUS_REG & 0x10)) { /* Wait a while */ }
|
||||
se_check_for_error();
|
||||
}
|
||||
|
||||
/* Secure AES Functionality. */
|
||||
void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, size_t src_size) {
|
||||
uint8_t block[0x10] = {0};
|
||||
|
||||
if (src_size > sizeof(block) || dst_size > sizeof(block)) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
/* Load src data into block. */
|
||||
if (src_size != 0) {
|
||||
memcpy(block, src, src_size);
|
||||
}
|
||||
|
||||
/* Trigger AES operation. */
|
||||
se_get_regs()->BLOCK_COUNT_REG = 0;
|
||||
trigger_se_blocking_op(OP_START, block, sizeof(block), block, sizeof(block));
|
||||
|
||||
/* Copy output data into dst. */
|
||||
if (dst_size != 0) {
|
||||
memcpy(dst, block, dst_size);
|
||||
}
|
||||
}
|
||||
|
||||
void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX || ctr_size != 0x10) {
|
||||
generic_panic();
|
||||
}
|
||||
unsigned int num_blocks = src_size >> 4;
|
||||
|
||||
/* Unknown what this write does, but official code writes it for CTR mode. */
|
||||
se->SPARE_0 = 1;
|
||||
se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY);
|
||||
se->CRYPTO_REG = (keyslot << 24) | 0x91E;
|
||||
set_se_ctr(ctr);
|
||||
|
||||
/* Handle any aligned blocks. */
|
||||
size_t aligned_size = (size_t)num_blocks << 4;
|
||||
if (aligned_size) {
|
||||
se->BLOCK_COUNT_REG = num_blocks - 1;
|
||||
trigger_se_blocking_op(OP_START, dst, dst_size, src, aligned_size);
|
||||
}
|
||||
|
||||
/* Handle final, unaligned block. */
|
||||
if (aligned_size < dst_size && aligned_size < src_size) {
|
||||
size_t last_block_size = dst_size - aligned_size;
|
||||
if (src_size < dst_size) {
|
||||
last_block_size = src_size - aligned_size;
|
||||
}
|
||||
se_perform_aes_block_operation(dst + aligned_size, last_block_size, (uint8_t *)src + aligned_size, src_size - aligned_size);
|
||||
}
|
||||
}
|
||||
|
||||
void se_aes_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, unsigned int config_high) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
/* Set configuration high (256-bit vs 128-bit) based on parameter. */
|
||||
se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (config_high << 16);
|
||||
se->CRYPTO_REG = keyslot << 24 | 0x100;
|
||||
se_perform_aes_block_operation(dst, 0x10, src, 0x10);
|
||||
}
|
||||
|
||||
void se_aes_128_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) {
|
||||
se_aes_ecb_encrypt_block(keyslot, dst, dst_size, src, src_size, 0);
|
||||
}
|
||||
|
||||
void se_aes_256_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) {
|
||||
se_aes_ecb_encrypt_block(keyslot, dst, dst_size, src, src_size, 0x202);
|
||||
}
|
||||
|
||||
void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
se->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY);
|
||||
se->CRYPTO_REG = keyslot << 24;
|
||||
se_perform_aes_block_operation(dst, 0x10, src, 0x10);
|
||||
}
|
||||
|
||||
void shift_left_xor_rb(uint8_t *key) {
|
||||
uint8_t prev_high_bit = 0;
|
||||
for (unsigned int i = 0; i < 0x10; i++) {
|
||||
uint8_t cur_byte = key[0xF - i];
|
||||
key[0xF - i] = (cur_byte << 1) | (prev_high_bit);
|
||||
prev_high_bit = cur_byte >> 7;
|
||||
}
|
||||
if (prev_high_bit) {
|
||||
key[0xF] ^= 0x87;
|
||||
}
|
||||
}
|
||||
|
||||
void shift_left_xor_rb_le(uint8_t *key) {
|
||||
uint8_t prev_high_bit = 0;
|
||||
for (unsigned int i = 0; i < 0x10; i++) {
|
||||
uint8_t cur_byte = key[i];
|
||||
key[i] = (cur_byte << 1) | (prev_high_bit);
|
||||
prev_high_bit = cur_byte >> 7;
|
||||
}
|
||||
if (prev_high_bit) {
|
||||
key[0x0] ^= 0x87;
|
||||
}
|
||||
}
|
||||
|
||||
void aes_128_xts_nintendo_get_tweak(uint8_t *tweak, size_t sector) {
|
||||
for (int i = 0xF; i >= 0; i--) { /* Nintendo LE custom tweak... */
|
||||
tweak[i] = (unsigned char)(sector & 0xFF);
|
||||
sector >>= 8;
|
||||
}
|
||||
}
|
||||
|
||||
void aes_128_xts_nintendo_xor_with_tweak(unsigned int keyslot, size_t sector, uint8_t *dst, const uint8_t *src, size_t size) {
|
||||
if ((size & 0xF) || size == 0) {
|
||||
generic_panic();
|
||||
}
|
||||
uint8_t tweak[0x10];
|
||||
aes_128_xts_nintendo_get_tweak(tweak, sector);
|
||||
se_aes_128_ecb_encrypt_block(keyslot, tweak, sizeof(tweak), tweak, sizeof(tweak));
|
||||
|
||||
for (unsigned int block = 0; block < (size >> 4); block++) {
|
||||
for (unsigned int i = 0; i < 0x10; i++) {
|
||||
dst[(block << 4) | i] = src[(block << 4) | i] ^ tweak[i];
|
||||
}
|
||||
shift_left_xor_rb_le(tweak);
|
||||
}
|
||||
}
|
||||
|
||||
void aes_128_xts_nintendo_crypt_sector(unsigned int keyslot_1, unsigned int keyslot_2, size_t sector, bool encrypt, void *dst, const void *src, size_t size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if ((size & 0xF) || size == 0) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
/* XOR. */
|
||||
aes_128_xts_nintendo_xor_with_tweak(keyslot_2, sector, dst, src, size);
|
||||
|
||||
/* Encrypt/Decrypt. */
|
||||
if (encrypt) {
|
||||
se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY);
|
||||
se->CRYPTO_REG = keyslot_1 << 24 | 0x100;
|
||||
} else {
|
||||
se->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY);
|
||||
se->CRYPTO_REG = keyslot_1 << 24;
|
||||
}
|
||||
se->BLOCK_COUNT_REG = (size >> 4) - 1;
|
||||
trigger_se_blocking_op(OP_START, dst, size, src, size);
|
||||
|
||||
/* XOR. */
|
||||
aes_128_xts_nintendo_xor_with_tweak(keyslot_2, sector, dst, dst, size);
|
||||
}
|
||||
|
||||
/* Encrypt with AES-XTS (Nintendo's custom tweak). */
|
||||
void se_aes_128_xts_nintendo_encrypt(unsigned int keyslot_1, unsigned int keyslot_2, size_t base_sector, void *dst, const void *src, size_t size, unsigned int sector_size) {
|
||||
if ((size & 0xF) || size == 0) {
|
||||
generic_panic();
|
||||
}
|
||||
size_t sector = base_sector;
|
||||
for (size_t ofs = 0; ofs < size; ofs += sector_size) {
|
||||
aes_128_xts_nintendo_crypt_sector(keyslot_1, keyslot_2, sector, true, dst + ofs, src + ofs, sector_size);
|
||||
sector++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Decrypt with AES-XTS (Nintendo's custom tweak). */
|
||||
void se_aes_128_xts_nintendo_decrypt(unsigned int keyslot_1, unsigned int keyslot_2, size_t base_sector, void *dst, const void *src, size_t size, unsigned int sector_size) {
|
||||
if ((size & 0xF) || size == 0) {
|
||||
generic_panic();
|
||||
}
|
||||
size_t sector = base_sector;
|
||||
for (size_t ofs = 0; ofs < size; ofs += sector_size) {
|
||||
aes_128_xts_nintendo_crypt_sector(keyslot_1, keyslot_2, sector, false, dst + ofs, src + ofs, sector_size);
|
||||
sector++;
|
||||
}
|
||||
}
|
||||
|
||||
void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size, unsigned int config_high) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
/* Generate the derived key, to be XOR'd with final output block. */
|
||||
uint8_t ALIGN(16) derived_key[0x10] = {0};
|
||||
se_aes_ecb_encrypt_block(keyslot, derived_key, sizeof(derived_key), derived_key, sizeof(derived_key), config_high);
|
||||
shift_left_xor_rb(derived_key);
|
||||
if (data_size & 0xF) {
|
||||
shift_left_xor_rb(derived_key);
|
||||
}
|
||||
|
||||
se->CONFIG_REG = (ALG_AES_ENC | DST_HASHREG) | (config_high << 16);
|
||||
se->CRYPTO_REG = (keyslot << 24) | (0x145);
|
||||
clear_aes_keyslot_iv(keyslot);
|
||||
|
||||
unsigned int num_blocks = (data_size + 0xF) >> 4;
|
||||
/* Handle aligned blocks. */
|
||||
if (num_blocks > 1) {
|
||||
se->BLOCK_COUNT_REG = num_blocks - 2;
|
||||
trigger_se_blocking_op(OP_START, NULL, 0, data, data_size);
|
||||
se->CRYPTO_REG |= 0x80;
|
||||
}
|
||||
|
||||
/* Create final block. */
|
||||
uint8_t ALIGN(16) last_block[0x10] = {0};
|
||||
if (data_size & 0xF) {
|
||||
memcpy(last_block, data + (data_size & ~0xF), data_size & 0xF);
|
||||
last_block[data_size & 0xF] = 0x80; /* Last block = data || 100...0 */
|
||||
} else if (data_size >= 0x10) {
|
||||
memcpy(last_block, data + data_size - 0x10, 0x10);
|
||||
}
|
||||
|
||||
for (unsigned int i = 0; i < 0x10; i++) {
|
||||
last_block[i] ^= derived_key[i];
|
||||
}
|
||||
|
||||
/* Perform last operation. */
|
||||
se->BLOCK_COUNT_REG = 0;
|
||||
trigger_se_blocking_op(OP_START, NULL, 0, last_block, sizeof(last_block));
|
||||
|
||||
/* Copy output CMAC. */
|
||||
for (unsigned int i = 0; i < (cmac_size >> 2); i++) {
|
||||
((uint32_t *)cmac)[i] = read32le(se->HASH_RESULT_REG, i << 2);
|
||||
}
|
||||
}
|
||||
|
||||
void se_compute_aes_128_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size) {
|
||||
se_compute_aes_cmac(keyslot, cmac, cmac_size, data, data_size, 0);
|
||||
}
|
||||
void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size) {
|
||||
se_compute_aes_cmac(keyslot, cmac, cmac_size, data, data_size, 0x202);
|
||||
}
|
||||
|
||||
void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX || src_size < 0x10) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (0x202 << 16);
|
||||
se->CRYPTO_REG = (keyslot << 24) | 0x144;
|
||||
set_aes_keyslot_iv(keyslot, iv, 0x10);
|
||||
se->BLOCK_COUNT_REG = (src_size >> 4) - 1;
|
||||
trigger_se_blocking_op(OP_START, dst, dst_size, src, src_size);
|
||||
}
|
||||
|
||||
/* SHA256 Implementation. */
|
||||
void se_calculate_sha256(void *dst, const void *src, size_t src_size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
/* Setup config for SHA256, size = BITS(src_size) */
|
||||
se->CONFIG_REG = (ENCMODE_SHA256 | ALG_SHA | DST_HASHREG);
|
||||
se->SHA_CONFIG_REG = 1;
|
||||
se->SHA_MSG_LENGTH_REG = (uint32_t)(src_size << 3);
|
||||
se->_0x208 = 0;
|
||||
se->_0x20C = 0;
|
||||
se->_0x210 = 0;
|
||||
se->SHA_MSG_LEFT_REG = (uint32_t)(src_size << 3);
|
||||
se->_0x218 = 0;
|
||||
se->_0x21C = 0;
|
||||
se->_0x220 = 0;
|
||||
|
||||
/* Trigger the operation. */
|
||||
trigger_se_blocking_op(OP_START, NULL, 0, src, src_size);
|
||||
|
||||
/* Copy output hash. */
|
||||
for (unsigned int i = 0; i < (0x20 >> 2); i++) {
|
||||
((uint32_t *)dst)[i] = read32be(se->HASH_RESULT_REG, i << 2);
|
||||
}
|
||||
}
|
||||
|
||||
/* RNG API */
|
||||
void se_initialize_rng(unsigned int keyslot) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
/* To initialize the RNG, we'll perform an RNG operation into an output buffer. */
|
||||
/* This will be discarded, when done. */
|
||||
uint8_t ALIGN(16) output_buf[0x10];
|
||||
|
||||
se->RNG_SRC_CONFIG_REG = 3; /* Entropy enable + Entropy lock enable */
|
||||
se->RNG_RESEED_INTERVAL_REG = 70001;
|
||||
se->CONFIG_REG = (ALG_RNG | DST_MEMORY);
|
||||
se->CRYPTO_REG = (keyslot << 24) | 0x108;
|
||||
se->RNG_CONFIG_REG = 5;
|
||||
se->BLOCK_COUNT_REG = 0;
|
||||
trigger_se_blocking_op(OP_START, output_buf, 0x10, NULL, 0);
|
||||
}
|
||||
|
||||
void se_generate_random(unsigned int keyslot, void *dst, size_t size) {
|
||||
volatile tegra_se_t *se = se_get_regs();
|
||||
|
||||
if (keyslot >= KEYSLOT_AES_MAX) {
|
||||
generic_panic();
|
||||
}
|
||||
|
||||
uint32_t num_blocks = size >> 4;
|
||||
size_t aligned_size = num_blocks << 4;
|
||||
se->CONFIG_REG = (ALG_RNG | DST_MEMORY);
|
||||
se->CRYPTO_REG = (keyslot << 24) | 0x108;
|
||||
se->RNG_CONFIG_REG = 4;
|
||||
|
||||
if (num_blocks >= 1) {
|
||||
se->BLOCK_COUNT_REG = num_blocks - 1;
|
||||
trigger_se_blocking_op(OP_START, dst, aligned_size, NULL, 0);
|
||||
}
|
||||
if (size > aligned_size) {
|
||||
se_perform_aes_block_operation(dst + aligned_size, size - aligned_size, NULL, 0);
|
||||
}
|
||||
}
|
||||
219
sept/sept-secondary/src/se.h
Normal file
219
sept/sept-secondary/src/se.h
Normal file
|
|
@ -0,0 +1,219 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_SE_H
|
||||
#define FUSEE_SE_H
|
||||
|
||||
#define SE_BASE 0x70012000
|
||||
#define MAKE_SE_REG(n) MAKE_REG32(SE_BASE + n)
|
||||
|
||||
#define KEYSLOT_SWITCH_LP0TZRAMKEY 0x2
|
||||
#define KEYSLOT_SWITCH_SRKGENKEY 0x8
|
||||
#define KEYSLOT_SWITCH_PACKAGE2KEY 0x8
|
||||
#define KEYSLOT_SWITCH_TEMPKEY 0x9
|
||||
#define KEYSLOT_SWITCH_SESSIONKEY 0xA
|
||||
#define KEYSLOT_SWITCH_RNGKEY 0xB
|
||||
#define KEYSLOT_SWITCH_MASTERKEY 0xC
|
||||
#define KEYSLOT_SWITCH_DEVICEKEY 0xD
|
||||
|
||||
/* This keyslot was added in 4.0.0. */
|
||||
#define KEYSLOT_SWITCH_4XNEWDEVICEKEYGENKEY 0xD
|
||||
#define KEYSLOT_SWITCH_4XNEWCONSOLEKEYGENKEY 0xE
|
||||
#define KEYSLOT_SWITCH_4XOLDDEVICEKEY 0xF
|
||||
|
||||
/* This keyslot was added in 5.0.0. */
|
||||
#define KEYSLOT_SWITCH_5XNEWDEVICEKEYGENKEY 0xA
|
||||
|
||||
#define KEYSLOT_AES_MAX 0x10
|
||||
#define KEYSLOT_RSA_MAX 0x2
|
||||
|
||||
#define KEYSIZE_AES_MAX 0x20
|
||||
#define KEYSIZE_RSA_MAX 0x100
|
||||
|
||||
#define ALG_SHIFT (12)
|
||||
#define ALG_DEC_SHIFT (8)
|
||||
#define ALG_NOP (0 << ALG_SHIFT)
|
||||
#define ALG_AES_ENC (1 << ALG_SHIFT)
|
||||
#define ALG_AES_DEC ((1 << ALG_DEC_SHIFT) | ALG_NOP)
|
||||
#define ALG_RNG (2 << ALG_SHIFT)
|
||||
#define ALG_SHA (3 << ALG_SHIFT)
|
||||
#define ALG_RSA (4 << ALG_SHIFT)
|
||||
|
||||
#define DST_SHIFT (2)
|
||||
#define DST_MEMORY (0 << DST_SHIFT)
|
||||
#define DST_HASHREG (1 << DST_SHIFT)
|
||||
#define DST_KEYTAB (2 << DST_SHIFT)
|
||||
#define DST_SRK (3 << DST_SHIFT)
|
||||
#define DST_RSAREG (4 << DST_SHIFT)
|
||||
|
||||
#define ENCMODE_SHIFT (24)
|
||||
#define DECMODE_SHIFT (16)
|
||||
#define ENCMODE_SHA256 (5 << ENCMODE_SHIFT)
|
||||
|
||||
#define HASH_DISABLE (0x0)
|
||||
#define HASH_ENABLE (0x1)
|
||||
|
||||
#define OP_ABORT 0
|
||||
#define OP_START 1
|
||||
#define OP_RESTART 2
|
||||
#define OP_CTX_SAVE 3
|
||||
#define OP_RESTART_IN 4
|
||||
|
||||
#define CTX_SAVE_SRC_SHIFT 29
|
||||
#define CTX_SAVE_SRC_STICKY_BITS (0 << CTX_SAVE_SRC_SHIFT)
|
||||
#define CTX_SAVE_SRC_KEYTABLE_AES (2 << CTX_SAVE_SRC_SHIFT)
|
||||
#define CTX_SAVE_SRC_KEYTABLE_RSA (1 << CTX_SAVE_SRC_SHIFT)
|
||||
#define CTX_SAVE_SRC_MEM (4 << CTX_SAVE_SRC_SHIFT)
|
||||
#define CTX_SAVE_SRC_SRK (6 << CTX_SAVE_SRC_SHIFT)
|
||||
|
||||
#define CTX_SAVE_KEY_LOW_BITS 0
|
||||
#define CTX_SAVE_KEY_HIGH_BITS 1
|
||||
#define CTX_SAVE_KEY_ORIGINAL_IV 2
|
||||
#define CTX_SAVE_KEY_UPDATED_IV 3
|
||||
|
||||
#define CTX_SAVE_STICKY_BIT_INDEX_SHIFT 24
|
||||
#define CTX_SAVE_KEY_INDEX_SHIFT 8
|
||||
#define CTX_SAVE_RSA_KEY_INDEX_SHIFT 16
|
||||
#define CTX_SAVE_RSA_KEY_BLOCK_INDEX_SHIFT 12
|
||||
|
||||
#define RSA_2048_BYTES 0x100
|
||||
|
||||
typedef struct {
|
||||
uint32_t _0x0;
|
||||
uint32_t _0x4;
|
||||
uint32_t OPERATION_REG;
|
||||
uint32_t INT_ENABLE_REG;
|
||||
uint32_t INT_STATUS_REG;
|
||||
uint32_t CONFIG_REG;
|
||||
uint32_t IN_LL_ADDR_REG;
|
||||
uint32_t _0x1C;
|
||||
uint32_t _0x20;
|
||||
uint32_t OUT_LL_ADDR_REG;
|
||||
uint32_t _0x28;
|
||||
uint32_t _0x2C;
|
||||
uint8_t HASH_RESULT_REG[0x20];
|
||||
uint8_t _0x50[0x20];
|
||||
uint32_t CONTEXT_SAVE_CONFIG_REG;
|
||||
uint8_t _0x74[0x18C];
|
||||
uint32_t SHA_CONFIG_REG;
|
||||
uint32_t SHA_MSG_LENGTH_REG;
|
||||
uint32_t _0x208;
|
||||
uint32_t _0x20C;
|
||||
uint32_t _0x210;
|
||||
uint32_t SHA_MSG_LEFT_REG;
|
||||
uint32_t _0x218;
|
||||
uint32_t _0x21C;
|
||||
uint32_t _0x220;
|
||||
uint32_t _0x224;
|
||||
uint8_t _0x228[0x58];
|
||||
uint32_t AES_KEY_READ_DISABLE_REG;
|
||||
uint32_t AES_KEYSLOT_FLAGS[0x10];
|
||||
uint8_t _0x2C4[0x3C];
|
||||
uint32_t _0x300;
|
||||
uint32_t CRYPTO_REG;
|
||||
uint32_t CRYPTO_CTR_REG[4];
|
||||
uint32_t BLOCK_COUNT_REG;
|
||||
uint32_t AES_KEYTABLE_ADDR;
|
||||
uint32_t AES_KEYTABLE_DATA;
|
||||
uint32_t _0x324;
|
||||
uint32_t _0x328;
|
||||
uint32_t _0x32C;
|
||||
uint32_t CRYPTO_KEYTABLE_DST_REG;
|
||||
uint8_t _0x334[0xC];
|
||||
uint32_t RNG_CONFIG_REG;
|
||||
uint32_t RNG_SRC_CONFIG_REG;
|
||||
uint32_t RNG_RESEED_INTERVAL_REG;
|
||||
uint8_t _0x34C[0xB4];
|
||||
uint32_t RSA_CONFIG;
|
||||
uint32_t RSA_KEY_SIZE_REG;
|
||||
uint32_t RSA_EXP_SIZE_REG;
|
||||
uint32_t RSA_KEY_READ_DISABLE_REG;
|
||||
uint32_t RSA_KEYSLOT_FLAGS[2];
|
||||
uint32_t _0x418;
|
||||
uint32_t _0x41C;
|
||||
uint32_t RSA_KEYTABLE_ADDR;
|
||||
uint32_t RSA_KEYTABLE_DATA;
|
||||
uint8_t RSA_OUTPUT[0x100];
|
||||
uint8_t _0x528[0x2D8];
|
||||
uint32_t FLAGS_REG;
|
||||
uint32_t ERR_STATUS_REG;
|
||||
uint32_t _0x808;
|
||||
uint32_t SPARE_0;
|
||||
uint32_t _0x810;
|
||||
uint32_t _0x814;
|
||||
uint32_t _0x818;
|
||||
uint32_t _0x81C;
|
||||
uint8_t _0x820[0x17E0];
|
||||
} tegra_se_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t address;
|
||||
uint32_t size;
|
||||
} se_addr_info_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t num_entries; /* Set to total entries - 1 */
|
||||
se_addr_info_t addr_info; /* This should really be an array...but for our use case it works. */
|
||||
} se_ll_t;
|
||||
|
||||
static inline volatile tegra_se_t *se_get_regs(void) {
|
||||
return (volatile tegra_se_t *)SE_BASE;
|
||||
}
|
||||
|
||||
void se_check_error_status_reg(void);
|
||||
void se_check_for_error(void);
|
||||
void se_trigger_interrupt(void);
|
||||
|
||||
void se_validate_stored_vector(void);
|
||||
void se_generate_stored_vector(void);
|
||||
|
||||
void se_verify_flags_cleared(void);
|
||||
|
||||
void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags);
|
||||
void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags);
|
||||
void clear_aes_keyslot(unsigned int keyslot);
|
||||
void clear_rsa_keyslot(unsigned int keyslot);
|
||||
|
||||
void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size);
|
||||
void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size);
|
||||
void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size);
|
||||
void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size);
|
||||
void set_se_ctr(const void *ctr);
|
||||
|
||||
/* Secure AES API */
|
||||
void se_aes_128_xts_nintendo_decrypt(unsigned int keyslot_1, unsigned int keyslot_2, unsigned int base_sector, void *dst, const void *src, size_t size, unsigned int sector_size);
|
||||
void se_aes_128_xts_nintendo_encrypt(unsigned int keyslot_1, unsigned int keyslot_2, unsigned int base_sector, void *dst, const void *src, size_t size, unsigned int sector_size);
|
||||
void se_compute_aes_128_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size);
|
||||
void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size);
|
||||
void se_aes_128_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size);
|
||||
void se_aes_256_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size);
|
||||
void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size);
|
||||
void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size);
|
||||
void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv);
|
||||
|
||||
/* Hash API */
|
||||
void se_calculate_sha256(void *dst, const void *src, size_t src_size);
|
||||
|
||||
/* RSA API */
|
||||
void se_get_exp_mod_output(void *buf, size_t size);
|
||||
void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size);
|
||||
bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const void *modulus, size_t modulus_size, const void *data, size_t data_size);
|
||||
|
||||
/* RNG API */
|
||||
void se_initialize_rng(unsigned int keyslot);
|
||||
void se_generate_random(unsigned int keyslot, void *dst, size_t size);
|
||||
|
||||
#endif
|
||||
124
sept/sept-secondary/src/stage2.c
Normal file
124
sept/sept-secondary/src/stage2.c
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "stage2.h"
|
||||
#include "chainloader.h"
|
||||
#include "fs_utils.h"
|
||||
#include "utils.h"
|
||||
|
||||
char g_stage2_path[0x100] = {0};
|
||||
|
||||
const char *stage2_get_program_path(void) {
|
||||
return g_stage2_path;
|
||||
}
|
||||
|
||||
static int stage2_ini_handler(void *user, const char *section, const char *name, const char *value) {
|
||||
stage2_config_t *config = (stage2_config_t *)user;
|
||||
uintptr_t x = 0;
|
||||
if (strcmp(section, "stage1") == 0) {
|
||||
if (strcmp(name, STAGE2_NAME_KEY) == 0) {
|
||||
strncpy(config->path, value, sizeof(config->path) - 1);
|
||||
config->path[sizeof(config->path) - 1] = '\0';
|
||||
} else if (strcmp(name, STAGE2_ADDRESS_KEY) == 0) {
|
||||
/* Read in load address as a hex string. */
|
||||
sscanf(value, "%x", &x);
|
||||
config->load_address = x;
|
||||
if (config->entrypoint == 0) {
|
||||
config->entrypoint = config->load_address;
|
||||
}
|
||||
} else if (strcmp(name, STAGE2_ENTRYPOINT_KEY) == 0) {
|
||||
/* Read in entrypoint as a hex string. */
|
||||
sscanf(value, "%x", &x);
|
||||
config->entrypoint = x;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
void load_stage2(const char *bct0) {
|
||||
stage2_config_t config = {0};
|
||||
FILINFO info;
|
||||
size_t size;
|
||||
uintptr_t tmp_addr;
|
||||
|
||||
if (ini_parse_string(bct0, stage2_ini_handler, &config) < 0) {
|
||||
fatal_error("Failed to parse BCT.ini!\n");
|
||||
}
|
||||
|
||||
if (config.load_address == 0 || config.path[0] == '\x00') {
|
||||
fatal_error("Failed to determine where to load stage2!\n");
|
||||
}
|
||||
|
||||
if (strlen(config.path) + 1 + sizeof(stage2_args_t) > CHAINLOADER_ARG_DATA_MAX_SIZE) {
|
||||
print(SCREEN_LOG_LEVEL_ERROR, "Stage2's path name is too big!\n");
|
||||
}
|
||||
|
||||
if (!check_32bit_address_loadable(config.entrypoint)) {
|
||||
fatal_error("Stage2's entrypoint is invalid!\n");
|
||||
}
|
||||
|
||||
if (!check_32bit_address_loadable(config.load_address)) {
|
||||
fatal_error("Stage2's load address is invalid!\n");
|
||||
}
|
||||
|
||||
print(SCREEN_LOG_LEVEL_DEBUG, "Stage 2 Config:\n");
|
||||
print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, " File Path: %s\n", config.path);
|
||||
print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, " Load Address: 0x%08x\n", config.load_address);
|
||||
print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, " Entrypoint: 0x%p\n", config.entrypoint);
|
||||
|
||||
if (f_stat(config.path, &info) != FR_OK) {
|
||||
fatal_error("Failed to stat stage2 (%s)!\n", config.path);
|
||||
}
|
||||
|
||||
size = (size_t)info.fsize;
|
||||
|
||||
/* the LFB is located at 0xC0000000 atm */
|
||||
if (size > 0xC0000000u - 0x80000000u) {
|
||||
fatal_error("Stage2 is way too big!\n");
|
||||
}
|
||||
|
||||
if (!check_32bit_address_range_loadable(config.load_address, size)) {
|
||||
fatal_error("Stage2 has an invalid load address & size combination (0x%08x 0x%08x)!\n", config.load_address, size);
|
||||
}
|
||||
|
||||
if (config.entrypoint < config.load_address || config.entrypoint >= config.load_address + size) {
|
||||
fatal_error("Stage2's entrypoint is outside Stage2!\n");
|
||||
}
|
||||
|
||||
if (check_32bit_address_range_in_program(config.load_address, size)) {
|
||||
tmp_addr = 0x80000000u;
|
||||
} else {
|
||||
tmp_addr = config.load_address;
|
||||
}
|
||||
|
||||
if (read_from_file((void *)tmp_addr, size, config.path) != size) {
|
||||
fatal_error("Failed to read stage2 (%s)!\n", config.path);
|
||||
}
|
||||
|
||||
g_chainloader_num_entries = 1;
|
||||
g_chainloader_entries[0].load_address = config.load_address;
|
||||
g_chainloader_entries[0].src_address = tmp_addr;
|
||||
g_chainloader_entries[0].size = size;
|
||||
g_chainloader_entries[0].num = 0;
|
||||
g_chainloader_entrypoint = config.entrypoint;
|
||||
|
||||
strncpy(g_stage2_path, config.path, sizeof(g_stage2_path) - 1);
|
||||
g_stage2_path[sizeof(g_stage2_path) - 1] = '\0';
|
||||
}
|
||||
55
sept/sept-secondary/src/stage2.h
Normal file
55
sept/sept-secondary/src/stage2.h
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_STAGE2_H
|
||||
#define FUSEE_STAGE2_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "display/video_fb.h"
|
||||
#include "lib/log.h"
|
||||
#include "lib/vsprintf.h"
|
||||
#include "lib/ini.h"
|
||||
#include "lib/fatfs/ff.h"
|
||||
|
||||
/* TODO: Is there a more concise way to do this? */
|
||||
#define STAGE2_ARGV_PROGRAM_PATH 0
|
||||
#define STAGE2_ARGV_ARGUMENT_STRUCT 1
|
||||
#define STAGE2_ARGC 2
|
||||
|
||||
#define STAGE2_NAME_KEY "stage2_path"
|
||||
#define STAGE2_ADDRESS_KEY "stage2_addr"
|
||||
#define STAGE2_ENTRYPOINT_KEY "stage2_entrypoint"
|
||||
#define BCTO_MAX_SIZE 0x5800
|
||||
|
||||
typedef struct {
|
||||
char path[0x100];
|
||||
uintptr_t load_address;
|
||||
uintptr_t entrypoint;
|
||||
} stage2_config_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t version;
|
||||
ScreenLogLevel log_level;
|
||||
bool display_initialized;
|
||||
char bct0[BCTO_MAX_SIZE];
|
||||
} stage2_args_t;
|
||||
|
||||
const char *stage2_get_program_path(void);
|
||||
void load_stage2(const char *bct0);
|
||||
|
||||
#endif
|
||||
86
sept/sept-secondary/src/start.s
Normal file
86
sept/sept-secondary/src/start.s
Normal file
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
.macro CLEAR_GPR_REG_ITER
|
||||
mov r\@, #0
|
||||
.endm
|
||||
|
||||
.section .text.start, "ax", %progbits
|
||||
.arm
|
||||
.align 5
|
||||
.global _start
|
||||
.type _start, %function
|
||||
_start:
|
||||
/* Switch to system mode, mask all interrupts, clear all flags */
|
||||
msr cpsr_cxsf, #0xDF
|
||||
|
||||
/* Relocate ourselves if necessary */
|
||||
ldr r2, =__start__
|
||||
adr r3, _start
|
||||
cmp r2, r3
|
||||
beq _relocation_loop_end
|
||||
|
||||
ldr r4, =_relocation_loop_end
|
||||
mov r4, #0x1000
|
||||
mov r1, #0x0
|
||||
_relocation_loop:
|
||||
ldmia r3!, {r5-r12}
|
||||
stmia r2!, {r5-r12}
|
||||
add r1, r1, #0x20
|
||||
cmp r1, r4
|
||||
bne _relocation_loop
|
||||
|
||||
ldr r12, =_second_relocation_start
|
||||
bx r12
|
||||
|
||||
_second_relocation_start:
|
||||
ldr r4, =__bss_start__
|
||||
sub r4, r4, r2
|
||||
mov r1, #0x0
|
||||
|
||||
_second_relocation_loop:
|
||||
ldmia r3!, {r5-r12}
|
||||
stmia r2!, {r5-r12}
|
||||
add r1, r1, #0x20
|
||||
cmp r1, r4
|
||||
bne _second_relocation_loop
|
||||
|
||||
ldr r12, =_relocation_loop_end
|
||||
bx r12
|
||||
|
||||
_relocation_loop_end:
|
||||
|
||||
/* Set the stack pointer */
|
||||
ldr sp, =__stack_top__
|
||||
mov fp, #0
|
||||
bl __program_init
|
||||
|
||||
/* Set r0 to r12 to 0 (for debugging) & call main */
|
||||
.rept 13
|
||||
CLEAR_GPR_REG_ITER
|
||||
.endr
|
||||
ldr lr, =__program_exit
|
||||
b main
|
||||
|
||||
/* No need to include this in normal programs: */
|
||||
.section .chainloader.text.start, "ax", %progbits
|
||||
.arm
|
||||
.align 5
|
||||
.global relocate_and_chainload
|
||||
.type relocate_and_chainload, %function
|
||||
relocate_and_chainload:
|
||||
ldr sp, =__stack_top__
|
||||
b relocate_and_chainload_main
|
||||
44
sept/sept-secondary/src/sysctr0.h
Normal file
44
sept/sept-secondary/src/sysctr0.h
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_SYSCTR0_H
|
||||
#define FUSEE_SYSCTR0_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define SYSCTR0_BASE 0x700F0000
|
||||
#define MAKE_SYSCTR0_REG(n) MAKE_REG32(SYSCTR0_BASE + n)
|
||||
|
||||
#define SYSCTR0_CNTCR_0 MAKE_SYSCTR0_REG(0x00)
|
||||
#define SYSCTR0_CNTSR_0 MAKE_SYSCTR0_REG(0x04)
|
||||
#define SYSCTR0_CNTCV0_0 MAKE_SYSCTR0_REG(0x08)
|
||||
#define SYSCTR0_CNTCV1_0 MAKE_SYSCTR0_REG(0x0C)
|
||||
#define SYSCTR0_CNTFID0_0 MAKE_SYSCTR0_REG(0x20)
|
||||
#define SYSCTR0_CNTFID1_0 MAKE_SYSCTR0_REG(0x24)
|
||||
#define SYSCTR0_COUNTERID4_0 MAKE_SYSCTR0_REG(0xFD0)
|
||||
#define SYSCTR0_COUNTERID5_0 MAKE_SYSCTR0_REG(0xFD4)
|
||||
#define SYSCTR0_COUNTERID6_0 MAKE_SYSCTR0_REG(0xFD8)
|
||||
#define SYSCTR0_COUNTERID7_0 MAKE_SYSCTR0_REG(0xFDC)
|
||||
#define SYSCTR0_COUNTERID0_0 MAKE_SYSCTR0_REG(0xFE0)
|
||||
#define SYSCTR0_COUNTERID1_0 MAKE_SYSCTR0_REG(0xFE4)
|
||||
#define SYSCTR0_COUNTERID2_0 MAKE_SYSCTR0_REG(0xFE8)
|
||||
#define SYSCTR0_COUNTERID3_0 MAKE_SYSCTR0_REG(0xFEC)
|
||||
#define SYSCTR0_COUNTERID8_0 MAKE_SYSCTR0_REG(0xFF0)
|
||||
#define SYSCTR0_COUNTERID9_0 MAKE_SYSCTR0_REG(0xFF4)
|
||||
#define SYSCTR0_COUNTERID10_0 MAKE_SYSCTR0_REG(0xFF8)
|
||||
#define SYSCTR0_COUNTERID11_0 MAKE_SYSCTR0_REG(0xFFC)
|
||||
|
||||
#endif
|
||||
48
sept/sept-secondary/src/sysreg.h
Normal file
48
sept/sept-secondary/src/sysreg.h
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_SYSREG_H
|
||||
#define FUSEE_SYSREG_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define SYSREG_BASE 0x6000C000
|
||||
#define SB_BASE (SYSREG_BASE + 0x200)
|
||||
#define EXCP_VEC_BASE 0x6000F000
|
||||
|
||||
#define MAKE_SYSREG(n) MAKE_REG32(SYSREG_BASE + n)
|
||||
#define MAKE_SB_REG(n) MAKE_REG32(SB_BASE + n)
|
||||
#define MAKE_EXCP_VEC_REG(n) MAKE_REG32(EXCP_VEC_BASE + n)
|
||||
|
||||
#define AHB_ARBITRATION_DISABLE_0 MAKE_SYSREG(0x004)
|
||||
#define AHB_ARBITRATION_XBAR_CTRL_0 MAKE_SYSREG(0x0E0)
|
||||
#define AHB_AHB_SPARE_REG_0 MAKE_SYSREG(0x110)
|
||||
|
||||
#define SB_CSR_0 MAKE_SB_REG(0x00)
|
||||
#define SB_PIROM_START_0 MAKE_SB_REG(0x04)
|
||||
#define SB_PFCFG_0 MAKE_SB_REG(0x08)
|
||||
#define SB_SECURE_SPAREREG_0_0 MAKE_SB_REG(0x0C)
|
||||
#define SB_SECURE_SPAREREG_1_0 MAKE_SB_REG(0x10)
|
||||
#define SB_SECURE_SPAREREG_2_0 MAKE_SB_REG(0x14)
|
||||
#define SB_SECURE_SPAREREG_3_0 MAKE_SB_REG(0x18)
|
||||
#define SB_SECURE_SPAREREG_4_0 MAKE_SB_REG(0x1C)
|
||||
#define SB_SECURE_SPAREREG_5_0 MAKE_SB_REG(0x20)
|
||||
#define SB_SECURE_SPAREREG_6_0 MAKE_SB_REG(0x24)
|
||||
#define SB_SECURE_SPAREREG_7_0 MAKE_SB_REG(0x28)
|
||||
#define SB_AA64_RESET_LOW_0 MAKE_SB_REG(0x30)
|
||||
#define SB_AA64_RESET_HIGH_0 MAKE_SB_REG(0x34)
|
||||
|
||||
#endif
|
||||
94
sept/sept-secondary/src/timers.h
Normal file
94
sept/sept-secondary/src/timers.h
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_TIMERS_H
|
||||
#define FUSEE_TIMERS_H
|
||||
|
||||
#include "utils.h"
|
||||
|
||||
#define TIMERS_BASE 0x60005000
|
||||
#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
|
||||
|
||||
#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
|
||||
#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
|
||||
#define SHARED_INTR_STATUS_0 MAKE_TIMERS_REG(0x1A0)
|
||||
#define SHARED_TIMER_SECURE_CFG_0 MAKE_TIMERS_REG(0x1A4)
|
||||
|
||||
#define RTC_BASE 0x7000E000
|
||||
#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
|
||||
|
||||
#define RTC_SECONDS MAKE_RTC_REG(0x08)
|
||||
#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
|
||||
#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
|
||||
|
||||
typedef struct {
|
||||
uint32_t CONFIG;
|
||||
uint32_t STATUS;
|
||||
uint32_t COMMAND;
|
||||
uint32_t PATTERN;
|
||||
} watchdog_timers_t;
|
||||
|
||||
#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
|
||||
#define WDT_REBOOT_PATTERN 0xC45A
|
||||
#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8 * n)
|
||||
|
||||
void wait(uint32_t microseconds);
|
||||
|
||||
static inline uint32_t get_time_s(void) {
|
||||
return RTC_SECONDS;
|
||||
}
|
||||
|
||||
static inline uint32_t get_time_ms(void) {
|
||||
return (RTC_MILLI_SECONDS | (RTC_SHADOW_SECONDS << 10));
|
||||
}
|
||||
|
||||
static inline uint32_t get_time_us(void) {
|
||||
return TIMERUS_CNTR_1US_0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns the time in microseconds.
|
||||
*/
|
||||
static inline uint32_t get_time(void) {
|
||||
return get_time_us();
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns the number of microseconds that have passed since a given get_time().
|
||||
*/
|
||||
static inline uint32_t get_time_since(uint32_t base) {
|
||||
return get_time_us() - base;
|
||||
}
|
||||
|
||||
/**
|
||||
* Delays for a given number of microseconds.
|
||||
*/
|
||||
static inline void udelay(uint32_t usecs) {
|
||||
uint32_t start = get_time_us();
|
||||
while (get_time_us() - start < usecs);
|
||||
}
|
||||
|
||||
/**
|
||||
* Delays for a given number of milliseconds.
|
||||
*/
|
||||
static inline void mdelay(uint32_t msecs) {
|
||||
uint32_t start = get_time_ms();
|
||||
while (get_time_ms() - start < msecs);
|
||||
}
|
||||
|
||||
__attribute__ ((noreturn)) void watchdog_reboot(void);
|
||||
|
||||
#endif
|
||||
72
sept/sept-secondary/src/uart.c
Normal file
72
sept/sept-secondary/src/uart.c
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "uart.h"
|
||||
#include "timers.h"
|
||||
|
||||
void uart_init(UartDevice dev, uint32_t baud) {
|
||||
volatile tegra_uart_t *uart = uart_get_regs(dev);
|
||||
|
||||
/* Set baud rate. */
|
||||
uint32_t rate = (8 * baud + 408000000) / (16 * baud);
|
||||
uart->UART_LCR = UART_LCR_DLAB; /* Enable DLAB. */
|
||||
uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */
|
||||
uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */
|
||||
uart->UART_LCR = 0; /* Diable DLAB. */
|
||||
|
||||
/* Setup UART in fifo mode. */
|
||||
uart->UART_IER_DLAB = 0;
|
||||
uart->UART_IIR_FCR = UART_FCR_FCR_EN_FIFO | UART_FCR_RX_CLR | UART_FCR_TX_CLR; /* Enable and clear TX and RX FIFOs. */
|
||||
(void)uart->UART_LSR;
|
||||
udelay(3 * ((baud + 999999) / baud));
|
||||
uart->UART_LCR = UART_LCR_WD_LENGTH_8; /* Set word length 8. */
|
||||
uart->UART_MCR = 0;
|
||||
uart->UART_MSR = 0;
|
||||
uart->UART_IRDA_CSR = 0;
|
||||
uart->UART_RX_FIFO_CFG = 1; /* Set RX_FIFO trigger level */
|
||||
uart->UART_MIE = 0;
|
||||
uart->UART_ASR = 0;
|
||||
}
|
||||
|
||||
/* This function blocks until the UART device (dev) is in the desired state (status). Make sure the desired state can be reached! */
|
||||
void uart_wait_idle(UartDevice dev, UartVendorStatus status) {
|
||||
while (!(uart_get_regs(dev)->UART_VENDOR_STATUS & status)) {
|
||||
/* Wait */
|
||||
}
|
||||
}
|
||||
|
||||
void uart_send(UartDevice dev, const void *buf, size_t len) {
|
||||
volatile tegra_uart_t *uart = uart_get_regs(dev);
|
||||
|
||||
for (size_t i = 0; i < len; i++) {
|
||||
while (uart->UART_LSR & UART_LSR_TX_FIFO_FULL) {
|
||||
/* Wait until the TX FIFO isn't full */
|
||||
}
|
||||
uart->UART_THR_DLAB = *((const uint8_t *)buf + i);
|
||||
}
|
||||
}
|
||||
|
||||
void uart_recv(UartDevice dev, void *buf, size_t len) {
|
||||
volatile tegra_uart_t *uart = uart_get_regs(dev);
|
||||
|
||||
for (size_t i = 0; i < len; i++) {
|
||||
while (uart->UART_LSR & UART_LSR_RX_FIFO_EMPTY) {
|
||||
/* Wait until the RX FIFO isn't empty */
|
||||
}
|
||||
*((uint8_t *)buf + i) = uart->UART_THR_DLAB;
|
||||
}
|
||||
}
|
||||
170
sept/sept-secondary/src/uart.h
Normal file
170
sept/sept-secondary/src/uart.h
Normal file
|
|
@ -0,0 +1,170 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_UART_H
|
||||
#define FUSEE_UART_H
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#define UART_BASE 0x70006000
|
||||
|
||||
#define BAUD_115200 115200
|
||||
|
||||
/* UART devices */
|
||||
typedef enum {
|
||||
UART_A = 0,
|
||||
UART_B = 1,
|
||||
UART_C = 2,
|
||||
UART_D = 3,
|
||||
UART_E = 4,
|
||||
} UartDevice;
|
||||
|
||||
/* 36.3.12 UART_VENDOR_STATUS_0_0 */
|
||||
typedef enum {
|
||||
UART_VENDOR_STATE_TX_IDLE = 1 << 0,
|
||||
UART_VENDOR_STATE_RX_IDLE = 1 << 1,
|
||||
|
||||
/* This bit is set to 1 when a read is issued to an empty FIFO and gets cleared on register read (sticky bit until read)
|
||||
0 = NO_UNDERRUN
|
||||
1 = UNDERRUN
|
||||
*/
|
||||
UART_VENDOR_STATE_RX_UNDERRUN = 1 << 2,
|
||||
|
||||
/* This bit is set to 1 when write data is issued to the TX FIFO when it is already full and gets cleared on register read (sticky bit until read)
|
||||
0 = NO_OVERRUN
|
||||
1 = OVERRUN
|
||||
*/
|
||||
UART_VENDOR_STATE_TX_OVERRUN = 1 << 3,
|
||||
|
||||
UART_VENDOR_STATE_RX_FIFO_COUNTER = 0b111111 << 16, /* reflects number of current entries in RX FIFO */
|
||||
UART_VENDOR_STATE_TX_FIFO_COUNTER = 0b111111 << 24 /* reflects number of current entries in TX FIFO */
|
||||
} UartVendorStatus;
|
||||
|
||||
/* 36.3.6 UART_LSR_0 */
|
||||
typedef enum {
|
||||
UART_LSR_RDR = 1 << 0, /* Receiver Data Ready */
|
||||
UART_LSR_OVRF = 1 << 1, /* Receiver Overrun Error */
|
||||
UART_LSR_PERR = 1 << 2, /* Parity Error */
|
||||
UART_LSR_FERR = 1 << 3, /* Framing Error */
|
||||
UART_LSR_BRK = 1 << 4, /* BREAK condition detected on line */
|
||||
UART_LSR_THRE = 1 << 5, /* Transmit Holding Register is Empty -- OK to write data */
|
||||
UART_LSR_TMTY = 1 << 6, /* Transmit Shift Register empty status */
|
||||
UART_LSR_FIFOE = 1 << 7, /* Receive FIFO Error */
|
||||
UART_LSR_TX_FIFO_FULL = 1 << 8, /* Transmitter FIFO full status */
|
||||
UART_LSR_RX_FIFO_EMPTY = 1 << 9, /* Receiver FIFO empty status */
|
||||
} UartLineStatus;
|
||||
|
||||
/* 36.3.4 UART_LCR_0 */
|
||||
typedef enum {
|
||||
UART_LCR_WD_LENGTH_5 = 0, /* word length 5 */
|
||||
UART_LCR_WD_LENGTH_6 = 1, /* word length 6 */
|
||||
UART_LCR_WD_LENGTH_7 = 2, /* word length 7 */
|
||||
UART_LCR_WD_LENGTH_8 = 3, /* word length 8 */
|
||||
|
||||
/* STOP:
|
||||
0 = Transmit 1 stop bit
|
||||
1 = Transmit 2 stop bits (receiver always checks for 1 stop bit)
|
||||
*/
|
||||
UART_LCR_STOP = 1 << 2,
|
||||
UART_LCR_PAR = 1 << 3, /* Parity enabled */
|
||||
UART_LCR_EVEN = 1 << 4, /* Even parity format. There will always be an even number of 1s in the binary representation (PAR = 1) */
|
||||
UART_LCR_SET_P = 1 << 5, /* Set (force) parity to value in LCR[4] */
|
||||
UART_LCR_SET_B = 1 << 6, /* Set BREAK condition -- Transmitter sends all zeroes to indicate BREAK */
|
||||
UART_LCR_DLAB = 1 << 7, /* Divisor Latch Access Bit (set to allow programming of the DLH, DLM Divisors) */
|
||||
} UartLineControl;
|
||||
|
||||
/* 36.3.3 UART_IIR_FCR_0 */
|
||||
typedef enum {
|
||||
UART_FCR_FCR_EN_FIFO = 1 << 0, /* Enable the transmit and receive FIFOs. This bit should be enabled */
|
||||
UART_FCR_RX_CLR = 1 << 1, /* Clears the contents of the receive FIFO and resets its counter logic to 0 (the receive shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */
|
||||
UART_FCR_TX_CLR = 1 << 2, /* Clears the contents of the transmit FIFO and resets its counter logic to 0 (the transmit shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */
|
||||
|
||||
/* DMA:
|
||||
0 = DMA_MODE_0
|
||||
1 = DMA_MODE_1
|
||||
*/
|
||||
UART_FCR_DMA = 1 << 3,
|
||||
|
||||
/* TX_TRIG
|
||||
0 = FIFO_COUNT_GREATER_16
|
||||
1 = FIFO_COUNT_GREATER_8
|
||||
2 = FIFO_COUNT_GREATER_4
|
||||
3 = FIFO_COUNT_GREATER_1
|
||||
*/
|
||||
UART_FCR_TX_TRIG = 3 << 4,
|
||||
UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_16 = 0 << 4,
|
||||
UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_8 = 1 << 4,
|
||||
UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_4 = 2 << 4,
|
||||
UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_1 = 3 << 4,
|
||||
|
||||
/* RX_TRIG
|
||||
0 = FIFO_COUNT_GREATER_1
|
||||
1 = FIFO_COUNT_GREATER_4
|
||||
2 = FIFO_COUNT_GREATER_8
|
||||
3 = FIFO_COUNT_GREATER_16
|
||||
*/
|
||||
UART_FCR_RX_TRIG = 3 << 6,
|
||||
UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_1 = 0 << 6,
|
||||
UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_4 = 1 << 6,
|
||||
UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_8 = 2 << 6,
|
||||
UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_16 = 3 << 6,
|
||||
} UartFifoControl;
|
||||
|
||||
/* 36.3.3 UART_IIR_FCR_0 */
|
||||
typedef enum {
|
||||
UART_IIR_IS_STA = 1 << 0, /* Interrupt Pending if ZERO */
|
||||
UART_IIR_IS_PRI0 = 1 << 1, /* Encoded Interrupt ID Refer to IIR[3:0] table [36.3.3] */
|
||||
UART_IIR_IS_PRI1 = 1 << 2, /* Encoded Interrupt ID Refer to IIR[3:0] table */
|
||||
UART_IIR_IS_PRI2 = 1 << 3, /* Encoded Interrupt ID Refer to IIR[3:0] table */
|
||||
|
||||
/* FIFO Mode Status
|
||||
0 = 16450 mode (no FIFO)
|
||||
1 = 16550 mode (FIFO)
|
||||
*/
|
||||
UART_IIR_EN_FIFO = 3 << 6,
|
||||
UART_IIR_MODE_16450 = 0 << 6,
|
||||
UART_IIR_MODE_16550 = 1 << 6,
|
||||
} UartInterruptIdentification;
|
||||
|
||||
typedef struct {
|
||||
uint32_t UART_THR_DLAB;
|
||||
uint32_t UART_IER_DLAB;
|
||||
uint32_t UART_IIR_FCR;
|
||||
uint32_t UART_LCR;
|
||||
uint32_t UART_MCR;
|
||||
uint32_t UART_LSR;
|
||||
uint32_t UART_MSR;
|
||||
uint32_t UART_SPR;
|
||||
uint32_t UART_IRDA_CSR;
|
||||
uint32_t UART_RX_FIFO_CFG;
|
||||
uint32_t UART_MIE;
|
||||
uint32_t UART_VENDOR_STATUS;
|
||||
uint8_t _0x30[0x0C];
|
||||
uint32_t UART_ASR;
|
||||
} tegra_uart_t;
|
||||
|
||||
void uart_init(UartDevice dev, uint32_t baud);
|
||||
void uart_wait_idle(UartDevice dev, UartVendorStatus status);
|
||||
void uart_send(UartDevice dev, const void *buf, size_t len);
|
||||
void uart_recv(UartDevice dev, void *buf, size_t len);
|
||||
|
||||
static inline volatile tegra_uart_t *uart_get_regs(UartDevice dev) {
|
||||
static const size_t offsets[] = {0, 0x40, 0x200, 0x300, 0x400};
|
||||
return (volatile tegra_uart_t *)(UART_BASE + offsets[dev]);
|
||||
}
|
||||
|
||||
#endif
|
||||
150
sept/sept-secondary/src/utils.c
Normal file
150
sept/sept-secondary/src/utils.c
Normal file
|
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdarg.h>
|
||||
#include "utils.h"
|
||||
#include "se.h"
|
||||
#include "fuse.h"
|
||||
#include "pmc.h"
|
||||
#include "timers.h"
|
||||
#include "panic.h"
|
||||
#include "car.h"
|
||||
#include "btn.h"
|
||||
|
||||
#include "lib/log.h"
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#define u8 uint8_t
|
||||
#define u32 uint32_t
|
||||
#include "rebootstub_bin.h"
|
||||
#undef u8
|
||||
#undef u32
|
||||
|
||||
void wait(uint32_t microseconds) {
|
||||
uint32_t old_time = TIMERUS_CNTR_1US_0;
|
||||
while (TIMERUS_CNTR_1US_0 - old_time <= microseconds) {
|
||||
/* Spin-lock. */
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((noreturn)) void watchdog_reboot(void) {
|
||||
volatile watchdog_timers_t *wdt = GET_WDT(4);
|
||||
wdt->PATTERN = WDT_REBOOT_PATTERN;
|
||||
wdt->COMMAND = 2; /* Disable Counter. */
|
||||
GET_WDT_REBOOT_CFG_REG(4) = 0xC0000000;
|
||||
wdt->CONFIG = 0x8019; /* Full System Reset after Fourth Counter expires, using TIMER(9). */
|
||||
wdt->COMMAND = 1; /* Enable Counter. */
|
||||
while (true) {
|
||||
/* Wait for reboot. */
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((noreturn)) void pmc_reboot(uint32_t scratch0) {
|
||||
APBDEV_PMC_SCRATCH0_0 = scratch0;
|
||||
|
||||
/* Reset the processor. */
|
||||
APBDEV_PMC_CONTROL = BIT(4);
|
||||
|
||||
while (true) {
|
||||
/* Wait for reboot. */
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((noreturn)) void reboot_to_self(void) {
|
||||
/* Patch SDRAM init to perform an SVC immediately after second write */
|
||||
APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF;
|
||||
APBDEV_PMC_SCRATCH46_0 = 0x6001DC28;
|
||||
/* Set SVC handler to jump to reboot stub in IRAM. */
|
||||
APBDEV_PMC_SCRATCH33_0 = 0x4003F000;
|
||||
APBDEV_PMC_SCRATCH40_0 = 0x6000F208;
|
||||
|
||||
/* Copy reboot stub into IRAM high. */
|
||||
for (size_t i = 0; i < rebootstub_bin_size; i += sizeof(uint32_t)) {
|
||||
write32le((void *)0x4003F000, i, read32le(rebootstub_bin, i));
|
||||
}
|
||||
|
||||
/* Trigger warm reboot. */
|
||||
pmc_reboot(1 << 0);
|
||||
}
|
||||
|
||||
__attribute__((noreturn)) void wait_for_button_and_reboot(void) {
|
||||
uint32_t button;
|
||||
while (true) {
|
||||
button = btn_read();
|
||||
if (button & BTN_POWER) {
|
||||
reboot_to_self();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__ ((noreturn)) void generic_panic(void) {
|
||||
panic(0xFF000006);
|
||||
}
|
||||
|
||||
__attribute__((noreturn)) void fatal_error(const char *fmt, ...) {
|
||||
va_list args;
|
||||
print(SCREEN_LOG_LEVEL_ERROR, "Fatal error: ");
|
||||
va_start(args, fmt);
|
||||
vprint(SCREEN_LOG_LEVEL_ERROR, fmt, args);
|
||||
va_end(args);
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX,"\nPress POWER to reboot\n");
|
||||
wait_for_button_and_reboot();
|
||||
}
|
||||
|
||||
__attribute__((noinline)) bool overlaps(uint64_t as, uint64_t ae, uint64_t bs, uint64_t be)
|
||||
{
|
||||
if(as <= bs && bs <= ae)
|
||||
return true;
|
||||
if(bs <= as && as <= be)
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Adapted from https://gist.github.com/ccbrown/9722406 */
|
||||
void hexdump(const void* data, size_t size, uintptr_t addrbase) {
|
||||
const uint8_t *d = (const uint8_t *)data;
|
||||
char ascii[17];
|
||||
ascii[16] = '\0';
|
||||
|
||||
for (size_t i = 0; i < size; i++) {
|
||||
if (i % 16 == 0) {
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "%0*" PRIXPTR ": | ", 2 * sizeof(addrbase), addrbase + i);
|
||||
}
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "%02X ", d[i]);
|
||||
if (d[i] >= ' ' && d[i] <= '~') {
|
||||
ascii[i % 16] = d[i];
|
||||
} else {
|
||||
ascii[i % 16] = '.';
|
||||
}
|
||||
if ((i+1) % 8 == 0 || i+1 == size) {
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, " ");
|
||||
if ((i+1) % 16 == 0) {
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "| %s \n", ascii);
|
||||
} else if (i+1 == size) {
|
||||
ascii[(i+1) % 16] = '\0';
|
||||
if ((i+1) % 16 <= 8) {
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, " ");
|
||||
}
|
||||
for (size_t j = (i+1) % 16; j < 16; j++) {
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, " ");
|
||||
}
|
||||
print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "| %s \n", ascii);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
131
sept/sept-secondary/src/utils.h
Normal file
131
sept/sept-secondary/src/utils.h
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef FUSEE_UTILS_H
|
||||
#define FUSEE_UTILS_H
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#define BIT(n) (1u << (n))
|
||||
#define BITL(n) (1ull << (n))
|
||||
#define MASK(n) (BIT(n) - 1)
|
||||
#define MASKL(n) (BITL(n) - 1)
|
||||
#define MASK2(a,b) (MASK(a) & ~MASK(b))
|
||||
#define MASK2L(a,b) (MASKL(a) & ~MASKL(b))
|
||||
|
||||
#define MAKE_REG32(a) (*(volatile uint32_t *)(a))
|
||||
|
||||
#define ALIGN(m) __attribute__((aligned(m)))
|
||||
#define PACKED __attribute__((packed))
|
||||
|
||||
#define ALINLINE __attribute__((always_inline))
|
||||
#define NOINLINE __attribute__((noinline))
|
||||
|
||||
#define SET_SYSREG(reg, val) do { temp_reg = (val); __asm__ __volatile__ ("msr " #reg ", %0" :: "r"(temp_reg) : "memory"); } while(false)
|
||||
|
||||
static inline uintptr_t get_physical_address(const void *addr) {
|
||||
return (uintptr_t)addr;
|
||||
}
|
||||
|
||||
static inline uint32_t read32le(const volatile void *dword, size_t offset) {
|
||||
uintptr_t addr = (uintptr_t)dword + offset;
|
||||
volatile uint32_t *target = (uint32_t *)addr;
|
||||
return *target;
|
||||
}
|
||||
|
||||
static inline uint32_t read32be(const volatile void *dword, size_t offset) {
|
||||
return __builtin_bswap32(read32le(dword, offset));
|
||||
}
|
||||
|
||||
static inline uint64_t read64le(const volatile void *qword, size_t offset) {
|
||||
uintptr_t addr = (uintptr_t)qword + offset;
|
||||
volatile uint64_t *target = (uint64_t *)addr;
|
||||
return *target;
|
||||
}
|
||||
|
||||
static inline uint64_t read64be(const volatile void *qword, size_t offset) {
|
||||
return __builtin_bswap64(read64le(qword, offset));
|
||||
}
|
||||
|
||||
static inline void write32le(volatile void *dword, size_t offset, uint32_t value) {
|
||||
uintptr_t addr = (uintptr_t)dword + offset;
|
||||
volatile uint32_t *target = (uint32_t *)addr;
|
||||
*target = value;
|
||||
}
|
||||
|
||||
static inline void write32be(volatile void *dword, size_t offset, uint32_t value) {
|
||||
write32le(dword, offset, __builtin_bswap32(value));
|
||||
}
|
||||
|
||||
static inline void write64le(volatile void *qword, size_t offset, uint64_t value) {
|
||||
uintptr_t addr = (uintptr_t)qword + offset;
|
||||
volatile uint64_t *target = (uint64_t *)addr;
|
||||
*target = value;
|
||||
}
|
||||
|
||||
static inline void write64be(volatile void *qword, size_t offset, uint64_t value) {
|
||||
write64le(qword, offset, __builtin_bswap64(value));
|
||||
}
|
||||
|
||||
static inline bool check_32bit_additive_overflow(uint32_t a, uint32_t b) {
|
||||
return __builtin_add_overflow_p(a, b, (uint32_t)0);
|
||||
}
|
||||
|
||||
static inline bool check_32bit_address_loadable(uintptr_t addr) {
|
||||
/* FWIW the bootROM forbids loading anything between 0x40000000 and 0x40010000, using it for itself... */
|
||||
return (addr >= 0x40010000u && addr < 0x40040000u) || addr >= 0x80000000u;
|
||||
}
|
||||
|
||||
static inline bool check_32bit_address_range_loadable(uintptr_t addr, size_t size) {
|
||||
return
|
||||
!__builtin_add_overflow_p(addr, size, (uintptr_t)0) && /* the range doesn't overflow */
|
||||
check_32bit_address_loadable(addr) && check_32bit_address_loadable(addr + size) && /* bounds are valid */
|
||||
!(addr >= 0x40010000u && addr < 0x40040000u && addr + size >= 0x40040000u) /* the range doesn't cross MMIO */
|
||||
;
|
||||
}
|
||||
|
||||
bool overlaps(uint64_t as, uint64_t ae, uint64_t bs, uint64_t be);
|
||||
static inline bool overlaps_a(const void *as, const void *ae, const void *bs, const void *be) {
|
||||
return overlaps((uint64_t)(uintptr_t)as, (uint64_t)(uintptr_t)ae, (uint64_t)(uintptr_t)bs, (uint64_t)(uintptr_t)be);
|
||||
}
|
||||
|
||||
static inline bool check_32bit_address_range_in_program(uintptr_t addr, size_t size) {
|
||||
extern uint8_t __chainloader_start__[], __chainloader_end__[];
|
||||
extern uint8_t __stack_bottom__[], __stack_top__[];
|
||||
extern uint8_t __start__[], __end__[];
|
||||
uint8_t *start = (uint8_t *)addr, *end = start + size;
|
||||
|
||||
return overlaps_a(start, end, __chainloader_start__, __chainloader_end__) ||
|
||||
overlaps_a(start, end, __stack_bottom__, __stack_top__) ||
|
||||
overlaps_a(start, end, (void *)0xC0000000, (void *)0xC03C0000) || /* framebuffer */
|
||||
overlaps_a(start, end, __start__, __end__);
|
||||
}
|
||||
|
||||
void hexdump(const void* data, size_t size, uintptr_t addrbase);
|
||||
|
||||
__attribute__((noreturn)) void watchdog_reboot(void);
|
||||
__attribute__((noreturn)) void pmc_reboot(uint32_t scratch0);
|
||||
__attribute__((noreturn)) void reboot_to_self(void);
|
||||
__attribute__((noreturn)) void wait_for_button_and_reboot(void);
|
||||
|
||||
__attribute__((noreturn)) void generic_panic(void);
|
||||
|
||||
__attribute__((noreturn)) void fatal_error(const char *fmt, ...);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue