From 5f7308efd1cc906566b826af966e6356c7a552ab Mon Sep 17 00:00:00 2001
From: Michael Scire <SciresM@gmail.com>
Date: Thu, 1 Mar 2018 22:50:00 -0800
Subject: [PATCH] Implement Clock/Reset Driver.

---
 exosphere/src/car.c | 67 +++++++++++++++++++++++++++++++++++++++++++++
 exosphere/src/car.h | 34 +++++++++++++++++++++++
 2 files changed, 101 insertions(+)
 create mode 100644 exosphere/src/car.c
 create mode 100644 exosphere/src/car.h

diff --git a/exosphere/src/car.c b/exosphere/src/car.c
new file mode 100644
index 000000000..689f2d888
--- /dev/null
+++ b/exosphere/src/car.c
@@ -0,0 +1,67 @@
+#include <stdint.h>
+
+#include "utils.h"
+#include "car.h"
+#include "timers.h"
+
+static inline uint32_t get_special_clk_reg(car_device_t dev) {
+    switch (dev) {
+        case CARDEVICE_UARTA: return 0x178;
+        case CARDEVICE_UARTB: return 0x17C;
+        case CARDEVICE_I2C1: return 0x124;
+        case CARDEVICE_I2C5: return 0x128;
+        case CARDEVICE_BPMP: return 0;
+        default: generic_panic();
+    }
+} 
+
+static inline uint32_t get_special_clk_val(car_device_t dev) {
+    switch (dev) {
+        case CARDEVICE_UARTA: return 0;
+        case CARDEVICE_UARTB: return 0;
+        case CARDEVICE_I2C1: return (6 << 29);
+        case CARDEVICE_I2C5: return (6 << 29);
+        case CARDEVICE_BPMP: return 0;
+        default: generic_panic();
+    }
+}
+
+static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x320, 0x328, 0x330, 0x440, 0x448, 0x284, 0x29C};
+static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x300, 0x308, 0x310, 0x430, 0x438, 0x290, 0x2A8}; 
+
+void clk_enable(car_device_t dev) {
+    uint32_t special_reg;
+    if ((special_reg = get_special_clk_reg(dev))) {
+        MAKE_CAR_REG(special_reg) = get_special_clk_val(dev);
+    }
+    MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT((dev & 0x1F));
+}
+
+void clk_disable(car_device_t dev) {
+    MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5] + 0x004) |= BIT((dev & 0x1F));
+}
+
+void rst_enable(car_device_t dev) {
+    MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT((dev & 0x1F));
+}
+
+void rst_disable(car_device_t dev) {
+    MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5] + 0x004) |= BIT((dev & 0x1F));
+}
+
+
+void clkrst_enable(car_device_t dev) {
+    clk_enable(dev);
+    rst_disable(dev);
+}
+
+void clkrst_disable(car_device_t dev) {
+    rst_enable(dev);
+    clk_disable(dev);
+}
+
+void clkrst_reboot(car_device_t dev) {
+    clkrst_disable(dev);
+    wait(100);
+    clkrst_enable(dev);
+}
diff --git a/exosphere/src/car.h b/exosphere/src/car.h
new file mode 100644
index 000000000..f38d35717
--- /dev/null
+++ b/exosphere/src/car.h
@@ -0,0 +1,34 @@
+#ifndef EXOSPHERE_CLOCK_AND_RESET_H
+#define EXOSPHERE_CLOCK_AND_RESET_H
+
+#include <stdint.h>
+
+#include "memory_map.h"
+
+/* Exosphere Driver for the Tegra X1 Clock and Reset registers. */
+
+#define CAR_BASE (MMIO_GET_DEVICE_ADDRESS(MMIO_DEVID_CLKRST))
+
+#define MAKE_CAR_REG(n) (*((volatile uint32_t *)(CAR_BASE + n)))
+
+#define NUM_CAR_BANKS 7
+
+typedef enum {
+    CARDEVICE_UARTA = 6,
+    CARDEVICE_UARTB = 7,
+    CARDEVICE_I2C1 = 12,
+    CARDEVICE_I2C5 = 47,
+    CARDEVICE_BPMP = 1
+} car_device_t;
+
+void clk_enable(car_device_t dev);
+void clk_disable(car_device_t dev);
+void rst_enable(car_device_t dev);
+void rst_disable(car_device_t dev);
+
+void clkrst_enable(car_device_t dev);
+void clkrst_disable(car_device_t dev);
+
+void clkrst_reboot(car_device_t dev);
+
+#endif
\ No newline at end of file