mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 20:31:14 +00:00
thermosphere: introduce "ENSURE"
This commit is contained in:
parent
310048a32c
commit
5b545f89f5
6 changed files with 47 additions and 51 deletions
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@ -56,11 +56,13 @@ INCLUDES := include ../common/include
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#---------------------------------------------------------------------------------
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# options for code generation
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#---------------------------------------------------------------------------------
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ARCH := -march=armv8-a -mtune=cortex-a57 -mgeneral-regs-only -ffixed-x18 #<- important
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# Note: -ffixed-x18 and -mgeneral-regs-only are very important and must be enabled
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ARCH := -march=armv8-a -mtune=cortex-a57 -mgeneral-regs-only -ffixed-x18
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DEFINES := -D__CCPLEX__ -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"\
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-DATMOSPHERE_RELEASE_VERSION_HASH="0x$(AMSHASH)" $(PLATFORM_DEFINES)
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CFLAGS := \
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-g \
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-fmacro-prefix-map=$(TOPDIR)/src/= \
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-Os \
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-ffunction-sections \
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-fdata-sections \
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@ -38,13 +38,10 @@ static void loadKernelViaSemihosting(void)
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DEBUG("Loading kernel via semihosted file I/O... ");
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handle = semihosting_file_open("test_kernel.bin", FOPEN_MODE_RB);
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if (handle < 0) {
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PANIC("failed to open file (%ld)!\n", handle);
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}
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ENSURE2(handle >= 0, "failed to open file (%ld)!\n", handle);
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if ((ret = semihosting_file_read(handle, &len, buf)) < 0) {
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PANIC("failed to read file (%ld)!\n", ret);
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}
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ret = semihosting_file_read(handle, &len, buf);
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ENSURE2(ret >= 0, "failed to read file (%ld)!\n", ret);
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DEBUG("OK!\n");
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semihosting_file_close(handle);
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@ -115,11 +112,8 @@ void thermosphereMain(ExceptionStackFrame *frame, u64 pct)
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if (currentCoreCtx->isBootCore) {
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if (currentCoreCtx->kernelEntrypoint == 0) {
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if (semihosting_connection_supported()) {
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loadKernelViaSemihosting();
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} else {
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PANIC("Kernel not loaded!\n");
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}
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ENSURE2(semihosting_connection_supported(), "Kernel not loaded!\n");
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loadKernelViaSemihosting();
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}
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}
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else {
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@ -178,11 +178,13 @@ void handleMcrMrcCP15Trap(ExceptionStackFrame *frame, ExceptionSyndromeRegister
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bool isRead = (iss & 1) != 0;
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u32 instructionLength = esr.il == 0 ? 2 : 4;
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if (LIKELY(opc1 == 0 && CRn == 14 && CRm == 2 && opc2 <= 1)) {
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iss = opc2 == 0 ? ENCODE_SYSREG_ISS(CNTP_TVAL_EL0) : ENCODE_SYSREG_ISS(CNTP_CTL_EL0);
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} else {
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PANIC("handleMcrMrcTrap: unexpected cp15 register, instruction: %s p15, #%u, r%u, c%u, c%u, #%u\n", isRead ? "mrc" : "mcr", opc1, Rt, CRn, CRm, opc2);
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}
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ENSURE2(
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opc1 == 0 && CRn == 14 && CRm == 2 && opc2 <= 1,
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"unexpected cp15 register, instruction: %s p15, #%u, r%u, c%u, c%u, #%u\n",
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isRead ? "mrc" : "mcr", opc1, Rt, CRn, CRm, opc2
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);
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iss = opc2 == 0 ? ENCODE_SYSREG_ISS(CNTP_TVAL_EL0) : ENCODE_SYSREG_ISS(CNTP_CTL_EL0);
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if (isRead) {
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doMrc(frame, iss, instructionLength, Rt);
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@ -209,11 +211,13 @@ void handleMcrrMrrcCP15Trap(ExceptionStackFrame *frame, ExceptionSyndromeRegiste
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bool isRead = (iss & 1) != 0;
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u32 instructionLength = esr.il == 0 ? 2 : 4;
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if (LIKELY(CRm == 14 && (opc1 == 0 || opc1 == 2))) {
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iss = opc1 == 0 ? ENCODE_SYSREG_ISS(CNTPCT_EL0) : ENCODE_SYSREG_ISS(CNTP_CVAL_EL0);
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} else {
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PANIC("handleMcrrMrrcTrap: unexpected cp15 register, instruction: %s p15, #%u, r%u, r%u, c%u\n", isRead ? "mrrc" : "mcrr", opc1, Rt, Rt, CRm);
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}
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ENSURE2(
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CRm == 14 && (opc1 == 0 || opc1 == 2),
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"handleMcrrMrrcTrap: unexpected cp15 register, instruction: %s p15, #%u, r%u, r%u, c%u\n",
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isRead ? "mrrc" : "mcrr", opc1, Rt, Rt, CRm
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);
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iss = opc1 == 0 ? ENCODE_SYSREG_ISS(CNTPCT_EL0) : ENCODE_SYSREG_ISS(CNTP_CVAL_EL0);
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if (isRead) {
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doMrrc(frame, iss, instructionLength, Rt, Rt2);
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@ -122,17 +122,13 @@ TransportInterface *transportInterfaceCreate(
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)
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{
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u64 irqFlags = recursiveSpinlockLockMaskIrq(&g_transportInterfaceLayerLock);
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if (transportInterfaceListIsEmpty(&g_transportInterfaceFreeList)) {
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PANIC("transportInterfaceCreateAndInit: resource exhaustion\n");
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}
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ENSURE(!transportInterfaceListIsEmpty(&g_transportInterfaceFreeList));
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TransportInterface *iface;
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FOREACH_LINK (link, &g_transportInterfaceList) {
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iface = transportInterfaceGetLinkParent(link);
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if (iface->type == type && iface->id == id) {
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PANIC("transportInterfaceCreateAndInit: device already registered\n");
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}
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ENSURE(iface->type != type || iface->id != id);
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}
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iface = transportInterfaceGetLinkParent(transportInterfaceListGetFirstLink(&g_transportInterfaceFreeList));
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@ -228,9 +224,7 @@ void transportInterfaceSetInterruptAffinity(TransportInterface *iface, u8 affini
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TransportInterface *transportInterfaceIrqHandlerTopHalf(u16 irqId)
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{
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TransportInterface *iface = transportInterfaceFindByIrqId(irqId);
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if (iface == NULL) {
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PANIC("transportInterfaceLayerIrqHandlerTop: irq id %x not found!\n", irqId);
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}
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ENSURE(iface != NULL);
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transportInterfaceAcquire(iface);
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@ -30,16 +30,26 @@
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#define MAKE_REG32(a) (*(volatile u32 *)(uintptr_t)(a))
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#define ALIGN(m) __attribute__((aligned(m)))
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#define PACKED __attribute__((packed))
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#define LIKELY(expr) __builtin_expect((expr), 1)
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#define UNLIKELY(expr) __builtin_expect((expr), 0)
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#define ALIGN(m) __attribute__((aligned(m)))
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#define PACKED __attribute__((packed))
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#define LIKELY(expr) __builtin_expect((expr), 1)
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#define UNLIKELY(expr) __builtin_expect((expr), 0)
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#define ALINLINE __attribute__((always_inline))
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#define ALINLINE __attribute__((always_inline))
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#define TEMPORARY __attribute__((section(".tempbss")))
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#define TEMPORARY __attribute__((section(".tempbss")))
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#define PANIC(...) do { DEBUG(__VA_ARGS__); panic(); } while (false)
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#define PANIC(...) do { DEBUG(__VA_ARGS__); panic(); } while (false)
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// Note: ##__VA_ARGS__ removing the comma if __VA_ARGS__ is empty is a GCC extension; __FUNCTION__ too
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#define ENSURE2(expr, msg, ...)\
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do {\
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if (UNLIKELY(!(expr))) {\
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PANIC("EL2 [core %u]: " __FILE__ ":" STRINGIZE(__LINE__) ": " msg, currentCoreCtx->coreId, ##__VA_ARGS__);\
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}\
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} while (false)
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#define ENSURE(expr) ENSURE2(expr, #expr"\n")
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#define FOREACH_BIT(tmpmsk, var, word) for (u64 tmpmsk = (word), var = __builtin_ctzll(word); tmpmsk != 0; tmpmsk &= ~BITL(var), var = __builtin_ctzll(tmpmsk))
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@ -237,9 +237,7 @@ static void vgicEnqueueVirqState(VirqStateList *list, VirqState *elem)
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{
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VirqState *pos;
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if (vgicIsStateQueued(elem)) {
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PANIC("vgicEnqueueVirqState: unsanitized argument idx=%u previd=%u nextid=%u\n", (u32)vgicGetVirqStateIndex(elem), elem->listPrev, elem->listNext);
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}
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ENSURE(!vgicIsStateQueued(elem));
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for (pos = list->first; pos != vgicGetQueueEnd(); pos = vgicGetNextQueuedVirqState(pos)) {
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// Sort predicate should be stable
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@ -256,9 +254,7 @@ static void vgicDequeueVirqState(VirqStateList *list, VirqState *elem)
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VirqState *prev = vgicGetPrevQueuedVirqState(elem);
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VirqState *next = vgicGetNextQueuedVirqState(elem);
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if (!vgicIsStateQueued(elem)) {
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PANIC("vgicDequeueVirqState: invalid id %x\n", vgicGetVirqStateIndex(elem));
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}
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ENSURE(vgicIsStateQueued(elem));
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--list->size;
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if (prev != vgicGetQueueEnd()) {
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@ -873,9 +869,7 @@ static bool vgicUpdateListRegister(volatile ArmGicV2ListRegister *lr)
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u32 srcCoreId = state->coreId;
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u32 coreId = currentCoreCtx->coreId;
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if (!state->handled) {
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PANIC("vgicUpdateListRegister: improper previous state for now pending irq idx %u, active=%d\n", vgicGetVirqStateIndex(state), (int)state->active);
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}
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ENSURE(state->handled);
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state->active = lrCopy.active;
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@ -995,10 +989,6 @@ void vgicMaintenanceInterruptHandler(void)
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DEBUG("EL2 [core %d]: Group 1 disabled maintenance interrupt\n", (int)currentCoreCtx->coreId);
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}
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if (misr.lrenp) {
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PANIC("EL2 [core %d]: List Register Entry Not Present maintenance interrupt!\n", currentCoreCtx->coreId);
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}
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if (misr.eoi) {
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//DEBUG("EL2 [core %d]: SGI EOI maintenance interrupt\n", currentCoreCtx->coreId);
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}
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@ -1007,6 +997,8 @@ void vgicMaintenanceInterruptHandler(void)
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//DEBUG("EL2 [core %d]: Underflow maintenance interrupt\n", currentCoreCtx->coreId);
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}
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ENSURE2(!misr.lrenp, "List Register Entry Not Present maintenance interrupt!\n");
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// The rest should be handled by the main loop...
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}
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