mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 12:21:18 +00:00
Clean up Fusee's SE API, removing unneeded functionality
This commit is contained in:
Michael Scire
parent
3140ddc301
commit
53cf46d20f
2 changed files with 1 additions and 302 deletions
287
fusee/src/se.c
287
fusee/src/se.c
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@ -4,19 +4,12 @@
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/*#include "interrupt.h"*/
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#include "se.h"
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void trigger_se_rsa_op(void *buf, size_t size);
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void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size);
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/* Globals for driver. */
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static unsigned int (*g_se_callback)(void);
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static unsigned int g_se_modulus_sizes[KEYSLOT_RSA_MAX];
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static unsigned int g_se_exp_sizes[KEYSLOT_RSA_MAX];
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static bool g_se_generated_vector = false;
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static uint8_t g_se_stored_test_vector[0x10];
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/* Initialize a SE linked list. */
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void ll_init(se_ll_t *ll, void *buffer, size_t size) {
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ll->num_entries = 0; /* 1 Entry. */
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@ -30,23 +23,6 @@ void ll_init(se_ll_t *ll, void *buffer, size_t size) {
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}
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}
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void set_security_engine_callback(unsigned int (*callback)(void)) {
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if (callback == NULL || g_se_callback != NULL) {
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generic_panic();
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}
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g_se_callback = callback;
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}
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/* Fires on Security Engine operation completion. */
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void se_operation_completed(void) {
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SECURITY_ENGINE->INT_ENABLE_REG = 0;
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if (g_se_callback != NULL) {
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g_se_callback();
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g_se_callback = NULL;
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}
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}
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void se_check_error_status_reg(void) {
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if (SECURITY_ENGINE->ERR_STATUS_REG) {
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generic_panic();
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@ -59,45 +35,12 @@ void se_check_for_error(void) {
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}
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}
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void se_trigger_interrupt(void) {
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/* TODO intr_set_pending(INTERRUPT_ID_USER_SECURITY_ENGINE); */
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}
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void se_verify_flags_cleared(void) {
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if (SECURITY_ENGINE->FLAGS_REG & 3) {
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generic_panic();
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}
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}
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void se_generate_test_vector(void *vector) {
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/* TODO: Implement real test vector generation. */
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memset(vector, 0, 0x10);
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}
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void se_validate_stored_vector(void) {
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if (!g_se_generated_vector) {
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generic_panic();
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}
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uint8_t ALIGN(16) calc_vector[0x10];
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se_generate_test_vector(calc_vector);
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/* Ensure nobody's messed with the security engine while we slept. */
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if (memcmp(calc_vector, g_se_stored_test_vector, 0x10) != 0) {
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generic_panic();
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}
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}
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void se_generate_stored_vector(void) {
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if (g_se_generated_vector) {
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generic_panic();
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}
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se_generate_test_vector(g_se_stored_test_vector);
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g_se_generated_vector = true;
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}
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/* Set the flags for an AES keyslot. */
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void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags) {
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if (keyslot >= KEYSLOT_AES_MAX) {
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@ -234,93 +177,6 @@ void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_sr
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trigger_se_blocking_op(OP_START, NULL, 0, wrapped_key, wrapped_key_size);
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}
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void se_aes_crypt_insecure_internal(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, unsigned int crypt_config, bool encrypt, unsigned int (*callback)(void)) {
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if (keyslot >= KEYSLOT_AES_MAX) {
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generic_panic();
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}
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if (size == 0) {
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return;
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}
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/* Setup Config register. */
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if (encrypt) {
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SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY);
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} else {
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SECURITY_ENGINE->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY);
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}
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/* Setup Crypto register. */
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SECURITY_ENGINE->CRYPTO_REG = crypt_config | (keyslot << 24) | (encrypt << 8);
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/* Mark this encryption as insecure -- this makes the SE not a secure busmaster. */
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SECURITY_ENGINE->CRYPTO_REG |= 0x80000000;
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/* Appropriate number of blocks. */
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SECURITY_ENGINE->BLOCK_COUNT_REG = (size >> 4) - 1;
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/* Set the callback, for after the async operation. */
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set_security_engine_callback(callback);
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/* Enable SE Interrupt firing for async op. */
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SECURITY_ENGINE->INT_ENABLE_REG = 0x10;
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/* Setup Input/Output lists */
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SECURITY_ENGINE->IN_LL_ADDR_REG = in_ll_paddr;
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SECURITY_ENGINE->OUT_LL_ADDR_REG = out_ll_paddr;
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/* Set registers for operation. */
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SECURITY_ENGINE->ERR_STATUS_REG = SECURITY_ENGINE->ERR_STATUS_REG;
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SECURITY_ENGINE->INT_STATUS_REG = SECURITY_ENGINE->INT_STATUS_REG;
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SECURITY_ENGINE->OPERATION_REG = 1;
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}
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void se_aes_ctr_crypt_insecure(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, const void *ctr, unsigned int (*callback)(void)) {
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/* Unknown what this write does, but official code writes it for CTR mode. */
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SECURITY_ENGINE->_0x80C = 1;
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set_se_ctr(ctr);
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se_aes_crypt_insecure_internal(keyslot, out_ll_paddr, in_ll_paddr, size, 0x81E, true, callback);
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}
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void se_aes_cbc_encrypt_insecure(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, const void *iv, unsigned int (*callback)(void)) {
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set_aes_keyslot_iv(keyslot, iv, 0x10);
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se_aes_crypt_insecure_internal(keyslot, out_ll_paddr, in_ll_paddr, size, 0x44, true, callback);
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}
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void se_aes_cbc_decrypt_insecure(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, const void *iv, unsigned int (*callback)(void)) {
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set_aes_keyslot_iv(keyslot, iv, 0x10);
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se_aes_crypt_insecure_internal(keyslot, out_ll_paddr, in_ll_paddr, size, 0x66, false, callback);
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}
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void se_exp_mod(unsigned int keyslot, void *buf, size_t size, unsigned int (*callback)(void)) {
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uint8_t ALIGN(16) stack_buf[KEYSIZE_RSA_MAX];
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if (keyslot >= KEYSLOT_RSA_MAX || size > KEYSIZE_RSA_MAX) {
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generic_panic();
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}
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/* Endian swap the input. */
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for (size_t i = 0; i < size; i++) {
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stack_buf[i] = *((uint8_t *)buf + size - i - 1);
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}
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SECURITY_ENGINE->CONFIG_REG = (ALG_RSA | DST_RSAREG);
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SECURITY_ENGINE->RSA_CONFIG = keyslot << 24;
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SECURITY_ENGINE->RSA_KEY_SIZE_REG = (g_se_modulus_sizes[keyslot] >> 6) - 1;
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SECURITY_ENGINE->RSA_EXP_SIZE_REG = g_se_exp_sizes[keyslot] >> 2;
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set_security_engine_callback(callback);
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/* Enable SE Interrupt firing for async op. */
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SECURITY_ENGINE->INT_ENABLE_REG = 0x10;
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trigger_se_rsa_op(stack_buf, size);
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while (!(SECURITY_ENGINE->INT_STATUS_REG & 2)) { /* Wait a while */ }
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}
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void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) {
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uint8_t ALIGN(16) stack_buf[KEYSIZE_RSA_MAX];
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@ -414,20 +270,6 @@ bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const v
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return memcmp(h_buf, validate_hash, 0x20) == 0;
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}
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void trigger_se_rsa_op(void *buf, size_t size) {
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se_ll_t in_ll;
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ll_init(&in_ll, (void *)buf, size);
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/* Set the input LL. */
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SECURITY_ENGINE->IN_LL_ADDR_REG = (uint32_t) get_physical_address(&in_ll);
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/* Set registers for operation. */
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SECURITY_ENGINE->ERR_STATUS_REG = SECURITY_ENGINE->ERR_STATUS_REG;
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SECURITY_ENGINE->INT_STATUS_REG = SECURITY_ENGINE->INT_STATUS_REG;
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SECURITY_ENGINE->OPERATION_REG = 1;
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}
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void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size) {
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se_ll_t in_ll;
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se_ll_t out_ll;
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@ -674,132 +516,3 @@ void se_generate_random(unsigned int keyslot, void *dst, size_t size) {
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}
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}
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/* SE context save API. */
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void se_set_in_context_save_mode(bool is_context_save_mode) {
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uint32_t val = SECURITY_ENGINE->_0x0;
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if (is_context_save_mode) {
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val |= 0x10000;
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} else {
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val &= 0xFFFEFFFF;
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}
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SECURITY_ENGINE->_0x0 = val;
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/* Perform a useless read from flags reg. */
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(void)(SECURITY_ENGINE->FLAGS_REG);
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}
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void se_generate_random_key(unsigned int dst_keyslot, unsigned int rng_keyslot) {
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if (dst_keyslot >= KEYSLOT_AES_MAX || rng_keyslot >= KEYSLOT_AES_MAX) {
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generic_panic();
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}
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/* Setup Config. */
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SECURITY_ENGINE->CONFIG_REG = (ALG_RNG | DST_KEYTAB);
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SECURITY_ENGINE->CRYPTO_REG = (rng_keyslot << 24) | 0x108;
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SECURITY_ENGINE->RNG_CONFIG_REG = 4;
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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/* Generate low part of key. */
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SECURITY_ENGINE->CRYPTO_KEYTABLE_DST_REG = (dst_keyslot << 8);
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trigger_se_blocking_op(OP_START, NULL, 0, NULL, 0);
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/* Generate high part of key. */
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SECURITY_ENGINE->CRYPTO_KEYTABLE_DST_REG = (dst_keyslot << 8) | 1;
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trigger_se_blocking_op(OP_START, NULL, 0, NULL, 0);
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}
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void se_generate_srk(unsigned int srkgen_keyslot) {
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SECURITY_ENGINE->CONFIG_REG = (ALG_RNG | DST_SRK);
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SECURITY_ENGINE->CRYPTO_REG = (srkgen_keyslot << 24) | 0x108;
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SECURITY_ENGINE->RNG_CONFIG_REG = 6;
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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trigger_se_blocking_op(OP_START, NULL, 0, NULL, 0);
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}
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void se_encrypt_with_srk(void *dst, size_t dst_size, const void *src, size_t src_size) {
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uint8_t ALIGN(16) output[0x80];
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uint8_t *aligned_out = (uint8_t *)(((uintptr_t)output + 0x7F) & ~0x3F);
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if (dst_size > 0x10) {
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generic_panic();
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}
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if (dst_size) {
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trigger_se_blocking_op(OP_CTX_SAVE, aligned_out, dst_size, src, src_size);
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memcpy(dst, aligned_out, dst_size);
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} else {
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trigger_se_blocking_op(OP_CTX_SAVE, aligned_out, 0, src, src_size);
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}
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}
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void se_save_context(unsigned int srkgen_keyslot, unsigned int rng_keyslot, void *dst) {
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uint8_t ALIGN(16) _work_buf[0x80];
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uint8_t *work_buf = (uint8_t *)(((uintptr_t)_work_buf + 0x7F) & ~0x3F);
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/* Generate the SRK (context save encryption key). */
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se_generate_random_key(srkgen_keyslot, rng_keyslot);
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se_generate_srk(srkgen_keyslot);
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se_generate_random(rng_keyslot, work_buf, 0x10);
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/* Save random initial block. */
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SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY);
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SECURITY_ENGINE->CONTEXT_SAVE_CONFIG_REG = (CTX_SAVE_SRC_MEM);
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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se_encrypt_with_srk(dst, 0x10, work_buf, 0x10);
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/* Save Sticky Bits. */
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for (unsigned int i = 0; i < 0x2; i++) {
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SECURITY_ENGINE->CONTEXT_SAVE_CONFIG_REG = (CTX_SAVE_SRC_STICKY_BITS) | (i << CTX_SAVE_STICKY_BIT_INDEX_SHIFT);
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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se_encrypt_with_srk(dst + 0x10 + (i * 0x10), 0x10, NULL, 0);
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}
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/* Save AES Key Table. */
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for (unsigned int i = 0; i < KEYSLOT_AES_MAX; i++) {
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SECURITY_ENGINE->CONTEXT_SAVE_CONFIG_REG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_LOW_BITS);
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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se_encrypt_with_srk(dst + 0x30 + (i * 0x20), 0x10, NULL, 0);
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SECURITY_ENGINE->CONTEXT_SAVE_CONFIG_REG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_HIGH_BITS);
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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se_encrypt_with_srk(dst + 0x40 + (i * 0x20), 0x10, NULL, 0);
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}
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/* Save AES Original IVs. */
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for (unsigned int i = 0; i < KEYSLOT_AES_MAX; i++) {
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SECURITY_ENGINE->CONTEXT_SAVE_CONFIG_REG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_ORIGINAL_IV);
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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se_encrypt_with_srk(dst + 0x230 + (i * 0x10), 0x10, NULL, 0);
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}
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/* Save AES Updated IVs */
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for (unsigned int i = 0; i < KEYSLOT_AES_MAX; i++) {
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SECURITY_ENGINE->CONTEXT_SAVE_CONFIG_REG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_UPDATED_IV);
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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se_encrypt_with_srk(dst + 0x330 + (i * 0x10), 0x10, NULL, 0);
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}
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/* Save RSA Keytable. */
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uint8_t *rsa_ctx_out = (uint8_t *)dst + 0x430;
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for (unsigned int rsa_key = 0; rsa_key < KEYSLOT_RSA_MAX; rsa_key++) {
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for (unsigned int mod_exp = 0; mod_exp < 2; mod_exp++) {
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for (unsigned int sub_block = 0; sub_block < 0x10; sub_block++) {
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SECURITY_ENGINE->CONTEXT_SAVE_CONFIG_REG = (CTX_SAVE_SRC_KEYTABLE_RSA) | ((2 * rsa_key + (1 - mod_exp)) << CTX_SAVE_RSA_KEY_INDEX_SHIFT) | (sub_block << CTX_SAVE_RSA_KEY_BLOCK_INDEX_SHIFT);
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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se_encrypt_with_srk(rsa_ctx_out, 0x10, NULL, 0);
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rsa_ctx_out += 0x10;
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}
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}
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}
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/* Save "Known Pattern. " */
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static const uint8_t context_save_known_pattern[0x10] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
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SECURITY_ENGINE->CONTEXT_SAVE_CONFIG_REG = (CTX_SAVE_SRC_MEM);
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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se_encrypt_with_srk(dst + 0x830, 0x10, context_save_known_pattern, 0x10);
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/* Save SRK into PMC registers. */
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SECURITY_ENGINE->CONTEXT_SAVE_CONFIG_REG = (CTX_SAVE_SRC_SRK);
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SECURITY_ENGINE->BLOCK_COUNT_REG = 0;
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se_encrypt_with_srk(work_buf, 0, NULL, 0);
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SECURITY_ENGINE->CONFIG_REG = 0;
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se_encrypt_with_srk(work_buf, 0, NULL, 0);
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}
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@ -161,7 +161,6 @@ static inline volatile security_engine_t *get_security_engine(void) {
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#define SECURITY_ENGINE (get_security_engine())
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/* This function MUST be registered to fire on the appropriate interrupt. */
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void se_operation_completed(void);
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void se_check_error_status_reg(void);
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void se_check_for_error(void);
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@ -183,12 +182,6 @@ void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_s
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void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size);
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void set_se_ctr(const void *ctr);
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/* Insecure AES API */
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void se_aes_ctr_crypt_insecure(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, const void *ctr, unsigned int (*callback)(void));
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void se_aes_cbc_encrypt_insecure(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, const void *iv, unsigned int (*callback)(void));
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void se_aes_cbc_decrypt_insecure(unsigned int keyslot, uint32_t out_ll_paddr, uint32_t in_ll_paddr, size_t size, const void *iv, unsigned int (*callback)(void));
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/* Secure AES API */
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void se_compute_aes_128_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size);
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void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size);
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@ -202,7 +195,6 @@ void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, co
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void se_calculate_sha256(void *dst, const void *src, size_t src_size);
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/* RSA API */
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void se_exp_mod(unsigned int keyslot, void *buf, size_t size, unsigned int (*callback)(void));
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||||
void se_get_exp_mod_output(void *buf, size_t size);
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||||
void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size);
|
||||
bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const void *modulus, size_t modulus_size, const void *data, size_t data_size);
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||||
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@ -211,10 +203,4 @@ bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const v
|
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void se_initialize_rng(unsigned int keyslot);
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||||
void se_generate_random(unsigned int keyslot, void *dst, size_t size);
|
||||
|
||||
/* SE context save API. */
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||||
void se_generate_srk(unsigned int srkgen_keyslot);
|
||||
void se_set_in_context_save_mode(bool is_context_save_mode);
|
||||
void se_generate_random_key(unsigned int dst_keyslot, unsigned int rng_keyslot);
|
||||
void se_save_context(unsigned int srk_keyslot, unsigned int rng_keyslot, void *dst);
|
||||
|
||||
#endif /* EXOSPHERE_SE_H */
|
||||
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Loading…
Reference in a new issue