diff --git a/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp b/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp
index b7f850e49..984abd560 100644
--- a/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp
+++ b/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp
@@ -25,6 +25,9 @@
 
 #define APB_MISC_GP_ASDBGREG                  (0x810)
 
+#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL      (0xA9C)
+#define APB_MISC_GP_SDMMC2_PAD_CFGPADCTRL     (0xA9C)
+
 #define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL      (0xAB4)
 #define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL (0xABC)
 
@@ -49,6 +52,15 @@ DEFINE_APB_MISC_REG_BIT_ENUM(PP_CONFIG_CTL_TBE,  7, DISABLE, ENABLE);
 
 DEFINE_APB_MISC_REG(GP_ASDBGREG_CFG2TMC_RAM_SVOP_PDP, 24, 2);
 
+DEFINE_APB_MISC_REG_BIT_ENUM(GP_EMMC2_PAD_CFGPADCTRL_CFG2TMC_EMMC2_PAD_E_SCH,       0, DISABLE, ENABLE);
+DEFINE_APB_MISC_REG         (GP_EMMC2_PAD_CFGPADCTRL_CFG2TMC_EMMC2_PAD_DRVDN_COMP,  2,  6);
+DEFINE_APB_MISC_REG         (GP_EMMC2_PAD_CFGPADCTRL_CFG2TMC_EMMC2_PAD_DRVUP_COMP,  8,  6);
+DEFINE_APB_MISC_REG         (GP_EMMC2_PAD_CFGPADCTRL_MISC2PMC_EMMC2_ALL_PARK,      14, 13);
+
+DEFINE_APB_MISC_REG         (GP_SDMMC2_PAD_CFGPADCTRL_CFG2TMC_SDMMC2_PAD_CAL_DRVDN, 12, 7);
+DEFINE_APB_MISC_REG         (GP_SDMMC2_PAD_CFGPADCTRL_CFG2TMC_SDMMC2_PAD_CAL_DRVUP, 20, 7);
+
+
 DEFINE_APB_MISC_REG_BIT_ENUM(GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_E_SCH,       0, DISABLE, ENABLE);
 DEFINE_APB_MISC_REG         (GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DRVDN_COMP,  2,  6);
 DEFINE_APB_MISC_REG         (GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DRVUP_COMP,  8,  6);
diff --git a/libraries/libvapours/source/sdmmc/impl/sdmmc_sdmmc_controller.board.nintendo_nx.hpp b/libraries/libvapours/source/sdmmc/impl/sdmmc_sdmmc_controller.board.nintendo_nx.hpp
index 64f5d2d70..ce8acc293 100644
--- a/libraries/libvapours/source/sdmmc/impl/sdmmc_sdmmc_controller.board.nintendo_nx.hpp
+++ b/libraries/libvapours/source/sdmmc/impl/sdmmc_sdmmc_controller.board.nintendo_nx.hpp
@@ -288,6 +288,79 @@ namespace ams::sdmmc::impl {
             }
     };
 
+    constexpr inline dd::PhysicalAddress Sdmmc2RegistersPhysicalAddress = UINT64_C(0x700B0200);
+
+    class Sdmmc2Controller : public Sdmmc2And4Controller {
+        private:
+            #if defined(AMS_SDMMC_USE_OS_EVENTS)
+                static constinit inline os::InterruptEventType s_interrupt_event{};
+            #endif
+        protected:
+            virtual void SetPad() override {
+                /* Nothing is needed here. */
+            }
+
+            virtual ClockResetController::Module GetClockResetModule() const override {
+                return ClockResetController::Module_Sdmmc2;
+            }
+
+            #if defined(AMS_SDMMC_USE_OS_EVENTS)
+            virtual int GetInterruptNumber() const override {
+                return 47;
+            }
+
+            virtual os::InterruptEventType *GetInterruptEvent() const override {
+                return std::addressof(s_interrupt_event);
+            }
+            #endif
+
+            virtual void ClearPadParked() override {
+                if (IsSocMariko()) {
+                    /* Nothing is needed here. */
+                } else {
+                    /* Get the apb registers address. */
+                    const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
+
+                    /* Clear all MISC2PMC_EMMC2_*_PARK bits. */
+                    reg::ReadWrite(apb_address + APB_MISC_GP_EMMC2_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_EMMC2_PAD_CFGPADCTRL_MISC2PMC_EMMC2_ALL_PARK, 0));
+
+                    /* Read to be sure our config takes. */
+                    reg::Read(apb_address + APB_MISC_GP_EMMC2_PAD_CFGPADCTRL);
+                }
+            }
+
+            virtual void SetDriveStrengthToDefaultValues(BusPower bus_power) override {
+                /* SDMMC4 only supports 1.8v. */
+                AMS_ABORT_UNLESS(bus_power == BusPower_1_8V);
+
+                /* Ensure that we can control registers. */
+                SdHostStandardController::EnsureControl();
+
+                /* Get the apb registers address. */
+                const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
+
+                if (IsSocMariko()) {
+                    /* Write the drv up/down values to APB_MISC_GP_SDMMC2_PAD_CFGPADCTRL. */
+                    reg::ReadWrite(apb_address + APB_MISC_GP_SDMMC2_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_SDMMC2_PAD_CFGPADCTRL_CFG2TMC_SDMMC2_PAD_CAL_DRVDN, 0xA),
+                                                                                    APB_MISC_REG_BITS_VALUE(GP_SDMMC2_PAD_CFGPADCTRL_CFG2TMC_SDMMC2_PAD_CAL_DRVUP, 0xA));
+
+                    /* Read to be sure our config takes. */
+                    reg::Read(apb_address + APB_MISC_GP_SDMMC2_PAD_CFGPADCTRL);
+                } else {
+                    /* Write the drv up/down values to APB_MISC_GP_EMMC4_PAD_CFGPADCTRL. */
+                    reg::ReadWrite(apb_address + APB_MISC_GP_EMMC2_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_EMMC2_PAD_CFGPADCTRL_CFG2TMC_EMMC2_PAD_DRVDN_COMP, 0x10),
+                                                                                   APB_MISC_REG_BITS_VALUE(GP_EMMC2_PAD_CFGPADCTRL_CFG2TMC_EMMC2_PAD_DRVUP_COMP, 0x10));
+
+                    /* Read to be sure our config takes. */
+                    reg::Read(apb_address + APB_MISC_GP_EMMC2_PAD_CFGPADCTRL);
+                }
+            }
+        public:
+            Sdmmc2Controller() : Sdmmc2And4Controller(Sdmmc2RegistersPhysicalAddress) {
+                /* ... */
+            }
+    };
+
     constexpr inline dd::PhysicalAddress Sdmmc4RegistersPhysicalAddress = UINT64_C(0x700B0600);
 
     class Sdmmc4Controller : public Sdmmc2And4Controller {