mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 20:31:14 +00:00
fusee_cpp: implement tsec_keygen firmware execution
This commit is contained in:
parent
80999988d4
commit
51cf28339b
11 changed files with 270 additions and 53 deletions
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@ -19,6 +19,10 @@ SECTIONS
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.text :
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{
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KEEP(*(.text._ZN3ams4util15GetMicroSecondsEv))
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KEEP(*(.text._ZN3ams4util16WaitMicroSecondsEi))
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KEEP(*(.text._ZN3ams6nxboot14ShowFatalErrorEPKcz))
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_*.o(SORT(.text*))
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*(.text.unlikely .text.*_unlikely .text.unlikely.*)
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*(.text.exit .text.exit.*)
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*(.text.startup .text.startup.*)
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@ -23,7 +23,7 @@ SECTIONS {
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BYTE(0x00);
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}
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.ovl_mtc_erista {
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KEEP(*(.text._ZN3ams6nxboot22DoMemoryTrainingEristaEv))
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KEEP(*(.text._ZN3ams6nxboot22DoMemoryTrainingEristaEi))
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fusee_mtc_erista.o(.text*);
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fusee_mtc_erista.o(.rodata*);
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fusee_mtc_erista.o(.data*);
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@ -33,7 +33,7 @@ SECTIONS {
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BYTE(0x00);
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}
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.ovl_mtc_mariko {
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KEEP(*(.text._ZN3ams6nxboot22DoMemoryTrainingMarikoEv))
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KEEP(*(.text._ZN3ams6nxboot22DoMemoryTrainingMarikoEi))
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fusee_mtc_mariko.o(.text*);
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fusee_mtc_mariko.o(.rodata*);
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fusee_mtc_mariko.o(.data*);
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@ -14,13 +14,40 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "fusee_secondary_archive.hpp"
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#include "fusee_setup_horizon.hpp"
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#include "fusee_fatal.hpp"
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namespace ams::nxboot {
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namespace {
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void DeriveAllKeys(const fuse::SocType soc_type) {
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/* If on erista, run the TSEC keygen firmware. */
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if (soc_type == fuse::SocType_Erista) {
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clkrst::SetBpmpClockRate(clkrst::BpmpClockRate_408MHz);
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if (!tsec::RunTsecFirmware(GetSecondaryArchive().tsec_keygen, sizeof(GetSecondaryArchive().tsec_keygen))) {
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ShowFatalError("Failed to run tsec_keygen firmware!\n");
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}
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clkrst::SetBpmpClockRate(clkrst::BpmpClockRate_576MHz);
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}
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ShowFatalError("DeriveAllKeys not fully implemented\n");
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}
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}
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void SetupAndStartHorizon() {
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/* TODO */
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/* Get soc/hardware type. */
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const auto soc_type = fuse::GetSocType();
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const auto hw_type = fuse::GetHardwareType();
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/* Derive all keys. */
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DeriveAllKeys(soc_type);
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AMS_UNUSED(hw_type);
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ShowFatalError("SetupAndStartHorizon not fully implemented\n");
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}
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@ -17,8 +17,8 @@
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namespace ams::nxboot {
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void DoMemoryTrainingErista();
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void DoMemoryTrainingMariko();
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void DoMemoryTrainingErista(int index);
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void DoMemoryTrainingMariko(int index);
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namespace {
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@ -56,21 +56,23 @@ namespace ams::nxboot {
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/* DramId_MarikoAulaSamsung1y8gbX */ 0x0D,
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};
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int GetMemoryTrainingTableIndex() {
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if (const auto dram_id = fuse::GetDramId(); dram_id < util::size(MemoryTrainingTableIndices) && MemoryTrainingTableIndices[dram_id] != MemoryTrainingTableIndex_Invalid) {
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return static_cast<int>(MemoryTrainingTableIndices[dram_id]);
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} else {
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return -1;
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}
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}
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}
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void DoMemoryTraining() {
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if (fuse::GetSocType() == fuse::SocType_Erista) {
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DoMemoryTrainingErista();
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} else {
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DoMemoryTrainingMariko();
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}
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}
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const auto index = GetMemoryTrainingTableIndex();
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int GetMemoryTrainingTableIndex() {
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if (const auto dram_id = fuse::GetDramId(); dram_id < util::size(MemoryTrainingTableIndices) && MemoryTrainingTableIndices[dram_id] != MemoryTrainingTableIndex_Invalid) {
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return static_cast<int>(MemoryTrainingTableIndices[dram_id]);
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if (fuse::GetSocType() == fuse::SocType_Erista) {
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DoMemoryTrainingErista(index);
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} else {
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return -1;
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DoMemoryTrainingMariko(index);
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}
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}
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@ -20,6 +20,4 @@ namespace ams::nxboot {
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void DoMemoryTraining();
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int GetMemoryTrainingTableIndex();
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}
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@ -72,8 +72,7 @@ namespace ams::nxboot {
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using EmcDvfsTimingTable = erista::EmcDvfsTimingTable;
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EmcDvfsTimingTable *GetEmcDvfsTimingTables() {
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const auto index = GetMemoryTrainingTableIndex();
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EmcDvfsTimingTable *GetEmcDvfsTimingTables(int index) {
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switch (index) {
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case 0:
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case 3:
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@ -2830,11 +2829,11 @@ namespace ams::nxboot {
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}
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void DoMemoryTrainingErista() {
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void DoMemoryTrainingErista(int index) {
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/* Get timing tables. */
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auto *timing_tables = GetEmcDvfsTimingTables();
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auto *src_timing = timing_tables + 0;
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auto *dst_timing = timing_tables + 1;
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auto *timing_tables = GetEmcDvfsTimingTables(index);
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auto *src_timing = timing_tables + 0;
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auto *dst_timing = timing_tables + 1;
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/* Check timing tables. */
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if (src_timing->rate_khz != 204000 || dst_timing->rate_khz != 1600000) {
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@ -27,9 +27,7 @@ namespace ams::nxboot {
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using EmcDvfsTimingTable = mariko::EmcDvfsTimingTable;
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EmcDvfsTimingTable *GetEmcDvfsTimingTables() {
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const auto index = GetMemoryTrainingTableIndex();
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EmcDvfsTimingTable *GetEmcDvfsTimingTables(int index) {
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/* Get the compressed table. */
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u8 *cmp_table;
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size_t cmp_table_size;
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}
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void DoMemoryTrainingMariko() {
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void DoMemoryTrainingMariko(int index) {
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/* Get timing tables. */
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auto *timing_tables = GetEmcDvfsTimingTables();
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auto *timing_tables = GetEmcDvfsTimingTables(index);
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auto *src_timing_tables = timing_tables + 0;
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auto *dst_timing_tables = timing_tables + 1;
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@ -149,7 +149,7 @@ $(OFILES) : $(GCH_FILES)
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$(OFILES_SRC) : $(HFILES_BIN)
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libc.o: CFLAGS += -fno-builtin -fno-lto
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libgcc_division.arch.arm.o: CFLAGS += -fno-builtin -fno-lto
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util_api.o: CXXFLAGS += -fno-lto
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#---------------------------------------------------------------------------------
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%_bin.h %.bin.o : %.bin
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32
libraries/libexosphere/source/kfuse/kfuse_registers.hpp
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32
libraries/libexosphere/source/kfuse/kfuse_registers.hpp
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public LicenKFUSE,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be uKFUSEful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOKFUSE. KFUSEe the GNU General Public LicenKFUSE for
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* more details.
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*
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* You should have received a copy of the GNU General Public LicenKFUSE
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* along with this program. If not, KFUSEe <http://www.gnu.org/licenKFUSEs/>.
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*/
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#include <exosphere.hpp>
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#define KFUSE_STATE (0x080)
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#define KFUSE_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (KFUSE, NAME)
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#define KFUSE_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (KFUSE, NAME, VALUE)
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#define KFUSE_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (KFUSE, NAME, ENUM)
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#define KFUSE_REG_BITS_ENUM_KFUSEL(NAME, __COND__, TRUE_ENUM, FALKFUSE_ENUM) REG_NAMED_BITS_ENUM_KFUSEL(KFUSE, NAME, __COND__, TRUE_ENUM, FALKFUSE_ENUM)
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#define DEFINE_KFUSE_REG(NAME, __OFFKFUSET__, __WIDTH__) REG_DEFINE_NAMED_REG (KFUSE, NAME, __OFFKFUSET__, __WIDTH__)
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#define DEFINE_KFUSE_REG_BIT_ENUM(NAME, __OFFKFUSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (KFUSE, NAME, __OFFKFUSET__, ZERO, ONE)
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#define DEFINE_KFUSE_REG_TWO_BIT_ENUM(NAME, __OFFKFUSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (KFUSE, NAME, __OFFKFUSET__, ZERO, ONE, TWO, THREE)
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#define DEFINE_KFUSE_REG_THREE_BIT_ENUM(NAME, __OFFKFUSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, KFUSEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(KFUSE, NAME, __OFFKFUSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, KFUSEVEN)
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#define DEFINE_KFUSE_REG_FOUR_BIT_ENUM(NAME, __OFFKFUSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, KFUSEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (KFUSE, NAME, __OFFKFUSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, KFUSEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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DEFINE_KFUSE_REG_BIT_ENUM(STATE_DONE, 16, NOT_DONE, DONE);
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DEFINE_KFUSE_REG_BIT_ENUM(STATE_CRCPASS, 17, FAIL, PASS);
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@ -14,46 +14,154 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "tsec_registers.hpp"
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#include "../kfuse/kfuse_registers.hpp"
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namespace ams::tsec {
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namespace {
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enum TsecResult {
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constexpr inline const uintptr_t KFUSE = 0x7000FC00;
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constexpr inline const uintptr_t TSEC = 0x54500000;
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enum TsecResult : u32 {
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TsecResult_Success = 0xB0B0B0B0,
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TsecResult_Failure = 0xD0D0D0D0,
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};
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bool RunFirmwareImpl(const void *fw, size_t fw_size) {
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/* Enable relevant clocks. */
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clkrst::EnableHost1xClock();
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clkrst::EnableTsecClock();
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clkrst::EnableSorSafeClock();
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clkrst::EnableSor0Clock();
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clkrst::EnableSor1Clock();
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clkrst::EnableKfuseClock();
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enum TsecMemory {
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TsecMemory_Imem,
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TsecMemory_Dmem,
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};
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/* Disable clocks once we're done. */
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ON_SCOPE_EXIT {
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clkrst::DisableHost1xClock();
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clkrst::DisableTsecClock();
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clkrst::DisableSorSafeClock();
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clkrst::DisableSor0Clock();
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clkrst::DisableSor1Clock();
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clkrst::DisableKfuseClock();
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};
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bool WaitForKfuseReady() {
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constexpr auto KfuseTimeout = 10 * 1000; /* 10 ms. */
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/* TODO */
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AMS_UNUSED(fw, fw_size);
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return true;
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const u32 end_time = util::GetMicroSeconds() + KfuseTimeout;
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/* Wait for STATE_DONE. */
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while (!reg::HasValue(KFUSE + KFUSE_STATE, KFUSE_REG_BITS_ENUM(STATE_DONE, DONE))) {
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if (util::GetMicroSeconds() >= end_time) {
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return false;
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}
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}
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/* Check for STATE_CRCPASS. */
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return reg::HasValue(KFUSE + KFUSE_STATE, KFUSE_REG_BITS_ENUM(STATE_CRCPASS, PASS));
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}
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void WaitForDmaIdle() {
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constexpr auto DmaTimeout = 10 * 1000 * 1000; /* 10 Seconds. */
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u32 cur_time = util::GetMicroSeconds();
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const u32 end_time = cur_time + DmaTimeout;
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while (cur_time <= end_time) {
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if (reg::HasValue(TSEC + TSEC_FALCON_DMATRFCMD, TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_BUSY, IDLE))) {
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return;
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}
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cur_time = util::GetMicroSeconds();
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}
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AMS_ABORT("tsec dma timeout");
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}
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void WaitForTsecIdle() {
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constexpr auto TsecTimeout = 2 * 1000 * 1000; /* 2 Seconds. */
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u32 cur_time = util::GetMicroSeconds();
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const u32 end_time = cur_time + TsecTimeout;
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while (cur_time <= end_time) {
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if (reg::HasValue(TSEC + TSEC_FALCON_CPUCTL, TSEC_REG_BITS_ENUM(FALCON_CPUCTL_HALTED, TRUE))) {
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return;
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}
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cur_time = util::GetMicroSeconds();
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}
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AMS_ABORT("tsec timeout");
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}
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void DoDma256(TsecMemory memory, u32 dst_offset, u32 src_offset) {
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reg::Write(TSEC + TSEC_FALCON_DMATRFMOFFS, TSEC_REG_BITS_VALUE(FALCON_DMATRFMOFFS_OFFSET, dst_offset));
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reg::Write(TSEC + TSEC_FALCON_DMATRFFBOFFS, src_offset);
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if (memory == TsecMemory_Imem) {
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reg::Write(TSEC + TSEC_FALCON_DMATRFCMD, TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_TO, IMEM),
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TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_SIZE, 4B));
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} else {
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reg::Write(TSEC + TSEC_FALCON_DMATRFCMD, TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_TO, DMEM),
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TSEC_REG_BITS_ENUM(FALCON_DMATRFCMD_SIZE, 256B));
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}
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WaitForDmaIdle();
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}
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}
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bool RunTsecFirmware(const void *fw, size_t fw_size) {
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/* TODO */
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AMS_UNUSED(fw, fw_size);
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return RunFirmwareImpl(fw, fw_size);
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/* Enable relevant clocks. */
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clkrst::EnableHost1xClock();
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clkrst::EnableTsecClock();
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clkrst::EnableSorSafeClock();
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clkrst::EnableSor0Clock();
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clkrst::EnableSor1Clock();
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clkrst::EnableKfuseClock();
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/* Disable clocks once we're done. */
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ON_SCOPE_EXIT {
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clkrst::DisableHost1xClock();
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clkrst::DisableTsecClock();
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clkrst::DisableSorSafeClock();
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clkrst::DisableSor0Clock();
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clkrst::DisableSor1Clock();
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clkrst::DisableKfuseClock();
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};
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/* Wait for kfuse to be ready. */
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if (!WaitForKfuseReady()) {
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return false;
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}
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/* Configure falcon. */
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reg::Write(TSEC + TSEC_FALCON_DMACTL, 0);
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reg::Write(TSEC + TSEC_FALCON_IRQMSET, 0xFFF2);
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reg::Write(TSEC + TSEC_FALCON_IRQDEST, 0xFFF0);
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reg::Write(TSEC + TSEC_FALCON_ITFEN, 0x3);
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/* Wait for TSEC dma to be idle. */
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WaitForDmaIdle();
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/* Set the base address for transfers. */
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reg::Write(TSEC + TSEC_FALCON_DMATRFBASE, reinterpret_cast<uintptr_t>(fw) >> 8);
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/* Transfer all data to TSEC imem. */
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for (size_t i = 0; i < fw_size; i += 0x100) {
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DoDma256(TsecMemory_Imem, i, i);
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}
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/* Write the magic value to host1x syncpoint 160. */
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reg::Write(0x50003300, 0x34C2E1DA);
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/* Execute the firmware. */
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reg::Write(TSEC + TSEC_FALCON_MAILBOX0, 0);
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reg::Write(TSEC + TSEC_FALCON_MAILBOX1, 0);
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reg::Write(TSEC + TSEC_FALCON_BOOTVEC, 0);
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reg::Write(TSEC + TSEC_FALCON_CPUCTL, TSEC_REG_BITS_ENUM(FALCON_CPUCTL_STARTCPU, TRUE));
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/* Wait for TSEC dma to be idle. */
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WaitForDmaIdle();
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/* Wait for TSEC to complete. */
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WaitForTsecIdle();
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/* Clear magic value from host1x syncpoint 160. */
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reg::Write(0x50003300, 0);
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/* Return whether the tsec firmware succeeded. */
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return reg::Read(TSEC + TSEC_FALCON_MAILBOX1) == TsecResult_Success;
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}
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void Lock() {
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49
libraries/libexosphere/source/tsec/tsec_registers.hpp
Normal file
49
libraries/libexosphere/source/tsec/tsec_registers.hpp
Normal file
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@ -0,0 +1,49 @@
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
|
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* under the terms and conditions of the GNU General Public LicenTSEC,
|
||||
* version 2, as published by the Free Software Foundation.
|
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*
|
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* This program is distributed in the hope it will be uTSECful, but WITHOUT
|
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOTSEC. TSECe the GNU General Public LicenTSEC for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public LicenTSEC
|
||||
* along with this program. If not, TSECe <http://www.gnu.org/licenTSECs/>.
|
||||
*/
|
||||
#include <exosphere.hpp>
|
||||
|
||||
#define TSEC_FALCON_IRQMSET (0x1010)
|
||||
#define TSEC_FALCON_IRQDEST (0x101C)
|
||||
#define TSEC_FALCON_MAILBOX0 (0x1040)
|
||||
#define TSEC_FALCON_MAILBOX1 (0x1044)
|
||||
#define TSEC_FALCON_ITFEN (0x1048)
|
||||
#define TSEC_FALCON_CPUCTL (0x1100)
|
||||
#define TSEC_FALCON_BOOTVEC (0x1104)
|
||||
#define TSEC_FALCON_DMACTL (0x110C)
|
||||
#define TSEC_FALCON_DMATRFBASE (0x1110)
|
||||
#define TSEC_FALCON_DMATRFMOFFS (0x1114)
|
||||
#define TSEC_FALCON_DMATRFCMD (0x1118)
|
||||
#define TSEC_FALCON_DMATRFFBOFFS (0x111C)
|
||||
|
||||
#define TSEC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (TSEC, NAME)
|
||||
#define TSEC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (TSEC, NAME, VALUE)
|
||||
#define TSEC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (TSEC, NAME, ENUM)
|
||||
#define TSEC_REG_BITS_ENUM_TSECL(NAME, __COND__, TRUE_ENUM, FALTSEC_ENUM) REG_NAMED_BITS_ENUM_TSECL(TSEC, NAME, __COND__, TRUE_ENUM, FALTSEC_ENUM)
|
||||
|
||||
#define DEFINE_TSEC_REG(NAME, __OFFTSECT__, __WIDTH__) REG_DEFINE_NAMED_REG (TSEC, NAME, __OFFTSECT__, __WIDTH__)
|
||||
#define DEFINE_TSEC_REG_BIT_ENUM(NAME, __OFFTSECT__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (TSEC, NAME, __OFFTSECT__, ZERO, ONE)
|
||||
#define DEFINE_TSEC_REG_TWO_BIT_ENUM(NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (TSEC, NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_TSEC_REG_THREE_BIT_ENUM(NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, TSECVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(TSEC, NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, TSECVEN)
|
||||
#define DEFINE_TSEC_REG_FOUR_BIT_ENUM(NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, TSECVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (TSEC, NAME, __OFFTSECT__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, TSECVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_TSEC_REG_BIT_ENUM(FALCON_CPUCTL_STARTCPU, 1, FALSE, TRUE);
|
||||
DEFINE_TSEC_REG_BIT_ENUM(FALCON_CPUCTL_HALTED, 4, FALSE, TRUE);
|
||||
|
||||
DEFINE_TSEC_REG(FALCON_DMATRFMOFFS_OFFSET, 0, 16);
|
||||
|
||||
DEFINE_TSEC_REG_BIT_ENUM(FALCON_DMATRFCMD_BUSY, 1, BUSY, IDLE);
|
||||
DEFINE_TSEC_REG_BIT_ENUM(FALCON_DMATRFCMD_TO, 4, DMEM, IMEM);
|
||||
DEFINE_TSEC_REG_THREE_BIT_ENUM(FALCON_DMATRFCMD_SIZE, 8, 4B, 8B, 16B, 32B, 64B, 128B, 256B, RSVD7);
|
Loading…
Reference in a new issue