From 4958d01153f2f507d8cdf5cdc71ffc423b5ce212 Mon Sep 17 00:00:00 2001 From: hexkyz Date: Sat, 14 Nov 2020 18:45:46 +0000 Subject: [PATCH] fusee/sept: support mariko fuses --- fusee/fusee-mtc/src/fuse.c | 73 +++++-- fusee/fusee-mtc/src/fuse.h | 352 ++++++++++++++++++++++++++----- fusee/fusee-primary/src/fuse.c | 73 +++++-- fusee/fusee-primary/src/fuse.h | 352 ++++++++++++++++++++++++++----- fusee/fusee-primary/src/hwinit.c | 2 +- fusee/fusee-secondary/src/fuse.c | 73 +++++-- fusee/fusee-secondary/src/fuse.h | 352 ++++++++++++++++++++++++++----- sept/sept-primary/src/fuse.c | 73 +++++-- sept/sept-primary/src/fuse.h | 352 ++++++++++++++++++++++++++----- sept/sept-secondary/src/fuse.c | 73 +++++-- sept/sept-secondary/src/fuse.h | 352 ++++++++++++++++++++++++++----- sept/sept-secondary/src/hwinit.c | 2 +- 12 files changed, 1782 insertions(+), 347 deletions(-) diff --git a/fusee/fusee-mtc/src/fuse.c b/fusee/fusee-mtc/src/fuse.c index 1b49f30d5..e53cda3b3 100644 --- a/fusee/fusee-mtc/src/fuse.c +++ b/fusee/fusee-mtc/src/fuse.c @@ -68,8 +68,9 @@ static void fuse_wait_idle(void) { uint32_t ctrl_val = 0; /* Wait for STATE_IDLE */ - while ((ctrl_val & (0xF0000)) != 0x40000) + while ((ctrl_val & (0xF0000)) != 0x40000) { ctrl_val = fuse->FUSE_FUSECTRL; + } } /* Read a fuse from the hardware array. */ @@ -134,34 +135,54 @@ void fuse_hw_sense(void) { /* Read the SKU info register. */ uint32_t fuse_get_sku_info(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); return fuse_chip->FUSE_SKU_INFO; } /* Read the bootrom patch version. */ uint32_t fuse_get_bootrom_patch_version(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB; } /* Read a spare bit register. */ -uint32_t fuse_get_spare_bit(uint32_t idx) { - if (idx < 32) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); - return fuse_chip->FUSE_SPARE_BIT[idx]; - } else { - return 0; +uint32_t fuse_get_spare_bit(uint32_t index) { + uint32_t soc_type = fuse_get_soc_type(); + if (soc_type == 0) { + if (index < 32) { + volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs(); + return fuse_chip->FUSE_SPARE_BIT[index]; + } + } else if (soc_type == 1) { + if (index < 30) { + volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); + return fuse_chip->FUSE_SPARE_BIT[index]; + } } + return 0; } /* Read a reserved ODM register. */ -uint32_t fuse_get_reserved_odm(uint32_t idx) { - if (idx < 8) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); - return fuse_chip->FUSE_RESERVED_ODM[idx]; - } else { - return 0; +uint32_t fuse_get_reserved_odm(uint32_t index) { + uint32_t soc_type = fuse_get_soc_type(); + if (index < 8) { + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); + return fuse_chip->FUSE_RESERVED_ODM0[index]; + } else if (soc_type == 1) { + volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); + if (index < 22) { + return fuse_chip->FUSE_RESERVED_ODM8[index - 8]; + } else if (index < 25) { + return fuse_chip->FUSE_RESERVED_ODM22[index - 22]; + } else if (index < 26) { + return fuse_chip->FUSE_RESERVED_ODM25; + } else if (index < 29) { + return fuse_chip->FUSE_RESERVED_ODM26[index - 26]; + } else if (index < 30) { + return fuse_chip->FUSE_RESERVED_ODM29; + } } + return 0; } /* Get the DramId. */ @@ -171,7 +192,7 @@ uint32_t fuse_get_dram_id(void) { /* Derive the DeviceId. */ uint64_t fuse_get_device_id(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint64_t device_id = 0; uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF; @@ -201,7 +222,7 @@ uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) { uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1)); if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1); switch (hardware_type) { @@ -262,7 +283,7 @@ uint32_t fuse_get_hardware_state(void) { /* Derive the 16-byte HardwareInfo and copy to output buffer. */ void fuse_get_hardware_info(void *dst) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint32_t hw_info[0x4]; uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F; @@ -283,9 +304,14 @@ void fuse_get_hardware_info(void *dst) { memcpy(dst, hw_info, 0x10); } +/* Check if have a new ODM fuse format. */ +bool fuse_is_new_format(void) { + return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)); +} + /* Get the DeviceUniqueKeyGeneration. */ uint32_t fuse_get_device_unique_key_generation(void) { - if ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)) { + if (fuse_is_new_format()) { return (fuse_get_reserved_odm(2) & 0x1F); } else { return 0; @@ -307,3 +333,12 @@ uint32_t fuse_get_soc_type(void) { return 0xF; /* SocType_Undefined */ } } + +/* Get the Regulator type. */ +uint32_t fuse_get_regulator(void) { + if (fuse_get_soc_type() == 1) { + return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */ + } else { + return 0; /* Regulator_Erista_Max77621 */ + } +} diff --git a/fusee/fusee-mtc/src/fuse.h b/fusee/fusee-mtc/src/fuse.h index 8bfec2b25..eb590553c 100644 --- a/fusee/fusee-mtc/src/fuse.h +++ b/fusee/fusee-mtc/src/fuse.h @@ -18,7 +18,7 @@ #define FUSEE_FUSE_H #define FUSE_BASE 0x7000F800 -#define FUSE_CHIP_BASE (FUSE_BASE + 0x100) +#define FUSE_CHIP_BASE (FUSE_BASE + 0x98) #define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n) #define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n) @@ -47,10 +47,11 @@ typedef struct { uint32_t FUSE_PRIVATE_KEY2_NONZERO; uint32_t FUSE_PRIVATE_KEY3_NONZERO; uint32_t FUSE_PRIVATE_KEY4_NONZERO; - uint32_t _0x90[0x1C]; + uint32_t _0x94; } tegra_fuse_t; typedef struct { + uint32_t _0x98[0x1A]; uint32_t FUSE_PRODUCTION_MODE; uint32_t FUSE_JTAG_SECUREID_VALID; uint32_t FUSE_ODM_LOCK; @@ -58,9 +59,7 @@ typedef struct { uint32_t FUSE_SKU_INFO; uint32_t FUSE_CPU_SPEEDO_0_CALIB; uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t FUSE_DAC_CRT_CALIB; - uint32_t FUSE_DAC_HDTV_CALIB; - uint32_t FUSE_DAC_SDTV_CALIB; + uint32_t _0x11C[0x3]; uint32_t FUSE_OPT_FT_REV; uint32_t FUSE_CPU_SPEEDO_1_CALIB; uint32_t FUSE_CPU_SPEEDO_2_CALIB; @@ -68,7 +67,7 @@ typedef struct { uint32_t FUSE_SOC_SPEEDO_1_CALIB; uint32_t FUSE_SOC_SPEEDO_2_CALIB; uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t FUSE_RESERVED_PRODUCTION_WP; + uint32_t _0x144; uint32_t FUSE_FA; uint32_t FUSE_RESERVED_PRODUCTION; uint32_t FUSE_HDMI_LANE0_CALIB; @@ -79,7 +78,7 @@ typedef struct { uint32_t FUSE_PUBLIC_KEY[0x8]; uint32_t FUSE_TSENSOR1_CALIB; uint32_t FUSE_TSENSOR2_CALIB; - uint32_t FUSE_VSENSOR_CALIB; + uint32_t _0x18C; uint32_t FUSE_OPT_CP_REV; uint32_t FUSE_OPT_PFG; uint32_t FUSE_TSENSOR0_CALIB; @@ -90,9 +89,9 @@ typedef struct { uint32_t FUSE_BOOT_DEVICE_INFO; uint32_t FUSE_RESERVED_SW; uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM[0x8]; + uint32_t FUSE_RESERVED_ODM0[0x8]; uint32_t FUSE_OBS_DIS; - uint32_t FUSE_NOR_INFO; + uint32_t _0x1EC; uint32_t FUSE_USB_CALIB; uint32_t FUSE_SKU_DIRECT_CONFIG; uint32_t FUSE_KFUSE_PRIVKEY_CTRL; @@ -106,14 +105,12 @@ typedef struct { uint32_t FUSE_OPT_Y_COORDINATE; uint32_t FUSE_OPT_SEC_DEBUG_EN; uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t FUSE_SATA_CALIB; + uint32_t _0x224; uint32_t FUSE_GPU_IDDQ_CALIB; uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_SKU_BOND_OUT_L; - uint32_t FUSE_SKU_BOND_OUT_H; - uint32_t FUSE_SKU_BOND_OUT_U; - uint32_t FUSE_SKU_BOND_OUT_V; - uint32_t FUSE_SKU_BOND_OUT_W; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t _0x238[0x3]; uint32_t FUSE_OPT_SAMPLE_TYPE; uint32_t FUSE_OPT_SUBREVISION; uint32_t FUSE_OPT_SW_RESERVED_0; @@ -123,35 +120,26 @@ typedef struct { uint32_t FUSE_TSENSOR6_CALIB; uint32_t FUSE_TSENSOR7_CALIB; uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t FUSE_PKC_DISABLE; - uint32_t _0x16C; - uint32_t _0x170; - uint32_t _0x174; - uint32_t _0x178; + uint32_t _0x268[0x5]; uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; uint32_t FUSE_TSENSOR_COMMON; uint32_t FUSE_OPT_CP_BIN; uint32_t FUSE_OPT_GPU_DISABLE; uint32_t FUSE_OPT_FT_BIN; uint32_t FUSE_OPT_DONE_MAP; - uint32_t _0x194; + uint32_t _0x294; uint32_t FUSE_APB2JTAG_DISABLE; uint32_t FUSE_ODM_INFO; - uint32_t _0x1A0; - uint32_t _0x1A4; + uint32_t _0x2A0[0x2]; uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x1AC; - uint32_t _0x1B0; - uint32_t _0x1B4; - uint32_t _0x1B8; - uint32_t _0x1BC; + uint32_t _0x2AC[0x5]; uint32_t FUSE_WOA_SKU_FLAG; uint32_t FUSE_ECO_RESERVE_1; uint32_t FUSE_GCPLEX_CONFIG_FUSE; uint32_t FUSE_PRODUCTION_MONTH; uint32_t FUSE_RAM_REPAIR_INDICATOR; uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x1D8; + uint32_t _0x2D8; uint32_t FUSE_VMIN_CALIBRATION; uint32_t FUSE_AGING_SENSOR_CALIBRATION; uint32_t FUSE_DEBUG_AUTHENTICATION; @@ -160,8 +148,7 @@ typedef struct { uint32_t FUSE_OPT_GPU_DISABLE_CP1; uint32_t FUSE_SPARE_ENDIS; uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x1FC; - uint32_t _0x200; + uint32_t _0x2FC[0x2]; uint32_t FUSE_RESERVED_CALIB0; uint32_t FUSE_RESERVED_CALIB1; uint32_t FUSE_OPT_GPU_TPC0_DISABLE; @@ -170,11 +157,7 @@ typedef struct { uint32_t FUSE_OPT_CPU_DISABLE_CP1; uint32_t FUSE_TSENSOR10_CALIB; uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t FUSE_OPT_RAM_SVOP_DP; - uint32_t FUSE_OPT_RAM_SVOP_PDP; - uint32_t FUSE_OPT_RAM_SVOP_REG; - uint32_t FUSE_OPT_RAM_SVOP_SP; - uint32_t FUSE_OPT_RAM_SVOP_SMPDP; + uint32_t _0x324[0x5]; uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; uint32_t FUSE_OPT_GPU_TPC1_DISABLE; uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; @@ -183,27 +166,294 @@ typedef struct { uint32_t FUSE_OPT_GPU_DISABLE_CP2; uint32_t FUSE_USB_CALIB_EXT; uint32_t FUSE_RESERVED_FIELD; - uint32_t FUSE_OPT_ECC_EN; - uint32_t _0x25C; - uint32_t _0x260; - uint32_t _0x264; - uint32_t _0x268; - uint32_t _0x26C; - uint32_t _0x270; - uint32_t _0x274; - uint32_t _0x278; + uint32_t _0x358[0x9]; uint32_t FUSE_SPARE_REALIGNMENT_REG; uint32_t FUSE_SPARE_BIT[0x20]; -} tegra_fuse_chip_t; +} tegra_fuse_chip_common_t; + +typedef struct { + uint32_t _0x98[0x1A]; + uint32_t FUSE_PRODUCTION_MODE; + uint32_t FUSE_JTAG_SECUREID_VALID; + uint32_t FUSE_ODM_LOCK; + uint32_t FUSE_OPT_OPENGL_EN; + uint32_t FUSE_SKU_INFO; + uint32_t FUSE_CPU_SPEEDO_0_CALIB; + uint32_t FUSE_CPU_IDDQ_CALIB; + uint32_t _0x11C[0x3]; + uint32_t FUSE_OPT_FT_REV; + uint32_t FUSE_CPU_SPEEDO_1_CALIB; + uint32_t FUSE_CPU_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_SPEEDO_0_CALIB; + uint32_t FUSE_SOC_SPEEDO_1_CALIB; + uint32_t FUSE_SOC_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_IDDQ_CALIB; + uint32_t _0x144; + uint32_t FUSE_FA; + uint32_t FUSE_RESERVED_PRODUCTION; + uint32_t FUSE_HDMI_LANE0_CALIB; + uint32_t FUSE_HDMI_LANE1_CALIB; + uint32_t FUSE_HDMI_LANE2_CALIB; + uint32_t FUSE_HDMI_LANE3_CALIB; + uint32_t FUSE_ENCRYPTION_RATE; + uint32_t FUSE_PUBLIC_KEY[0x8]; + uint32_t FUSE_TSENSOR1_CALIB; + uint32_t FUSE_TSENSOR2_CALIB; + uint32_t _0x18C; + uint32_t FUSE_OPT_CP_REV; + uint32_t FUSE_OPT_PFG; + uint32_t FUSE_TSENSOR0_CALIB; + uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; + uint32_t FUSE_SECURITY_MODE; + uint32_t FUSE_PRIVATE_KEY[0x5]; + uint32_t FUSE_ARM_JTAG_DIS; + uint32_t FUSE_BOOT_DEVICE_INFO; + uint32_t FUSE_RESERVED_SW; + uint32_t FUSE_OPT_VP9_DISABLE; + uint32_t FUSE_RESERVED_ODM0[0x8]; + uint32_t FUSE_OBS_DIS; + uint32_t _0x1EC; + uint32_t FUSE_USB_CALIB; + uint32_t FUSE_SKU_DIRECT_CONFIG; + uint32_t FUSE_KFUSE_PRIVKEY_CTRL; + uint32_t FUSE_PACKAGE_INFO; + uint32_t FUSE_OPT_VENDOR_CODE; + uint32_t FUSE_OPT_FAB_CODE; + uint32_t FUSE_OPT_LOT_CODE_0; + uint32_t FUSE_OPT_LOT_CODE_1; + uint32_t FUSE_OPT_WAFER_ID; + uint32_t FUSE_OPT_X_COORDINATE; + uint32_t FUSE_OPT_Y_COORDINATE; + uint32_t FUSE_OPT_SEC_DEBUG_EN; + uint32_t FUSE_OPT_OPS_RESERVED; + uint32_t FUSE_SATA_CALIB; /* Erista only. */ + uint32_t FUSE_GPU_IDDQ_CALIB; + uint32_t FUSE_TSENSOR3_CALIB; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t _0x238[0x3]; + uint32_t FUSE_OPT_SAMPLE_TYPE; + uint32_t FUSE_OPT_SUBREVISION; + uint32_t FUSE_OPT_SW_RESERVED_0; + uint32_t FUSE_OPT_SW_RESERVED_1; + uint32_t FUSE_TSENSOR4_CALIB; + uint32_t FUSE_TSENSOR5_CALIB; + uint32_t FUSE_TSENSOR6_CALIB; + uint32_t FUSE_TSENSOR7_CALIB; + uint32_t FUSE_OPT_PRIV_SEC_EN; + uint32_t FUSE_PKC_DISABLE; /* Erista only. */ + uint32_t _0x26C[0x4]; + uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; + uint32_t FUSE_TSENSOR_COMMON; + uint32_t FUSE_OPT_CP_BIN; + uint32_t FUSE_OPT_GPU_DISABLE; + uint32_t FUSE_OPT_FT_BIN; + uint32_t FUSE_OPT_DONE_MAP; + uint32_t _0x294; + uint32_t FUSE_APB2JTAG_DISABLE; + uint32_t FUSE_ODM_INFO; + uint32_t _0x2A0[0x2]; + uint32_t FUSE_ARM_CRYPT_DE_FEATURE; + uint32_t _0x2AC[0x5]; + uint32_t FUSE_WOA_SKU_FLAG; + uint32_t FUSE_ECO_RESERVE_1; + uint32_t FUSE_GCPLEX_CONFIG_FUSE; + uint32_t FUSE_PRODUCTION_MONTH; + uint32_t FUSE_RAM_REPAIR_INDICATOR; + uint32_t FUSE_TSENSOR9_CALIB; + uint32_t _0x2D8; + uint32_t FUSE_VMIN_CALIBRATION; + uint32_t FUSE_AGING_SENSOR_CALIBRATION; + uint32_t FUSE_DEBUG_AUTHENTICATION; + uint32_t FUSE_SECURE_PROVISION_INDEX; + uint32_t FUSE_SECURE_PROVISION_INFO; + uint32_t FUSE_OPT_GPU_DISABLE_CP1; + uint32_t FUSE_SPARE_ENDIS; + uint32_t FUSE_ECO_RESERVE_0; + uint32_t _0x2FC[0x2]; + uint32_t FUSE_RESERVED_CALIB0; + uint32_t FUSE_RESERVED_CALIB1; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; + uint32_t FUSE_OPT_CPU_DISABLE; + uint32_t FUSE_OPT_CPU_DISABLE_CP1; + uint32_t FUSE_TSENSOR10_CALIB; + uint32_t FUSE_TSENSOR10_CALIB_AUX; + uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */ + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; + uint32_t FUSE_OPT_CPU_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_DISABLE_CP2; + uint32_t FUSE_USB_CALIB_EXT; + uint32_t FUSE_RESERVED_FIELD; + uint32_t _0x358[0x9]; + uint32_t FUSE_SPARE_REALIGNMENT_REG; + uint32_t FUSE_SPARE_BIT[0x20]; +} tegra_fuse_chip_erista_t; + +typedef struct { + uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */ + uint32_t FUSE_KEK[0x4]; /* Mariko only. */ + uint32_t FUSE_BEK[0x4]; /* Mariko only. */ + uint32_t _0xF0; /* Mariko only. */ + uint32_t _0xF4; /* Mariko only. */ + uint32_t _0xF8; /* Mariko only. */ + uint32_t _0xFC; /* Mariko only. */ + uint32_t FUSE_PRODUCTION_MODE; + uint32_t FUSE_JTAG_SECUREID_VALID; + uint32_t FUSE_ODM_LOCK; + uint32_t FUSE_OPT_OPENGL_EN; + uint32_t FUSE_SKU_INFO; + uint32_t FUSE_CPU_SPEEDO_0_CALIB; + uint32_t FUSE_CPU_IDDQ_CALIB; + uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */ + uint32_t FUSE_OPT_FT_REV; + uint32_t FUSE_CPU_SPEEDO_1_CALIB; + uint32_t FUSE_CPU_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_SPEEDO_0_CALIB; + uint32_t FUSE_SOC_SPEEDO_1_CALIB; + uint32_t FUSE_SOC_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_IDDQ_CALIB; + uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */ + uint32_t FUSE_FA; + uint32_t FUSE_RESERVED_PRODUCTION; + uint32_t FUSE_HDMI_LANE0_CALIB; + uint32_t FUSE_HDMI_LANE1_CALIB; + uint32_t FUSE_HDMI_LANE2_CALIB; + uint32_t FUSE_HDMI_LANE3_CALIB; + uint32_t FUSE_ENCRYPTION_RATE; + uint32_t FUSE_PUBLIC_KEY[0x8]; + uint32_t FUSE_TSENSOR1_CALIB; + uint32_t FUSE_TSENSOR2_CALIB; + uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */ + uint32_t FUSE_OPT_CP_REV; + uint32_t FUSE_OPT_PFG; + uint32_t FUSE_TSENSOR0_CALIB; + uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; + uint32_t FUSE_SECURITY_MODE; + uint32_t FUSE_PRIVATE_KEY[0x5]; + uint32_t FUSE_ARM_JTAG_DIS; + uint32_t FUSE_BOOT_DEVICE_INFO; + uint32_t FUSE_RESERVED_SW; + uint32_t FUSE_OPT_VP9_DISABLE; + uint32_t FUSE_RESERVED_ODM0[0x8]; + uint32_t FUSE_OBS_DIS; + uint32_t _0x1EC; /* Mariko only. */ + uint32_t FUSE_USB_CALIB; + uint32_t FUSE_SKU_DIRECT_CONFIG; + uint32_t FUSE_KFUSE_PRIVKEY_CTRL; + uint32_t FUSE_PACKAGE_INFO; + uint32_t FUSE_OPT_VENDOR_CODE; + uint32_t FUSE_OPT_FAB_CODE; + uint32_t FUSE_OPT_LOT_CODE_0; + uint32_t FUSE_OPT_LOT_CODE_1; + uint32_t FUSE_OPT_WAFER_ID; + uint32_t FUSE_OPT_X_COORDINATE; + uint32_t FUSE_OPT_Y_COORDINATE; + uint32_t FUSE_OPT_SEC_DEBUG_EN; + uint32_t FUSE_OPT_OPS_RESERVED; + uint32_t _0x224; /* Mariko only. */ + uint32_t FUSE_GPU_IDDQ_CALIB; + uint32_t FUSE_TSENSOR3_CALIB; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */ + uint32_t FUSE_OPT_SAMPLE_TYPE; + uint32_t FUSE_OPT_SUBREVISION; + uint32_t FUSE_OPT_SW_RESERVED_0; + uint32_t FUSE_OPT_SW_RESERVED_1; + uint32_t FUSE_TSENSOR4_CALIB; + uint32_t FUSE_TSENSOR5_CALIB; + uint32_t FUSE_TSENSOR6_CALIB; + uint32_t FUSE_TSENSOR7_CALIB; + uint32_t FUSE_OPT_PRIV_SEC_EN; + uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */ + uint32_t _0x26C; /* Mariko only. */ + uint32_t _0x270; /* Mariko only. */ + uint32_t _0x274; /* Mariko only. */ + uint32_t _0x278; /* Mariko only. */ + uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; + uint32_t FUSE_TSENSOR_COMMON; + uint32_t FUSE_OPT_CP_BIN; + uint32_t FUSE_OPT_GPU_DISABLE; + uint32_t FUSE_OPT_FT_BIN; + uint32_t FUSE_OPT_DONE_MAP; + uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */ + uint32_t FUSE_APB2JTAG_DISABLE; + uint32_t FUSE_ODM_INFO; + uint32_t _0x2A0[0x2]; + uint32_t FUSE_ARM_CRYPT_DE_FEATURE; + uint32_t _0x2AC; + uint32_t _0x2B0; /* Mariko only. */ + uint32_t _0x2B4; /* Mariko only. */ + uint32_t _0x2B8; /* Mariko only. */ + uint32_t _0x2BC; /* Mariko only. */ + uint32_t FUSE_WOA_SKU_FLAG; + uint32_t FUSE_ECO_RESERVE_1; + uint32_t FUSE_GCPLEX_CONFIG_FUSE; + uint32_t FUSE_PRODUCTION_MONTH; + uint32_t FUSE_RAM_REPAIR_INDICATOR; + uint32_t FUSE_TSENSOR9_CALIB; + uint32_t _0x2D8; + uint32_t FUSE_VMIN_CALIBRATION; + uint32_t FUSE_AGING_SENSOR_CALIBRATION; + uint32_t FUSE_DEBUG_AUTHENTICATION; + uint32_t FUSE_SECURE_PROVISION_INDEX; + uint32_t FUSE_SECURE_PROVISION_INFO; + uint32_t FUSE_OPT_GPU_DISABLE_CP1; + uint32_t FUSE_SPARE_ENDIS; + uint32_t FUSE_ECO_RESERVE_0; + uint32_t _0x2FC[0x2]; + uint32_t FUSE_RESERVED_CALIB0; + uint32_t FUSE_RESERVED_CALIB1; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; + uint32_t FUSE_OPT_CPU_DISABLE; + uint32_t FUSE_OPT_CPU_DISABLE_CP1; + uint32_t FUSE_TSENSOR10_CALIB; + uint32_t FUSE_TSENSOR10_CALIB_AUX; + uint32_t _0x324; /* Mariko only. */ + uint32_t _0x328; /* Mariko only. */ + uint32_t _0x32C; /* Mariko only. */ + uint32_t _0x330; /* Mariko only. */ + uint32_t _0x334; /* Mariko only. */ + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; + uint32_t FUSE_OPT_CPU_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_DISABLE_CP2; + uint32_t FUSE_USB_CALIB_EXT; + uint32_t FUSE_RESERVED_FIELD; + uint32_t _0x358[0x9]; + uint32_t FUSE_SPARE_REALIGNMENT_REG; + uint32_t FUSE_SPARE_BIT[0x1E]; +} tegra_fuse_chip_mariko_t; static inline volatile tegra_fuse_t *fuse_get_regs(void) { return (volatile tegra_fuse_t *)FUSE_BASE; } -static inline volatile tegra_fuse_chip_t *fuse_chip_get_regs(void) +static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void) { - return (volatile tegra_fuse_chip_t *)FUSE_CHIP_BASE; + return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE; +} + +static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void) +{ + return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE; +} + +static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void) +{ + return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE; } void fuse_init(void); @@ -213,8 +463,8 @@ void fuse_enable_power(void); void fuse_disable_power(void); uint32_t fuse_get_sku_info(void); -uint32_t fuse_get_spare_bit(uint32_t idx); -uint32_t fuse_get_reserved_odm(uint32_t idx); +uint32_t fuse_get_spare_bit(uint32_t index); +uint32_t fuse_get_reserved_odm(uint32_t index); uint32_t fuse_get_bootrom_patch_version(void); uint64_t fuse_get_device_id(void); uint32_t fuse_get_dram_id(void); @@ -222,8 +472,10 @@ uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware); uint32_t fuse_get_hardware_type(void); uint32_t fuse_get_retail_type(void); void fuse_get_hardware_info(void *dst); +bool fuse_is_new_format(void); uint32_t fuse_get_device_unique_key_generation(void); uint32_t fuse_get_soc_type(void); +uint32_t fuse_get_regulator(void); uint32_t fuse_hw_read(uint32_t addr); void fuse_hw_write(uint32_t value, uint32_t addr); diff --git a/fusee/fusee-primary/src/fuse.c b/fusee/fusee-primary/src/fuse.c index 1b49f30d5..e53cda3b3 100644 --- a/fusee/fusee-primary/src/fuse.c +++ b/fusee/fusee-primary/src/fuse.c @@ -68,8 +68,9 @@ static void fuse_wait_idle(void) { uint32_t ctrl_val = 0; /* Wait for STATE_IDLE */ - while ((ctrl_val & (0xF0000)) != 0x40000) + while ((ctrl_val & (0xF0000)) != 0x40000) { ctrl_val = fuse->FUSE_FUSECTRL; + } } /* Read a fuse from the hardware array. */ @@ -134,34 +135,54 @@ void fuse_hw_sense(void) { /* Read the SKU info register. */ uint32_t fuse_get_sku_info(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); return fuse_chip->FUSE_SKU_INFO; } /* Read the bootrom patch version. */ uint32_t fuse_get_bootrom_patch_version(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB; } /* Read a spare bit register. */ -uint32_t fuse_get_spare_bit(uint32_t idx) { - if (idx < 32) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); - return fuse_chip->FUSE_SPARE_BIT[idx]; - } else { - return 0; +uint32_t fuse_get_spare_bit(uint32_t index) { + uint32_t soc_type = fuse_get_soc_type(); + if (soc_type == 0) { + if (index < 32) { + volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs(); + return fuse_chip->FUSE_SPARE_BIT[index]; + } + } else if (soc_type == 1) { + if (index < 30) { + volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); + return fuse_chip->FUSE_SPARE_BIT[index]; + } } + return 0; } /* Read a reserved ODM register. */ -uint32_t fuse_get_reserved_odm(uint32_t idx) { - if (idx < 8) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); - return fuse_chip->FUSE_RESERVED_ODM[idx]; - } else { - return 0; +uint32_t fuse_get_reserved_odm(uint32_t index) { + uint32_t soc_type = fuse_get_soc_type(); + if (index < 8) { + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); + return fuse_chip->FUSE_RESERVED_ODM0[index]; + } else if (soc_type == 1) { + volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); + if (index < 22) { + return fuse_chip->FUSE_RESERVED_ODM8[index - 8]; + } else if (index < 25) { + return fuse_chip->FUSE_RESERVED_ODM22[index - 22]; + } else if (index < 26) { + return fuse_chip->FUSE_RESERVED_ODM25; + } else if (index < 29) { + return fuse_chip->FUSE_RESERVED_ODM26[index - 26]; + } else if (index < 30) { + return fuse_chip->FUSE_RESERVED_ODM29; + } } + return 0; } /* Get the DramId. */ @@ -171,7 +192,7 @@ uint32_t fuse_get_dram_id(void) { /* Derive the DeviceId. */ uint64_t fuse_get_device_id(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint64_t device_id = 0; uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF; @@ -201,7 +222,7 @@ uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) { uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1)); if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1); switch (hardware_type) { @@ -262,7 +283,7 @@ uint32_t fuse_get_hardware_state(void) { /* Derive the 16-byte HardwareInfo and copy to output buffer. */ void fuse_get_hardware_info(void *dst) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint32_t hw_info[0x4]; uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F; @@ -283,9 +304,14 @@ void fuse_get_hardware_info(void *dst) { memcpy(dst, hw_info, 0x10); } +/* Check if have a new ODM fuse format. */ +bool fuse_is_new_format(void) { + return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)); +} + /* Get the DeviceUniqueKeyGeneration. */ uint32_t fuse_get_device_unique_key_generation(void) { - if ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)) { + if (fuse_is_new_format()) { return (fuse_get_reserved_odm(2) & 0x1F); } else { return 0; @@ -307,3 +333,12 @@ uint32_t fuse_get_soc_type(void) { return 0xF; /* SocType_Undefined */ } } + +/* Get the Regulator type. */ +uint32_t fuse_get_regulator(void) { + if (fuse_get_soc_type() == 1) { + return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */ + } else { + return 0; /* Regulator_Erista_Max77621 */ + } +} diff --git a/fusee/fusee-primary/src/fuse.h b/fusee/fusee-primary/src/fuse.h index 8bfec2b25..eb590553c 100644 --- a/fusee/fusee-primary/src/fuse.h +++ b/fusee/fusee-primary/src/fuse.h @@ -18,7 +18,7 @@ #define FUSEE_FUSE_H #define FUSE_BASE 0x7000F800 -#define FUSE_CHIP_BASE (FUSE_BASE + 0x100) +#define FUSE_CHIP_BASE (FUSE_BASE + 0x98) #define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n) #define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n) @@ -47,10 +47,11 @@ typedef struct { uint32_t FUSE_PRIVATE_KEY2_NONZERO; uint32_t FUSE_PRIVATE_KEY3_NONZERO; uint32_t FUSE_PRIVATE_KEY4_NONZERO; - uint32_t _0x90[0x1C]; + uint32_t _0x94; } tegra_fuse_t; typedef struct { + uint32_t _0x98[0x1A]; uint32_t FUSE_PRODUCTION_MODE; uint32_t FUSE_JTAG_SECUREID_VALID; uint32_t FUSE_ODM_LOCK; @@ -58,9 +59,7 @@ typedef struct { uint32_t FUSE_SKU_INFO; uint32_t FUSE_CPU_SPEEDO_0_CALIB; uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t FUSE_DAC_CRT_CALIB; - uint32_t FUSE_DAC_HDTV_CALIB; - uint32_t FUSE_DAC_SDTV_CALIB; + uint32_t _0x11C[0x3]; uint32_t FUSE_OPT_FT_REV; uint32_t FUSE_CPU_SPEEDO_1_CALIB; uint32_t FUSE_CPU_SPEEDO_2_CALIB; @@ -68,7 +67,7 @@ typedef struct { uint32_t FUSE_SOC_SPEEDO_1_CALIB; uint32_t FUSE_SOC_SPEEDO_2_CALIB; uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t FUSE_RESERVED_PRODUCTION_WP; + uint32_t _0x144; uint32_t FUSE_FA; uint32_t FUSE_RESERVED_PRODUCTION; uint32_t FUSE_HDMI_LANE0_CALIB; @@ -79,7 +78,7 @@ typedef struct { uint32_t FUSE_PUBLIC_KEY[0x8]; uint32_t FUSE_TSENSOR1_CALIB; uint32_t FUSE_TSENSOR2_CALIB; - uint32_t FUSE_VSENSOR_CALIB; + uint32_t _0x18C; uint32_t FUSE_OPT_CP_REV; uint32_t FUSE_OPT_PFG; uint32_t FUSE_TSENSOR0_CALIB; @@ -90,9 +89,9 @@ typedef struct { uint32_t FUSE_BOOT_DEVICE_INFO; uint32_t FUSE_RESERVED_SW; uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM[0x8]; + uint32_t FUSE_RESERVED_ODM0[0x8]; uint32_t FUSE_OBS_DIS; - uint32_t FUSE_NOR_INFO; + uint32_t _0x1EC; uint32_t FUSE_USB_CALIB; uint32_t FUSE_SKU_DIRECT_CONFIG; uint32_t FUSE_KFUSE_PRIVKEY_CTRL; @@ -106,14 +105,12 @@ typedef struct { uint32_t FUSE_OPT_Y_COORDINATE; uint32_t FUSE_OPT_SEC_DEBUG_EN; uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t FUSE_SATA_CALIB; + uint32_t _0x224; uint32_t FUSE_GPU_IDDQ_CALIB; uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_SKU_BOND_OUT_L; - uint32_t FUSE_SKU_BOND_OUT_H; - uint32_t FUSE_SKU_BOND_OUT_U; - uint32_t FUSE_SKU_BOND_OUT_V; - uint32_t FUSE_SKU_BOND_OUT_W; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t _0x238[0x3]; uint32_t FUSE_OPT_SAMPLE_TYPE; uint32_t FUSE_OPT_SUBREVISION; uint32_t FUSE_OPT_SW_RESERVED_0; @@ -123,35 +120,26 @@ typedef struct { uint32_t FUSE_TSENSOR6_CALIB; uint32_t FUSE_TSENSOR7_CALIB; uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t FUSE_PKC_DISABLE; - uint32_t _0x16C; - uint32_t _0x170; - uint32_t _0x174; - uint32_t _0x178; + uint32_t _0x268[0x5]; uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; uint32_t FUSE_TSENSOR_COMMON; uint32_t FUSE_OPT_CP_BIN; uint32_t FUSE_OPT_GPU_DISABLE; uint32_t FUSE_OPT_FT_BIN; uint32_t FUSE_OPT_DONE_MAP; - uint32_t _0x194; + uint32_t _0x294; uint32_t FUSE_APB2JTAG_DISABLE; uint32_t FUSE_ODM_INFO; - uint32_t _0x1A0; - uint32_t _0x1A4; + uint32_t _0x2A0[0x2]; uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x1AC; - uint32_t _0x1B0; - uint32_t _0x1B4; - uint32_t _0x1B8; - uint32_t _0x1BC; + uint32_t _0x2AC[0x5]; uint32_t FUSE_WOA_SKU_FLAG; uint32_t FUSE_ECO_RESERVE_1; uint32_t FUSE_GCPLEX_CONFIG_FUSE; uint32_t FUSE_PRODUCTION_MONTH; uint32_t FUSE_RAM_REPAIR_INDICATOR; uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x1D8; + uint32_t _0x2D8; uint32_t FUSE_VMIN_CALIBRATION; uint32_t FUSE_AGING_SENSOR_CALIBRATION; uint32_t FUSE_DEBUG_AUTHENTICATION; @@ -160,8 +148,7 @@ typedef struct { uint32_t FUSE_OPT_GPU_DISABLE_CP1; uint32_t FUSE_SPARE_ENDIS; uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x1FC; - uint32_t _0x200; + uint32_t _0x2FC[0x2]; uint32_t FUSE_RESERVED_CALIB0; uint32_t FUSE_RESERVED_CALIB1; uint32_t FUSE_OPT_GPU_TPC0_DISABLE; @@ -170,11 +157,7 @@ typedef struct { uint32_t FUSE_OPT_CPU_DISABLE_CP1; uint32_t FUSE_TSENSOR10_CALIB; uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t FUSE_OPT_RAM_SVOP_DP; - uint32_t FUSE_OPT_RAM_SVOP_PDP; - uint32_t FUSE_OPT_RAM_SVOP_REG; - uint32_t FUSE_OPT_RAM_SVOP_SP; - uint32_t FUSE_OPT_RAM_SVOP_SMPDP; + uint32_t _0x324[0x5]; uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; uint32_t FUSE_OPT_GPU_TPC1_DISABLE; uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; @@ -183,27 +166,294 @@ typedef struct { uint32_t FUSE_OPT_GPU_DISABLE_CP2; uint32_t FUSE_USB_CALIB_EXT; uint32_t FUSE_RESERVED_FIELD; - uint32_t FUSE_OPT_ECC_EN; - uint32_t _0x25C; - uint32_t _0x260; - uint32_t _0x264; - uint32_t _0x268; - uint32_t _0x26C; - uint32_t _0x270; - uint32_t _0x274; - uint32_t _0x278; + uint32_t _0x358[0x9]; uint32_t FUSE_SPARE_REALIGNMENT_REG; uint32_t FUSE_SPARE_BIT[0x20]; -} tegra_fuse_chip_t; +} tegra_fuse_chip_common_t; + +typedef struct { + uint32_t _0x98[0x1A]; + uint32_t FUSE_PRODUCTION_MODE; + uint32_t FUSE_JTAG_SECUREID_VALID; + uint32_t FUSE_ODM_LOCK; + uint32_t FUSE_OPT_OPENGL_EN; + uint32_t FUSE_SKU_INFO; + uint32_t FUSE_CPU_SPEEDO_0_CALIB; + uint32_t FUSE_CPU_IDDQ_CALIB; + uint32_t _0x11C[0x3]; + uint32_t FUSE_OPT_FT_REV; + uint32_t FUSE_CPU_SPEEDO_1_CALIB; + uint32_t FUSE_CPU_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_SPEEDO_0_CALIB; + uint32_t FUSE_SOC_SPEEDO_1_CALIB; + uint32_t FUSE_SOC_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_IDDQ_CALIB; + uint32_t _0x144; + uint32_t FUSE_FA; + uint32_t FUSE_RESERVED_PRODUCTION; + uint32_t FUSE_HDMI_LANE0_CALIB; + uint32_t FUSE_HDMI_LANE1_CALIB; + uint32_t FUSE_HDMI_LANE2_CALIB; + uint32_t FUSE_HDMI_LANE3_CALIB; + uint32_t FUSE_ENCRYPTION_RATE; + uint32_t FUSE_PUBLIC_KEY[0x8]; + uint32_t FUSE_TSENSOR1_CALIB; + uint32_t FUSE_TSENSOR2_CALIB; + uint32_t _0x18C; + uint32_t FUSE_OPT_CP_REV; + uint32_t FUSE_OPT_PFG; + uint32_t FUSE_TSENSOR0_CALIB; + uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; + uint32_t FUSE_SECURITY_MODE; + uint32_t FUSE_PRIVATE_KEY[0x5]; + uint32_t FUSE_ARM_JTAG_DIS; + uint32_t FUSE_BOOT_DEVICE_INFO; + uint32_t FUSE_RESERVED_SW; + uint32_t FUSE_OPT_VP9_DISABLE; + uint32_t FUSE_RESERVED_ODM0[0x8]; + uint32_t FUSE_OBS_DIS; + uint32_t _0x1EC; + uint32_t FUSE_USB_CALIB; + uint32_t FUSE_SKU_DIRECT_CONFIG; + uint32_t FUSE_KFUSE_PRIVKEY_CTRL; + uint32_t FUSE_PACKAGE_INFO; + uint32_t FUSE_OPT_VENDOR_CODE; + uint32_t FUSE_OPT_FAB_CODE; + uint32_t FUSE_OPT_LOT_CODE_0; + uint32_t FUSE_OPT_LOT_CODE_1; + uint32_t FUSE_OPT_WAFER_ID; + uint32_t FUSE_OPT_X_COORDINATE; + uint32_t FUSE_OPT_Y_COORDINATE; + uint32_t FUSE_OPT_SEC_DEBUG_EN; + uint32_t FUSE_OPT_OPS_RESERVED; + uint32_t FUSE_SATA_CALIB; /* Erista only. */ + uint32_t FUSE_GPU_IDDQ_CALIB; + uint32_t FUSE_TSENSOR3_CALIB; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t _0x238[0x3]; + uint32_t FUSE_OPT_SAMPLE_TYPE; + uint32_t FUSE_OPT_SUBREVISION; + uint32_t FUSE_OPT_SW_RESERVED_0; + uint32_t FUSE_OPT_SW_RESERVED_1; + uint32_t FUSE_TSENSOR4_CALIB; + uint32_t FUSE_TSENSOR5_CALIB; + uint32_t FUSE_TSENSOR6_CALIB; + uint32_t FUSE_TSENSOR7_CALIB; + uint32_t FUSE_OPT_PRIV_SEC_EN; + uint32_t FUSE_PKC_DISABLE; /* Erista only. */ + uint32_t _0x26C[0x4]; + uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; + uint32_t FUSE_TSENSOR_COMMON; + uint32_t FUSE_OPT_CP_BIN; + uint32_t FUSE_OPT_GPU_DISABLE; + uint32_t FUSE_OPT_FT_BIN; + uint32_t FUSE_OPT_DONE_MAP; + uint32_t _0x294; + uint32_t FUSE_APB2JTAG_DISABLE; + uint32_t FUSE_ODM_INFO; + uint32_t _0x2A0[0x2]; + uint32_t FUSE_ARM_CRYPT_DE_FEATURE; + uint32_t _0x2AC[0x5]; + uint32_t FUSE_WOA_SKU_FLAG; + uint32_t FUSE_ECO_RESERVE_1; + uint32_t FUSE_GCPLEX_CONFIG_FUSE; + uint32_t FUSE_PRODUCTION_MONTH; + uint32_t FUSE_RAM_REPAIR_INDICATOR; + uint32_t FUSE_TSENSOR9_CALIB; + uint32_t _0x2D8; + uint32_t FUSE_VMIN_CALIBRATION; + uint32_t FUSE_AGING_SENSOR_CALIBRATION; + uint32_t FUSE_DEBUG_AUTHENTICATION; + uint32_t FUSE_SECURE_PROVISION_INDEX; + uint32_t FUSE_SECURE_PROVISION_INFO; + uint32_t FUSE_OPT_GPU_DISABLE_CP1; + uint32_t FUSE_SPARE_ENDIS; + uint32_t FUSE_ECO_RESERVE_0; + uint32_t _0x2FC[0x2]; + uint32_t FUSE_RESERVED_CALIB0; + uint32_t FUSE_RESERVED_CALIB1; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; + uint32_t FUSE_OPT_CPU_DISABLE; + uint32_t FUSE_OPT_CPU_DISABLE_CP1; + uint32_t FUSE_TSENSOR10_CALIB; + uint32_t FUSE_TSENSOR10_CALIB_AUX; + uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */ + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; + uint32_t FUSE_OPT_CPU_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_DISABLE_CP2; + uint32_t FUSE_USB_CALIB_EXT; + uint32_t FUSE_RESERVED_FIELD; + uint32_t _0x358[0x9]; + uint32_t FUSE_SPARE_REALIGNMENT_REG; + uint32_t FUSE_SPARE_BIT[0x20]; +} tegra_fuse_chip_erista_t; + +typedef struct { + uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */ + uint32_t FUSE_KEK[0x4]; /* Mariko only. */ + uint32_t FUSE_BEK[0x4]; /* Mariko only. */ + uint32_t _0xF0; /* Mariko only. */ + uint32_t _0xF4; /* Mariko only. */ + uint32_t _0xF8; /* Mariko only. */ + uint32_t _0xFC; /* Mariko only. */ + uint32_t FUSE_PRODUCTION_MODE; + uint32_t FUSE_JTAG_SECUREID_VALID; + uint32_t FUSE_ODM_LOCK; + uint32_t FUSE_OPT_OPENGL_EN; + uint32_t FUSE_SKU_INFO; + uint32_t FUSE_CPU_SPEEDO_0_CALIB; + uint32_t FUSE_CPU_IDDQ_CALIB; + uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */ + uint32_t FUSE_OPT_FT_REV; + uint32_t FUSE_CPU_SPEEDO_1_CALIB; + uint32_t FUSE_CPU_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_SPEEDO_0_CALIB; + uint32_t FUSE_SOC_SPEEDO_1_CALIB; + uint32_t FUSE_SOC_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_IDDQ_CALIB; + uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */ + uint32_t FUSE_FA; + uint32_t FUSE_RESERVED_PRODUCTION; + uint32_t FUSE_HDMI_LANE0_CALIB; + uint32_t FUSE_HDMI_LANE1_CALIB; + uint32_t FUSE_HDMI_LANE2_CALIB; + uint32_t FUSE_HDMI_LANE3_CALIB; + uint32_t FUSE_ENCRYPTION_RATE; + uint32_t FUSE_PUBLIC_KEY[0x8]; + uint32_t FUSE_TSENSOR1_CALIB; + uint32_t FUSE_TSENSOR2_CALIB; + uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */ + uint32_t FUSE_OPT_CP_REV; + uint32_t FUSE_OPT_PFG; + uint32_t FUSE_TSENSOR0_CALIB; + uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; + uint32_t FUSE_SECURITY_MODE; + uint32_t FUSE_PRIVATE_KEY[0x5]; + uint32_t FUSE_ARM_JTAG_DIS; + uint32_t FUSE_BOOT_DEVICE_INFO; + uint32_t FUSE_RESERVED_SW; + uint32_t FUSE_OPT_VP9_DISABLE; + uint32_t FUSE_RESERVED_ODM0[0x8]; + uint32_t FUSE_OBS_DIS; + uint32_t _0x1EC; /* Mariko only. */ + uint32_t FUSE_USB_CALIB; + uint32_t FUSE_SKU_DIRECT_CONFIG; + uint32_t FUSE_KFUSE_PRIVKEY_CTRL; + uint32_t FUSE_PACKAGE_INFO; + uint32_t FUSE_OPT_VENDOR_CODE; + uint32_t FUSE_OPT_FAB_CODE; + uint32_t FUSE_OPT_LOT_CODE_0; + uint32_t FUSE_OPT_LOT_CODE_1; + uint32_t FUSE_OPT_WAFER_ID; + uint32_t FUSE_OPT_X_COORDINATE; + uint32_t FUSE_OPT_Y_COORDINATE; + uint32_t FUSE_OPT_SEC_DEBUG_EN; + uint32_t FUSE_OPT_OPS_RESERVED; + uint32_t _0x224; /* Mariko only. */ + uint32_t FUSE_GPU_IDDQ_CALIB; + uint32_t FUSE_TSENSOR3_CALIB; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */ + uint32_t FUSE_OPT_SAMPLE_TYPE; + uint32_t FUSE_OPT_SUBREVISION; + uint32_t FUSE_OPT_SW_RESERVED_0; + uint32_t FUSE_OPT_SW_RESERVED_1; + uint32_t FUSE_TSENSOR4_CALIB; + uint32_t FUSE_TSENSOR5_CALIB; + uint32_t FUSE_TSENSOR6_CALIB; + uint32_t FUSE_TSENSOR7_CALIB; + uint32_t FUSE_OPT_PRIV_SEC_EN; + uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */ + uint32_t _0x26C; /* Mariko only. */ + uint32_t _0x270; /* Mariko only. */ + uint32_t _0x274; /* Mariko only. */ + uint32_t _0x278; /* Mariko only. */ + uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; + uint32_t FUSE_TSENSOR_COMMON; + uint32_t FUSE_OPT_CP_BIN; + uint32_t FUSE_OPT_GPU_DISABLE; + uint32_t FUSE_OPT_FT_BIN; + uint32_t FUSE_OPT_DONE_MAP; + uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */ + uint32_t FUSE_APB2JTAG_DISABLE; + uint32_t FUSE_ODM_INFO; + uint32_t _0x2A0[0x2]; + uint32_t FUSE_ARM_CRYPT_DE_FEATURE; + uint32_t _0x2AC; + uint32_t _0x2B0; /* Mariko only. */ + uint32_t _0x2B4; /* Mariko only. */ + uint32_t _0x2B8; /* Mariko only. */ + uint32_t _0x2BC; /* Mariko only. */ + uint32_t FUSE_WOA_SKU_FLAG; + uint32_t FUSE_ECO_RESERVE_1; + uint32_t FUSE_GCPLEX_CONFIG_FUSE; + uint32_t FUSE_PRODUCTION_MONTH; + uint32_t FUSE_RAM_REPAIR_INDICATOR; + uint32_t FUSE_TSENSOR9_CALIB; + uint32_t _0x2D8; + uint32_t FUSE_VMIN_CALIBRATION; + uint32_t FUSE_AGING_SENSOR_CALIBRATION; + uint32_t FUSE_DEBUG_AUTHENTICATION; + uint32_t FUSE_SECURE_PROVISION_INDEX; + uint32_t FUSE_SECURE_PROVISION_INFO; + uint32_t FUSE_OPT_GPU_DISABLE_CP1; + uint32_t FUSE_SPARE_ENDIS; + uint32_t FUSE_ECO_RESERVE_0; + uint32_t _0x2FC[0x2]; + uint32_t FUSE_RESERVED_CALIB0; + uint32_t FUSE_RESERVED_CALIB1; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; + uint32_t FUSE_OPT_CPU_DISABLE; + uint32_t FUSE_OPT_CPU_DISABLE_CP1; + uint32_t FUSE_TSENSOR10_CALIB; + uint32_t FUSE_TSENSOR10_CALIB_AUX; + uint32_t _0x324; /* Mariko only. */ + uint32_t _0x328; /* Mariko only. */ + uint32_t _0x32C; /* Mariko only. */ + uint32_t _0x330; /* Mariko only. */ + uint32_t _0x334; /* Mariko only. */ + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; + uint32_t FUSE_OPT_CPU_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_DISABLE_CP2; + uint32_t FUSE_USB_CALIB_EXT; + uint32_t FUSE_RESERVED_FIELD; + uint32_t _0x358[0x9]; + uint32_t FUSE_SPARE_REALIGNMENT_REG; + uint32_t FUSE_SPARE_BIT[0x1E]; +} tegra_fuse_chip_mariko_t; static inline volatile tegra_fuse_t *fuse_get_regs(void) { return (volatile tegra_fuse_t *)FUSE_BASE; } -static inline volatile tegra_fuse_chip_t *fuse_chip_get_regs(void) +static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void) { - return (volatile tegra_fuse_chip_t *)FUSE_CHIP_BASE; + return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE; +} + +static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void) +{ + return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE; +} + +static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void) +{ + return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE; } void fuse_init(void); @@ -213,8 +463,8 @@ void fuse_enable_power(void); void fuse_disable_power(void); uint32_t fuse_get_sku_info(void); -uint32_t fuse_get_spare_bit(uint32_t idx); -uint32_t fuse_get_reserved_odm(uint32_t idx); +uint32_t fuse_get_spare_bit(uint32_t index); +uint32_t fuse_get_reserved_odm(uint32_t index); uint32_t fuse_get_bootrom_patch_version(void); uint64_t fuse_get_device_id(void); uint32_t fuse_get_dram_id(void); @@ -222,8 +472,10 @@ uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware); uint32_t fuse_get_hardware_type(void); uint32_t fuse_get_retail_type(void); void fuse_get_hardware_info(void *dst); +bool fuse_is_new_format(void); uint32_t fuse_get_device_unique_key_generation(void); uint32_t fuse_get_soc_type(void); +uint32_t fuse_get_regulator(void); uint32_t fuse_hw_read(uint32_t addr); void fuse_hw_write(uint32_t value, uint32_t addr); diff --git a/fusee/fusee-primary/src/hwinit.c b/fusee/fusee-primary/src/hwinit.c index 44b7d9456..adc701ce4 100644 --- a/fusee/fusee-primary/src/hwinit.c +++ b/fusee/fusee-primary/src/hwinit.c @@ -153,7 +153,7 @@ void mbist_workaround() void config_se_brom() { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); volatile tegra_se_t *se = se_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs(); diff --git a/fusee/fusee-secondary/src/fuse.c b/fusee/fusee-secondary/src/fuse.c index 1b49f30d5..e53cda3b3 100644 --- a/fusee/fusee-secondary/src/fuse.c +++ b/fusee/fusee-secondary/src/fuse.c @@ -68,8 +68,9 @@ static void fuse_wait_idle(void) { uint32_t ctrl_val = 0; /* Wait for STATE_IDLE */ - while ((ctrl_val & (0xF0000)) != 0x40000) + while ((ctrl_val & (0xF0000)) != 0x40000) { ctrl_val = fuse->FUSE_FUSECTRL; + } } /* Read a fuse from the hardware array. */ @@ -134,34 +135,54 @@ void fuse_hw_sense(void) { /* Read the SKU info register. */ uint32_t fuse_get_sku_info(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); return fuse_chip->FUSE_SKU_INFO; } /* Read the bootrom patch version. */ uint32_t fuse_get_bootrom_patch_version(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB; } /* Read a spare bit register. */ -uint32_t fuse_get_spare_bit(uint32_t idx) { - if (idx < 32) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); - return fuse_chip->FUSE_SPARE_BIT[idx]; - } else { - return 0; +uint32_t fuse_get_spare_bit(uint32_t index) { + uint32_t soc_type = fuse_get_soc_type(); + if (soc_type == 0) { + if (index < 32) { + volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs(); + return fuse_chip->FUSE_SPARE_BIT[index]; + } + } else if (soc_type == 1) { + if (index < 30) { + volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); + return fuse_chip->FUSE_SPARE_BIT[index]; + } } + return 0; } /* Read a reserved ODM register. */ -uint32_t fuse_get_reserved_odm(uint32_t idx) { - if (idx < 8) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); - return fuse_chip->FUSE_RESERVED_ODM[idx]; - } else { - return 0; +uint32_t fuse_get_reserved_odm(uint32_t index) { + uint32_t soc_type = fuse_get_soc_type(); + if (index < 8) { + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); + return fuse_chip->FUSE_RESERVED_ODM0[index]; + } else if (soc_type == 1) { + volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); + if (index < 22) { + return fuse_chip->FUSE_RESERVED_ODM8[index - 8]; + } else if (index < 25) { + return fuse_chip->FUSE_RESERVED_ODM22[index - 22]; + } else if (index < 26) { + return fuse_chip->FUSE_RESERVED_ODM25; + } else if (index < 29) { + return fuse_chip->FUSE_RESERVED_ODM26[index - 26]; + } else if (index < 30) { + return fuse_chip->FUSE_RESERVED_ODM29; + } } + return 0; } /* Get the DramId. */ @@ -171,7 +192,7 @@ uint32_t fuse_get_dram_id(void) { /* Derive the DeviceId. */ uint64_t fuse_get_device_id(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint64_t device_id = 0; uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF; @@ -201,7 +222,7 @@ uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) { uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1)); if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1); switch (hardware_type) { @@ -262,7 +283,7 @@ uint32_t fuse_get_hardware_state(void) { /* Derive the 16-byte HardwareInfo and copy to output buffer. */ void fuse_get_hardware_info(void *dst) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint32_t hw_info[0x4]; uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F; @@ -283,9 +304,14 @@ void fuse_get_hardware_info(void *dst) { memcpy(dst, hw_info, 0x10); } +/* Check if have a new ODM fuse format. */ +bool fuse_is_new_format(void) { + return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)); +} + /* Get the DeviceUniqueKeyGeneration. */ uint32_t fuse_get_device_unique_key_generation(void) { - if ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)) { + if (fuse_is_new_format()) { return (fuse_get_reserved_odm(2) & 0x1F); } else { return 0; @@ -307,3 +333,12 @@ uint32_t fuse_get_soc_type(void) { return 0xF; /* SocType_Undefined */ } } + +/* Get the Regulator type. */ +uint32_t fuse_get_regulator(void) { + if (fuse_get_soc_type() == 1) { + return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */ + } else { + return 0; /* Regulator_Erista_Max77621 */ + } +} diff --git a/fusee/fusee-secondary/src/fuse.h b/fusee/fusee-secondary/src/fuse.h index 8bfec2b25..eb590553c 100644 --- a/fusee/fusee-secondary/src/fuse.h +++ b/fusee/fusee-secondary/src/fuse.h @@ -18,7 +18,7 @@ #define FUSEE_FUSE_H #define FUSE_BASE 0x7000F800 -#define FUSE_CHIP_BASE (FUSE_BASE + 0x100) +#define FUSE_CHIP_BASE (FUSE_BASE + 0x98) #define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n) #define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n) @@ -47,10 +47,11 @@ typedef struct { uint32_t FUSE_PRIVATE_KEY2_NONZERO; uint32_t FUSE_PRIVATE_KEY3_NONZERO; uint32_t FUSE_PRIVATE_KEY4_NONZERO; - uint32_t _0x90[0x1C]; + uint32_t _0x94; } tegra_fuse_t; typedef struct { + uint32_t _0x98[0x1A]; uint32_t FUSE_PRODUCTION_MODE; uint32_t FUSE_JTAG_SECUREID_VALID; uint32_t FUSE_ODM_LOCK; @@ -58,9 +59,7 @@ typedef struct { uint32_t FUSE_SKU_INFO; uint32_t FUSE_CPU_SPEEDO_0_CALIB; uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t FUSE_DAC_CRT_CALIB; - uint32_t FUSE_DAC_HDTV_CALIB; - uint32_t FUSE_DAC_SDTV_CALIB; + uint32_t _0x11C[0x3]; uint32_t FUSE_OPT_FT_REV; uint32_t FUSE_CPU_SPEEDO_1_CALIB; uint32_t FUSE_CPU_SPEEDO_2_CALIB; @@ -68,7 +67,7 @@ typedef struct { uint32_t FUSE_SOC_SPEEDO_1_CALIB; uint32_t FUSE_SOC_SPEEDO_2_CALIB; uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t FUSE_RESERVED_PRODUCTION_WP; + uint32_t _0x144; uint32_t FUSE_FA; uint32_t FUSE_RESERVED_PRODUCTION; uint32_t FUSE_HDMI_LANE0_CALIB; @@ -79,7 +78,7 @@ typedef struct { uint32_t FUSE_PUBLIC_KEY[0x8]; uint32_t FUSE_TSENSOR1_CALIB; uint32_t FUSE_TSENSOR2_CALIB; - uint32_t FUSE_VSENSOR_CALIB; + uint32_t _0x18C; uint32_t FUSE_OPT_CP_REV; uint32_t FUSE_OPT_PFG; uint32_t FUSE_TSENSOR0_CALIB; @@ -90,9 +89,9 @@ typedef struct { uint32_t FUSE_BOOT_DEVICE_INFO; uint32_t FUSE_RESERVED_SW; uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM[0x8]; + uint32_t FUSE_RESERVED_ODM0[0x8]; uint32_t FUSE_OBS_DIS; - uint32_t FUSE_NOR_INFO; + uint32_t _0x1EC; uint32_t FUSE_USB_CALIB; uint32_t FUSE_SKU_DIRECT_CONFIG; uint32_t FUSE_KFUSE_PRIVKEY_CTRL; @@ -106,14 +105,12 @@ typedef struct { uint32_t FUSE_OPT_Y_COORDINATE; uint32_t FUSE_OPT_SEC_DEBUG_EN; uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t FUSE_SATA_CALIB; + uint32_t _0x224; uint32_t FUSE_GPU_IDDQ_CALIB; uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_SKU_BOND_OUT_L; - uint32_t FUSE_SKU_BOND_OUT_H; - uint32_t FUSE_SKU_BOND_OUT_U; - uint32_t FUSE_SKU_BOND_OUT_V; - uint32_t FUSE_SKU_BOND_OUT_W; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t _0x238[0x3]; uint32_t FUSE_OPT_SAMPLE_TYPE; uint32_t FUSE_OPT_SUBREVISION; uint32_t FUSE_OPT_SW_RESERVED_0; @@ -123,35 +120,26 @@ typedef struct { uint32_t FUSE_TSENSOR6_CALIB; uint32_t FUSE_TSENSOR7_CALIB; uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t FUSE_PKC_DISABLE; - uint32_t _0x16C; - uint32_t _0x170; - uint32_t _0x174; - uint32_t _0x178; + uint32_t _0x268[0x5]; uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; uint32_t FUSE_TSENSOR_COMMON; uint32_t FUSE_OPT_CP_BIN; uint32_t FUSE_OPT_GPU_DISABLE; uint32_t FUSE_OPT_FT_BIN; uint32_t FUSE_OPT_DONE_MAP; - uint32_t _0x194; + uint32_t _0x294; uint32_t FUSE_APB2JTAG_DISABLE; uint32_t FUSE_ODM_INFO; - uint32_t _0x1A0; - uint32_t _0x1A4; + uint32_t _0x2A0[0x2]; uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x1AC; - uint32_t _0x1B0; - uint32_t _0x1B4; - uint32_t _0x1B8; - uint32_t _0x1BC; + uint32_t _0x2AC[0x5]; uint32_t FUSE_WOA_SKU_FLAG; uint32_t FUSE_ECO_RESERVE_1; uint32_t FUSE_GCPLEX_CONFIG_FUSE; uint32_t FUSE_PRODUCTION_MONTH; uint32_t FUSE_RAM_REPAIR_INDICATOR; uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x1D8; + uint32_t _0x2D8; uint32_t FUSE_VMIN_CALIBRATION; uint32_t FUSE_AGING_SENSOR_CALIBRATION; uint32_t FUSE_DEBUG_AUTHENTICATION; @@ -160,8 +148,7 @@ typedef struct { uint32_t FUSE_OPT_GPU_DISABLE_CP1; uint32_t FUSE_SPARE_ENDIS; uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x1FC; - uint32_t _0x200; + uint32_t _0x2FC[0x2]; uint32_t FUSE_RESERVED_CALIB0; uint32_t FUSE_RESERVED_CALIB1; uint32_t FUSE_OPT_GPU_TPC0_DISABLE; @@ -170,11 +157,7 @@ typedef struct { uint32_t FUSE_OPT_CPU_DISABLE_CP1; uint32_t FUSE_TSENSOR10_CALIB; uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t FUSE_OPT_RAM_SVOP_DP; - uint32_t FUSE_OPT_RAM_SVOP_PDP; - uint32_t FUSE_OPT_RAM_SVOP_REG; - uint32_t FUSE_OPT_RAM_SVOP_SP; - uint32_t FUSE_OPT_RAM_SVOP_SMPDP; + uint32_t _0x324[0x5]; uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; uint32_t FUSE_OPT_GPU_TPC1_DISABLE; uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; @@ -183,27 +166,294 @@ typedef struct { uint32_t FUSE_OPT_GPU_DISABLE_CP2; uint32_t FUSE_USB_CALIB_EXT; uint32_t FUSE_RESERVED_FIELD; - uint32_t FUSE_OPT_ECC_EN; - uint32_t _0x25C; - uint32_t _0x260; - uint32_t _0x264; - uint32_t _0x268; - uint32_t _0x26C; - uint32_t _0x270; - uint32_t _0x274; - uint32_t _0x278; + uint32_t _0x358[0x9]; uint32_t FUSE_SPARE_REALIGNMENT_REG; uint32_t FUSE_SPARE_BIT[0x20]; -} tegra_fuse_chip_t; +} tegra_fuse_chip_common_t; + +typedef struct { + uint32_t _0x98[0x1A]; + uint32_t FUSE_PRODUCTION_MODE; + uint32_t FUSE_JTAG_SECUREID_VALID; + uint32_t FUSE_ODM_LOCK; + uint32_t FUSE_OPT_OPENGL_EN; + uint32_t FUSE_SKU_INFO; + uint32_t FUSE_CPU_SPEEDO_0_CALIB; + uint32_t FUSE_CPU_IDDQ_CALIB; + uint32_t _0x11C[0x3]; + uint32_t FUSE_OPT_FT_REV; + uint32_t FUSE_CPU_SPEEDO_1_CALIB; + uint32_t FUSE_CPU_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_SPEEDO_0_CALIB; + uint32_t FUSE_SOC_SPEEDO_1_CALIB; + uint32_t FUSE_SOC_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_IDDQ_CALIB; + uint32_t _0x144; + uint32_t FUSE_FA; + uint32_t FUSE_RESERVED_PRODUCTION; + uint32_t FUSE_HDMI_LANE0_CALIB; + uint32_t FUSE_HDMI_LANE1_CALIB; + uint32_t FUSE_HDMI_LANE2_CALIB; + uint32_t FUSE_HDMI_LANE3_CALIB; + uint32_t FUSE_ENCRYPTION_RATE; + uint32_t FUSE_PUBLIC_KEY[0x8]; + uint32_t FUSE_TSENSOR1_CALIB; + uint32_t FUSE_TSENSOR2_CALIB; + uint32_t _0x18C; + uint32_t FUSE_OPT_CP_REV; + uint32_t FUSE_OPT_PFG; + uint32_t FUSE_TSENSOR0_CALIB; + uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; + uint32_t FUSE_SECURITY_MODE; + uint32_t FUSE_PRIVATE_KEY[0x5]; + uint32_t FUSE_ARM_JTAG_DIS; + uint32_t FUSE_BOOT_DEVICE_INFO; + uint32_t FUSE_RESERVED_SW; + uint32_t FUSE_OPT_VP9_DISABLE; + uint32_t FUSE_RESERVED_ODM0[0x8]; + uint32_t FUSE_OBS_DIS; + uint32_t _0x1EC; + uint32_t FUSE_USB_CALIB; + uint32_t FUSE_SKU_DIRECT_CONFIG; + uint32_t FUSE_KFUSE_PRIVKEY_CTRL; + uint32_t FUSE_PACKAGE_INFO; + uint32_t FUSE_OPT_VENDOR_CODE; + uint32_t FUSE_OPT_FAB_CODE; + uint32_t FUSE_OPT_LOT_CODE_0; + uint32_t FUSE_OPT_LOT_CODE_1; + uint32_t FUSE_OPT_WAFER_ID; + uint32_t FUSE_OPT_X_COORDINATE; + uint32_t FUSE_OPT_Y_COORDINATE; + uint32_t FUSE_OPT_SEC_DEBUG_EN; + uint32_t FUSE_OPT_OPS_RESERVED; + uint32_t FUSE_SATA_CALIB; /* Erista only. */ + uint32_t FUSE_GPU_IDDQ_CALIB; + uint32_t FUSE_TSENSOR3_CALIB; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t _0x238[0x3]; + uint32_t FUSE_OPT_SAMPLE_TYPE; + uint32_t FUSE_OPT_SUBREVISION; + uint32_t FUSE_OPT_SW_RESERVED_0; + uint32_t FUSE_OPT_SW_RESERVED_1; + uint32_t FUSE_TSENSOR4_CALIB; + uint32_t FUSE_TSENSOR5_CALIB; + uint32_t FUSE_TSENSOR6_CALIB; + uint32_t FUSE_TSENSOR7_CALIB; + uint32_t FUSE_OPT_PRIV_SEC_EN; + uint32_t FUSE_PKC_DISABLE; /* Erista only. */ + uint32_t _0x26C[0x4]; + uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; + uint32_t FUSE_TSENSOR_COMMON; + uint32_t FUSE_OPT_CP_BIN; + uint32_t FUSE_OPT_GPU_DISABLE; + uint32_t FUSE_OPT_FT_BIN; + uint32_t FUSE_OPT_DONE_MAP; + uint32_t _0x294; + uint32_t FUSE_APB2JTAG_DISABLE; + uint32_t FUSE_ODM_INFO; + uint32_t _0x2A0[0x2]; + uint32_t FUSE_ARM_CRYPT_DE_FEATURE; + uint32_t _0x2AC[0x5]; + uint32_t FUSE_WOA_SKU_FLAG; + uint32_t FUSE_ECO_RESERVE_1; + uint32_t FUSE_GCPLEX_CONFIG_FUSE; + uint32_t FUSE_PRODUCTION_MONTH; + uint32_t FUSE_RAM_REPAIR_INDICATOR; + uint32_t FUSE_TSENSOR9_CALIB; + uint32_t _0x2D8; + uint32_t FUSE_VMIN_CALIBRATION; + uint32_t FUSE_AGING_SENSOR_CALIBRATION; + uint32_t FUSE_DEBUG_AUTHENTICATION; + uint32_t FUSE_SECURE_PROVISION_INDEX; + uint32_t FUSE_SECURE_PROVISION_INFO; + uint32_t FUSE_OPT_GPU_DISABLE_CP1; + uint32_t FUSE_SPARE_ENDIS; + uint32_t FUSE_ECO_RESERVE_0; + uint32_t _0x2FC[0x2]; + uint32_t FUSE_RESERVED_CALIB0; + uint32_t FUSE_RESERVED_CALIB1; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; + uint32_t FUSE_OPT_CPU_DISABLE; + uint32_t FUSE_OPT_CPU_DISABLE_CP1; + uint32_t FUSE_TSENSOR10_CALIB; + uint32_t FUSE_TSENSOR10_CALIB_AUX; + uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */ + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; + uint32_t FUSE_OPT_CPU_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_DISABLE_CP2; + uint32_t FUSE_USB_CALIB_EXT; + uint32_t FUSE_RESERVED_FIELD; + uint32_t _0x358[0x9]; + uint32_t FUSE_SPARE_REALIGNMENT_REG; + uint32_t FUSE_SPARE_BIT[0x20]; +} tegra_fuse_chip_erista_t; + +typedef struct { + uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */ + uint32_t FUSE_KEK[0x4]; /* Mariko only. */ + uint32_t FUSE_BEK[0x4]; /* Mariko only. */ + uint32_t _0xF0; /* Mariko only. */ + uint32_t _0xF4; /* Mariko only. */ + uint32_t _0xF8; /* Mariko only. */ + uint32_t _0xFC; /* Mariko only. */ + uint32_t FUSE_PRODUCTION_MODE; + uint32_t FUSE_JTAG_SECUREID_VALID; + uint32_t FUSE_ODM_LOCK; + uint32_t FUSE_OPT_OPENGL_EN; + uint32_t FUSE_SKU_INFO; + uint32_t FUSE_CPU_SPEEDO_0_CALIB; + uint32_t FUSE_CPU_IDDQ_CALIB; + uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */ + uint32_t FUSE_OPT_FT_REV; + uint32_t FUSE_CPU_SPEEDO_1_CALIB; + uint32_t FUSE_CPU_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_SPEEDO_0_CALIB; + uint32_t FUSE_SOC_SPEEDO_1_CALIB; + uint32_t FUSE_SOC_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_IDDQ_CALIB; + uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */ + uint32_t FUSE_FA; + uint32_t FUSE_RESERVED_PRODUCTION; + uint32_t FUSE_HDMI_LANE0_CALIB; + uint32_t FUSE_HDMI_LANE1_CALIB; + uint32_t FUSE_HDMI_LANE2_CALIB; + uint32_t FUSE_HDMI_LANE3_CALIB; + uint32_t FUSE_ENCRYPTION_RATE; + uint32_t FUSE_PUBLIC_KEY[0x8]; + uint32_t FUSE_TSENSOR1_CALIB; + uint32_t FUSE_TSENSOR2_CALIB; + uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */ + uint32_t FUSE_OPT_CP_REV; + uint32_t FUSE_OPT_PFG; + uint32_t FUSE_TSENSOR0_CALIB; + uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; + uint32_t FUSE_SECURITY_MODE; + uint32_t FUSE_PRIVATE_KEY[0x5]; + uint32_t FUSE_ARM_JTAG_DIS; + uint32_t FUSE_BOOT_DEVICE_INFO; + uint32_t FUSE_RESERVED_SW; + uint32_t FUSE_OPT_VP9_DISABLE; + uint32_t FUSE_RESERVED_ODM0[0x8]; + uint32_t FUSE_OBS_DIS; + uint32_t _0x1EC; /* Mariko only. */ + uint32_t FUSE_USB_CALIB; + uint32_t FUSE_SKU_DIRECT_CONFIG; + uint32_t FUSE_KFUSE_PRIVKEY_CTRL; + uint32_t FUSE_PACKAGE_INFO; + uint32_t FUSE_OPT_VENDOR_CODE; + uint32_t FUSE_OPT_FAB_CODE; + uint32_t FUSE_OPT_LOT_CODE_0; + uint32_t FUSE_OPT_LOT_CODE_1; + uint32_t FUSE_OPT_WAFER_ID; + uint32_t FUSE_OPT_X_COORDINATE; + uint32_t FUSE_OPT_Y_COORDINATE; + uint32_t FUSE_OPT_SEC_DEBUG_EN; + uint32_t FUSE_OPT_OPS_RESERVED; + uint32_t _0x224; /* Mariko only. */ + uint32_t FUSE_GPU_IDDQ_CALIB; + uint32_t FUSE_TSENSOR3_CALIB; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */ + uint32_t FUSE_OPT_SAMPLE_TYPE; + uint32_t FUSE_OPT_SUBREVISION; + uint32_t FUSE_OPT_SW_RESERVED_0; + uint32_t FUSE_OPT_SW_RESERVED_1; + uint32_t FUSE_TSENSOR4_CALIB; + uint32_t FUSE_TSENSOR5_CALIB; + uint32_t FUSE_TSENSOR6_CALIB; + uint32_t FUSE_TSENSOR7_CALIB; + uint32_t FUSE_OPT_PRIV_SEC_EN; + uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */ + uint32_t _0x26C; /* Mariko only. */ + uint32_t _0x270; /* Mariko only. */ + uint32_t _0x274; /* Mariko only. */ + uint32_t _0x278; /* Mariko only. */ + uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; + uint32_t FUSE_TSENSOR_COMMON; + uint32_t FUSE_OPT_CP_BIN; + uint32_t FUSE_OPT_GPU_DISABLE; + uint32_t FUSE_OPT_FT_BIN; + uint32_t FUSE_OPT_DONE_MAP; + uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */ + uint32_t FUSE_APB2JTAG_DISABLE; + uint32_t FUSE_ODM_INFO; + uint32_t _0x2A0[0x2]; + uint32_t FUSE_ARM_CRYPT_DE_FEATURE; + uint32_t _0x2AC; + uint32_t _0x2B0; /* Mariko only. */ + uint32_t _0x2B4; /* Mariko only. */ + uint32_t _0x2B8; /* Mariko only. */ + uint32_t _0x2BC; /* Mariko only. */ + uint32_t FUSE_WOA_SKU_FLAG; + uint32_t FUSE_ECO_RESERVE_1; + uint32_t FUSE_GCPLEX_CONFIG_FUSE; + uint32_t FUSE_PRODUCTION_MONTH; + uint32_t FUSE_RAM_REPAIR_INDICATOR; + uint32_t FUSE_TSENSOR9_CALIB; + uint32_t _0x2D8; + uint32_t FUSE_VMIN_CALIBRATION; + uint32_t FUSE_AGING_SENSOR_CALIBRATION; + uint32_t FUSE_DEBUG_AUTHENTICATION; + uint32_t FUSE_SECURE_PROVISION_INDEX; + uint32_t FUSE_SECURE_PROVISION_INFO; + uint32_t FUSE_OPT_GPU_DISABLE_CP1; + uint32_t FUSE_SPARE_ENDIS; + uint32_t FUSE_ECO_RESERVE_0; + uint32_t _0x2FC[0x2]; + uint32_t FUSE_RESERVED_CALIB0; + uint32_t FUSE_RESERVED_CALIB1; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; + uint32_t FUSE_OPT_CPU_DISABLE; + uint32_t FUSE_OPT_CPU_DISABLE_CP1; + uint32_t FUSE_TSENSOR10_CALIB; + uint32_t FUSE_TSENSOR10_CALIB_AUX; + uint32_t _0x324; /* Mariko only. */ + uint32_t _0x328; /* Mariko only. */ + uint32_t _0x32C; /* Mariko only. */ + uint32_t _0x330; /* Mariko only. */ + uint32_t _0x334; /* Mariko only. */ + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; + uint32_t FUSE_OPT_CPU_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_DISABLE_CP2; + uint32_t FUSE_USB_CALIB_EXT; + uint32_t FUSE_RESERVED_FIELD; + uint32_t _0x358[0x9]; + uint32_t FUSE_SPARE_REALIGNMENT_REG; + uint32_t FUSE_SPARE_BIT[0x1E]; +} tegra_fuse_chip_mariko_t; static inline volatile tegra_fuse_t *fuse_get_regs(void) { return (volatile tegra_fuse_t *)FUSE_BASE; } -static inline volatile tegra_fuse_chip_t *fuse_chip_get_regs(void) +static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void) { - return (volatile tegra_fuse_chip_t *)FUSE_CHIP_BASE; + return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE; +} + +static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void) +{ + return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE; +} + +static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void) +{ + return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE; } void fuse_init(void); @@ -213,8 +463,8 @@ void fuse_enable_power(void); void fuse_disable_power(void); uint32_t fuse_get_sku_info(void); -uint32_t fuse_get_spare_bit(uint32_t idx); -uint32_t fuse_get_reserved_odm(uint32_t idx); +uint32_t fuse_get_spare_bit(uint32_t index); +uint32_t fuse_get_reserved_odm(uint32_t index); uint32_t fuse_get_bootrom_patch_version(void); uint64_t fuse_get_device_id(void); uint32_t fuse_get_dram_id(void); @@ -222,8 +472,10 @@ uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware); uint32_t fuse_get_hardware_type(void); uint32_t fuse_get_retail_type(void); void fuse_get_hardware_info(void *dst); +bool fuse_is_new_format(void); uint32_t fuse_get_device_unique_key_generation(void); uint32_t fuse_get_soc_type(void); +uint32_t fuse_get_regulator(void); uint32_t fuse_hw_read(uint32_t addr); void fuse_hw_write(uint32_t value, uint32_t addr); diff --git a/sept/sept-primary/src/fuse.c b/sept/sept-primary/src/fuse.c index 5edbbbc7f..1787bffb4 100644 --- a/sept/sept-primary/src/fuse.c +++ b/sept/sept-primary/src/fuse.c @@ -68,8 +68,9 @@ static void fuse_wait_idle(void) { uint32_t ctrl_val = 0; /* Wait for STATE_IDLE */ - while ((ctrl_val & (0xF0000)) != 0x40000) + while ((ctrl_val & (0xF0000)) != 0x40000) { ctrl_val = fuse->FUSE_FUSECTRL; + } } /* Read a fuse from the hardware array. */ @@ -134,34 +135,54 @@ void fuse_hw_sense(void) { /* Read the SKU info register. */ uint32_t fuse_get_sku_info(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); return fuse_chip->FUSE_SKU_INFO; } /* Read the bootrom patch version. */ uint32_t fuse_get_bootrom_patch_version(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB; } /* Read a spare bit register. */ -uint32_t fuse_get_spare_bit(uint32_t idx) { - if (idx < 32) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); - return fuse_chip->FUSE_SPARE_BIT[idx]; - } else { - return 0; +uint32_t fuse_get_spare_bit(uint32_t index) { + uint32_t soc_type = fuse_get_soc_type(); + if (soc_type == 0) { + if (index < 32) { + volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs(); + return fuse_chip->FUSE_SPARE_BIT[index]; + } + } else if (soc_type == 1) { + if (index < 30) { + volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); + return fuse_chip->FUSE_SPARE_BIT[index]; + } } + return 0; } /* Read a reserved ODM register. */ -uint32_t fuse_get_reserved_odm(uint32_t idx) { - if (idx < 8) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); - return fuse_chip->FUSE_RESERVED_ODM[idx]; - } else { - return 0; +uint32_t fuse_get_reserved_odm(uint32_t index) { + uint32_t soc_type = fuse_get_soc_type(); + if (index < 8) { + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); + return fuse_chip->FUSE_RESERVED_ODM0[index]; + } else if (soc_type == 1) { + volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); + if (index < 22) { + return fuse_chip->FUSE_RESERVED_ODM8[index - 8]; + } else if (index < 25) { + return fuse_chip->FUSE_RESERVED_ODM22[index - 22]; + } else if (index < 26) { + return fuse_chip->FUSE_RESERVED_ODM25; + } else if (index < 29) { + return fuse_chip->FUSE_RESERVED_ODM26[index - 26]; + } else if (index < 30) { + return fuse_chip->FUSE_RESERVED_ODM29; + } } + return 0; } /* Get the DramId. */ @@ -171,7 +192,7 @@ uint32_t fuse_get_dram_id(void) { /* Derive the DeviceId. */ uint64_t fuse_get_device_id(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint64_t device_id = 0; uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF; @@ -201,7 +222,7 @@ uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) { uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1)); if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1); switch (hardware_type) { @@ -262,7 +283,7 @@ uint32_t fuse_get_hardware_state(void) { /* Derive the 16-byte HardwareInfo and copy to output buffer. */ void fuse_get_hardware_info(void *dst) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint32_t hw_info[0x4]; uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F; @@ -283,9 +304,14 @@ void fuse_get_hardware_info(void *dst) { memcpy(dst, hw_info, 0x10); } +/* Check if have a new ODM fuse format. */ +bool fuse_is_new_format(void) { + return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)); +} + /* Get the DeviceUniqueKeyGeneration. */ uint32_t fuse_get_device_unique_key_generation(void) { - if ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)) { + if (fuse_is_new_format()) { return (fuse_get_reserved_odm(2) & 0x1F); } else { return 0; @@ -307,3 +333,12 @@ uint32_t fuse_get_soc_type(void) { return 0xF; /* SocType_Undefined */ } } + +/* Get the Regulator type. */ +uint32_t fuse_get_regulator(void) { + if (fuse_get_soc_type() == 1) { + return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */ + } else { + return 0; /* Regulator_Erista_Max77621 */ + } +} diff --git a/sept/sept-primary/src/fuse.h b/sept/sept-primary/src/fuse.h index 8bfec2b25..eb590553c 100644 --- a/sept/sept-primary/src/fuse.h +++ b/sept/sept-primary/src/fuse.h @@ -18,7 +18,7 @@ #define FUSEE_FUSE_H #define FUSE_BASE 0x7000F800 -#define FUSE_CHIP_BASE (FUSE_BASE + 0x100) +#define FUSE_CHIP_BASE (FUSE_BASE + 0x98) #define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n) #define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n) @@ -47,10 +47,11 @@ typedef struct { uint32_t FUSE_PRIVATE_KEY2_NONZERO; uint32_t FUSE_PRIVATE_KEY3_NONZERO; uint32_t FUSE_PRIVATE_KEY4_NONZERO; - uint32_t _0x90[0x1C]; + uint32_t _0x94; } tegra_fuse_t; typedef struct { + uint32_t _0x98[0x1A]; uint32_t FUSE_PRODUCTION_MODE; uint32_t FUSE_JTAG_SECUREID_VALID; uint32_t FUSE_ODM_LOCK; @@ -58,9 +59,7 @@ typedef struct { uint32_t FUSE_SKU_INFO; uint32_t FUSE_CPU_SPEEDO_0_CALIB; uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t FUSE_DAC_CRT_CALIB; - uint32_t FUSE_DAC_HDTV_CALIB; - uint32_t FUSE_DAC_SDTV_CALIB; + uint32_t _0x11C[0x3]; uint32_t FUSE_OPT_FT_REV; uint32_t FUSE_CPU_SPEEDO_1_CALIB; uint32_t FUSE_CPU_SPEEDO_2_CALIB; @@ -68,7 +67,7 @@ typedef struct { uint32_t FUSE_SOC_SPEEDO_1_CALIB; uint32_t FUSE_SOC_SPEEDO_2_CALIB; uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t FUSE_RESERVED_PRODUCTION_WP; + uint32_t _0x144; uint32_t FUSE_FA; uint32_t FUSE_RESERVED_PRODUCTION; uint32_t FUSE_HDMI_LANE0_CALIB; @@ -79,7 +78,7 @@ typedef struct { uint32_t FUSE_PUBLIC_KEY[0x8]; uint32_t FUSE_TSENSOR1_CALIB; uint32_t FUSE_TSENSOR2_CALIB; - uint32_t FUSE_VSENSOR_CALIB; + uint32_t _0x18C; uint32_t FUSE_OPT_CP_REV; uint32_t FUSE_OPT_PFG; uint32_t FUSE_TSENSOR0_CALIB; @@ -90,9 +89,9 @@ typedef struct { uint32_t FUSE_BOOT_DEVICE_INFO; uint32_t FUSE_RESERVED_SW; uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM[0x8]; + uint32_t FUSE_RESERVED_ODM0[0x8]; uint32_t FUSE_OBS_DIS; - uint32_t FUSE_NOR_INFO; + uint32_t _0x1EC; uint32_t FUSE_USB_CALIB; uint32_t FUSE_SKU_DIRECT_CONFIG; uint32_t FUSE_KFUSE_PRIVKEY_CTRL; @@ -106,14 +105,12 @@ typedef struct { uint32_t FUSE_OPT_Y_COORDINATE; uint32_t FUSE_OPT_SEC_DEBUG_EN; uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t FUSE_SATA_CALIB; + uint32_t _0x224; uint32_t FUSE_GPU_IDDQ_CALIB; uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_SKU_BOND_OUT_L; - uint32_t FUSE_SKU_BOND_OUT_H; - uint32_t FUSE_SKU_BOND_OUT_U; - uint32_t FUSE_SKU_BOND_OUT_V; - uint32_t FUSE_SKU_BOND_OUT_W; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t _0x238[0x3]; uint32_t FUSE_OPT_SAMPLE_TYPE; uint32_t FUSE_OPT_SUBREVISION; uint32_t FUSE_OPT_SW_RESERVED_0; @@ -123,35 +120,26 @@ typedef struct { uint32_t FUSE_TSENSOR6_CALIB; uint32_t FUSE_TSENSOR7_CALIB; uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t FUSE_PKC_DISABLE; - uint32_t _0x16C; - uint32_t _0x170; - uint32_t _0x174; - uint32_t _0x178; + uint32_t _0x268[0x5]; uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; uint32_t FUSE_TSENSOR_COMMON; uint32_t FUSE_OPT_CP_BIN; uint32_t FUSE_OPT_GPU_DISABLE; uint32_t FUSE_OPT_FT_BIN; uint32_t FUSE_OPT_DONE_MAP; - uint32_t _0x194; + uint32_t _0x294; uint32_t FUSE_APB2JTAG_DISABLE; uint32_t FUSE_ODM_INFO; - uint32_t _0x1A0; - uint32_t _0x1A4; + uint32_t _0x2A0[0x2]; uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x1AC; - uint32_t _0x1B0; - uint32_t _0x1B4; - uint32_t _0x1B8; - uint32_t _0x1BC; + uint32_t _0x2AC[0x5]; uint32_t FUSE_WOA_SKU_FLAG; uint32_t FUSE_ECO_RESERVE_1; uint32_t FUSE_GCPLEX_CONFIG_FUSE; uint32_t FUSE_PRODUCTION_MONTH; uint32_t FUSE_RAM_REPAIR_INDICATOR; uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x1D8; + uint32_t _0x2D8; uint32_t FUSE_VMIN_CALIBRATION; uint32_t FUSE_AGING_SENSOR_CALIBRATION; uint32_t FUSE_DEBUG_AUTHENTICATION; @@ -160,8 +148,7 @@ typedef struct { uint32_t FUSE_OPT_GPU_DISABLE_CP1; uint32_t FUSE_SPARE_ENDIS; uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x1FC; - uint32_t _0x200; + uint32_t _0x2FC[0x2]; uint32_t FUSE_RESERVED_CALIB0; uint32_t FUSE_RESERVED_CALIB1; uint32_t FUSE_OPT_GPU_TPC0_DISABLE; @@ -170,11 +157,7 @@ typedef struct { uint32_t FUSE_OPT_CPU_DISABLE_CP1; uint32_t FUSE_TSENSOR10_CALIB; uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t FUSE_OPT_RAM_SVOP_DP; - uint32_t FUSE_OPT_RAM_SVOP_PDP; - uint32_t FUSE_OPT_RAM_SVOP_REG; - uint32_t FUSE_OPT_RAM_SVOP_SP; - uint32_t FUSE_OPT_RAM_SVOP_SMPDP; + uint32_t _0x324[0x5]; uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; uint32_t FUSE_OPT_GPU_TPC1_DISABLE; uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; @@ -183,27 +166,294 @@ typedef struct { uint32_t FUSE_OPT_GPU_DISABLE_CP2; uint32_t FUSE_USB_CALIB_EXT; uint32_t FUSE_RESERVED_FIELD; - uint32_t FUSE_OPT_ECC_EN; - uint32_t _0x25C; - uint32_t _0x260; - uint32_t _0x264; - uint32_t _0x268; - uint32_t _0x26C; - uint32_t _0x270; - uint32_t _0x274; - uint32_t _0x278; + uint32_t _0x358[0x9]; uint32_t FUSE_SPARE_REALIGNMENT_REG; uint32_t FUSE_SPARE_BIT[0x20]; -} tegra_fuse_chip_t; +} tegra_fuse_chip_common_t; + +typedef struct { + uint32_t _0x98[0x1A]; + uint32_t FUSE_PRODUCTION_MODE; + uint32_t FUSE_JTAG_SECUREID_VALID; + uint32_t FUSE_ODM_LOCK; + uint32_t FUSE_OPT_OPENGL_EN; + uint32_t FUSE_SKU_INFO; + uint32_t FUSE_CPU_SPEEDO_0_CALIB; + uint32_t FUSE_CPU_IDDQ_CALIB; + uint32_t _0x11C[0x3]; + uint32_t FUSE_OPT_FT_REV; + uint32_t FUSE_CPU_SPEEDO_1_CALIB; + uint32_t FUSE_CPU_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_SPEEDO_0_CALIB; + uint32_t FUSE_SOC_SPEEDO_1_CALIB; + uint32_t FUSE_SOC_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_IDDQ_CALIB; + uint32_t _0x144; + uint32_t FUSE_FA; + uint32_t FUSE_RESERVED_PRODUCTION; + uint32_t FUSE_HDMI_LANE0_CALIB; + uint32_t FUSE_HDMI_LANE1_CALIB; + uint32_t FUSE_HDMI_LANE2_CALIB; + uint32_t FUSE_HDMI_LANE3_CALIB; + uint32_t FUSE_ENCRYPTION_RATE; + uint32_t FUSE_PUBLIC_KEY[0x8]; + uint32_t FUSE_TSENSOR1_CALIB; + uint32_t FUSE_TSENSOR2_CALIB; + uint32_t _0x18C; + uint32_t FUSE_OPT_CP_REV; + uint32_t FUSE_OPT_PFG; + uint32_t FUSE_TSENSOR0_CALIB; + uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; + uint32_t FUSE_SECURITY_MODE; + uint32_t FUSE_PRIVATE_KEY[0x5]; + uint32_t FUSE_ARM_JTAG_DIS; + uint32_t FUSE_BOOT_DEVICE_INFO; + uint32_t FUSE_RESERVED_SW; + uint32_t FUSE_OPT_VP9_DISABLE; + uint32_t FUSE_RESERVED_ODM0[0x8]; + uint32_t FUSE_OBS_DIS; + uint32_t _0x1EC; + uint32_t FUSE_USB_CALIB; + uint32_t FUSE_SKU_DIRECT_CONFIG; + uint32_t FUSE_KFUSE_PRIVKEY_CTRL; + uint32_t FUSE_PACKAGE_INFO; + uint32_t FUSE_OPT_VENDOR_CODE; + uint32_t FUSE_OPT_FAB_CODE; + uint32_t FUSE_OPT_LOT_CODE_0; + uint32_t FUSE_OPT_LOT_CODE_1; + uint32_t FUSE_OPT_WAFER_ID; + uint32_t FUSE_OPT_X_COORDINATE; + uint32_t FUSE_OPT_Y_COORDINATE; + uint32_t FUSE_OPT_SEC_DEBUG_EN; + uint32_t FUSE_OPT_OPS_RESERVED; + uint32_t FUSE_SATA_CALIB; /* Erista only. */ + uint32_t FUSE_GPU_IDDQ_CALIB; + uint32_t FUSE_TSENSOR3_CALIB; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t _0x238[0x3]; + uint32_t FUSE_OPT_SAMPLE_TYPE; + uint32_t FUSE_OPT_SUBREVISION; + uint32_t FUSE_OPT_SW_RESERVED_0; + uint32_t FUSE_OPT_SW_RESERVED_1; + uint32_t FUSE_TSENSOR4_CALIB; + uint32_t FUSE_TSENSOR5_CALIB; + uint32_t FUSE_TSENSOR6_CALIB; + uint32_t FUSE_TSENSOR7_CALIB; + uint32_t FUSE_OPT_PRIV_SEC_EN; + uint32_t FUSE_PKC_DISABLE; /* Erista only. */ + uint32_t _0x26C[0x4]; + uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; + uint32_t FUSE_TSENSOR_COMMON; + uint32_t FUSE_OPT_CP_BIN; + uint32_t FUSE_OPT_GPU_DISABLE; + uint32_t FUSE_OPT_FT_BIN; + uint32_t FUSE_OPT_DONE_MAP; + uint32_t _0x294; + uint32_t FUSE_APB2JTAG_DISABLE; + uint32_t FUSE_ODM_INFO; + uint32_t _0x2A0[0x2]; + uint32_t FUSE_ARM_CRYPT_DE_FEATURE; + uint32_t _0x2AC[0x5]; + uint32_t FUSE_WOA_SKU_FLAG; + uint32_t FUSE_ECO_RESERVE_1; + uint32_t FUSE_GCPLEX_CONFIG_FUSE; + uint32_t FUSE_PRODUCTION_MONTH; + uint32_t FUSE_RAM_REPAIR_INDICATOR; + uint32_t FUSE_TSENSOR9_CALIB; + uint32_t _0x2D8; + uint32_t FUSE_VMIN_CALIBRATION; + uint32_t FUSE_AGING_SENSOR_CALIBRATION; + uint32_t FUSE_DEBUG_AUTHENTICATION; + uint32_t FUSE_SECURE_PROVISION_INDEX; + uint32_t FUSE_SECURE_PROVISION_INFO; + uint32_t FUSE_OPT_GPU_DISABLE_CP1; + uint32_t FUSE_SPARE_ENDIS; + uint32_t FUSE_ECO_RESERVE_0; + uint32_t _0x2FC[0x2]; + uint32_t FUSE_RESERVED_CALIB0; + uint32_t FUSE_RESERVED_CALIB1; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; + uint32_t FUSE_OPT_CPU_DISABLE; + uint32_t FUSE_OPT_CPU_DISABLE_CP1; + uint32_t FUSE_TSENSOR10_CALIB; + uint32_t FUSE_TSENSOR10_CALIB_AUX; + uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */ + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; + uint32_t FUSE_OPT_CPU_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_DISABLE_CP2; + uint32_t FUSE_USB_CALIB_EXT; + uint32_t FUSE_RESERVED_FIELD; + uint32_t _0x358[0x9]; + uint32_t FUSE_SPARE_REALIGNMENT_REG; + uint32_t FUSE_SPARE_BIT[0x20]; +} tegra_fuse_chip_erista_t; + +typedef struct { + uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */ + uint32_t FUSE_KEK[0x4]; /* Mariko only. */ + uint32_t FUSE_BEK[0x4]; /* Mariko only. */ + uint32_t _0xF0; /* Mariko only. */ + uint32_t _0xF4; /* Mariko only. */ + uint32_t _0xF8; /* Mariko only. */ + uint32_t _0xFC; /* Mariko only. */ + uint32_t FUSE_PRODUCTION_MODE; + uint32_t FUSE_JTAG_SECUREID_VALID; + uint32_t FUSE_ODM_LOCK; + uint32_t FUSE_OPT_OPENGL_EN; + uint32_t FUSE_SKU_INFO; + uint32_t FUSE_CPU_SPEEDO_0_CALIB; + uint32_t FUSE_CPU_IDDQ_CALIB; + uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */ + uint32_t FUSE_OPT_FT_REV; + uint32_t FUSE_CPU_SPEEDO_1_CALIB; + uint32_t FUSE_CPU_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_SPEEDO_0_CALIB; + uint32_t FUSE_SOC_SPEEDO_1_CALIB; + uint32_t FUSE_SOC_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_IDDQ_CALIB; + uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */ + uint32_t FUSE_FA; + uint32_t FUSE_RESERVED_PRODUCTION; + uint32_t FUSE_HDMI_LANE0_CALIB; + uint32_t FUSE_HDMI_LANE1_CALIB; + uint32_t FUSE_HDMI_LANE2_CALIB; + uint32_t FUSE_HDMI_LANE3_CALIB; + uint32_t FUSE_ENCRYPTION_RATE; + uint32_t FUSE_PUBLIC_KEY[0x8]; + uint32_t FUSE_TSENSOR1_CALIB; + uint32_t FUSE_TSENSOR2_CALIB; + uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */ + uint32_t FUSE_OPT_CP_REV; + uint32_t FUSE_OPT_PFG; + uint32_t FUSE_TSENSOR0_CALIB; + uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; + uint32_t FUSE_SECURITY_MODE; + uint32_t FUSE_PRIVATE_KEY[0x5]; + uint32_t FUSE_ARM_JTAG_DIS; + uint32_t FUSE_BOOT_DEVICE_INFO; + uint32_t FUSE_RESERVED_SW; + uint32_t FUSE_OPT_VP9_DISABLE; + uint32_t FUSE_RESERVED_ODM0[0x8]; + uint32_t FUSE_OBS_DIS; + uint32_t _0x1EC; /* Mariko only. */ + uint32_t FUSE_USB_CALIB; + uint32_t FUSE_SKU_DIRECT_CONFIG; + uint32_t FUSE_KFUSE_PRIVKEY_CTRL; + uint32_t FUSE_PACKAGE_INFO; + uint32_t FUSE_OPT_VENDOR_CODE; + uint32_t FUSE_OPT_FAB_CODE; + uint32_t FUSE_OPT_LOT_CODE_0; + uint32_t FUSE_OPT_LOT_CODE_1; + uint32_t FUSE_OPT_WAFER_ID; + uint32_t FUSE_OPT_X_COORDINATE; + uint32_t FUSE_OPT_Y_COORDINATE; + uint32_t FUSE_OPT_SEC_DEBUG_EN; + uint32_t FUSE_OPT_OPS_RESERVED; + uint32_t _0x224; /* Mariko only. */ + uint32_t FUSE_GPU_IDDQ_CALIB; + uint32_t FUSE_TSENSOR3_CALIB; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */ + uint32_t FUSE_OPT_SAMPLE_TYPE; + uint32_t FUSE_OPT_SUBREVISION; + uint32_t FUSE_OPT_SW_RESERVED_0; + uint32_t FUSE_OPT_SW_RESERVED_1; + uint32_t FUSE_TSENSOR4_CALIB; + uint32_t FUSE_TSENSOR5_CALIB; + uint32_t FUSE_TSENSOR6_CALIB; + uint32_t FUSE_TSENSOR7_CALIB; + uint32_t FUSE_OPT_PRIV_SEC_EN; + uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */ + uint32_t _0x26C; /* Mariko only. */ + uint32_t _0x270; /* Mariko only. */ + uint32_t _0x274; /* Mariko only. */ + uint32_t _0x278; /* Mariko only. */ + uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; + uint32_t FUSE_TSENSOR_COMMON; + uint32_t FUSE_OPT_CP_BIN; + uint32_t FUSE_OPT_GPU_DISABLE; + uint32_t FUSE_OPT_FT_BIN; + uint32_t FUSE_OPT_DONE_MAP; + uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */ + uint32_t FUSE_APB2JTAG_DISABLE; + uint32_t FUSE_ODM_INFO; + uint32_t _0x2A0[0x2]; + uint32_t FUSE_ARM_CRYPT_DE_FEATURE; + uint32_t _0x2AC; + uint32_t _0x2B0; /* Mariko only. */ + uint32_t _0x2B4; /* Mariko only. */ + uint32_t _0x2B8; /* Mariko only. */ + uint32_t _0x2BC; /* Mariko only. */ + uint32_t FUSE_WOA_SKU_FLAG; + uint32_t FUSE_ECO_RESERVE_1; + uint32_t FUSE_GCPLEX_CONFIG_FUSE; + uint32_t FUSE_PRODUCTION_MONTH; + uint32_t FUSE_RAM_REPAIR_INDICATOR; + uint32_t FUSE_TSENSOR9_CALIB; + uint32_t _0x2D8; + uint32_t FUSE_VMIN_CALIBRATION; + uint32_t FUSE_AGING_SENSOR_CALIBRATION; + uint32_t FUSE_DEBUG_AUTHENTICATION; + uint32_t FUSE_SECURE_PROVISION_INDEX; + uint32_t FUSE_SECURE_PROVISION_INFO; + uint32_t FUSE_OPT_GPU_DISABLE_CP1; + uint32_t FUSE_SPARE_ENDIS; + uint32_t FUSE_ECO_RESERVE_0; + uint32_t _0x2FC[0x2]; + uint32_t FUSE_RESERVED_CALIB0; + uint32_t FUSE_RESERVED_CALIB1; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; + uint32_t FUSE_OPT_CPU_DISABLE; + uint32_t FUSE_OPT_CPU_DISABLE_CP1; + uint32_t FUSE_TSENSOR10_CALIB; + uint32_t FUSE_TSENSOR10_CALIB_AUX; + uint32_t _0x324; /* Mariko only. */ + uint32_t _0x328; /* Mariko only. */ + uint32_t _0x32C; /* Mariko only. */ + uint32_t _0x330; /* Mariko only. */ + uint32_t _0x334; /* Mariko only. */ + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; + uint32_t FUSE_OPT_CPU_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_DISABLE_CP2; + uint32_t FUSE_USB_CALIB_EXT; + uint32_t FUSE_RESERVED_FIELD; + uint32_t _0x358[0x9]; + uint32_t FUSE_SPARE_REALIGNMENT_REG; + uint32_t FUSE_SPARE_BIT[0x1E]; +} tegra_fuse_chip_mariko_t; static inline volatile tegra_fuse_t *fuse_get_regs(void) { return (volatile tegra_fuse_t *)FUSE_BASE; } -static inline volatile tegra_fuse_chip_t *fuse_chip_get_regs(void) +static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void) { - return (volatile tegra_fuse_chip_t *)FUSE_CHIP_BASE; + return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE; +} + +static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void) +{ + return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE; +} + +static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void) +{ + return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE; } void fuse_init(void); @@ -213,8 +463,8 @@ void fuse_enable_power(void); void fuse_disable_power(void); uint32_t fuse_get_sku_info(void); -uint32_t fuse_get_spare_bit(uint32_t idx); -uint32_t fuse_get_reserved_odm(uint32_t idx); +uint32_t fuse_get_spare_bit(uint32_t index); +uint32_t fuse_get_reserved_odm(uint32_t index); uint32_t fuse_get_bootrom_patch_version(void); uint64_t fuse_get_device_id(void); uint32_t fuse_get_dram_id(void); @@ -222,8 +472,10 @@ uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware); uint32_t fuse_get_hardware_type(void); uint32_t fuse_get_retail_type(void); void fuse_get_hardware_info(void *dst); +bool fuse_is_new_format(void); uint32_t fuse_get_device_unique_key_generation(void); uint32_t fuse_get_soc_type(void); +uint32_t fuse_get_regulator(void); uint32_t fuse_hw_read(uint32_t addr); void fuse_hw_write(uint32_t value, uint32_t addr); diff --git a/sept/sept-secondary/src/fuse.c b/sept/sept-secondary/src/fuse.c index 6f07da8ea..ef42ce431 100644 --- a/sept/sept-secondary/src/fuse.c +++ b/sept/sept-secondary/src/fuse.c @@ -68,8 +68,9 @@ static void fuse_wait_idle(void) { uint32_t ctrl_val = 0; /* Wait for STATE_IDLE */ - while ((ctrl_val & (0xF0000)) != 0x40000) + while ((ctrl_val & (0xF0000)) != 0x40000) { ctrl_val = fuse->FUSE_FUSECTRL; + } } /* Read a fuse from the hardware array. */ @@ -134,34 +135,54 @@ void fuse_hw_sense(void) { /* Read the SKU info register. */ uint32_t fuse_get_sku_info(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); return fuse_chip->FUSE_SKU_INFO; } /* Read the bootrom patch version. */ uint32_t fuse_get_bootrom_patch_version(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB; } /* Read a spare bit register. */ -uint32_t fuse_get_spare_bit(uint32_t idx) { - if (idx < 32) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); - return fuse_chip->FUSE_SPARE_BIT[idx]; - } else { - return 0; +uint32_t fuse_get_spare_bit(uint32_t index) { + uint32_t soc_type = fuse_get_soc_type(); + if (soc_type == 0) { + if (index < 32) { + volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs(); + return fuse_chip->FUSE_SPARE_BIT[index]; + } + } else if (soc_type == 1) { + if (index < 30) { + volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); + return fuse_chip->FUSE_SPARE_BIT[index]; + } } + return 0; } /* Read a reserved ODM register. */ -uint32_t fuse_get_reserved_odm(uint32_t idx) { - if (idx < 8) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); - return fuse_chip->FUSE_RESERVED_ODM[idx]; - } else { - return 0; +uint32_t fuse_get_reserved_odm(uint32_t index) { + uint32_t soc_type = fuse_get_soc_type(); + if (index < 8) { + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); + return fuse_chip->FUSE_RESERVED_ODM0[index]; + } else if (soc_type == 1) { + volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); + if (index < 22) { + return fuse_chip->FUSE_RESERVED_ODM8[index - 8]; + } else if (index < 25) { + return fuse_chip->FUSE_RESERVED_ODM22[index - 22]; + } else if (index < 26) { + return fuse_chip->FUSE_RESERVED_ODM25; + } else if (index < 29) { + return fuse_chip->FUSE_RESERVED_ODM26[index - 26]; + } else if (index < 30) { + return fuse_chip->FUSE_RESERVED_ODM29; + } } + return 0; } /* Get the DramId. */ @@ -171,7 +192,7 @@ uint32_t fuse_get_dram_id(void) { /* Derive the DeviceId. */ uint64_t fuse_get_device_id(void) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint64_t device_id = 0; uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF; @@ -201,7 +222,7 @@ uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) { uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1)); if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1); switch (hardware_type) { @@ -262,7 +283,7 @@ uint32_t fuse_get_hardware_state(void) { /* Derive the 16-byte HardwareInfo and copy to output buffer. */ void fuse_get_hardware_info(void *dst) { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); uint32_t hw_info[0x4]; uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F; @@ -283,9 +304,14 @@ void fuse_get_hardware_info(void *dst) { memcpy(dst, hw_info, 0x10); } +/* Check if have a new ODM fuse format. */ +bool fuse_is_new_format(void) { + return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)); +} + /* Get the DeviceUniqueKeyGeneration. */ uint32_t fuse_get_device_unique_key_generation(void) { - if ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)) { + if (fuse_is_new_format()) { return (fuse_get_reserved_odm(2) & 0x1F); } else { return 0; @@ -307,3 +333,12 @@ uint32_t fuse_get_soc_type(void) { return 0xF; /* SocType_Undefined */ } } + +/* Get the Regulator type. */ +uint32_t fuse_get_regulator(void) { + if (fuse_get_soc_type() == 1) { + return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */ + } else { + return 0; /* Regulator_Erista_Max77621 */ + } +} diff --git a/sept/sept-secondary/src/fuse.h b/sept/sept-secondary/src/fuse.h index 8bfec2b25..eb590553c 100644 --- a/sept/sept-secondary/src/fuse.h +++ b/sept/sept-secondary/src/fuse.h @@ -18,7 +18,7 @@ #define FUSEE_FUSE_H #define FUSE_BASE 0x7000F800 -#define FUSE_CHIP_BASE (FUSE_BASE + 0x100) +#define FUSE_CHIP_BASE (FUSE_BASE + 0x98) #define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n) #define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n) @@ -47,10 +47,11 @@ typedef struct { uint32_t FUSE_PRIVATE_KEY2_NONZERO; uint32_t FUSE_PRIVATE_KEY3_NONZERO; uint32_t FUSE_PRIVATE_KEY4_NONZERO; - uint32_t _0x90[0x1C]; + uint32_t _0x94; } tegra_fuse_t; typedef struct { + uint32_t _0x98[0x1A]; uint32_t FUSE_PRODUCTION_MODE; uint32_t FUSE_JTAG_SECUREID_VALID; uint32_t FUSE_ODM_LOCK; @@ -58,9 +59,7 @@ typedef struct { uint32_t FUSE_SKU_INFO; uint32_t FUSE_CPU_SPEEDO_0_CALIB; uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t FUSE_DAC_CRT_CALIB; - uint32_t FUSE_DAC_HDTV_CALIB; - uint32_t FUSE_DAC_SDTV_CALIB; + uint32_t _0x11C[0x3]; uint32_t FUSE_OPT_FT_REV; uint32_t FUSE_CPU_SPEEDO_1_CALIB; uint32_t FUSE_CPU_SPEEDO_2_CALIB; @@ -68,7 +67,7 @@ typedef struct { uint32_t FUSE_SOC_SPEEDO_1_CALIB; uint32_t FUSE_SOC_SPEEDO_2_CALIB; uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t FUSE_RESERVED_PRODUCTION_WP; + uint32_t _0x144; uint32_t FUSE_FA; uint32_t FUSE_RESERVED_PRODUCTION; uint32_t FUSE_HDMI_LANE0_CALIB; @@ -79,7 +78,7 @@ typedef struct { uint32_t FUSE_PUBLIC_KEY[0x8]; uint32_t FUSE_TSENSOR1_CALIB; uint32_t FUSE_TSENSOR2_CALIB; - uint32_t FUSE_VSENSOR_CALIB; + uint32_t _0x18C; uint32_t FUSE_OPT_CP_REV; uint32_t FUSE_OPT_PFG; uint32_t FUSE_TSENSOR0_CALIB; @@ -90,9 +89,9 @@ typedef struct { uint32_t FUSE_BOOT_DEVICE_INFO; uint32_t FUSE_RESERVED_SW; uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM[0x8]; + uint32_t FUSE_RESERVED_ODM0[0x8]; uint32_t FUSE_OBS_DIS; - uint32_t FUSE_NOR_INFO; + uint32_t _0x1EC; uint32_t FUSE_USB_CALIB; uint32_t FUSE_SKU_DIRECT_CONFIG; uint32_t FUSE_KFUSE_PRIVKEY_CTRL; @@ -106,14 +105,12 @@ typedef struct { uint32_t FUSE_OPT_Y_COORDINATE; uint32_t FUSE_OPT_SEC_DEBUG_EN; uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t FUSE_SATA_CALIB; + uint32_t _0x224; uint32_t FUSE_GPU_IDDQ_CALIB; uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_SKU_BOND_OUT_L; - uint32_t FUSE_SKU_BOND_OUT_H; - uint32_t FUSE_SKU_BOND_OUT_U; - uint32_t FUSE_SKU_BOND_OUT_V; - uint32_t FUSE_SKU_BOND_OUT_W; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t _0x238[0x3]; uint32_t FUSE_OPT_SAMPLE_TYPE; uint32_t FUSE_OPT_SUBREVISION; uint32_t FUSE_OPT_SW_RESERVED_0; @@ -123,35 +120,26 @@ typedef struct { uint32_t FUSE_TSENSOR6_CALIB; uint32_t FUSE_TSENSOR7_CALIB; uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t FUSE_PKC_DISABLE; - uint32_t _0x16C; - uint32_t _0x170; - uint32_t _0x174; - uint32_t _0x178; + uint32_t _0x268[0x5]; uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; uint32_t FUSE_TSENSOR_COMMON; uint32_t FUSE_OPT_CP_BIN; uint32_t FUSE_OPT_GPU_DISABLE; uint32_t FUSE_OPT_FT_BIN; uint32_t FUSE_OPT_DONE_MAP; - uint32_t _0x194; + uint32_t _0x294; uint32_t FUSE_APB2JTAG_DISABLE; uint32_t FUSE_ODM_INFO; - uint32_t _0x1A0; - uint32_t _0x1A4; + uint32_t _0x2A0[0x2]; uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x1AC; - uint32_t _0x1B0; - uint32_t _0x1B4; - uint32_t _0x1B8; - uint32_t _0x1BC; + uint32_t _0x2AC[0x5]; uint32_t FUSE_WOA_SKU_FLAG; uint32_t FUSE_ECO_RESERVE_1; uint32_t FUSE_GCPLEX_CONFIG_FUSE; uint32_t FUSE_PRODUCTION_MONTH; uint32_t FUSE_RAM_REPAIR_INDICATOR; uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x1D8; + uint32_t _0x2D8; uint32_t FUSE_VMIN_CALIBRATION; uint32_t FUSE_AGING_SENSOR_CALIBRATION; uint32_t FUSE_DEBUG_AUTHENTICATION; @@ -160,8 +148,7 @@ typedef struct { uint32_t FUSE_OPT_GPU_DISABLE_CP1; uint32_t FUSE_SPARE_ENDIS; uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x1FC; - uint32_t _0x200; + uint32_t _0x2FC[0x2]; uint32_t FUSE_RESERVED_CALIB0; uint32_t FUSE_RESERVED_CALIB1; uint32_t FUSE_OPT_GPU_TPC0_DISABLE; @@ -170,11 +157,7 @@ typedef struct { uint32_t FUSE_OPT_CPU_DISABLE_CP1; uint32_t FUSE_TSENSOR10_CALIB; uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t FUSE_OPT_RAM_SVOP_DP; - uint32_t FUSE_OPT_RAM_SVOP_PDP; - uint32_t FUSE_OPT_RAM_SVOP_REG; - uint32_t FUSE_OPT_RAM_SVOP_SP; - uint32_t FUSE_OPT_RAM_SVOP_SMPDP; + uint32_t _0x324[0x5]; uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; uint32_t FUSE_OPT_GPU_TPC1_DISABLE; uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; @@ -183,27 +166,294 @@ typedef struct { uint32_t FUSE_OPT_GPU_DISABLE_CP2; uint32_t FUSE_USB_CALIB_EXT; uint32_t FUSE_RESERVED_FIELD; - uint32_t FUSE_OPT_ECC_EN; - uint32_t _0x25C; - uint32_t _0x260; - uint32_t _0x264; - uint32_t _0x268; - uint32_t _0x26C; - uint32_t _0x270; - uint32_t _0x274; - uint32_t _0x278; + uint32_t _0x358[0x9]; uint32_t FUSE_SPARE_REALIGNMENT_REG; uint32_t FUSE_SPARE_BIT[0x20]; -} tegra_fuse_chip_t; +} tegra_fuse_chip_common_t; + +typedef struct { + uint32_t _0x98[0x1A]; + uint32_t FUSE_PRODUCTION_MODE; + uint32_t FUSE_JTAG_SECUREID_VALID; + uint32_t FUSE_ODM_LOCK; + uint32_t FUSE_OPT_OPENGL_EN; + uint32_t FUSE_SKU_INFO; + uint32_t FUSE_CPU_SPEEDO_0_CALIB; + uint32_t FUSE_CPU_IDDQ_CALIB; + uint32_t _0x11C[0x3]; + uint32_t FUSE_OPT_FT_REV; + uint32_t FUSE_CPU_SPEEDO_1_CALIB; + uint32_t FUSE_CPU_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_SPEEDO_0_CALIB; + uint32_t FUSE_SOC_SPEEDO_1_CALIB; + uint32_t FUSE_SOC_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_IDDQ_CALIB; + uint32_t _0x144; + uint32_t FUSE_FA; + uint32_t FUSE_RESERVED_PRODUCTION; + uint32_t FUSE_HDMI_LANE0_CALIB; + uint32_t FUSE_HDMI_LANE1_CALIB; + uint32_t FUSE_HDMI_LANE2_CALIB; + uint32_t FUSE_HDMI_LANE3_CALIB; + uint32_t FUSE_ENCRYPTION_RATE; + uint32_t FUSE_PUBLIC_KEY[0x8]; + uint32_t FUSE_TSENSOR1_CALIB; + uint32_t FUSE_TSENSOR2_CALIB; + uint32_t _0x18C; + uint32_t FUSE_OPT_CP_REV; + uint32_t FUSE_OPT_PFG; + uint32_t FUSE_TSENSOR0_CALIB; + uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; + uint32_t FUSE_SECURITY_MODE; + uint32_t FUSE_PRIVATE_KEY[0x5]; + uint32_t FUSE_ARM_JTAG_DIS; + uint32_t FUSE_BOOT_DEVICE_INFO; + uint32_t FUSE_RESERVED_SW; + uint32_t FUSE_OPT_VP9_DISABLE; + uint32_t FUSE_RESERVED_ODM0[0x8]; + uint32_t FUSE_OBS_DIS; + uint32_t _0x1EC; + uint32_t FUSE_USB_CALIB; + uint32_t FUSE_SKU_DIRECT_CONFIG; + uint32_t FUSE_KFUSE_PRIVKEY_CTRL; + uint32_t FUSE_PACKAGE_INFO; + uint32_t FUSE_OPT_VENDOR_CODE; + uint32_t FUSE_OPT_FAB_CODE; + uint32_t FUSE_OPT_LOT_CODE_0; + uint32_t FUSE_OPT_LOT_CODE_1; + uint32_t FUSE_OPT_WAFER_ID; + uint32_t FUSE_OPT_X_COORDINATE; + uint32_t FUSE_OPT_Y_COORDINATE; + uint32_t FUSE_OPT_SEC_DEBUG_EN; + uint32_t FUSE_OPT_OPS_RESERVED; + uint32_t FUSE_SATA_CALIB; /* Erista only. */ + uint32_t FUSE_GPU_IDDQ_CALIB; + uint32_t FUSE_TSENSOR3_CALIB; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t _0x238[0x3]; + uint32_t FUSE_OPT_SAMPLE_TYPE; + uint32_t FUSE_OPT_SUBREVISION; + uint32_t FUSE_OPT_SW_RESERVED_0; + uint32_t FUSE_OPT_SW_RESERVED_1; + uint32_t FUSE_TSENSOR4_CALIB; + uint32_t FUSE_TSENSOR5_CALIB; + uint32_t FUSE_TSENSOR6_CALIB; + uint32_t FUSE_TSENSOR7_CALIB; + uint32_t FUSE_OPT_PRIV_SEC_EN; + uint32_t FUSE_PKC_DISABLE; /* Erista only. */ + uint32_t _0x26C[0x4]; + uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; + uint32_t FUSE_TSENSOR_COMMON; + uint32_t FUSE_OPT_CP_BIN; + uint32_t FUSE_OPT_GPU_DISABLE; + uint32_t FUSE_OPT_FT_BIN; + uint32_t FUSE_OPT_DONE_MAP; + uint32_t _0x294; + uint32_t FUSE_APB2JTAG_DISABLE; + uint32_t FUSE_ODM_INFO; + uint32_t _0x2A0[0x2]; + uint32_t FUSE_ARM_CRYPT_DE_FEATURE; + uint32_t _0x2AC[0x5]; + uint32_t FUSE_WOA_SKU_FLAG; + uint32_t FUSE_ECO_RESERVE_1; + uint32_t FUSE_GCPLEX_CONFIG_FUSE; + uint32_t FUSE_PRODUCTION_MONTH; + uint32_t FUSE_RAM_REPAIR_INDICATOR; + uint32_t FUSE_TSENSOR9_CALIB; + uint32_t _0x2D8; + uint32_t FUSE_VMIN_CALIBRATION; + uint32_t FUSE_AGING_SENSOR_CALIBRATION; + uint32_t FUSE_DEBUG_AUTHENTICATION; + uint32_t FUSE_SECURE_PROVISION_INDEX; + uint32_t FUSE_SECURE_PROVISION_INFO; + uint32_t FUSE_OPT_GPU_DISABLE_CP1; + uint32_t FUSE_SPARE_ENDIS; + uint32_t FUSE_ECO_RESERVE_0; + uint32_t _0x2FC[0x2]; + uint32_t FUSE_RESERVED_CALIB0; + uint32_t FUSE_RESERVED_CALIB1; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; + uint32_t FUSE_OPT_CPU_DISABLE; + uint32_t FUSE_OPT_CPU_DISABLE_CP1; + uint32_t FUSE_TSENSOR10_CALIB; + uint32_t FUSE_TSENSOR10_CALIB_AUX; + uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */ + uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */ + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; + uint32_t FUSE_OPT_CPU_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_DISABLE_CP2; + uint32_t FUSE_USB_CALIB_EXT; + uint32_t FUSE_RESERVED_FIELD; + uint32_t _0x358[0x9]; + uint32_t FUSE_SPARE_REALIGNMENT_REG; + uint32_t FUSE_SPARE_BIT[0x20]; +} tegra_fuse_chip_erista_t; + +typedef struct { + uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */ + uint32_t FUSE_KEK[0x4]; /* Mariko only. */ + uint32_t FUSE_BEK[0x4]; /* Mariko only. */ + uint32_t _0xF0; /* Mariko only. */ + uint32_t _0xF4; /* Mariko only. */ + uint32_t _0xF8; /* Mariko only. */ + uint32_t _0xFC; /* Mariko only. */ + uint32_t FUSE_PRODUCTION_MODE; + uint32_t FUSE_JTAG_SECUREID_VALID; + uint32_t FUSE_ODM_LOCK; + uint32_t FUSE_OPT_OPENGL_EN; + uint32_t FUSE_SKU_INFO; + uint32_t FUSE_CPU_SPEEDO_0_CALIB; + uint32_t FUSE_CPU_IDDQ_CALIB; + uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */ + uint32_t FUSE_OPT_FT_REV; + uint32_t FUSE_CPU_SPEEDO_1_CALIB; + uint32_t FUSE_CPU_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_SPEEDO_0_CALIB; + uint32_t FUSE_SOC_SPEEDO_1_CALIB; + uint32_t FUSE_SOC_SPEEDO_2_CALIB; + uint32_t FUSE_SOC_IDDQ_CALIB; + uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */ + uint32_t FUSE_FA; + uint32_t FUSE_RESERVED_PRODUCTION; + uint32_t FUSE_HDMI_LANE0_CALIB; + uint32_t FUSE_HDMI_LANE1_CALIB; + uint32_t FUSE_HDMI_LANE2_CALIB; + uint32_t FUSE_HDMI_LANE3_CALIB; + uint32_t FUSE_ENCRYPTION_RATE; + uint32_t FUSE_PUBLIC_KEY[0x8]; + uint32_t FUSE_TSENSOR1_CALIB; + uint32_t FUSE_TSENSOR2_CALIB; + uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */ + uint32_t FUSE_OPT_CP_REV; + uint32_t FUSE_OPT_PFG; + uint32_t FUSE_TSENSOR0_CALIB; + uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; + uint32_t FUSE_SECURITY_MODE; + uint32_t FUSE_PRIVATE_KEY[0x5]; + uint32_t FUSE_ARM_JTAG_DIS; + uint32_t FUSE_BOOT_DEVICE_INFO; + uint32_t FUSE_RESERVED_SW; + uint32_t FUSE_OPT_VP9_DISABLE; + uint32_t FUSE_RESERVED_ODM0[0x8]; + uint32_t FUSE_OBS_DIS; + uint32_t _0x1EC; /* Mariko only. */ + uint32_t FUSE_USB_CALIB; + uint32_t FUSE_SKU_DIRECT_CONFIG; + uint32_t FUSE_KFUSE_PRIVKEY_CTRL; + uint32_t FUSE_PACKAGE_INFO; + uint32_t FUSE_OPT_VENDOR_CODE; + uint32_t FUSE_OPT_FAB_CODE; + uint32_t FUSE_OPT_LOT_CODE_0; + uint32_t FUSE_OPT_LOT_CODE_1; + uint32_t FUSE_OPT_WAFER_ID; + uint32_t FUSE_OPT_X_COORDINATE; + uint32_t FUSE_OPT_Y_COORDINATE; + uint32_t FUSE_OPT_SEC_DEBUG_EN; + uint32_t FUSE_OPT_OPS_RESERVED; + uint32_t _0x224; /* Mariko only. */ + uint32_t FUSE_GPU_IDDQ_CALIB; + uint32_t FUSE_TSENSOR3_CALIB; + uint32_t FUSE_CLOCK_BOUNDOUT0; + uint32_t FUSE_CLOCK_BOUNDOUT1; + uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */ + uint32_t FUSE_OPT_SAMPLE_TYPE; + uint32_t FUSE_OPT_SUBREVISION; + uint32_t FUSE_OPT_SW_RESERVED_0; + uint32_t FUSE_OPT_SW_RESERVED_1; + uint32_t FUSE_TSENSOR4_CALIB; + uint32_t FUSE_TSENSOR5_CALIB; + uint32_t FUSE_TSENSOR6_CALIB; + uint32_t FUSE_TSENSOR7_CALIB; + uint32_t FUSE_OPT_PRIV_SEC_EN; + uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */ + uint32_t _0x26C; /* Mariko only. */ + uint32_t _0x270; /* Mariko only. */ + uint32_t _0x274; /* Mariko only. */ + uint32_t _0x278; /* Mariko only. */ + uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; + uint32_t FUSE_TSENSOR_COMMON; + uint32_t FUSE_OPT_CP_BIN; + uint32_t FUSE_OPT_GPU_DISABLE; + uint32_t FUSE_OPT_FT_BIN; + uint32_t FUSE_OPT_DONE_MAP; + uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */ + uint32_t FUSE_APB2JTAG_DISABLE; + uint32_t FUSE_ODM_INFO; + uint32_t _0x2A0[0x2]; + uint32_t FUSE_ARM_CRYPT_DE_FEATURE; + uint32_t _0x2AC; + uint32_t _0x2B0; /* Mariko only. */ + uint32_t _0x2B4; /* Mariko only. */ + uint32_t _0x2B8; /* Mariko only. */ + uint32_t _0x2BC; /* Mariko only. */ + uint32_t FUSE_WOA_SKU_FLAG; + uint32_t FUSE_ECO_RESERVE_1; + uint32_t FUSE_GCPLEX_CONFIG_FUSE; + uint32_t FUSE_PRODUCTION_MONTH; + uint32_t FUSE_RAM_REPAIR_INDICATOR; + uint32_t FUSE_TSENSOR9_CALIB; + uint32_t _0x2D8; + uint32_t FUSE_VMIN_CALIBRATION; + uint32_t FUSE_AGING_SENSOR_CALIBRATION; + uint32_t FUSE_DEBUG_AUTHENTICATION; + uint32_t FUSE_SECURE_PROVISION_INDEX; + uint32_t FUSE_SECURE_PROVISION_INFO; + uint32_t FUSE_OPT_GPU_DISABLE_CP1; + uint32_t FUSE_SPARE_ENDIS; + uint32_t FUSE_ECO_RESERVE_0; + uint32_t _0x2FC[0x2]; + uint32_t FUSE_RESERVED_CALIB0; + uint32_t FUSE_RESERVED_CALIB1; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE; + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; + uint32_t FUSE_OPT_CPU_DISABLE; + uint32_t FUSE_OPT_CPU_DISABLE_CP1; + uint32_t FUSE_TSENSOR10_CALIB; + uint32_t FUSE_TSENSOR10_CALIB_AUX; + uint32_t _0x324; /* Mariko only. */ + uint32_t _0x328; /* Mariko only. */ + uint32_t _0x32C; /* Mariko only. */ + uint32_t _0x330; /* Mariko only. */ + uint32_t _0x334; /* Mariko only. */ + uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; + uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; + uint32_t FUSE_OPT_CPU_DISABLE_CP2; + uint32_t FUSE_OPT_GPU_DISABLE_CP2; + uint32_t FUSE_USB_CALIB_EXT; + uint32_t FUSE_RESERVED_FIELD; + uint32_t _0x358[0x9]; + uint32_t FUSE_SPARE_REALIGNMENT_REG; + uint32_t FUSE_SPARE_BIT[0x1E]; +} tegra_fuse_chip_mariko_t; static inline volatile tegra_fuse_t *fuse_get_regs(void) { return (volatile tegra_fuse_t *)FUSE_BASE; } -static inline volatile tegra_fuse_chip_t *fuse_chip_get_regs(void) +static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void) { - return (volatile tegra_fuse_chip_t *)FUSE_CHIP_BASE; + return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE; +} + +static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void) +{ + return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE; +} + +static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void) +{ + return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE; } void fuse_init(void); @@ -213,8 +463,8 @@ void fuse_enable_power(void); void fuse_disable_power(void); uint32_t fuse_get_sku_info(void); -uint32_t fuse_get_spare_bit(uint32_t idx); -uint32_t fuse_get_reserved_odm(uint32_t idx); +uint32_t fuse_get_spare_bit(uint32_t index); +uint32_t fuse_get_reserved_odm(uint32_t index); uint32_t fuse_get_bootrom_patch_version(void); uint64_t fuse_get_device_id(void); uint32_t fuse_get_dram_id(void); @@ -222,8 +472,10 @@ uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware); uint32_t fuse_get_hardware_type(void); uint32_t fuse_get_retail_type(void); void fuse_get_hardware_info(void *dst); +bool fuse_is_new_format(void); uint32_t fuse_get_device_unique_key_generation(void); uint32_t fuse_get_soc_type(void); +uint32_t fuse_get_regulator(void); uint32_t fuse_hw_read(uint32_t addr); void fuse_hw_write(uint32_t value, uint32_t addr); diff --git a/sept/sept-secondary/src/hwinit.c b/sept/sept-secondary/src/hwinit.c index 44b7d9456..adc701ce4 100644 --- a/sept/sept-secondary/src/hwinit.c +++ b/sept/sept-secondary/src/hwinit.c @@ -153,7 +153,7 @@ void mbist_workaround() void config_se_brom() { - volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); volatile tegra_se_t *se = se_get_regs(); volatile tegra_pmc_t *pmc = pmc_get_regs();