mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-22 04:11:18 +00:00
fusee_cpp: implement bpmp overclock
This commit is contained in:
parent
1a8f886a6e
commit
4480e7a8a5
7 changed files with 191 additions and 16 deletions
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@ -23,6 +23,7 @@ namespace ams::secmon::fatal {
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constexpr inline size_t FrameBufferSize = FrameBufferHeight * FrameBufferWidth * sizeof(u32);
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void InitializeDisplay();
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void ShowDisplay();
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void ShowDisplay(const ams::impl::FatalErrorContext *f_ctx, const Result save_result);
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}
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@ -572,6 +572,16 @@ namespace ams::nxboot {
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g_display_initialized = false;
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}
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void ShowDisplay() {
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/* Enable backlight. */
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constexpr auto DisplayBrightness = 100;
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if (g_lcd_vendor == 0x2050) {
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EnableBacklightForVendor2050ForAula(DisplayBrightness);
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} else {
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EnableBacklightForGeneric(DisplayBrightness);
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}
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}
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void ShowFatalError(const ams::impl::FatalErrorContext *f_ctx, const Result save_result) {
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/* If needed, initialize the display. */
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if (!IsDisplayInitialized()) {
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@ -601,13 +611,8 @@ namespace ams::nxboot {
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/* Ensure the device will see consistent data. */
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hw::FlushDataCache(g_frame_buffer, FrameBufferSize);
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/* Enable backlight. */
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constexpr auto DisplayBrightness = 100;
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if (g_lcd_vendor == 0x2050) {
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EnableBacklightForVendor2050ForAula(DisplayBrightness);
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} else {
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EnableBacklightForGeneric(DisplayBrightness);
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}
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/* Show the console. */
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ShowDisplay();
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}
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void ShowFatalError(const char *fmt, ...) {
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@ -635,13 +640,8 @@ namespace ams::nxboot {
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/* Ensure the device will see consistent data. */
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hw::FlushDataCache(g_frame_buffer, FrameBufferSize);
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/* Enable backlight. */
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constexpr auto DisplayBrightness = 100;
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if (g_lcd_vendor == 0x2050) {
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EnableBacklightForVendor2050ForAula(DisplayBrightness);
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} else {
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EnableBacklightForGeneric(DisplayBrightness);
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}
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/* Show the console. */
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ShowDisplay();
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WaitForReboot();
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}
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@ -26,4 +26,6 @@ namespace ams::nxboot {
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void InitializeDisplay();
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void FinalizeDisplay();
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void ShowDisplay();
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}
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@ -63,6 +63,9 @@ namespace ams::nxboot {
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/* Perform secure hardware initialization. */
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SecureInitialize(true);
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/* Overclock the bpmp. */
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clkrst::SetBpmpClockRate(fuse::GetSocType() == fuse::SocType_Mariko ? clkrst::BpmpClockRate_589MHz : clkrst::BpmpClockRate_576MHz);
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/* Initialize Sdram. */
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InitializeSdram();
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@ -88,7 +91,12 @@ namespace ams::nxboot {
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/* Read our overlay file. */
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ReadFuseeSecondary();
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/* Initialize display (splash screen will be visible from this point onwards). */
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InitializeDisplay();
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ShowDisplay();
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/* TODO */
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WaitForReboot();
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/* TODO */
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AMS_INFINITE_LOOP();
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@ -52,4 +52,17 @@ namespace ams::clkrst {
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void DisableSor1Clock();
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void DisableKfuseClock();
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enum BpmpClockRate {
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BpmpClockRate_408MHz,
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BpmpClockRate_544MHz,
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BpmpClockRate_576MHz,
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BpmpClockRate_589MHz,
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BpmpClockRate_Count,
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};
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BpmpClockRate GetBpmpClockRate();
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BpmpClockRate SetBpmpClockRate(BpmpClockRate rate);
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}
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@ -21,6 +21,8 @@ namespace ams::clkrst {
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constinit uintptr_t g_register_address = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress();
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constinit BpmpClockRate g_bpmp_clock_rate = BpmpClockRate_408MHz;
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struct ClockParameters {
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uintptr_t reset_offset;
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uintptr_t clk_enb_offset;
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@ -99,6 +101,64 @@ namespace ams::clkrst {
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(Cache2Clock, L, CACHE2);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(Cram2Clock, U, CRAM2);
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constexpr const u32 PllcDivn[] = {
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[BpmpClockRate_408MHz] = 0,
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[BpmpClockRate_544MHz] = 85,
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[BpmpClockRate_576MHz] = 90,
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[BpmpClockRate_589MHz] = 92,
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};
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void EnablePllc(BpmpClockRate rate) {
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const u32 desired_divn = PllcDivn[rate];
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/* Check if we're already enabled. */
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const bool is_enabled = reg::HasValue(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_ENABLE, ENABLE));
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const bool is_good_divn = reg::HasValue(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_VALUE(PLLC_BASE_PLLC_DIVN, desired_divn));
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if (is_enabled && is_good_divn) {
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return;
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}
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/* Take PLLC out of reset. */
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reg::Write(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC, (reg::Read(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC) & 0xBFF0000F) | (0x80000 << 4));
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reg::SetBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC2, 0xF0 << 8);
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/* Disable pll. */
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_ENABLE, DISABLE));
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reg::ClearBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC1, (1u << 27));
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util::WaitMicroSeconds(10);
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/* Set dividers. */
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reg::Write(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_VALUE(PLLC_BASE_PLLC_DIVM, 4),
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CLK_RST_REG_BITS_VALUE(PLLC_BASE_PLLC_DIVN, desired_divn));
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/* Enable pll. */
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_ENABLE, ENABLE));
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while (!reg::HasValue(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_LOCK, LOCK))) {
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/* ... */
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}
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/* Disable PLLC_OUT1. */
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reg::Write(g_register_address + CLK_RST_CONTROLLER_PLLC_OUT, CLK_RST_REG_BITS_VALUE(PLLC_OUT_PLLC_OUT1_RATIO, 1));
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/* Enable PLLC_OUT1. */
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_OUT, CLK_RST_REG_BITS_ENUM(PLLC_OUT_PLLC_OUT1_RSTN, RESET_DISABLE),
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CLK_RST_REG_BITS_ENUM(PLLC_OUT_PLLC_OUT1_CLKEN, ENABLE));
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util::WaitMicroSeconds(1'000);
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}
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void DisablePllc() {
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/* Disable PLLC/PLLC_OUT1. */
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_OUT, CLK_RST_REG_BITS_ENUM(PLLC_OUT_PLLC_OUT1_RSTN, RESET_ENABLE),
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CLK_RST_REG_BITS_ENUM(PLLC_OUT_PLLC_OUT1_CLKEN, DISABLE));
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_ENABLE, DISABLE));
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_REF_DIS, REF_DISABLE));
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_REF_DIS, REF_DISABLE));
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reg::SetBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC1, (1u << 27));
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reg::SetBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC, (1u << 30));
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util::WaitMicroSeconds(10);
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}
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}
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void SetRegisterAddress(uintptr_t address) {
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@ -208,4 +268,80 @@ namespace ams::clkrst {
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DisableClock(KfuseClock);
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}
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BpmpClockRate GetBpmpClockRate() {
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return g_bpmp_clock_rate;
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}
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BpmpClockRate SetBpmpClockRate(BpmpClockRate rate) {
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/* Get the current rate. */
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const auto prev_rate = g_bpmp_clock_rate;
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/* Cap our rate. */
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if (rate >= BpmpClockRate_Count) {
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rate = BpmpClockRate_589MHz;
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}
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/* Configure the rate. */
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if (rate != BpmpClockRate_408MHz) {
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/* If we were previously overclocked, restore to PLLP_OUT. */
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if (prev_rate != BpmpClockRate_408MHz) {
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reg::Write(g_register_address + CLK_RST_CONTROLLER_SCLK_BURST_POLICY, CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SYS_STATE, RUN),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_FIQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE, PLLP_OUT0));
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util::WaitMicroSeconds(1'000);
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}
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/* Configure PLLC. */
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EnablePllc(rate);
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/* Set SCLK. */
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reg::Write(g_register_address + CLK_RST_CONTROLLER_CLK_SYSTEM_RATE, CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_HCLK_DIS, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_AHB_RATE, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_PCLK_DIS, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_APB_RATE, 3));
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reg::Write(g_register_address + CLK_RST_CONTROLLER_SCLK_BURST_POLICY, CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SYS_STATE, RUN),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_FIQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE, PLLC_OUT1),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE, CLKM));
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} else {
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/* Configure to use PLLP_OUT0. */
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reg::Write(g_register_address + CLK_RST_CONTROLLER_SCLK_BURST_POLICY, CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SYS_STATE, RUN),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_FIQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE, CLKM));
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util::WaitMicroSeconds(1'000);
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reg::Write(g_register_address + CLK_RST_CONTROLLER_CLK_SYSTEM_RATE, CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_HCLK_DIS, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_AHB_RATE, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_PCLK_DIS, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_APB_RATE, 2));
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/* Disable PLLC. */
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DisablePllc();
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}
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/* Set the clock rate. */
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g_bpmp_clock_rate = rate;
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/* Return the previous rate. */
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return prev_rate;
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}
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}
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@ -41,6 +41,10 @@
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#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE (0x030)
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048)
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#define CLK_RST_CONTROLLER_OSC_CTRL (0x050)
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#define CLK_RST_CONTROLLER_PLLC_BASE (0x080)
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#define CLK_RST_CONTROLLER_PLLC_OUT (0x084)
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#define CLK_RST_CONTROLLER_PLLC_MISC (0x088)
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#define CLK_RST_CONTROLLER_PLLC_MISC1 (0x08C)
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#define CLK_RST_CONTROLLER_PLLM_BASE (0x090)
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#define CLK_RST_CONTROLLER_PLLM_MISC1 (0x098)
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#define CLK_RST_CONTROLLER_PLLM_MISC2 (0x09C)
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#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 (0x388)
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#define CLK_RST_CONTROLLER_SPARE_REG0 (0x55C)
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#define CLK_RST_CONTROLLER_PLLC4_BASE (0x5A4)
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#define CLK_RST_CONTROLLER_PLLC_MISC2 (0x5D0)
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#define CLK_RST_CONTROLLER_PLLMB_BASE (0x5E8)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA (0x0F8)
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@ -74,7 +79,6 @@ DEFINE_CLK_RST_REG_BIT_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_FIQ, 26, NOP
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DEFINE_CLK_RST_REG_BIT_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_FIQ, 27, NOP, BURST);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(SCLK_BURST_POLICY_SYS_STATE, 28, STDBY, IDLE, RUN, RSVD3, IRQ, RSVD5, RSVD6, RSVD7, FIQ, RSVD9, RSVD10, RSVD11, RSVD12, RSVD13, RSVD14, RSVD15);
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DEFINE_CLK_RST_REG(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIVISOR, 0, 8);
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DEFINE_CLK_RST_REG(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIVIDEND, 8, 8);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIS_FROM_CPU_IRQ, 24, NOP, DISABLE);
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@ -83,7 +87,6 @@ DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIS_FROM_CPU_FIQ, 26,
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIS_FROM_COP_FIQ, 27, NOP, DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_SCLK_DIVIDER_SUPER_SDIV_ENB, 31, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(CLK_SYSTEM_RATE_APB_RATE, 0, 2);
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DEFINE_CLK_RST_REG(CLK_SYSTEM_RATE_PCLK_DIS, 3, 1);
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DEFINE_CLK_RST_REG(CLK_SYSTEM_RATE_AHB_RATE, 4, 2);
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@ -95,6 +98,18 @@ DEFINE_CLK_RST_REG_BIT_ENUM(OSC_CTRL_XOE, 0, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(OSC_CTRL_XOFS, 4, 6);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(OSC_CTRL_OSC_FREQ, 28, OSC13, OSC16P8, RSVD2, RSVD3, OSC19P2, OSC38P4, RSVD6, RSVD7, OSC12, OSC48, RSVD10, RSVD11, OSC26, RSVD13, RSVD14, RSVD15);
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DEFINE_CLK_RST_REG(PLLC_BASE_PLLC_DIVM, 0, 8);
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DEFINE_CLK_RST_REG(PLLC_BASE_PLLC_DIVN, 10, 8);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_BASE_PLLC_LOCK, 27, NOT_LOCK, LOCK);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_BASE_PLLC_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_BASE_PLLC_ENABLE, 30, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_BASE_PLLC_BYPASS, 31, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_OUT_PLLC_OUT1_RSTN, 0, RESET_ENABLE, RESET_DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_OUT_PLLC_OUT1_CLKEN, 1, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(PLLC_OUT_PLLC_OUT1_RATIO, 8, 8);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_OUT_PLLC_OUT1_DIV_BYP, 16, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVM, 0, 8);
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DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVN, 8, 8);
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DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVP, 20, 5);
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