diff --git a/fusee/fusee-primary/Makefile b/fusee/fusee-primary/Makefile index 975160cb0..34307fcbe 100644 --- a/fusee/fusee-primary/Makefile +++ b/fusee/fusee-primary/Makefile @@ -18,7 +18,7 @@ include $(DEVKITARM)/base_rules #--------------------------------------------------------------------------------- TARGET := $(notdir $(CURDIR)) BUILD := build -SOURCES := src src/sdmmc src/hwinit src/lib src/lib/fatfs src/display +SOURCES := src src/sdmmc src/lib src/lib/fatfs src/display DATA := data INCLUDES := include diff --git a/fusee/fusee-primary/src/apb_misc.h b/fusee/fusee-primary/src/apb_misc.h index 114b7496a..4552a61b5 100644 --- a/fusee/fusee-primary/src/apb_misc.h +++ b/fusee/fusee-primary/src/apb_misc.h @@ -1,6 +1,17 @@ #ifndef FUSEE_APB_MISC_H #define FUSEE_APB_MISC_H +#include + +#define APB_MISC_BASE 0x70000000 +#define APB_PADCTL_BASE 0x70000810 +#define MAKE_APB_MISC_REG(n) MAKE_REG32(APB_MISC_BASE + n) +#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n) + +#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40) +#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64) +#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68) + #define SDMMC1_PAD_CAL_DRVUP_SHIFT (20) #define SDMMC1_PAD_CAL_DRVDN_SHIFT (12) #define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT) @@ -48,7 +59,7 @@ typedef struct { static inline volatile tegra_padctl_t *padctl_get_regs(void) { - return (volatile tegra_padctl_t *)0x70000810; + return (volatile tegra_padctl_t *)APB_PADCTL_BASE; } #endif diff --git a/fusee/fusee-primary/src/btn.c b/fusee/fusee-primary/src/btn.c new file mode 100644 index 000000000..bffc8e79d --- /dev/null +++ b/fusee/fusee-primary/src/btn.c @@ -0,0 +1,64 @@ +#include + +#include "btn.h" +#include "i2c.h" +#include "gpio.h" +#include "timers.h" + +uint32_t btn_read() +{ + uint32_t res = 0; + + if (!gpio_read(GPIO_BUTTON_VOL_DOWN)) + res |= BTN_VOL_DOWN; + + if (!gpio_read(GPIO_BUTTON_VOL_UP)) + res |= BTN_VOL_UP; + + uint32_t val = 0; + if (i2c_query(4, 0x3C, 0x15, &val, 1)) + { + if (val & 0x4) + res |= BTN_POWER; + } + + return res; +} + +uint32_t btn_wait() +{ + uint32_t res = 0, btn = btn_read(); + int pwr = 0; + + if (btn & BTN_POWER) + { + pwr = 1; + btn &= ~BTN_POWER; + } + + do + { + res = btn_read(); + + if (!(res & BTN_POWER) && pwr) + pwr = 0; + else if (pwr) + res &= ~BTN_POWER; + } while (btn == res); + + return res; +} + +uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask) +{ + uint32_t timeout = get_time_ms() + time_ms; + uint32_t res = btn_read() & mask; + + do + { + if (!(res & mask)) + res = btn_read() & mask; + } while (get_time_ms() < timeout); + + return res; +} \ No newline at end of file diff --git a/fusee/fusee-primary/src/btn.h b/fusee/fusee-primary/src/btn.h new file mode 100644 index 000000000..08f6f6921 --- /dev/null +++ b/fusee/fusee-primary/src/btn.h @@ -0,0 +1,12 @@ +#ifndef FUSEE_BTN_H_ +#define FUSEE_BTN_H_ + +#define BTN_POWER 0x1 +#define BTN_VOL_DOWN 0x2 +#define BTN_VOL_UP 0x4 + +uint32_t btn_read(); +uint32_t btn_wait(); +uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask); + +#endif \ No newline at end of file diff --git a/fusee/fusee-primary/src/car.c b/fusee/fusee-primary/src/car.c new file mode 100644 index 000000000..bc79be9a6 --- /dev/null +++ b/fusee/fusee-primary/src/car.c @@ -0,0 +1,114 @@ +#include "car.h" +#include "utils.h" + +static inline uint32_t get_clk_source_reg(CarDevice dev) { + switch (dev) { + case CARDEVICE_UARTA: return 0x178; + case CARDEVICE_UARTB: return 0x17C; + case CARDEVICE_UARTC: return 0x1A0; + case CARDEVICE_I2C1: return 0x124; + case CARDEVICE_I2C5: return 0x128; + case CARDEVICE_UNK: return 0; + case CARDEVICE_SE: return 0x42C; + case CARDEVICE_HOST1X: return 0x180; + case CARDEVICE_TSEC: return 0x1F4; + case CARDEVICE_SOR_SAFE: return 0; + case CARDEVICE_SOR0: return 0; + case CARDEVICE_SOR1: return 0x410; + case CARDEVICE_KFUSE: return 0; + case CARDEVICE_CL_DVFS: return 0; + case CARDEVICE_CORESIGHT: return 0x1D4; + case CARDEVICE_ACTMON: return 0x3E8; + case CARDEVICE_BPMP: return 0; + default: generic_panic(); + } +} + +static inline uint32_t get_clk_source_val(CarDevice dev) { + switch (dev) { + case CARDEVICE_UARTA: return 0; + case CARDEVICE_UARTB: return 0; + case CARDEVICE_UARTC: return 0; + case CARDEVICE_I2C1: return 6; + case CARDEVICE_I2C5: return 6; + case CARDEVICE_UNK: return 0; + case CARDEVICE_SE: return 0; + case CARDEVICE_HOST1X: return 4; + case CARDEVICE_TSEC: return 0; + case CARDEVICE_SOR_SAFE: return 0; + case CARDEVICE_SOR0: return 0; + case CARDEVICE_SOR1: return 0; + case CARDEVICE_KFUSE: return 0; + case CARDEVICE_CL_DVFS: return 0; + case CARDEVICE_CORESIGHT: return 0; + case CARDEVICE_ACTMON: return 6; + case CARDEVICE_BPMP: return 0; + default: generic_panic(); + } +} + +static inline uint32_t get_clk_source_div(CarDevice dev) { + switch (dev) { + case CARDEVICE_UARTA: return 0; + case CARDEVICE_UARTB: return 0; + case CARDEVICE_UARTC: return 0; + case CARDEVICE_I2C1: return 0; + case CARDEVICE_I2C5: return 0; + case CARDEVICE_UNK: return 0; + case CARDEVICE_SE: return 0; + case CARDEVICE_HOST1X: return 3; + case CARDEVICE_TSEC: return 2; + case CARDEVICE_SOR_SAFE: return 0; + case CARDEVICE_SOR0: return 0; + case CARDEVICE_SOR1: return 2; + case CARDEVICE_KFUSE: return 0; + case CARDEVICE_CL_DVFS: return 0; + case CARDEVICE_CORESIGHT: return 4; + case CARDEVICE_ACTMON: return 0; + case CARDEVICE_BPMP: return 0; + default: generic_panic(); + } +} + +static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298}; +static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4}; + +void clk_enable(CarDevice dev) { + uint32_t clk_source_reg; + if ((clk_source_reg = get_clk_source_reg(dev))) { + MAKE_CAR_REG(clk_source_reg) = (get_clk_source_val(dev) << 29) | get_clk_source_div(dev); + } + MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F); +} + +void clk_disable(CarDevice dev) { + MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F)); +} + +void rst_enable(CarDevice dev) { + MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F); +} + +void rst_disable(CarDevice dev) { + MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F)); +} + +void clkrst_enable(CarDevice dev) { + clk_enable(dev); + rst_disable(dev); +} + +void clkrst_disable(CarDevice dev) { + rst_enable(dev); + clk_disable(dev); +} + +void clkrst_reboot(CarDevice dev) { + clkrst_disable(dev); + clkrst_enable(dev); +} + +void clkrst_enable_fuse_regs(bool enable) { + volatile tegra_car_t *car = car_get_regs(); + car->misc_clk_enb = ((car->misc_clk_enb & 0xEFFFFFFF) | ((enable & 1) << 28)); +} diff --git a/fusee/fusee-primary/src/car.h b/fusee/fusee-primary/src/car.h index 8cc0fb139..6ec42e744 100644 --- a/fusee/fusee-primary/src/car.h +++ b/fusee/fusee-primary/src/car.h @@ -1,121 +1,202 @@ #ifndef FUSEE_CAR_H #define FUSEE_CAR_H -#define CLK_SOURCE_SDMMC1 20 -#define CLK_SOURCE_SDMMC2 21 -#define CLK_SOURCE_SDMMC3 47 -#define CLK_SOURCE_SDMMC4 25 -#define CLK_SOURCE_SDMMC_LEGACY 0 +#include +#include + +#define CAR_BASE 0x60006000 +#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n) #define CLK_L_SDMMC1 (1 << 14) #define CLK_L_SDMMC2 (1 << 9) #define CLK_U_SDMMC3 (1 << 5) #define CLK_L_SDMMC4 (1 << 15) -#define TEGRA_CLK_PLLS 6 /* Number of normal PLLs */ -#define TEGRA_CLK_SIMPLE_PLLS 3 /* Number of simple PLLs */ -#define TEGRA_CLK_SOURCES 64 /* Number of ppl clock sources L/H/U */ -#define TEGRA_CLK_SOURCES_VW 32 /* Number of ppl clock sources V/W */ -#define TEGRA_CLK_SOURCES_X 32 /* Number of ppl clock sources X */ -#define TEGRA_CLK_SOURCES_Y 18 /* Number of ppl clock sources Y */ - #define CLK_SOURCE_MASK (0b111 << 29) #define CLK_SOURCE_FIRST (0b000 << 29) #define CLK_DIVIDER_MASK (0xff << 0) #define CLK_DIVIDER_UNITY (0x00 << 0) -#define CAR_CONTROL_SDMMC1 (1 << 14) -#define CAR_CONTROL_SDMMC4 (1 << 15) -#define CAR_CONTROL_SDMMC_LEGACY (1 << 1) +#define NUM_CAR_BANKS 7 -/* PLL registers - there are several PLLs in the clock controller */ -typedef struct { - uint32_t pll_base; /* the control register */ - - /* pll_out[0] is output A control, pll_out[1] is output B control */ - uint32_t pll_out[2]; - uint32_t pll_misc; /* other misc things */ -} clk_pll_t; - -/* PLL registers - there are several PLLs in the clock controller */ -typedef struct { - uint32_t pll_base; /* the control register */ - uint32_t pll_misc; /* other misc things */ -} clk_pll_simple_t; - -typedef struct { - uint32_t pllm_base; /* the control register */ - uint32_t pllm_out; /* output control */ - uint32_t pllm_misc1; /* misc1 */ - uint32_t pllm_misc2; /* misc2 */ -} clk_pllm_t; +/* Clock and reset devices. */ +typedef enum { + CARDEVICE_UARTA = ((0 << 5) | 0x6), + CARDEVICE_UARTB = ((0 << 5) | 0x7), + CARDEVICE_UARTC = ((1 << 5) | 0x17), + CARDEVICE_I2C1 = ((0 << 5) | 0xC), + CARDEVICE_I2C5 = ((1 << 5) | 0xF), + CARDEVICE_UNK = ((3 << 5) | 0x1E), + CARDEVICE_SE = ((3 << 5) | 0x1F), + CARDEVICE_HOST1X = ((0 << 5) | 0x1C), + CARDEVICE_TSEC = ((2 << 5) | 0x13), + CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E), + CARDEVICE_SOR0 = ((5 << 5) | 0x16), + CARDEVICE_SOR1 = ((5 << 5) | 0x17), + CARDEVICE_KFUSE = ((1 << 5) | 0x8), + CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B), + CARDEVICE_CORESIGHT = ((2 << 5) | 0x9), + CARDEVICE_ACTMON = ((3 << 5) | 0x17), + CARDEVICE_BPMP = ((0 << 5) | 0x1) +} CarDevice; /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ typedef struct { - uint32_t rst_src; /* _RST_SOURCE_0,0x00 */ + uint32_t rst_src; /* _RST_SOURCE_0, 0x00 */ + /* _RST_DEVICES_L/H/U_0 0x4-0xc */ uint32_t rst_dev_l; uint32_t rst_dev_h; uint32_t rst_dev_u; + /* _CLK_OUT_ENB_L/H/U_0 0x10-0x18 */ uint32_t clk_out_enb_l; uint32_t clk_out_enb_h; uint32_t clk_out_enb_u; - uint32_t reserved0; /* reserved_0, 0x1C */ - uint32_t cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ - uint32_t super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ - uint32_t sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ - uint32_t super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ - uint32_t clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ - uint32_t prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ - uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ - uint32_t reserved1; /* reserved_1, 0x3C */ - uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ - uint32_t clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ - uint32_t misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ - uint32_t clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ - uint32_t osc_ctrl; /* _OSC_CTRL_0, 0x50 */ - uint32_t pll_lfsr; /* _PLL_LFSR_0, 0x54 */ - uint32_t osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ - uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ - uint32_t reserved2[8]; /* reserved_2[8], 0x60-7C */ + uint32_t _0x1C; + uint32_t cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ + uint32_t super_cclk_div; /* _SUPER_CCLK_DIVIDER_0, 0x24 */ + uint32_t sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ + uint32_t super_sclk_div; /* _SUPER_SCLK_DIVIDER_0, 0x2c */ + uint32_t clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ + uint32_t prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ + uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0, 0x38 */ + uint32_t _0x3C; + uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0, 0x40 */ + uint32_t clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ + uint32_t misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ + uint32_t clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4c */ + uint32_t osc_ctrl; /* _OSC_CTRL_0, 0x50 */ + uint32_t pll_lfsr; /* _PLL_LFSR_0, 0x54 */ + uint32_t osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ + uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0, 0x5c */ + uint32_t _0x60[2]; + uint32_t plle_ss_cntl; /* _PLLE_SS_CNTL_0, 0x68 */ + uint32_t plle_misc1; /* _PLLE_MISC1_0, 0x6c */ + uint32_t _0x70[4]; - clk_pll_t pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ + /* PLLC 0x80-0x8c */ + uint32_t pllc_base; + uint32_t pllc_out; + uint32_t pllc_misc0; + uint32_t pllc_misc1; + + /* PLLM 0x90-0x9c */ + uint32_t pllm_base; + uint32_t pllm_out; + uint32_t pllm_misc1; + uint32_t pllm_misc2; + + /* PLLP 0xa0-0xac */ + uint32_t pllp_base; + uint32_t pllp_outa; + uint32_t pllp_outb; + uint32_t pllp_misc; + + /* PLLA 0xb0-0xbc */ + uint32_t plla_base; + uint32_t plla_out; + uint32_t plla_misc0; + uint32_t plla_misc1; + + /* PLLU 0xc0-0xcc */ + uint32_t pllu_base; + uint32_t pllu_out; + uint32_t pllu_misc1; + uint32_t pllu_misc2; + + /* PLLD 0xd0-0xdc */ + uint32_t plld_base; + uint32_t plld_out; + uint32_t plld_misc1; + uint32_t plld_misc2; - /* PLLs from 0xe0 to 0xf4 */ - clk_pll_simple_t pll_simple[TEGRA_CLK_SIMPLE_PLLS]; + /* PLLX 0xe0-0xe4 */ + uint32_t pllx_base; + uint32_t pllx_misc; + + /* PLLE 0xe8-0xf4 */ + uint32_t plle_base; + uint32_t plle_misc; + uint32_t plle_ss_cntl1; + uint32_t plle_ss_cntl2; + + uint32_t lvl2_clk_gate_ovra; /* _LVL2_CLK_GATE_OVRA_0, 0xf8 */ + uint32_t lvl2_clk_gate_ovrb; /* _LVL2_CLK_GATE_OVRB_0, 0xfc */ - uint32_t reserved10; /* _reserved_10, 0xF8 */ - uint32_t reserved11; /* _reserved_11, 0xFC */ + uint32_t clk_source_i2s2; /* _CLK_SOURCE_I2S2_0, 0x100 */ + uint32_t clk_source_i2s3; /* _CLK_SOURCE_I2S3_0, 0x104 */ + uint32_t clk_source_spdif_out; /* _CLK_SOURCE_SPDIF_OUT_0, 0x108 */ + uint32_t clk_source_spdif_in; /* _CLK_SOURCE_SPDIF_IN_0, 0x10c */ + uint32_t clk_source_pwm; /* _CLK_SOURCE_PWM_0, 0x110 */ + uint32_t _0x114; + uint32_t clk_source_spi2; /* _CLK_SOURCE_SPI2_0, 0x118 */ + uint32_t clk_source_spi3; /* _CLK_SOURCE_SPI3_0, 0x11c */ + uint32_t _0x120; + uint32_t clk_source_i2c1; /* _CLK_SOURCE_I2C1_0, 0x124 */ + uint32_t clk_source_i2c5; /* _CLK_SOURCE_I2C5_0, 0x128 */ + uint32_t _0x12c[2]; + uint32_t clk_source_spi1; /* _CLK_SOURCE_SPI1_0, 0x134 */ + uint32_t clk_source_disp1; /* _CLK_SOURCE_DISP1_0, 0x138 */ + uint32_t clk_source_disp2; /* _CLK_SOURCE_DISP2_0, 0x13c */ + uint32_t _0x140; + uint32_t clk_source_isp; /* _CLK_SOURCE_ISP_0, 0x144 */ + uint32_t clk_source_vi; /* _CLK_SOURCE_VI_0, 0x148 */ + uint32_t _0x14c; + uint32_t clk_source_sdmmc1; /* _CLK_SOURCE_SDMMC1_0, 0x150 */ + uint32_t clk_source_sdmmc2; /* _CLK_SOURCE_SDMMC2_0, 0x154 */ + uint32_t _0x158[3]; + uint32_t clk_source_sdmmc4; /* _CLK_SOURCE_SDMMC4_0, 0x164 */ + uint32_t _0x168[4]; + uint32_t clk_source_uarta; /* _CLK_SOURCE_UARTA_0, 0x178 */ + uint32_t clk_source_uartb; /* _CLK_SOURCE_UARTB_0, 0x17c */ + uint32_t clk_source_host1x; /* _CLK_SOURCE_HOST1X_0, 0x180 */ + uint32_t _0x184[5]; + uint32_t clk_source_i2c2; /* _CLK_SOURCE_I2C2_0, 0x198 */ + uint32_t clk_source_emc; /* _CLK_SOURCE_EMC_0, 0x19c */ + uint32_t clk_source_uartc; /* _CLK_SOURCE_UARTC_0, 0x1a0 */ + uint32_t _0x1a4; + uint32_t clk_source_vi_sensor; /* _CLK_SOURCE_VI_SENSOR_0, 0x1a8 */ + uint32_t _0x1ac[2]; + uint32_t clk_source_spi4; /* _CLK_SOURCE_SPI4_0, 0x1b4 */ + uint32_t clk_source_i2c3; /* _CLK_SOURCE_I2C3_0, 0x1b8 */ + uint32_t clk_source_sdmmc3; /* _CLK_SOURCE_SDMMC3_0, 0x1bc */ + uint32_t clk_source_uartd; /* _CLK_SOURCE_UARTD_0, 0x1c0 */ + uint32_t _0x1c4[2]; + uint32_t clk_source_owr; /* _CLK_SOURCE_OWR_0, 0x1cc */ + uint32_t _0x1d0; + uint32_t clk_source_csite; /* _CLK_SOURCE_CSITE_0, 0x1d4 */ + uint32_t clk_source_i2s1; /* _CLK_SOURCE_I2S1_0, 0x1d8 */ + uint32_t clk_source_dtv; /* _CLK_SOURCE_DTV_0, 0x1dc */ + uint32_t _0x1e0[5]; + uint32_t clk_source_tsec; /* _CLK_SOURCE_TSEC_0, 0x1f4 */ + uint32_t _0x1f8; + + uint32_t clk_spare2; /* _CLK_SPARE2_0, 0x1fc */ + uint32_t _0x200[32]; - uint32_t clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ + uint32_t clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + uint32_t clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + uint32_t clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ - uint32_t reserved20[32]; /* _reserved_20, 0x200-27c */ + uint32_t rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ + uint32_t rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + uint32_t rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - uint32_t clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ - uint32_t clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ - uint32_t clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + uint32_t clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ + uint32_t clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */ + uint32_t clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */ - uint32_t rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ - uint32_t rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ - uint32_t rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + uint32_t rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */ + uint32_t rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */ + uint32_t rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */ - uint32_t clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ - uint32_t clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */ - uint32_t clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */ + uint32_t _0x2b0[17]; + uint32_t dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + uint32_t _0x2f8[2]; - uint32_t rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */ - uint32_t rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */ - uint32_t rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */ - - uint32_t reserved21[17]; /* _reserved_21, 0x2b0-2f0 */ - - uint32_t dfll_base; /* _DFLL_BASE_0, 0x2f4 */ - - uint32_t reserved22[2]; /* _reserved_22, 0x2f8-2fc */ - - /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ + /* _RST_DEV_L/H/U_SET_0 0x300-0x314 */ uint32_t rst_dev_l_set; uint32_t rst_dev_l_clr; uint32_t rst_dev_h_set; @@ -123,9 +204,9 @@ typedef struct { uint32_t rst_dev_u_set; uint32_t rst_dev_u_clr; - uint32_t reserved30[2]; /* _reserved_30, 0x318, 0x31c */ + uint32_t _0x318[2]; - /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */ + /* _CLK_ENB_L/H/U_CLR_0 0x320-0x334 */ uint32_t clk_enb_l_set; uint32_t clk_enb_l_clr; uint32_t clk_enb_h_set; @@ -133,136 +214,275 @@ typedef struct { uint32_t clk_enb_u_set; uint32_t clk_enb_u_clr; - uint32_t reserved31[2]; /* _reserved_31, 0x338, 0x33c */ - - uint32_t cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ - uint32_t cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ + uint32_t _0x338; + uint32_t ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD_0, 0x33c */ + uint32_t rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ + uint32_t rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ /* Additional (T30) registers */ - uint32_t clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ - uint32_t clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ + uint32_t clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ + uint32_t clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ - uint32_t reserved32[2]; /* _reserved_32, 0x350,0x354 */ + uint32_t _0x350[2]; + uint32_t rst_dev_v; /* _RST_DEVICES_V/W_0 */ + uint32_t rst_dev_w; /* _RST_DEVICES_V/W_0 */ + uint32_t clk_out_enb_v; /* _CLK_OUT_ENB_V/W_0 */ + uint32_t clk_out_enb_w; /* _CLK_OUT_ENB_V/W_0 */ + uint32_t cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ + uint32_t super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ + uint32_t cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ + uint32_t super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ + uint32_t clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ + uint32_t clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ + uint32_t cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ + uint32_t cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ + uint32_t cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ + uint32_t _0x38c[5]; + uint32_t lvl2_clk_gate_ovrc; /* _LVL2_CLK_GATE_OVRC, 0x3a0 */ + uint32_t lvl2_clk_gate_ovrd; /* _LVL2_CLK_GATE_OVRD, 0x3a4 */ + uint32_t _0x3a8[2]; + + uint32_t _0x3b0; + uint32_t clk_source_mselect; /* _CLK_SOURCE_MSELECT_0, 0x3b4 */ + uint32_t clk_source_tsensor; /* _CLK_SOURCE_TSENSOR_0, 0x3b8 */ + uint32_t clk_source_i2s4; /* _CLK_SOURCE_I2S4_0, 0x3bc */ + uint32_t clk_source_i2s5; /* _CLK_SOURCE_I2S5_0, 0x3c0 */ + uint32_t clk_source_i2c4; /* _CLK_SOURCE_I2C4_0, 0x3c4 */ + uint32_t _0x3c8[2]; + uint32_t clk_source_ahub; /* _CLK_SOURCE_AHUB_0, 0x3d0 */ + uint32_t _0x3d4[4]; + uint32_t clk_source_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X_0, 0x3e4 */ + uint32_t clk_source_actmon; /* _CLK_SOURCE_ACTMON_0, 0x3e8 */ + uint32_t clk_source_extperiph1; /* _CLK_SOURCE_EXTPERIPH1_0, 0x3ec */ + uint32_t clk_source_extperiph2; /* _CLK_SOURCE_EXTPERIPH2_0, 0x3f0 */ + uint32_t clk_source_extperiph3; /* _CLK_SOURCE_EXTPERIPH3_0, 0x3f4 */ + uint32_t _0x3f8; + uint32_t clk_source_i2c_slow; /* _CLK_SOURCE_I2C_SLOW_0, 0x3fc */ + uint32_t clk_source_sys; /* _CLK_SOURCE_SYS_0, 0x400 */ + uint32_t clk_source_ispb; /* _CLK_SOURCE_ISPB_0, 0x404 */ + uint32_t _0x408[2]; + uint32_t clk_source_sor1; /* _CLK_SOURCE_SOR1_0, 0x410 */ + uint32_t clk_source_sor0; /* _CLK_SOURCE_SOR0_0, 0x414 */ + uint32_t _0x418[2]; + uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */ + uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */ + uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */ + uint32_t _0x42c; - uint32_t rst_dev_v; /* _RST_DEVICES_V/W_0 */ - uint32_t rst_dev_w; /* _RST_DEVICES_V/W_0 */ - - uint32_t clk_out_enb_v; /* _CLK_OUT_ENB_V/W_0 */ - uint32_t clk_out_enb_w; /* _CLK_OUT_ENB_V/W_0 */ - uint32_t cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ - uint32_t super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ - uint32_t cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ - uint32_t super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ - uint32_t clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ - uint32_t clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ - uint32_t cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - uint32_t cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ - uint32_t cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ - uint32_t reserved33[9]; /* _reserved_33, 0x38c-3ac */ - uint32_t clk_src_v; /* 0x3B0-0x42C */ - uint32_t clk_src_w; /* 0x3B0-0x42C */ - - /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ + /* _RST_DEV_V/W_SET_0 0x430-0x43c */ uint32_t rst_dev_v_set; uint32_t rst_dev_v_clr; uint32_t rst_dev_w_set; uint32_t rst_dev_w_clr; - /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ - uint32_t rst_clk_v_set; - uint32_t rst_clk_v_clr; - uint32_t rst_clk_w_set; - uint32_t rst_clk_w_clr; + /* _CLK_ENB_V/W_CLR_0 0x440-0x44c */ + uint32_t clk_enb_v_set; + uint32_t clk_enb_v_clr; + uint32_t clk_enb_w_set; + uint32_t clk_enb_w_clr; /* Additional (T114+) registers */ - uint32_t rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ - uint32_t rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ - uint32_t rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ - uint32_t rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */ - uint32_t clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ - uint32_t clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ - uint32_t clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ - uint32_t clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */ - uint32_t cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ - uint32_t reserved40[1]; /* _reserved_40, 0x474 */ - uint32_t intstatus; /* __INTSTATUS_0, 0x478 */ - uint32_t intmask; /* __INTMASK_0, 0x47C */ - uint32_t utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ - uint32_t utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ - uint32_t utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ + uint32_t rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ + uint32_t rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ + uint32_t rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ + uint32_t rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45c */ + uint32_t clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ + uint32_t clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ + uint32_t clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ + uint32_t clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46c */ + uint32_t cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ + uint32_t _0x474; + uint32_t intstatus; /* _INTSTATUS_0, 0x478 */ + uint32_t intmask; /* _INTMASK_0, 0x47c */ + uint32_t utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ + uint32_t utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ + uint32_t utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ - uint32_t plle_aux; /* _PLLE_AUX_0, 0x48C */ - uint32_t sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ - uint32_t sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ - uint32_t pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ + uint32_t plle_aux; /* _PLLE_AUX_0, 0x48c */ + uint32_t sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ + uint32_t sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ + uint32_t pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ - uint32_t prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */ - uint32_t audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */ - uint32_t audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */ - uint32_t audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */ - uint32_t audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ - uint32_t audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ - uint32_t audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ + uint32_t prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49c */ + uint32_t audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4a0 */ + uint32_t audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4a4 */ + uint32_t audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4a8 */ + uint32_t audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4ac */ + uint32_t audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4b0 */ + uint32_t audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4b4 */ - uint32_t plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ - uint32_t plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ - uint32_t utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ - uint32_t pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ - uint32_t pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ - uint32_t crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ - uint32_t pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ - uint32_t pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ - uint32_t pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ - uint32_t pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ - uint32_t pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ - uint32_t pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ + uint32_t plld2_base; /* _PLLD2_BASE_0, 0x4b8 */ + uint32_t plld2_misc; /* _PLLD2_MISC_0, 0x4bc */ + uint32_t utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4c0 */ + uint32_t pllrefe_base; /* _PLLREFE_BASE_0, 0x4c4 */ + uint32_t pllrefe_misc; /* _PLLREFE_MISC_0, 0x4c8 */ + uint32_t pllrefe_out; /* _PLLREFE_OUT_0, 0x4cc */ + uint32_t cpu_finetrim_byp; /* _CPU_FINETRIM_BYP_0, 0x4d0 */ + uint32_t cpu_finetrim_select; /* _CPU_FINETRIM_SELECT_0, 0x4d4 */ + uint32_t cpu_finetrim_dr; /* _CPU_FINETRIM_DR_0, 0x4d8 */ + uint32_t cpu_finetrim_df; /* _CPU_FINETRIM_DF_0, 0x4dc */ + uint32_t cpu_finetrim_f; /* _CPU_FINETRIM_F_0, 0x4e0 */ + uint32_t cpu_finetrim_r; /* _CPU_FINETRIM_R_0, 0x4e4 */ + uint32_t pllc2_base; /* _PLLC2_BASE_0, 0x4e8 */ + uint32_t pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4ec */ + uint32_t pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4f0 */ + uint32_t pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4f4 */ + uint32_t pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4f8 */ + uint32_t pllc3_base; /* _PLLC3_BASE_0, 0x4fc */ uint32_t pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ uint32_t pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ uint32_t pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ - uint32_t pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ + uint32_t pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50c */ uint32_t pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ uint32_t pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ uint32_t pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ - uint32_t xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ + uint32_t xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51c */ uint32_t xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ uint32_t plle_aux1; /* _PLLE_AUX1_0, 0x524 */ uint32_t pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ - uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ + uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52c */ uint32_t pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ uint32_t xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ - uint32_t reserved51[1]; /* _reserved_51, 0x538 */ - uint32_t clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ + uint32_t _0x538; + uint32_t clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53c */ uint32_t clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ uint32_t clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ uint32_t pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ - uint32_t pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ + uint32_t pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54c */ uint32_t pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ - uint32_t reserved52[1]; /* _reserved_52, 0x554 */ + uint32_t lvl2_clk_gate_ovre; /* _LVL2_CLK_GATE_OVRE, 0x554 */ uint32_t super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ - uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55C */ - uint32_t _rsv32[4]; /* 0x560-0x56c */ - uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ - uint32_t _rsv32_1[7]; /* 0x574-58c */ - clk_pll_simple_t plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */ - uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ - - /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */ - uint32_t _rsrv32_2[25]; /* _0x59C - 0x5FC */ - uint32_t clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */ - - /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */ - uint32_t reserved61[5]; /* _reserved_61, 0x680 - 0x690 */ + uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55c */ + uint32_t audio_sync_clk_dmic1; /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */ + uint32_t audio_sync_clk_dmic2; /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */ - /* - * NOTE: PLLA1 regs are in the middle of this Y region. Break this in - * two later if PLLA1 is needed, but for now this is cleaner. - */ - uint32_t clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */ + uint32_t _0x568[2]; + uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG, 0x570 */ + uint32_t plld2_ss_ctrl1; /* _PLLD2_SS_CTRL1_0, 0x574 */ + uint32_t plld2_ss_ctrl2; /* _PLLD2_SS_CTRL2_0, 0x578 */ + uint32_t _0x57c[5]; + + uint32_t plldp_base; /* _PLLDP_BASE, 0x590*/ + uint32_t plldp_misc; /* _PLLDP_MISC, 0x594 */ + uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ + uint32_t plldp_ss_ctrl1; /* _PLLDP_SS_CTRL1_0, 0x59c */ + uint32_t plldp_ss_ctrl2; /* _PLLDP_SS_CTRL2_0, 0x5a0 */ + uint32_t pllc4_base; /* _PLLC4_BASE_0, 0x5a4 */ + uint32_t pllc4_misc; /* _PLLC4_MISC_0, 0x5a8 */ + uint32_t _0x5ac[6]; + uint32_t clk_spare0; /* _CLK_SPARE0_0, 0x5c4 */ + uint32_t clk_spare1; /* _CLK_SPARE1_0, 0x5c8 */ + uint32_t gpu_isob_ctrl; /* _GPU_ISOB_CTRL_0, 0x5cc */ + uint32_t pllc_misc2; /* _PLLC_MISC_2_0, 0x5d0 */ + uint32_t pllc_misc3; /* _PLLC_MISC_3_0, 0x5d4 */ + uint32_t plla_misc2; /* _PLLA_MISC2_0, 0x5d8 */ + uint32_t _0x5dc[2]; + uint32_t pllc4_out; /* _PLLC4_OUT_0, 0x5e4 */ + uint32_t pllmb_base; /* _PLLMB_BASE_0, 0x5e8 */ + uint32_t pllmb_misc1; /* _PLLMB_MISC1_0, 0x5ec */ + uint32_t pllx_misc4; /* _PLLX_MISC_4_0, 0x5f0 */ + uint32_t pllx_misc5; /* _PLLX_MISC_5_0, 0x5f4 */ + uint32_t _0x5f8[2]; + + uint32_t clk_source_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST_0, 0x600 */ + uint32_t clk_source_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON_0, 0x604 */ + uint32_t clk_source_xusb_fs; /* _CLK_SOURCE_XUSB_FS_0, 0x608 */ + uint32_t clk_source_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV_0, 0x60c */ + uint32_t clk_source_xusb_ss; /* _CLK_SOURCE_XUSB_SS_0, 0x610 */ + uint32_t clk_source_cilab; /* _CLK_SOURCE_CILAB_0, 0x614 */ + uint32_t clk_source_cilcd; /* _CLK_SOURCE_CILCD_0, 0x618 */ + uint32_t clk_source_cilef; /* _CLK_SOURCE_CILEF_0, 0x61c */ + uint32_t clk_source_dsia_lp; /* _CLK_SOURCE_DSIA_LP_0, 0x620 */ + uint32_t clk_source_dsib_lp; /* _CLK_SOURCE_DSIB_LP_0, 0x624 */ + uint32_t clk_source_entropy; /* _CLK_SOURCE_ENTROPY_0, 0x628 */ + uint32_t clk_source_dvfs_ref; /* _CLK_SOURCE_DVFS_REF_0, 0x62c */ + uint32_t clk_source_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC_0, 0x630 */ + uint32_t _0x634[3]; + uint32_t clk_source_emc_latency; /* _CLK_SOURCE_EMC_LATENCY_0, 0x640 */ + uint32_t clk_source_soc_therm; /* _CLK_SOURCE_SOC_THERM_0, 0x644 */ + uint32_t _0x648; + uint32_t clk_source_dmic1; /* _CLK_SOURCE_DMIC1_0, 0x64c */ + uint32_t clk_source_dmic2; /* _CLK_SOURCE_DMIC2_0, 0x650 */ + uint32_t _0x654; + uint32_t clk_source_vi_sensor2; /* _CLK_SOURCE_VI_SENSOR2_0, 0x658 */ + uint32_t clk_source_i2c6; /* _CLK_SOURCE_I2C6_0, 0x65c */ + uint32_t clk_source_mipibif; /* _CLK_SOURCE_MIPIBIF_0, 0x660 */ + uint32_t clk_source_emc_dll; /* _CLK_SOURCE_EMC_DLL_0, 0x664 */ + uint32_t _0x668; + uint32_t clk_source_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIPI_CAL_0, 0x66c */ + uint32_t _0x670[2]; + uint32_t clk_source_vic; /* _CLK_SOURCE_VIC_0, 0x678 */ + + uint32_t pllp_outc; /* _PLLP_OUTC_0, 0x67c */ + uint32_t pllp_misc1; /* _PLLP_MISC1_0, 0x680 */ + uint32_t _0x684[2]; + uint32_t emc_div_clk_shaper_ctrl; /* _EMC_DIV_CLK_SHAPER_CTRL_0, 0x68c */ + uint32_t emc_pllc_shaper_ctrl; /* _EMC_PLLC_SHAPER_CTRL_0, 0x690 */ + + uint32_t clk_source_sdmmc_legacy_tm; /* _CLK_SOURCE_SDMMC_LEGACY_TM_0, 0x694 */ + uint32_t clk_source_nvdec; /* _CLK_SOURCE_NVDEC_0, 0x698 */ + uint32_t clk_source_nvjpg; /* _CLK_SOURCE_NVJPG_0, 0x69c */ + uint32_t clk_source_nvenc; /* _CLK_SOURCE_NVENC_0, 0x6a0 */ + + uint32_t plla1_base; /* _PLLA1_BASE_0, 0x6a4 */ + uint32_t plla1_misc0; /* _PLLA1_MISC_0_0, 0x6a8 */ + uint32_t plla1_misc1; /* _PLLA1_MISC_1_0, 0x6ac */ + uint32_t plla1_misc2; /* _PLLA1_MISC_2_0, 0x6b0 */ + uint32_t plla1_misc3; /* _PLLA1_MISC_3_0, 0x6b4 */ + uint32_t audio_sync_clk_dmic3; /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */ + + uint32_t clk_source_dmic3; /* _CLK_SOURCE_DMIC3_0, 0x6bc */ + uint32_t clk_source_ape; /* _CLK_SOURCE_APE_0, 0x6c0 */ + uint32_t clk_source_qspi; /* _CLK_SOURCE_QSPI_0, 0x6c4 */ + uint32_t clk_source_vi_i2c; /* _CLK_SOURCE_VI_I2C_0, 0x6c8 */ + uint32_t clk_source_usb2_hsic_trk; /* _CLK_SOURCE_USB2_HSIC_TRK_0, 0x6cc */ + uint32_t clk_source_pex_sata_usb_rx_byp; /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0, 0x6d0 */ + uint32_t clk_source_maud; /* _CLK_SOURCE_MAUD_0, 0x6d4 */ + uint32_t clk_source_tsecb; /* _CLK_SOURCE_TSECB_0, 0x6d8 */ + + uint32_t clk_cpug_misc1; /* _CLK_CPUG_MISC1_0, 0x6dc */ + uint32_t aclk_burst_policy; /* _ACLK_BURST_POLICY_0, 0x6e0 */ + uint32_t super_aclk_divider; /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */ + + uint32_t nvenc_super_clk_divider; /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */ + uint32_t vi_super_clk_divider; /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */ + uint32_t vic_super_clk_divider; /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */ + uint32_t nvdec_super_clk_divider; /* _NVDEC_SUPER_CLK_DIVIDER_0, 0x6f4 */ + uint32_t isp_super_clk_divider; /* _ISP_SUPER_CLK_DIVIDER_0, 0x6f8 */ + uint32_t ispb_super_clk_divider; /* _ISPB_SUPER_CLK_DIVIDER_0, 0x6fc */ + uint32_t nvjpg_super_clk_divider; /* _NVJPG_SUPER_CLK_DIVIDER_0, 0x700 */ + uint32_t se_super_clk_divider; /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */ + uint32_t tsec_super_clk_divider; /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */ + uint32_t tsecb_super_clk_divider; /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */ + + uint32_t clk_source_uartape; /* _CLK_SOURCE_UARTAPE_0, 0x710 */ + uint32_t clk_source_dbgapb; /* _CLK_SOURCE_DBGAPB_0, 0x718 */ + uint32_t clk_ccplex_cc4_ret_clk_enb; /* _CLK_CCPLEX_CC4_RET_CLK_ENB_0, 0x71c */ + uint32_t actmon_cpu_clk; /* _ACTMON_CPU_CLK_0, 0x720 */ + uint32_t clk_source_emc_safe; /* _CLK_SOURCE_EMC_SAFE_0, 0x724 */ + uint32_t sdmmc2_pllc4_out0_shaper_ctrl; /* _SDMMC2_PLLC4_OUT0_SHAPER_CTRL_0, 0x728 */ + uint32_t sdmmc2_pllc4_out1_shaper_ctrl; /* _SDMMC2_PLLC4_OUT1_SHAPER_CTRL_0, 0x72c */ + uint32_t sdmmc2_pllc4_out2_shaper_ctrl; /* _SDMMC2_PLLC4_OUT2_SHAPER_CTRL_0, 0x730 */ + uint32_t sdmmc2_div_clk_shaper_ctrl; /* _SDMMC2_DIV_CLK_SHAPER_CTRL_0, 0x734 */ + uint32_t sdmmc4_pllc4_out0_shaper_ctrl; /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */ + uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */ + uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */ + uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */ } tegra_car_t; -static inline volatile tegra_car_t *car_get_regs(void) -{ - return (volatile tegra_car_t *)0x60006000; +static inline volatile tegra_car_t *car_get_regs(void) { + return (volatile tegra_car_t *)CAR_BASE; } +void clk_enable(CarDevice dev); +void clk_disable(CarDevice dev); +void rst_enable(CarDevice dev); +void rst_disable(CarDevice dev); + +void clkrst_enable(CarDevice dev); +void clkrst_disable(CarDevice dev); +void clkrst_reboot(CarDevice dev); + +void clkrst_enable_fuse_regs(bool enable); + #endif diff --git a/fusee/fusee-primary/src/di.c b/fusee/fusee-primary/src/di.c new file mode 100644 index 000000000..e22257465 --- /dev/null +++ b/fusee/fusee-primary/src/di.c @@ -0,0 +1,255 @@ +#include + +#include "di.h" +#include "timers.h" +#include "i2c.h" +#include "pmc.h" +#include "max77620.h" +#include "gpio.h" +#include "pinmux.h" +#include "car.h" + +#include "di.inl" + +static uint32_t _display_ver = 0; + +static void exec_cfg(uint32_t *base, const cfg_op_t *ops, uint32_t num_ops) +{ + for (uint32_t i = 0; i < num_ops; i++) + base[ops[i].off] = ops[i].val; +} + +static void _display_dsi_wait(uint32_t timeout, uint32_t off, uint32_t mask) +{ + uint32_t end = get_time_us() + timeout; + while ((get_time_us() < end) && (MAKE_DSI_REG(off) & mask)) { + /* Wait. */ + } + udelay(5); +} + +void display_init() +{ + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pmc_t *pmc = pmc_get_regs(); + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + /* Power on. */ + uint8_t val = 0xD0; + i2c_send(4, 0x3C, MAX77620_REG_LDO0_CFG, &val, 1); + val = 0x09; + i2c_send(4, 0x3C, MAX77620_REG_GPIO7, &val, 1); + + /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */ + car->rst_dev_h_clr = 0x1010000; + car->clk_enb_h_set = 0x1010000; + car->rst_dev_l_clr = 0x18000000; + car->clk_enb_l_set = 0x18000000; + car->clk_enb_x_set = 0x20000; + car->clk_source_uart_fst_mipi_cal = 0xA; + car->clk_enb_w_set = 0x80000; + car->clk_source_dsia_lp = 0xA; + + /* DPD idle. */ + pmc->io_dpd_req = 0x40000000; + pmc->io_dpd2_req = 0x40000000; + + /* Configure pins. */ + pinmux->nfc_en &= ~PINMUX_TRISTATE; + pinmux->nfc_int &= ~PINMUX_TRISTATE; + pinmux->lcd_bl_pwm &= ~PINMUX_TRISTATE; + pinmux->lcd_bl_en &= ~PINMUX_TRISTATE; + pinmux->lcd_rst &= ~PINMUX_TRISTATE; + + /* Configure Backlight +-5V GPIOs. */ + gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT); + + /* Enable Backlight +5V. */ + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); + + udelay(10000u); + + /* Enable Backlight -5V. */ + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); + + udelay(10000); + + /* Configure Backlight PWM, EN and RST GPIOs. */ + gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT); + + /* Enable Backlight EN. */ + gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH); + + /* Configure display interface and display. */ + MAKE_MIPI_CAL_REG(0x60) = 0; + + exec_cfg((uint32_t *)CAR_BASE, _display_config_1, 4); + exec_cfg((uint32_t *)DI_BASE, _display_config_2, 94); + exec_cfg((uint32_t *)DSI_BASE, _display_config_3, 60); + + udelay(10000); + + /* Enable Backlight RST. */ + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH); + + udelay(60000); + + MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204; + MAKE_DSI_REG(DSI_WR_DATA) = 0x337; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + _display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO)); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x406; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + _display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO)); + + MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC); + _display_dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA); + + udelay(5000); + + _display_ver = MAKE_DSI_REG(DSI_RD_DATA); + + if (_display_ver == 0x10) + exec_cfg((uint32_t *)DSI_BASE, _display_config_4, 43); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x1105; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + + udelay(180000); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x2905; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + + udelay(20000); + + exec_cfg((uint32_t *)DSI_BASE, _display_config_5, 21); + exec_cfg((uint32_t *)CAR_BASE, _display_config_6, 3); + + MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4; + exec_cfg((uint32_t *)DSI_BASE, _display_config_7, 10); + + udelay(10000); + + exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_8, 6); + exec_cfg((uint32_t *)DSI_BASE, _display_config_9, 4); + exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_10, 16); + + udelay(10000); + + exec_cfg((uint32_t *)DI_BASE, _display_config_11, 113); +} + +void display_backlight(bool enable) +{ + /* Enable Backlight PWM. */ + gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); +} + +void display_end() +{ + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + /* Disable Backlight. */ + display_backlight(false); + + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; + MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; + + uint32_t host1x_delay = MAKE_HOST1X_REG(0x30A4) + 5; + while (MAKE_HOST1X_REG(0x30A4) < host1x_delay) { + /* Wait. */ + } + + MAKE_DI_REG(DC_CMD_STATE_ACCESS) = 5; + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; + + exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17); + exec_cfg((uint32_t *)DSI_BASE, _display_config_13, 16); + + udelay(10000); + + if (_display_ver == 0x10) + exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; + MAKE_DSI_REG(DSI_TRIGGER) = 2; + + udelay(50000); + + /* Disable Backlight RST. */ + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable Backlight -5V. */ + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable Backlight +5V. */ + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable clocks. */ + car->rst_dev_h_set = 0x1010000; + car->clk_enb_h_clr = 0x1010000; + car->rst_dev_l_set = 0x18000000; + car->clk_enb_l_clr = 0x18000000; + + MAKE_DSI_REG(DSI_PAD_CONTROL_0) = 0x10F010F; + MAKE_DSI_REG(DSI_POWER_CONTROL) = 0; + + /* Backlight PWM. */ + gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO); + + pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE); + pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1); +} + +void display_color_screen(uint32_t color) +{ + exec_cfg((uint32_t *)DI_BASE, cfg_display_one_color, 8); + + /* Configure display to show single color. */ + MAKE_DI_REG(DC_WIN_AD_WIN_OPTIONS) = 0; + MAKE_DI_REG(DC_WIN_BD_WIN_OPTIONS) = 0; + MAKE_DI_REG(DC_WIN_CD_WIN_OPTIONS) = 0; + MAKE_DI_REG(DC_DISP_BLEND_BACKGROUND_COLOR) = color; + MAKE_DI_REG(DC_CMD_STATE_CONTROL) = ((MAKE_DI_REG(DC_CMD_STATE_CONTROL) & 0xFFFFFFFE) | GENERAL_ACT_REQ); + + udelay(35000); + + display_backlight(true); +} + +uint32_t *display_init_framebuffer(void *address) +{ + static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0}; + if(conf[0].val == 0) { + for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) { + conf[i] = cfg_display_framebuffer[i]; + } + } + + uint32_t *lfb_addr = (uint32_t *)address; + + conf[19].val = (uint32_t)address; + + //This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). + exec_cfg((uint32_t *)DI_BASE, conf, 32); + + udelay(35000); + + return lfb_addr; +} diff --git a/fusee/fusee-primary/src/di.h b/fusee/fusee-primary/src/di.h new file mode 100644 index 000000000..bca4b569a --- /dev/null +++ b/fusee/fusee-primary/src/di.h @@ -0,0 +1,350 @@ +#ifndef FUSEE_DI_H_ +#define FUSEE_DI_H_ + +#include +#include + +#define HOST1X_BASE 0x50000000 +#define DI_BASE 0x54200000 +#define DSI_BASE 0x54300000 +#define VIC_BASE 0x54340000 +#define MIPI_CAL_BASE 0x700E3000 +#define MAKE_HOST1X_REG(n) MAKE_REG32(HOST1X_BASE + n) +#define MAKE_DI_REG(n) MAKE_REG32(DI_BASE + n * 4) +#define MAKE_DSI_REG(n) MAKE_REG32(DSI_BASE + n * 4) +#define MAKE_MIPI_CAL_REG(n) MAKE_REG32(MIPI_CAL_BASE + n) +#define MAKE_VIC_REG(n) MAKE_REG32(VIC_BASE + n) + +/* Display registers. */ +#define DC_CMD_GENERAL_INCR_SYNCPT 0x00 + +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01 +#define SYNCPT_CNTRL_NO_STALL (1 << 8) +#define SYNCPT_CNTRL_SOFT_RESET (1 << 0) + +#define DC_CMD_CONT_SYNCPT_VSYNC 0x28 +#define SYNCPT_VSYNC_ENABLE (1 << 8) + +#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 + +#define DC_CMD_DISPLAY_COMMAND 0x32 +#define DISP_CTRL_MODE_STOP (0 << 5) +#define DISP_CTRL_MODE_C_DISPLAY (1 << 5) +#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) +#define DISP_CTRL_MODE_MASK (3 << 5) + +#define DC_CMD_DISPLAY_POWER_CONTROL 0x36 +#define PW0_ENABLE (1 << 0) +#define PW1_ENABLE (1 << 2) +#define PW2_ENABLE (1 << 4) +#define PW3_ENABLE (1 << 6) +#define PW4_ENABLE (1 << 8) +#define PM0_ENABLE (1 << 16) +#define PM1_ENABLE (1 << 18) + +#define DC_CMD_INT_MASK 0x38 +#define DC_CMD_INT_ENABLE 0x39 + +#define DC_CMD_STATE_ACCESS 0x40 +#define READ_MUX (1 << 0) +#define WRITE_MUX (1 << 2) + +#define DC_CMD_STATE_CONTROL 0x41 +#define GENERAL_ACT_REQ (1 << 0) +#define WIN_A_ACT_REQ (1 << 1) +#define WIN_B_ACT_REQ (1 << 2) +#define WIN_C_ACT_REQ (1 << 3) +#define CURSOR_ACT_REQ (1 << 7) +#define GENERAL_UPDATE (1 << 8) +#define WIN_A_UPDATE (1 << 9) +#define WIN_B_UPDATE (1 << 10) +#define WIN_C_UPDATE (1 << 11) +#define CURSOR_UPDATE (1 << 15) +#define NC_HOST_TRIG (1 << 24) + +#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42 +#define WINDOW_A_SELECT (1 << 4) +#define WINDOW_B_SELECT (1 << 5) +#define WINDOW_C_SELECT (1 << 6) + +#define DC_CMD_REG_ACT_CONTROL 0x043 + +#define DC_COM_CRC_CONTROL 0x300 +#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) +#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) + +#define DC_COM_DSC_TOP_CTL 0x33E + +#define DC_DISP_DISP_WIN_OPTIONS 0x402 +#define HDMI_ENABLE (1 << 30) +#define DSI_ENABLE (1 << 29) +#define SOR1_TIMING_CYA (1 << 27) +#define SOR1_ENABLE (1 << 26) +#define SOR_ENABLE (1 << 25) +#define CURSOR_ENABLE (1 << 16) + +#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 +#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 +#define DC_DISP_DISP_TIMING_OPTIONS 0x405 +#define DC_DISP_REF_TO_SYNC 0x406 +#define DC_DISP_SYNC_WIDTH 0x407 +#define DC_DISP_BACK_PORCH 0x408 +#define DC_DISP_ACTIVE 0x409 +#define DC_DISP_FRONT_PORCH 0x40A + +#define DC_DISP_DISP_CLOCK_CONTROL 0x42E +#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) +#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) +#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) +#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) +#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) +#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) +#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) +#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) +#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) +#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) +#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) +#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) +#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) +#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) + +#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F +#define DISP_DATA_FORMAT_DF1P1C (0 << 0) +#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) +#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) +#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) +#define DISP_DATA_FORMAT_DF2S (4 << 0) +#define DISP_DATA_FORMAT_DF3S (5 << 0) +#define DISP_DATA_FORMAT_DFSPI (6 << 0) +#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) +#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) +#define DISP_ALIGNMENT_MSB (0 << 8) +#define DISP_ALIGNMENT_LSB (1 << 8) +#define DISP_ORDER_RED_BLUE (0 << 9) +#define DISP_ORDER_BLUE_RED (1 << 9) + +#define DC_DISP_DISP_COLOR_CONTROL 0x430 +#define DITHER_CONTROL_MASK (3 << 8) +#define DITHER_CONTROL_DISABLE (0 << 8) +#define DITHER_CONTROL_ORDERED (2 << 8) +#define DITHER_CONTROL_ERRDIFF (3 << 8) +#define BASE_COLOR_SIZE_MASK (0xf << 0) +#define BASE_COLOR_SIZE_666 (0 << 0) +#define BASE_COLOR_SIZE_111 (1 << 0) +#define BASE_COLOR_SIZE_222 (2 << 0) +#define BASE_COLOR_SIZE_333 (3 << 0) +#define BASE_COLOR_SIZE_444 (4 << 0) +#define BASE_COLOR_SIZE_555 (5 << 0) +#define BASE_COLOR_SIZE_565 (6 << 0) +#define BASE_COLOR_SIZE_332 (7 << 0) +#define BASE_COLOR_SIZE_888 (8 << 0) + +#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 +#define SC1_H_QUALIFIER_NONE (1 << 16) +#define SC0_H_QUALIFIER_NONE (1 << 0) + +#define DC_DISP_DATA_ENABLE_OPTIONS 0x432 +#define DE_SELECT_ACTIVE_BLANK (0 << 0) +#define DE_SELECT_ACTIVE (1 << 0) +#define DE_SELECT_ACTIVE_IS (2 << 0) +#define DE_CONTROL_ONECLK (0 << 2) +#define DE_CONTROL_NORMAL (1 << 2) +#define DE_CONTROL_EARLY_EXT (2 << 2) +#define DE_CONTROL_EARLY (3 << 2) +#define DE_CONTROL_ACTIVE_BLANK (4 << 2) + +#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 +#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4 + +#define DC_WIN_CSC_YOF 0x611 +#define DC_WIN_CSC_KYRGB 0x612 +#define DC_WIN_CSC_KUR 0x613 +#define DC_WIN_CSC_KVR 0x614 +#define DC_WIN_CSC_KUG 0x615 +#define DC_WIN_CSC_KVG 0x616 +#define DC_WIN_CSC_KUB 0x617 +#define DC_WIN_CSC_KVB 0x618 +#define DC_WIN_AD_WIN_OPTIONS 0xB80 +#define DC_WIN_BD_WIN_OPTIONS 0xD80 +#define DC_WIN_CD_WIN_OPTIONS 0xF80 + +/* The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER). */ +#define DC_WIN_WIN_OPTIONS 0x700 +#define H_DIRECTION (1 << 0) +#define V_DIRECTION (1 << 2) +#define COLOR_EXPAND (1 << 6) +#define CSC_ENABLE (1 << 18) +#define WIN_ENABLE (1 << 30) + +#define DC_WIN_COLOR_DEPTH 0x703 +#define WIN_COLOR_DEPTH_P1 0x0 +#define WIN_COLOR_DEPTH_P2 0x1 +#define WIN_COLOR_DEPTH_P4 0x2 +#define WIN_COLOR_DEPTH_P8 0x3 +#define WIN_COLOR_DEPTH_B4G4R4A4 0x4 +#define WIN_COLOR_DEPTH_B5G5R5A 0x5 +#define WIN_COLOR_DEPTH_B5G6R5 0x6 +#define WIN_COLOR_DEPTH_AB5G5R5 0x7 +#define WIN_COLOR_DEPTH_B8G8R8A8 0xC +#define WIN_COLOR_DEPTH_R8G8B8A8 0xD +#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE +#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF +#define WIN_COLOR_DEPTH_YCbCr422 0x10 +#define WIN_COLOR_DEPTH_YUV422 0x11 +#define WIN_COLOR_DEPTH_YCbCr420P 0x12 +#define WIN_COLOR_DEPTH_YUV420P 0x13 +#define WIN_COLOR_DEPTH_YCbCr422P 0x14 +#define WIN_COLOR_DEPTH_YUV422P 0x15 +#define WIN_COLOR_DEPTH_YCbCr422R 0x16 +#define WIN_COLOR_DEPTH_YUV422R 0x17 +#define WIN_COLOR_DEPTH_YCbCr422RA 0x18 +#define WIN_COLOR_DEPTH_YUV422RA 0x19 + +#define DC_WIN_BUFFER_CONTROL 0x702 +#define DC_WIN_POSITION 0x704 + +#define DC_WIN_SIZE 0x705 +#define H_SIZE(x) (((x) & 0x1fff) << 0) +#define V_SIZE(x) (((x) & 0x1fff) << 16) + +#define DC_WIN_PRESCALED_SIZE 0x706 +#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) +#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) + +#define DC_WIN_H_INITIAL_DDA 0x707 +#define DC_WIN_V_INITIAL_DDA 0x708 + +#define DC_WIN_DDA_INC 0x709 +#define H_DDA_INC(x) (((x) & 0xffff) << 0) +#define V_DDA_INC(x) (((x) & 0xffff) << 16) + +#define DC_WIN_LINE_STRIDE 0x70A +#define DC_WIN_DV_CONTROL 0x70E + +/* The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */ +#define DC_WINBUF_START_ADDR 0x800 +#define DC_WINBUF_ADDR_H_OFFSET 0x806 +#define DC_WINBUF_ADDR_V_OFFSET 0x808 +#define DC_WINBUF_SURFACE_KIND 0x80B + +/* Display serial interface registers. */ +#define DSI_RD_DATA 0x9 +#define DSI_WR_DATA 0xA + +#define DSI_POWER_CONTROL 0xB +#define DSI_POWER_CONTROL_ENABLE 1 + +#define DSI_INT_ENABLE 0xC +#define DSI_INT_STATUS 0xD +#define DSI_INT_MASK 0xE + +#define DSI_HOST_CONTROL 0xF +#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21) +#define DSI_HOST_CONTROL_CRC_RESET (1 << 20) +#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12) +#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12) +#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12) +#define DSI_HOST_CONTROL_RAW (1 << 6) +#define DSI_HOST_CONTROL_HS (1 << 5) +#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4) +#define DSI_HOST_CONTROL_IMM_BTA (1 << 3) +#define DSI_HOST_CONTROL_PKT_BTA (1 << 2) +#define DSI_HOST_CONTROL_CS (1 << 1) +#define DSI_HOST_CONTROL_ECC (1 << 0) + +#define DSI_CONTROL 0x10 +#define DSI_CONTROL_HS_CLK_CTRL (1 << 20) +#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16) +#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12) +#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8) +#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4) +#define DSI_CONTROL_DCS_ENABLE (1 << 3) +#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2) +#define DSI_CONTROL_VIDEO_ENABLE (1 << 1) +#define DSI_CONTROL_HOST_ENABLE (1 << 0) + +#define DSI_SOL_DELAY 0x11 +#define DSI_MAX_THRESHOLD 0x12 + +#define DSI_TRIGGER 0x13 +#define DSI_TRIGGER_HOST (1 << 1) +#define DSI_TRIGGER_VIDEO (1 << 0) + +#define DSI_TX_CRC 0x14 +#define DSI_STATUS 0x15 +#define DSI_INIT_SEQ_CONTROL 0x1A +#define DSI_INIT_SEQ_DATA_0 0x1B +#define DSI_INIT_SEQ_DATA_1 0x1C +#define DSI_INIT_SEQ_DATA_2 0x1D +#define DSI_INIT_SEQ_DATA_3 0x1E +#define DSI_PKT_SEQ_0_LO 0x23 +#define DSI_PKT_SEQ_0_HI 0x24 +#define DSI_PKT_SEQ_1_LO 0x25 +#define DSI_PKT_SEQ_1_HI 0x26 +#define DSI_PKT_SEQ_2_LO 0x27 +#define DSI_PKT_SEQ_2_HI 0x28 +#define DSI_PKT_SEQ_3_LO 0x29 +#define DSI_PKT_SEQ_3_HI 0x2A +#define DSI_PKT_SEQ_4_LO 0x2B +#define DSI_PKT_SEQ_4_HI 0x2C +#define DSI_PKT_SEQ_5_LO 0x2D +#define DSI_PKT_SEQ_5_HI 0x2E +#define DSI_DCS_CMDS 0x33 +#define DSI_PKT_LEN_0_1 0x34 +#define DSI_PKT_LEN_2_3 0x35 +#define DSI_PKT_LEN_4_5 0x36 +#define DSI_PKT_LEN_6_7 0x37 +#define DSI_PHY_TIMING_0 0x3C +#define DSI_PHY_TIMING_1 0x3D +#define DSI_PHY_TIMING_2 0x3E +#define DSI_BTA_TIMING 0x3F + +#define DSI_TIMEOUT_0 0x44 +#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) +#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) + +#define DSI_TIMEOUT_1 0x45 +#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) +#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) + +#define DSI_TO_TALLY 0x46 + +#define DSI_PAD_CONTROL_0 0x4B +#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24) +#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) +#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) +#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) + +#define DSI_PAD_CONTROL_CD 0x4c +#define DSI_VIDEO_MODE_CONTROL 0x4E + +#define DSI_PAD_CONTROL_1 0x4F +#define DSI_PAD_CONTROL_2 0x50 + +#define DSI_PAD_CONTROL_3 0x51 +#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12) +#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8) +#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4) +#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) + +#define DSI_PAD_CONTROL_4 0x52 + +typedef struct _cfg_op_t +{ + uint32_t off; + uint32_t val; +} cfg_op_t; + +void display_init(); +void display_end(); + +/* Show one single color on the display. */ +void display_color_screen(uint32_t color); + +/* Switches screen backlight ON/OFF. */ +void display_backlight(bool enable); + +/* Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */ +uint32_t *display_init_framebuffer(void *address); + +#endif diff --git a/fusee/fusee-primary/src/di.inl b/fusee/fusee-primary/src/di.inl new file mode 100644 index 000000000..c34fb4cf2 --- /dev/null +++ b/fusee/fusee-primary/src/di.inl @@ -0,0 +1,546 @@ +//Clock config. +static const cfg_op_t _display_config_1[4] = { + {0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 + {0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE + {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 + {0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC +}; + +//Display A config. +static const cfg_op_t _display_config_2[94] = { + {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_REG_ACT_CONTROL, 0x54}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_DISP_DC_MCCIF_FIFOCTRL, 0}, + {DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, + {DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, + {DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, + {DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, + {DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {0x4E4, 0}, + {DC_COM_CRC_CONTROL, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_COMMAND, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ} +}; + +//DSI Init config. +static const cfg_op_t _display_config_3[60] = { + {DSI_WR_DATA, 0}, + {DSI_INT_ENABLE, 0}, + {DSI_INT_STATUS, 0}, + {DSI_INT_MASK, 0}, + {DSI_INIT_SEQ_DATA_0, 0}, + {DSI_INIT_SEQ_DATA_1, 0}, + {DSI_INIT_SEQ_DATA_2, 0}, + {DSI_INIT_SEQ_DATA_3, 0}, + {DSI_DCS_CMDS, 0}, + {DSI_PKT_SEQ_0_LO, 0}, + {DSI_PKT_SEQ_1_LO, 0}, + {DSI_PKT_SEQ_2_LO, 0}, + {DSI_PKT_SEQ_3_LO, 0}, + {DSI_PKT_SEQ_4_LO, 0}, + {DSI_PKT_SEQ_5_LO, 0}, + {DSI_PKT_SEQ_0_HI, 0}, + {DSI_PKT_SEQ_1_HI, 0}, + {DSI_PKT_SEQ_2_HI, 0}, + {DSI_PKT_SEQ_3_HI, 0}, + {DSI_PKT_SEQ_4_HI, 0}, + {DSI_PKT_SEQ_5_HI, 0}, + {DSI_CONTROL, 0}, + {DSI_PAD_CONTROL_CD, 0}, + {DSI_SOL_DELAY, 0x18}, + {DSI_MAX_THRESHOLD, 0x1E0}, + {DSI_TRIGGER, 0}, + {DSI_INIT_SEQ_CONTROL, 0}, + {DSI_PKT_LEN_0_1, 0}, + {DSI_PKT_LEN_2_3, 0}, + {DSI_PKT_LEN_4_5, 0}, + {DSI_PKT_LEN_6_7, 0}, + {DSI_PAD_CONTROL_1, 0}, + {DSI_PHY_TIMING_0, 0x6070601}, + {DSI_PHY_TIMING_1, 0x40A0E05}, + {DSI_PHY_TIMING_2, 0x30109}, + {DSI_BTA_TIMING, 0x190A14}, + {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TO_TALLY, 0}, + {DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_POWER_CONTROL, 0}, + {DSI_POWER_CONTROL, 0}, + {DSI_PAD_CONTROL_1, 0}, + {DSI_PHY_TIMING_0, 0x6070601}, + {DSI_PHY_TIMING_1, 0x40A0E05}, + {DSI_PHY_TIMING_2, 0x30118}, + {DSI_BTA_TIMING, 0x190A14}, + {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TO_TALLY, 0}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_MAX_THRESHOLD, 0x40}, + {DSI_TRIGGER, 0}, + {DSI_TX_CRC, 0}, + {DSI_INIT_SEQ_CONTROL, 0} +}; + +//DSI config (if ver == 0x10). +static const cfg_op_t _display_config_4[43] = { + {DSI_WR_DATA, 0x439}, + {DSI_WR_DATA, 0x9483FFB9}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0xBD15}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x1939}, + {DSI_WR_DATA, 0xAAAAAAD8}, + {DSI_WR_DATA, 0xAAAAAAEB}, + {DSI_WR_DATA, 0xAAEBAAAA}, + {DSI_WR_DATA, 0xAAAAAAAA}, + {DSI_WR_DATA, 0xAAAAAAEB}, + {DSI_WR_DATA, 0xAAEBAAAA}, + {DSI_WR_DATA, 0xAA}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x1BD15}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x2739}, + {DSI_WR_DATA, 0xFFFFFFD8}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFF}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x2BD15}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0xF39}, + {DSI_WR_DATA, 0xFFFFFFD8}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFF}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0xBD15}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x6D915}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x439}, + {DSI_WR_DATA, 0xB9}, + {DSI_TRIGGER, DSI_TRIGGER_HOST} +}; + +//DSI config. +static const cfg_op_t _display_config_5[21] = { + {DSI_PAD_CONTROL_1, 0}, + {DSI_PHY_TIMING_0, 0x6070601}, + {DSI_PHY_TIMING_1, 0x40A0E05}, + {DSI_PHY_TIMING_2, 0x30172}, + {DSI_BTA_TIMING, 0x190A14}, + {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TO_TALLY, 0}, + {DSI_PKT_SEQ_0_LO, 0x40000208}, + {DSI_PKT_SEQ_2_LO, 0x40000308}, + {DSI_PKT_SEQ_4_LO, 0x40000308}, + {DSI_PKT_SEQ_1_LO, 0x40000308}, + {DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, + {DSI_PKT_SEQ_3_HI, 0x2CC}, + {DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, + {DSI_PKT_SEQ_5_HI, 0x2CC}, + {DSI_PKT_LEN_0_1, 0xCE0000}, + {DSI_PKT_LEN_2_3, 0x87001A2}, + {DSI_PKT_LEN_4_5, 0x190}, + {DSI_PKT_LEN_6_7, 0x190}, + {DSI_HOST_CONTROL, 0}, +}; + +//Clock config. +static const cfg_op_t _display_config_6[3] = { + {0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE + {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 + {0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC +}; + +//DSI config. +static const cfg_op_t _display_config_7[10] = { + {DSI_TRIGGER, 0}, + {DSI_CONTROL, 0}, + {DSI_SOL_DELAY, 6}, + {DSI_MAX_THRESHOLD, 0x1E0}, + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} +}; + +//MIPI CAL config. +static const cfg_op_t _display_config_8[6] = { + {0x18, 0}, + {2, 0xF3F10000}, + {0x16, 1}, + {0x18, 0}, + {0x18, 0x10010}, + {0x17, 0x300} +}; + +//DSI config. +static const cfg_op_t _display_config_9[4] = { + {DSI_PAD_CONTROL_1, 0}, + {DSI_PAD_CONTROL_2, 0}, + {DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, + {DSI_PAD_CONTROL_4, 0} +}; + +//MIPI CAL config. +static const cfg_op_t _display_config_10[16] = { + {0xE, 0x200200}, + {0xF, 0x200200}, + {0x19, 0x200002}, + {0x1A, 0x200002}, + {5, 0}, + {6, 0}, + {7, 0}, + {8, 0}, + {9, 0}, + {0xA, 0}, + {0x10, 0}, + {0x11, 0}, + {0x1A, 0}, + {0x1C, 0}, + {0x1D, 0}, + {0, 0x2A000001} +}; + +//Display A config. +static const cfg_op_t _display_config_11[113] = { + {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {0x4E4, 0}, + {DC_COM_CRC_CONTROL, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_COMMAND, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {DC_CMD_STATE_ACCESS, 0}, + /* Set Display timings */ + {DC_DISP_DISP_TIMING_OPTIONS, 0}, + {DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1. + {DC_DISP_SYNC_WIDTH, 0x10048}, + {DC_DISP_BACK_PORCH, 0x90048}, + {DC_DISP_ACTIVE, 0x50002D0}, + {DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd. + /* End of Display timings */ + {DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, + {DC_COM_PIN_OUTPUT_ENABLE(1), 0}, + {DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, + {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {DC_DISP_DISP_CLOCK_CONTROL, 0}, + {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, + {DC_DISP_FRONT_PORCH, 0xA0088}, + {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_STATE_ACCESS, 0}, + {DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, + {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {DC_CMD_DISPLAY_COMMAND_OPTION0, 0} +}; + +////Display A config. +static const cfg_op_t _display_config_12[17] = { + {DC_DISP_FRONT_PORCH, 0xA0088}, + {DC_CMD_INT_MASK, 0}, + {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_INT_ENABLE, 0}, + {DC_CMD_CONT_SYNCPT_VSYNC, 0}, + {DC_CMD_DISPLAY_COMMAND, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_DISPLAY_POWER_CONTROL, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, +}; + +//DSI config. +static const cfg_op_t _display_config_13[16] = { + {DSI_POWER_CONTROL, 0}, + {DSI_PAD_CONTROL_1, 0}, + {DSI_PHY_TIMING_0, 0x6070601}, + {DSI_PHY_TIMING_1, 0x40A0E05}, + {DSI_PHY_TIMING_2, 0x30109}, + {DSI_BTA_TIMING, 0x190A14}, + {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TO_TALLY, 0}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_MAX_THRESHOLD, 0x40}, + {DSI_TRIGGER, 0}, + {DSI_TX_CRC, 0}, + {DSI_INIT_SEQ_CONTROL, 0} +}; + +//DSI config (if ver == 0x10). +static const cfg_op_t _display_config_14[22] = { + {DSI_WR_DATA, 0x439}, + {DSI_WR_DATA, 0x9483FFB9}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x2139}, + {DSI_WR_DATA, 0x191919D5}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0xB39}, + {DSI_WR_DATA, 0x4F0F41B1}, + {DSI_WR_DATA, 0xF179A433}, + {DSI_WR_DATA, 0x2D81}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x439}, + {DSI_WR_DATA, 0xB9}, + {DSI_TRIGGER, DSI_TRIGGER_HOST} +}; + +//Display A config. +static const cfg_op_t cfg_display_one_color[8] = { + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display. +}; + +//Display A config. +static const cfg_op_t cfg_display_framebuffer[32] = { + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 + {DC_WIN_WIN_OPTIONS, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_WIN_POSITION, 0}, //(0,0) + {DC_WIN_H_INITIAL_DDA, 0}, + {DC_WIN_V_INITIAL_DDA, 0}, + {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. + {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, + {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. + {DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_BUFFER_CONTROL, 0}, + {DC_WINBUF_SURFACE_KIND, 0}, //Regular surface. + {DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address. + {DC_WINBUF_ADDR_H_OFFSET, 0}, + {DC_WINBUF_ADDR_V_OFFSET, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD. + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display. + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update. + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request. +}; diff --git a/fusee/fusee-primary/src/hwinit/emc.h b/fusee/fusee-primary/src/emc.h similarity index 98% rename from fusee/fusee-primary/src/hwinit/emc.h rename to fusee/fusee-primary/src/emc.h index ce134c2fe..a032d5c97 100644 --- a/fusee/fusee-primary/src/hwinit/emc.h +++ b/fusee/fusee-primary/src/emc.h @@ -1,27 +1,11 @@ -/* -* arch/arm/mach-tegra/tegra21_emc.h -* -* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -* -*/ +#ifndef FUSEE_EMC_H_ +#define FUSEE_EMC_H_ -#ifndef _EMC_H_ -#define _EMC_H_ +#define EMC_BASE 0x7001B000 +#define MAKE_EMC_REG(n) MAKE_REG32(EMC_BASE + n) +#define EMC_DBG 0x8 +#define EMC_CFG 0xC #define EMC_CONFIG_SAMPLE_DELAY 0x5f0 #define EMC_CFG_UPDATE 0x5f4 #define EMC_ADR_CFG 0x10 diff --git a/fusee/fusee-primary/src/flow.h b/fusee/fusee-primary/src/flow.h new file mode 100644 index 000000000..b3128d55e --- /dev/null +++ b/fusee/fusee-primary/src/flow.h @@ -0,0 +1,15 @@ +#ifndef FUSEE_FLOW_CTLR_H +#define FUSEE_FLOW_CTLR_H + +#include + +#define FLOW_CTLR_BASE 0x60007000 +#define MAKE_FLOW_REG(ofs) MAKE_REG32(FLOW_CTLR_BASE + ofs) + +#define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004) +#define FLOW_CTLR_RAM_REPAIR_0 MAKE_FLOW_REG(0x040) +#define FLOW_CTLR_FLOW_DBG_QUAL_0 MAKE_FLOW_REG(0x050) +#define FLOW_CTLR_L2FLUSH_CONTROL_0 MAKE_FLOW_REG(0x094) +#define FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 MAKE_FLOW_REG(0x098) + +#endif diff --git a/fusee/fusee-primary/src/fs_utils.c b/fusee/fusee-primary/src/fs_utils.c index c3ee71d4c..1c8529f07 100644 --- a/fusee/fusee-primary/src/fs_utils.c +++ b/fusee/fusee-primary/src/fs_utils.c @@ -1,5 +1,5 @@ #include "fs_utils.h" -#include "hwinit.h" +#include "mc.h" #include "lib/printk.h" #include "lib/fatfs/ff.h" diff --git a/fusee/fusee-primary/src/fuse.c b/fusee/fusee-primary/src/fuse.c index 2bdfa3740..04780c9ce 100644 --- a/fusee/fusee-primary/src/fuse.c +++ b/fusee/fusee-primary/src/fuse.c @@ -2,7 +2,7 @@ #include #include -#include "hwinit.h" +#include "car.h" #include "fuse.h" #include "timers.h" @@ -13,154 +13,155 @@ void fuse_enable_power(void); void fuse_disable_power(void); void fuse_wait_idle(void); -/* Initialize the FUSE driver */ -void fuse_init(void) -{ - /* - Already done by hwinit, except maybe fuse_secondary_private_key_disable (?) - fuse_make_regs_visible(); - fuse_secondary_private_key_disable(); - fuse_disable_programming(); - */ +/* Initialize the fuse driver */ +void fuse_init(void) { + fuse_make_regs_visible(); + fuse_secondary_private_key_disable(); + fuse_disable_programming(); /* TODO: Overrides (iROM patches) and various reads happen here */ } /* Make all fuse registers visible */ -void fuse_make_regs_visible(void) -{ - clock_enable_fuse(1); +void fuse_make_regs_visible(void) { + clkrst_enable_fuse_regs(true); } /* Enable power to the fuse hardware array */ -void fuse_enable_power(void) -{ - FUSE_REGS->FUSE_PWR_GOOD_SW = 1; - wait(1); +void fuse_enable_power(void) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); + fuse->FUSE_PWR_GOOD_SW = 1; + udelay(1); } /* Disable power to the fuse hardware array */ -void fuse_disable_power(void) -{ - FUSE_REGS->FUSE_PWR_GOOD_SW = 0; - wait(1); +void fuse_disable_power(void) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); + fuse->FUSE_PWR_GOOD_SW = 0; + udelay(1); } /* Wait for the fuse driver to go idle */ -void fuse_wait_idle(void) -{ +void fuse_wait_idle(void) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); uint32_t ctrl_val = 0; /* Wait for STATE_IDLE */ while ((ctrl_val & (0xF0000)) != 0x40000) { - wait(1); - ctrl_val = FUSE_REGS->FUSE_CTRL; + udelay(1); + ctrl_val = fuse->FUSE_CTRL; } } /* Read a fuse from the hardware array */ -uint32_t fuse_hw_read(uint32_t addr) -{ +uint32_t fuse_hw_read(uint32_t addr) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); fuse_wait_idle(); /* Program the target address */ - FUSE_REGS->FUSE_REG_ADDR = addr; + fuse->FUSE_REG_ADDR = addr; /* Enable read operation in control register */ - uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL; + uint32_t ctrl_val = fuse->FUSE_CTRL; ctrl_val &= ~0x3; ctrl_val |= 0x1; /* Set FUSE_READ command */ - FUSE_REGS->FUSE_CTRL = ctrl_val; + fuse->FUSE_CTRL = ctrl_val; fuse_wait_idle(); - return FUSE_REGS->FUSE_REG_READ; + return fuse->FUSE_REG_READ; } /* Write a fuse in the hardware array */ -void fuse_hw_write(uint32_t value, uint32_t addr) -{ +void fuse_hw_write(uint32_t value, uint32_t addr) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); fuse_wait_idle(); /* Program the target address and value */ - FUSE_REGS->FUSE_REG_ADDR = addr; - FUSE_REGS->FUSE_REG_WRITE = value; + fuse->FUSE_REG_ADDR = addr; + fuse->FUSE_REG_WRITE = value; /* Enable write operation in control register */ - uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL; + uint32_t ctrl_val = fuse->FUSE_CTRL; ctrl_val &= ~0x3; ctrl_val |= 0x2; /* Set FUSE_WRITE command */ - FUSE_REGS->FUSE_CTRL = ctrl_val; + fuse->FUSE_CTRL = ctrl_val; fuse_wait_idle(); } /* Sense the fuse hardware array into the shadow cache */ -void fuse_hw_sense(void) -{ +void fuse_hw_sense(void) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); fuse_wait_idle(); /* Enable sense operation in control register */ - uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL; + uint32_t ctrl_val = fuse->FUSE_CTRL; ctrl_val &= ~0x3; ctrl_val |= 0x3; /* Set FUSE_SENSE command */ - FUSE_REGS->FUSE_CTRL = ctrl_val; + fuse->FUSE_CTRL = ctrl_val; fuse_wait_idle(); } /* Disables all fuse programming. */ void fuse_disable_programming(void) { - FUSE_REGS->FUSE_DIS_PGM = 1; + volatile tegra_fuse_t *fuse = fuse_get_regs(); + fuse->FUSE_DIS_PGM = 1; } /* Unknown exactly what this does, but it alters the contents read from the fuse cache. */ void fuse_secondary_private_key_disable(void) { - FUSE_REGS->FUSE_PRIVATEKEYDISABLE = 0x10; + volatile tegra_fuse_t *fuse = fuse_get_regs(); + fuse->FUSE_PRIVATEKEYDISABLE = 0x10; } /* Read the SKU info register from the shadow cache */ -uint32_t fuse_get_sku_info(void) -{ - return FUSE_CHIP_REGS->FUSE_SKU_INFO; +uint32_t fuse_get_sku_info(void) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + return fuse_chip->FUSE_SKU_INFO; } /* Read the bootrom patch version from a register in the shadow cache */ -uint32_t fuse_get_bootrom_patch_version(void) -{ - return FUSE_CHIP_REGS->FUSE_SOC_SPEEDO_1; +uint32_t fuse_get_bootrom_patch_version(void) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + return fuse_chip->FUSE_SOC_SPEEDO_1; } /* Read a spare bit register from the shadow cache */ -uint32_t fuse_get_spare_bit(uint32_t idx) -{ +uint32_t fuse_get_spare_bit(uint32_t idx) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + if (idx >= 32) { return 0; } - return FUSE_CHIP_REGS->FUSE_SPARE_BIT[idx]; + return fuse_chip->FUSE_SPARE_BIT[idx]; } /* Read a reserved ODM register from the shadow cache */ -uint32_t fuse_get_reserved_odm(uint32_t idx) -{ +uint32_t fuse_get_reserved_odm(uint32_t idx) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + if (idx >= 8) { return 0; } - return FUSE_CHIP_REGS->FUSE_RESERVED_ODM[idx]; + return fuse_chip->FUSE_RESERVED_ODM[idx]; } /* Derive the Device ID using values in the shadow cache */ uint64_t fuse_get_device_id(void) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + uint64_t device_id = 0; - uint64_t y_coord = FUSE_CHIP_REGS->FUSE_Y_COORDINATE & 0x1FF; - uint64_t x_coord = FUSE_CHIP_REGS->FUSE_X_COORDINATE & 0x1FF; - uint64_t wafer_id = FUSE_CHIP_REGS->FUSE_WAFER_ID & 0x3F; - uint32_t lot_code = FUSE_CHIP_REGS->FUSE_LOT_CODE_0; - uint64_t fab_code = FUSE_CHIP_REGS->FUSE_FAB_CODE & 0x3F; + uint64_t y_coord = fuse_chip->FUSE_Y_COORDINATE & 0x1FF; + uint64_t x_coord = fuse_chip->FUSE_X_COORDINATE & 0x1FF; + uint64_t wafer_id = fuse_chip->FUSE_WAFER_ID & 0x3F; + uint32_t lot_code = fuse_chip->FUSE_LOT_CODE_0; + uint64_t fab_code = fuse_chip->FUSE_FAB_CODE & 0x3F; uint64_t derived_lot_code = 0; for (unsigned int i = 0; i < 5; i++) { derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F); @@ -177,24 +178,27 @@ uint64_t fuse_get_device_id(void) { /* Get the DRAM ID using values in the shadow cache */ uint32_t fuse_get_dram_id(void) { - return (FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 3) & 0x7; + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + return (fuse_chip->FUSE_RESERVED_ODM[4] >> 3) & 0x7; } /* Derive the Hardware Type using values in the shadow cache */ uint32_t fuse_get_hardware_type(void) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + /* This function is very different between 4.x and < 4.x */ - uint32_t hardware_type = ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 7) & 2) | ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 2) & 1); + uint32_t hardware_type = ((fuse_chip->FUSE_RESERVED_ODM[4] >> 7) & 2) | ((fuse_chip->FUSE_RESERVED_ODM[4] >> 2) & 1); /* TODO: choose; if (mkey_get_revision() >= MASTERKEY_REVISION_400_CURRENT) { static const uint32_t types[] = {0,1,4,3}; - hardware_type |= (FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 14) & 0x3C; + hardware_type |= (fuse_chip->FUSE_RESERVED_ODM[4] >> 14) & 0x3C; hardware_type--; return hardware_type > 3 ? 4 : types[hardware_type]; } else {*/ if (hardware_type >= 1) { return hardware_type > 2 ? 3 : hardware_type - 1; - } else if ((FUSE_CHIP_REGS->FUSE_SPARE_BIT[9] & 1) == 0) { + } else if ((fuse_chip->FUSE_SPARE_BIT[9] & 1) == 0) { return 0; } else { return 3; @@ -204,8 +208,10 @@ uint32_t fuse_get_hardware_type(void) { /* Derive the Retail Type using values in the shadow cache */ uint32_t fuse_get_retail_type(void) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + /* Retail type = IS_RETAIL | UNIT_TYPE */ - uint32_t retail_type = ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 7) & 4) | (FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] & 3); + uint32_t retail_type = ((fuse_chip->FUSE_RESERVED_ODM[4] >> 7) & 4) | (fuse_chip->FUSE_RESERVED_ODM[4] & 3); if (retail_type == 4) { /* Standard retail unit, IS_RETAIL | 0. */ return 1; } else if (retail_type == 3) { /* Standard dev unit, 0 | DEV_UNIT. */ @@ -216,16 +222,17 @@ uint32_t fuse_get_retail_type(void) { /* Derive the 16-byte Hardware Info using values in the shadow cache, and copy to output buffer. */ void fuse_get_hardware_info(void *dst) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); uint32_t hw_info[0x4]; - uint32_t unk_hw_fuse = FUSE_CHIP_REGS->_0x120 & 0x3F; - uint32_t y_coord = FUSE_CHIP_REGS->FUSE_Y_COORDINATE & 0x1FF; - uint32_t x_coord = FUSE_CHIP_REGS->FUSE_X_COORDINATE & 0x1FF; - uint32_t wafer_id = FUSE_CHIP_REGS->FUSE_WAFER_ID & 0x3F; - uint32_t lot_code_0 = FUSE_CHIP_REGS->FUSE_LOT_CODE_0; - uint32_t lot_code_1 = FUSE_CHIP_REGS->FUSE_LOT_CODE_1 & 0x0FFFFFFF; - uint32_t fab_code = FUSE_CHIP_REGS->FUSE_FAB_CODE & 0x3F; - uint32_t vendor_code = FUSE_CHIP_REGS->FUSE_VENDOR_CODE & 0xF; + uint32_t unk_hw_fuse = fuse_chip->_0x120 & 0x3F; + uint32_t y_coord = fuse_chip->FUSE_Y_COORDINATE & 0x1FF; + uint32_t x_coord = fuse_chip->FUSE_X_COORDINATE & 0x1FF; + uint32_t wafer_id = fuse_chip->FUSE_WAFER_ID & 0x3F; + uint32_t lot_code_0 = fuse_chip->FUSE_LOT_CODE_0; + uint32_t lot_code_1 = fuse_chip->FUSE_LOT_CODE_1 & 0x0FFFFFFF; + uint32_t fab_code = fuse_chip->FUSE_FAB_CODE & 0x3F; + uint32_t vendor_code = fuse_chip->FUSE_VENDOR_CODE & 0xF; /* Hardware Info = unk_hw_fuse || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */ hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (unk_hw_fuse)); diff --git a/fusee/fusee-primary/src/fuse.h b/fusee/fusee-primary/src/fuse.h index 989f564bf..63285b64f 100644 --- a/fusee/fusee-primary/src/fuse.h +++ b/fusee/fusee-primary/src/fuse.h @@ -1,6 +1,11 @@ #ifndef FUSEE_FUSE_H #define FUSEE_FUSE_H +#define FUSE_BASE 0x7000F800 +#define FUSE_CHIP_BASE (FUSE_BASE + 0x100) +#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n) +#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n) + typedef struct { uint32_t FUSE_CTRL; uint32_t FUSE_REG_ADDR; @@ -17,7 +22,7 @@ typedef struct { uint32_t FUSE_WRITE_ACCESS; uint32_t FUSE_PWR_GOOD_SW; uint32_t _0x38[0x32]; -} fuse_registers_t; +} tegra_fuse_t; typedef struct { uint32_t FUSE_PRODUCTION_MODE; @@ -160,17 +165,15 @@ typedef struct { uint32_t _0x278; uint32_t _0x27C; uint32_t FUSE_SPARE_BIT[0x20]; -} fuse_chip_registers_t; +} tegra_fuse_chip_t; -static inline volatile fuse_registers_t *get_fuse_regs(void) { - return (volatile fuse_registers_t *)(0x7000F000 + 0x800); +static inline volatile tegra_fuse_t *fuse_get_regs(void) { + return (volatile tegra_fuse_t *)FUSE_BASE; } -static inline volatile fuse_chip_registers_t *get_fuse_chip_regs(void) { - return (volatile fuse_chip_registers_t *)(0x7000F000 + 0x900); +static inline volatile tegra_fuse_chip_t *fuse_chip_get_regs(void) { + return (volatile tegra_fuse_chip_t *)FUSE_CHIP_BASE; } -#define FUSE_REGS (get_fuse_regs()) -#define FUSE_CHIP_REGS (get_fuse_chip_regs()) void fuse_init(void); diff --git a/fusee/fusee-primary/src/gpio.h b/fusee/fusee-primary/src/gpio.h index b3da7dc56..a916c989c 100644 --- a/fusee/fusee-primary/src/gpio.h +++ b/fusee/fusee-primary/src/gpio.h @@ -1,6 +1,11 @@ #ifndef FUSEE_GPIO_H #define FUSEE_GPIO_H +#include + +#define GPIO_BASE 0x6000D000 +#define MAKE_GPIO_REG(n) MAKE_REG32(GPIO_BASE + n) + #define TEGRA_GPIO_PORTS 4 #define TEGRA_GPIO_BANKS 8 #define GPIO_BANK_SHIFT 5 @@ -68,7 +73,7 @@ typedef struct { static inline volatile tegra_gpio_t *gpio_get_regs(void) { - return (volatile tegra_gpio_t *)0x6000D000; + return (volatile tegra_gpio_t *)GPIO_BASE; } #define TEGRA_GPIO(port, offset) \ @@ -87,9 +92,16 @@ static inline volatile tegra_gpio_t *gpio_get_regs(void) #define GPIO_LEVEL_HIGH 1 /* Named GPIOs */ +#define GPIO_BUTTON_VOL_DOWN TEGRA_GPIO(X, 7) +#define GPIO_BUTTON_VOL_UP TEGRA_GPIO(X, 6) #define GPIO_MICROSD_CARD_DETECT TEGRA_GPIO(Z, 1) #define GPIO_MICROSD_WRITE_PROTECT TEGRA_GPIO(Z, 4) #define GPIO_MICROSD_SUPPLY_ENABLE TEGRA_GPIO(E, 4) +#define GPIO_LCD_BL_P5V TEGRA_GPIO(I, 0) +#define GPIO_LCD_BL_N5V TEGRA_GPIO(I, 1) +#define GPIO_LCD_BL_PWM TEGRA_GPIO(V, 0) +#define GPIO_LCD_BL_EN TEGRA_GPIO(V, 1) +#define GPIO_LCD_BL_RST TEGRA_GPIO(V, 2) void gpio_configure_mode(uint32_t pin, uint32_t mode); void gpio_configure_direction(uint32_t pin, uint32_t dir); diff --git a/fusee/fusee-primary/src/hwinit.c b/fusee/fusee-primary/src/hwinit.c new file mode 100644 index 000000000..903b750bd --- /dev/null +++ b/fusee/fusee-primary/src/hwinit.c @@ -0,0 +1,245 @@ +#include "hwinit.h" +#include "apb_misc.h" +#include "car.h" +#include "di.h" +#include "fuse.h" +#include "gpio.h" +#include "i2c.h" +#include "max77620.h" +#include "mc.h" +#include "pinmux.h" +#include "pmc.h" +#include "se.h" +#include "sdram.h" +#include "sysctr0.h" +#include "sysreg.h" +#include "timers.h" +#include "uart.h" + +void config_oscillators() +{ + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pmc_t *pmc = pmc_get_regs(); + + car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4); + + SYSCTR0_CNTFID0_0 = 19200000; + MAKE_TIMERS_REG(0x14) = 0x45F; + + car->osc_ctrl = 0x50000071; + pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE); + pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFBFFFFF) | 0x400000); + pmc->cntrl2 = ((pmc->cntrl2 & 0xFFFFEFFF) | 0x1000); + pmc->scratch188 = ((pmc->scratch188 & 0xFCFFFFFF) | 0x2000000); + car->clk_sys_rate = 0x10; + car->pllmb_base &= 0xBFFFFFFF; + pmc->tsc_mult = ((pmc->tsc_mult & 0xFFFF0000) | 0x249F); /* 0x249F = 19200000 * (16 / 32.768 kHz) */ + car->sclk_brst_pol = 0x20004444; + car->super_sclk_div = 0x80000000; + car->clk_sys_rate = 2; +} + +void config_gpios() +{ + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + pinmux->uart2_tx = 0; + pinmux->uart3_tx = 0; + pinmux->pe6 = PINMUX_INPUT; + pinmux->ph6 = PINMUX_INPUT; + + gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO); + gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO); + gpio_configure_mode(TEGRA_GPIO(E, 6), GPIO_MODE_GPIO); + gpio_configure_mode(TEGRA_GPIO(H, 6), GPIO_MODE_GPIO); + gpio_configure_direction(TEGRA_GPIO(G, 0), GPIO_DIRECTION_INPUT); + gpio_configure_direction(TEGRA_GPIO(D, 1), GPIO_DIRECTION_INPUT); + gpio_configure_direction(TEGRA_GPIO(E, 6), GPIO_DIRECTION_INPUT); + gpio_configure_direction(TEGRA_GPIO(H, 6), GPIO_DIRECTION_INPUT); + + pinmux->gen1_i2c_scl = PINMUX_INPUT; + pinmux->gen1_i2c_sda = PINMUX_INPUT; + pinmux->pwr_i2c_scl = PINMUX_INPUT; + pinmux->pwr_i2c_sda = PINMUX_INPUT; + pinmux->uart1_rx = 0; + pinmux->uart1_tx = (PINMUX_INPUT | PINMUX_PULL_UP); + pinmux->uart1_rts = 0; + pinmux->uart1_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN); + + /* Configure volume up/down as inputs. */ + gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT); + gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT); +} + +void config_pmc_scratch() +{ + volatile tegra_pmc_t *pmc = pmc_get_regs(); + + pmc->scratch20 &= 0xFFF3FFFF; + pmc->scratch190 &= 0xFFFFFFFE; + pmc->secure_scratch21 |= 0x10; +} + +void mbist_workaround() +{ + volatile tegra_car_t *car = car_get_regs(); + + car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF); + car->plld_base |= 0x40800000u; + car->rst_dev_y_clr = 0x40; + car->rst_dev_x_clr = 0x40000; + car->rst_dev_l_clr = 0x18000000; + udelay(2); + + /* Setup I2S. */ + MAKE_I2S_REG(0x0A0) |= 0x400; + MAKE_I2S_REG(0x088) &= 0xFFFFFFFE; + MAKE_I2S_REG(0x1A0) |= 0x400; + MAKE_I2S_REG(0x188) &= 0xFFFFFFFE; + MAKE_I2S_REG(0x2A0) |= 0x400; + MAKE_I2S_REG(0x288) &= 0xFFFFFFFE; + MAKE_I2S_REG(0x3A0) |= 0x400; + MAKE_I2S_REG(0x388) &= 0xFFFFFFFE; + MAKE_I2S_REG(0x4A0) |= 0x400; + MAKE_I2S_REG(0x488) &= 0xFFFFFFFE; + + MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4; + MAKE_VIC_REG(0x8C) = 0xFFFFFFFF; + udelay(2); + + /* Set devices in reset. */ + car->rst_dev_y_set = 0x40; + car->rst_dev_l_set = 0x18000000; + car->rst_dev_x_set = 0x40000; + + /* Clock out enables. */ + car->clk_out_enb_h = 0xC0; + car->clk_out_enb_l = 0x80000130; + car->clk_out_enb_u = 0x1F00200; + car->clk_out_enb_v = 0x80400808; + car->clk_out_enb_w = 0x402000FC; + car->clk_out_enb_x = 0x23000780; + car->clk_out_enb_y = 0x300; + + /* LVL2 clock gate overrides. */ + car->lvl2_clk_gate_ovra = 0; + car->lvl2_clk_gate_ovrb = 0; + car->lvl2_clk_gate_ovrc = 0; + car->lvl2_clk_gate_ovrd = 0; + car->lvl2_clk_gate_ovre = 0; + + /* Configure clock sources. */ + car->plld_base &= 0x1F7FFFFF; + car->clk_source_sor1 &= 0xFFFF3FFF; + car->clk_source_vi = ((car->clk_source_vi & 0x1FFFFFFF) | 0x80000000); + car->clk_source_host1x = ((car->clk_source_host1x & 0x1FFFFFFF) | 0x80000000); + car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000); +} + +void config_se_brom() +{ + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + volatile tegra_se_t *se = se_get_regs(); + volatile tegra_pmc_t *pmc = pmc_get_regs(); + + /* Bootrom part we skipped. */ + uint32_t sbk[4] = {fuse_chip->FUSE_PRIVATE_KEY[0], fuse_chip->FUSE_PRIVATE_KEY[1], fuse_chip->FUSE_PRIVATE_KEY[2], fuse_chip->FUSE_PRIVATE_KEY[3]}; + set_aes_keyslot(0xE, sbk, 0x10); + + /* Lock SBK from being read. */ + se->AES_KEYSLOT_FLAGS[0xE] = 0x7E; + + /* This memset needs to happen here, else TZRAM will behave weirdly later on. */ + memset((void *)0x7C010000, 0, 0x10000); + + pmc->crypto_op = 0; + se->INT_STATUS_REG = 0x1F; + + /* Lock SSK (although it's not set and unused anyways). */ + se->AES_KEYSLOT_FLAGS[0xF] = 0x7E; + + /* Clear the boot reason to avoid problems later */ + pmc->scratch200 = 0; + pmc->reset_status = 0; +} + +void nx_hwinit() +{ + volatile tegra_pmc_t *pmc = pmc_get_regs(); + volatile tegra_car_t *car = car_get_regs(); + + /* Bootrom stuff we skipped by going through RCM. */ + config_se_brom(); + + AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F; + pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD); + + mbist_workaround(); + clkrst_reboot(CARDEVICE_SE); + + /* Initialize the fuse driver. */ + fuse_init(); + + /* Initialize the memory controller. */ + mc_enable(); + + /* Configure oscillators, pinmux and GPIOs. */ + config_oscillators(); + APB_MISC_PP_PINMUX_GLOBAL_0 = 0; + config_gpios(); + + /* Uncomment for UART debugging. */ + /* + clkrst_reboot(CARDEVICE_UARTC); + uart_init(UART_C, 115200); + */ + + clkrst_reboot(CARDEVICE_CL_DVFS); + clkrst_reboot(CARDEVICE_I2C1); + clkrst_reboot(CARDEVICE_I2C5); + clkrst_reboot(CARDEVICE_SE); + clkrst_reboot(CARDEVICE_UNK); + + /* Initialize I2C1 and I2C5. */ + i2c_init(0); + i2c_init(4); + + uint8_t val = 0x40; + i2c_send(4, 0x3C, MAX77620_REG_CNFGBBC, &val, 1); + val = 0x78; + i2c_send(4, 0x3C, MAX77620_REG_ONOFFCNFG1, &val, 1); + + val = 0x38; + i2c_send(4, 0x3C, MAX77620_REG_FPS_CFG0, &val, 1); + val = 0x3A; + i2c_send(4, 0x3C, MAX77620_REG_FPS_CFG1, &val, 1); + val = 0x38; + i2c_send(4, 0x3C, MAX77620_REG_FPS_CFG2, &val, 1); + val = 0xF; + i2c_send(4, 0x3C, MAX77620_REG_FPS_LDO4, &val, 1); + val = 0xC7; + i2c_send(4, 0x3C, MAX77620_REG_FPS_LDO8, &val, 1); + val = 0x4F; + i2c_send(4, 0x3C, MAX77620_REG_FPS_SD0, &val, 1); + val = 0x29; + i2c_send(4, 0x3C, MAX77620_REG_FPS_SD1, &val, 1); + val = 0x1B; + i2c_send(4, 0x3C, MAX77620_REG_FPS_SD3, &val, 1); + + val = 42; /* 42 = (1125000 - 600000) / 12500 -> 1.125V */ + i2c_send(4, 0x3C, MAX77620_REG_SD0, &val, 1); + + /* Configure and lock PMC scratch registers. */ + config_pmc_scratch(); + + car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333); + + /* Configure memory controller carveouts. */ + mc_config_carveout(); + + /* Initialize and save SDRAM. */ + sdram_init(); + sdram_lp0_save_params(sdram_get_params()); +} \ No newline at end of file diff --git a/fusee/fusee-primary/src/hwinit.h b/fusee/fusee-primary/src/hwinit.h index 7b66f07b7..da197ae83 100644 --- a/fusee/fusee-primary/src/hwinit.h +++ b/fusee/fusee-primary/src/hwinit.h @@ -1,39 +1,9 @@ -#ifndef FUSEE_HWINIT_H -#define FUSEE_HWINIT_H +#ifndef FUSEE_HWINIT_H_ +#define FUSEE_HWINIT_H_ -/* Symbols from hwinit that we're using, but w/o importing macro definitions that may clash with ours */ +#define I2S_BASE 0x702D1000 +#define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n) -#include "hwinit/types.h" -#include "hwinit/hwinit.h" -#include "hwinit/i2c.h" +void nx_hwinit(); -#include - -#define UART_A 0 -#define UART_B 1 -#define UART_C 2 -#define BAUD_115200 115200 - -void uart_init(u32 idx, u32 baud); -void uart_wait_idle(u32 idx, u32 which); -void uart_send(u32 idx, u8 *buf, u32 len); -void uart_recv(u32 idx, u8 *buf, u32 len); - -void display_init(); -void display_end(); - -void clock_enable_fuse(u32 enable); - -/*! Show one single color on the display. */ -void display_color_screen(u32 color); - -/*! Init display in full 1280x720 resolution (32bpp, line stride 768, framebuffer size = 1280*768*4 bytes). */ -u32 *display_init_framebuffer(void *address); - -/*! Enable or disable the backlight. Should only be called when the screen is completely set up, to avoid flickering. */ -void display_enable_backlight(bool on); - -void cluster_enable_cpu0(u64 entry, u32 ns_disable); - -void mc_enable_ahb_redirect(); #endif diff --git a/fusee/fusee-primary/src/hwinit/btn.c b/fusee/fusee-primary/src/hwinit/btn.c deleted file mode 100644 index 50bf1b37d..000000000 --- a/fusee/fusee-primary/src/hwinit/btn.c +++ /dev/null @@ -1,25 +0,0 @@ -#include "btn.h" -#include "i2c.h" -#include "t210.h" - -u32 btn_read() -{ - u32 res = 0; - if(!(GPIO_6(0x3C) & 0x80)) - res |= BTN_VOL_DOWN; - if(!(GPIO_6(0x3C) & 0x40)) - res |= BTN_VOL_UP; - if(i2c_recv_byte(4, 0x3C, 0x15) & 0x4) - res |= BTN_POWER; - return res; -} - -u32 btn_wait() -{ - u32 res = 0, btn = btn_read(); - do - { - res = btn_read(); - } while (btn == res); - return res; -} diff --git a/fusee/fusee-primary/src/hwinit/btn.h b/fusee/fusee-primary/src/hwinit/btn.h deleted file mode 100644 index 7ae7af9e7..000000000 --- a/fusee/fusee-primary/src/hwinit/btn.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _BTN_H_ -#define _BTN_H_ - -#include "types.h" - -#define BTN_POWER 0x1 -#define BTN_VOL_DOWN 0x2 -#define BTN_VOL_UP 0x4 - -u32 btn_read(); -u32 btn_wait(); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/clock.c b/fusee/fusee-primary/src/hwinit/clock.c deleted file mode 100644 index b0b4ab93b..000000000 --- a/fusee/fusee-primary/src/hwinit/clock.c +++ /dev/null @@ -1,145 +0,0 @@ -#include "clock.h" -#include "t210.h" -#include "util.h" - -static const clock_t _clock_uart[] = { - /* UART A */ { 4, 0x10, 0x178, 6, 0, 0 }, - /* UART B */ { 4, 0x10, 0x17C, 7, 0, 0 }, - /* UART C */ { 8, 0x14, 0x1A0, 0x17, 0, 0 }, - /* UART D */ { 0 }, - /* UART E */ { 0 } -}; - -static const clock_t _clock_i2c[] = { - /* I2C1 */ { 4, 0x10, 0x124, 0xC, 6, 0 }, - /* I2C2 */ { 0 }, - /* I2C3 */ { 0 }, - /* I2C4 */ { 0 }, - /* I2C5 */ { 8, 0x14, 0x128, 0xF, 6, 0 }, - /* I2C6 */ { 0 } -}; - -static clock_t _clock_se = { 0x358, 0x360, 0x42C, 0x1F, 0, 0 }; - -static clock_t _clock_host1x = { 4, 0x10, 0x180, 0x1C, 4, 3 }; -static clock_t _clock_tsec = { 0xC, 0x18, 0x1F4, 0x13, 0, 2 }; -static clock_t _clock_sor_safe = { 0x2A4, 0x298, 0, 0x1E, 0, 0 }; -static clock_t _clock_sor0 = { 0x28C, 0x280, 0, 0x16, 0, 0 }; -static clock_t _clock_sor1 = { 0x28C, 0x280, 0x410, 0x17, 0, 2 }; -static clock_t _clock_kfuse = { 8, 0x14, 0, 8, 0, 0 }; - -static clock_t _clock_coresight = { 0xC, 0x18, 0x1D4, 9, 0, 4}; - -void clock_enable(const clock_t *clk) -{ - //Put clock into reset. - CLOCK(clk->reset) = CLOCK(clk->reset) & ~(1 << clk->index) | (1 << clk->index); - //Disable. - CLOCK(clk->enable) &= ~(1 << clk->index); - //Configure clock source if required. - if (clk->source) - CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29); - //Enable. - CLOCK(clk->enable) = CLOCK(clk->enable) & ~(1 << clk->index) | (1 << clk->index); - //Take clock off reset. - CLOCK(clk->reset) &= ~(1 << clk->index); -} - -void clock_disable(const clock_t *clk) -{ - //Put clock into reset. - CLOCK(clk->reset) = CLOCK(clk->reset) & ~(1 << clk->index) | (1 << clk->index); - //Disable. - CLOCK(clk->enable) &= ~(1 << clk->index); -} - -void clock_enable_fuse(u32 enable) -{ - CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF | ((enable & 1) << 28) & 0x10000000; -} - -void clock_enable_uart(u32 idx) -{ - clock_enable(&_clock_uart[idx]); -} - -void clock_enable_i2c(u32 idx) -{ - clock_enable(&_clock_i2c[idx]); -} - -void clock_enable_se() -{ - clock_enable(&_clock_se); -} - -void clock_enable_host1x() -{ - clock_enable(&_clock_host1x); -} - -void clock_enable_tsec() -{ - clock_enable(&_clock_tsec); -} - -void clock_enable_sor_safe() -{ - clock_enable(&_clock_sor_safe); -} - -void clock_enable_sor0() -{ - clock_enable(&_clock_sor0); -} - -void clock_enable_sor1() -{ - clock_enable(&_clock_sor1); -} - -void clock_enable_kfuse() -{ - //clock_enable(&_clock_kfuse); - CLOCK(0x8) = CLOCK(0x8) & 0xFFFFFEFF | 0x100; - CLOCK(0x14) &= 0xFFFFFEFF; - CLOCK(0x14) = CLOCK(0x14) & 0xFFFFFEFF | 0x100; - sleep(10); - CLOCK(0x8) &= 0xFFFFFEFF; - sleep(20); -} - -void clock_disable_host1x() -{ - clock_disable(&_clock_host1x); -} - -void clock_disable_tsec() -{ - clock_disable(&_clock_tsec); -} - -void clock_disable_sor_safe() -{ - clock_disable(&_clock_sor_safe); -} - -void clock_disable_sor0() -{ - clock_disable(&_clock_sor0); -} - -void clock_disable_sor1() -{ - clock_disable(&_clock_sor1); -} - -void clock_disable_kfuse() -{ - clock_disable(&_clock_kfuse); -} - -void clock_enable_coresight() -{ - clock_enable(&_clock_coresight); -} diff --git a/fusee/fusee-primary/src/hwinit/clock.h b/fusee/fusee-primary/src/hwinit/clock.h deleted file mode 100644 index 027fd4b26..000000000 --- a/fusee/fusee-primary/src/hwinit/clock.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _CLOCK_H_ -#define _CLOCK_H_ - -#include "types.h" - -/*! Clock registers. */ -#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY 0x28 -#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2C -#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 -#define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48 -#define CLK_RST_CONTROLLER_OSC_CTRL 0x50 -#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C -#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284 -#define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308 -#define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328 -#define CLK_RST_CONTROLLER_RST_DEVICES_V 0x358 -#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454 -#define CLK_RST_CONTROLLER_SPARE_REG0 0x55C -#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8 - -typedef struct _clock_t -{ - u32 reset; - u32 enable; - u32 source; - u8 index; - u8 clk_src; - u8 clk_div; -} clock_t; - -void clock_enable(const clock_t *clk); -void clock_disable(const clock_t *clk); -void clock_enable_fuse(u32 enable); -void clock_enable_uart(u32 idx); -void clock_enable_i2c(u32 idx); -void clock_enable_se(); -void clock_enable_host1x(); -void clock_enable_tsec(); -void clock_enable_sor_safe(); -void clock_enable_sor0(); -void clock_enable_sor1(); -void clock_enable_kfuse(); -void clock_disable_host1x(); -void clock_disable_tsec(); -void clock_disable_sor_safe(); -void clock_disable_sor0(); -void clock_disable_sor1(); -void clock_disable_kfuse(); -void clock_enable_coresight(); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/cluster.c b/fusee/fusee-primary/src/hwinit/cluster.c deleted file mode 100644 index 90015205f..000000000 --- a/fusee/fusee-primary/src/hwinit/cluster.c +++ /dev/null @@ -1,114 +0,0 @@ -#include "cluster.h" -#include "i2c.h" -#include "clock.h" -#include "util.h" -#include "pmc.h" -#include "t210.h" - -void _cluster_enable_power() -{ - u8 tmp; - - if (i2c_recv_buf_small(&tmp, 1, I2C_5, 0x3C, 0x40)) - { - tmp &= 0xDFu; - i2c_send_byte(I2C_5, 0x3C, 0x40, tmp); - } - i2c_send_byte(I2C_5, 0x3C, 0x3B, 0x09); - - //Enable cores power. - i2c_send_byte(I2C_5, 0x1B, 0x02, 0x20); - i2c_send_byte(I2C_5, 0x1B, 0x03, 0x8D); - i2c_send_byte(I2C_5, 0x1B, 0x00, 0xB7); - i2c_send_byte(I2C_5, 0x1B, 0x01, 0xB7); -} - -int _cluster_pmc_enable_partition(u32 part, u32 toggle) -{ - //Check if the partition has already been turned on. - if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part) - return 0; - - u32 i = 5001; - while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100) - { - sleep(1); - i--; - if (i < 1) - return 0; - } - - PMC(APBDEV_PMC_PWRGATE_TOGGLE) = toggle | 0x100; - - i = 5001; - while (i > 0) - { - if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part) - break; - sleep(1); - i--; - } - - return 1; -} - -void cluster_enable_cpu0(u64 entry, u32 ns_disable) -{ - //Set ACTIVE_CLUSER to FAST. - FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= 0xFFFFFFFE; - - _cluster_enable_power(); - - if (!(CLOCK(0xE0) & 0x40000000)) - { - CLOCK(0x518) &= 0xFFFFFFF7; - sleep(2); - CLOCK(0xE4) = CLOCK(0xE4) & 0xFFFBFFFF | 0x40000; - CLOCK(0xE0) = 0x40404E02; - } - while (!(CLOCK(0xE0) & 0x8000000)) - ; - - CLOCK(0x3B4) = CLOCK(0x3B4) & 0x1FFFFF00 | 6; - CLOCK(0x360) = CLOCK(0x360) & 0xFFFFFFF7 | 8; - CLOCK(0x20) = 0x20008888; - CLOCK(0x24) = 0x80000000; - CLOCK(0x440) = 1; - - clock_enable_coresight(); - - CLOCK(0x388) = CLOCK(0x388) & 0xFFFFE000; - - //Enable CPU rail. - _cluster_pmc_enable_partition(1, 0); - //Enable cluster 0 non-CPU. - _cluster_pmc_enable_partition(0x8000, 15); - //Enable CE0. - _cluster_pmc_enable_partition(0x4000, 14); - - //Request and wait for RAM repair. - FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1; - while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2)) - ; - - EXCP_VEC(0x100) = 0; - - if(ns_disable) - { - //Set reset vectors. - SB(SB_AA64_RESET_LOW) = (u32)entry | 1; - SB(SB_AA64_RESET_HIGH) = (u32)(entry >> 32); - //Non-secure reset vector write disable. - SB(SB_CSR_0) = 2; - } - else - { - //Set reset vectors. - SB(SB_AA64_RESET_LOW) = (u32)entry; - SB(SB_AA64_RESET_HIGH) = (u32)(entry >> 32); - } - - //Until here the CPU was in reset, this kicks execution. - CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7; - CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x411F000F; -} diff --git a/fusee/fusee-primary/src/hwinit/cluster.h b/fusee/fusee-primary/src/hwinit/cluster.h deleted file mode 100644 index 41ae68f52..000000000 --- a/fusee/fusee-primary/src/hwinit/cluster.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _CLUSTER_H_ -#define _CLUSTER_H_ - -#include "types.h" - -/*! Flow controller registers. */ -#define FLOW_CTLR_RAM_REPAIR 0x40 -#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98 - -void cluster_enable_cpu0(u64 entry, u32 ns_disable); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/di.c b/fusee/fusee-primary/src/hwinit/di.c deleted file mode 100644 index a168f8dc4..000000000 --- a/fusee/fusee-primary/src/hwinit/di.c +++ /dev/null @@ -1,209 +0,0 @@ -#include "di.h" -#include "t210.h" -#include "util.h" -#include "i2c.h" -#include "pmc.h" - -#include "di.inl" - -static u32 _display_ver = 0; - -static void _display_dsi_wait(u32 timeout, u32 off, u32 mask) -{ - u32 end = TMR(0x10) + timeout; - while (TMR(0x10) < end && DSI(off) & mask) - ; - sleep(5); -} - -void display_init() -{ - //Power on. - i2c_send_byte(I2C_5, 0x3C, 0x23, 0xD0); - i2c_send_byte(I2C_5, 0x3C, 0x3D, 0x09); - - //Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. - CLOCK(0x30C) = 0x1010000; - CLOCK(0x328) = 0x1010000; - CLOCK(0x304) = 0x18000000; - CLOCK(0x320) = 0x18000000; - CLOCK(0x284) = 0x20000; - CLOCK(0x66C) = 0xA; - CLOCK(0x448) = 0x80000; - CLOCK(0x620) = 0xA; - - //DPD idle. - PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000; - PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000; - - //Config pins. - PINMUX_AUX(0x1D0) &= 0xFFFFFFEF; - PINMUX_AUX(0x1D4) &= 0xFFFFFFEF; - PINMUX_AUX(0x1FC) &= 0xFFFFFFEF; - PINMUX_AUX(0x200) &= 0xFFFFFFEF; - PINMUX_AUX(0x204) &= 0xFFFFFFEF; - - GPIO_3(0x00) = GPIO_3(0x00) & 0xFFFFFFFC | 0x3; - GPIO_3(0x10) = GPIO_3(0x10) & 0xFFFFFFFC | 0x3; - GPIO_3(0x20) = GPIO_3(0x20) & 0xFFFFFFFE | 0x1; - - sleep(10000u); - - GPIO_3(0x20) = GPIO_3(0x20) & 0xFFFFFFFD | 0x2; - - sleep(10000); - - GPIO_6(0x04) = GPIO_6(0x04) & 0xFFFFFFF8 | 0x7; - GPIO_6(0x14) = GPIO_6(0x14) & 0xFFFFFFF8 | 0x7; - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFD | 0x2; - - //Config display interface and display. - MIPI_CAL(0x60) = 0; - - exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4); - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94); - exec_cfg((u32 *)DSI_BASE, _display_config_3, 60); - - sleep(10000); - - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFB | 0x4; - - sleep(60000); - - DSI(_DSIREG(DSI_DSI_BTA_TIMING)) = 0x50204; - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x337; - DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; - _display_dsi_wait(250000, _DSIREG(DSI_DSI_TRIGGER), 3); - - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x406; - DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; - _display_dsi_wait(250000, _DSIREG(DSI_DSI_TRIGGER), 3); - - DSI(_DSIREG(DSI_HOST_DSI_CONTROL)) = 0x200B; - _display_dsi_wait(150000, _DSIREG(DSI_HOST_DSI_CONTROL), 8); - - sleep(5000); - - _display_ver = DSI(_DSIREG(DSI_DSI_RD_DATA)); - if (_display_ver == 0x10) - exec_cfg((u32 *)DSI_BASE, _display_config_4, 43); - - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x1105; - DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; - - sleep(180000); - - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x2905; - DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; - - sleep(20000); - - exec_cfg((u32 *)DSI_BASE, _display_config_5, 21); - exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3); - DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; - exec_cfg((u32 *)DSI_BASE, _display_config_7, 10); - - sleep(10000); - - exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6); - exec_cfg((u32 *)DSI_BASE, _display_config_9, 4); - exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16); - - sleep(10000); - - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113); -} - -void display_end() -{ - GPIO_6(0x24) &= 0xFFFFFFFE; - DSI(_DSIREG(DSI_DSI_VID_MODE_CONTROL)) = 1; - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x2805; - - u32 end = HOST1X(0x30A4) + 5; - while (HOST1X(0x30A4) < end) - ; - - DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = 5; - DSI(_DSIREG(DSI_DSI_VID_MODE_CONTROL)) = 0; - - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17); - exec_cfg((u32 *)DSI_BASE, _display_config_13, 16); - - sleep(10000); - - if (_display_ver == 0x10) - exec_cfg((u32 *)DSI_BASE, _display_config_14, 22); - - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x1005; - DSI(_DSIREG(DSI_DSI_TRIGGER)) = 2; - - sleep(50000); - - GPIO_6(0x24) &= 0xFFFFFFFB; - - sleep(10000); - - GPIO_3(0x20) &= 0xFFFFFFFD; - - sleep(10000); - - GPIO_3(0x20) = (GPIO_3(0x20) >> 1) << 1; - - sleep(10000); - - //Disable clocks. - CLOCK(0x308) = 0x1010000; - CLOCK(0x32C) = 0x1010000; - CLOCK(0x300) = 0x18000000; - CLOCK(0x324) = 0x18000000; - - DSI(_DSIREG(DSI_PAD_CONTROL)) = 0x10F010F; - DSI(_DSIREG(DSI_DSI_POWER_CONTROL)) = 0; - - GPIO_6(0x04) &= 0xFFFFFFFE; - - PINMUX_AUX(0x1FC) = PINMUX_AUX(0x1FC) & 0xFFFFFFEF | 0x10; - PINMUX_AUX(0x1FC) = (PINMUX_AUX(0x1FC) >> 2) << 2 | 1; -} - -void display_color_screen(u32 color) -{ - exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_one_color, 8); - - //Configure display to show single color. - DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0; - DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0; - DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0; - DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE | 1; - - sleep(35000); - - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFE | 1; -} - -void display_enable_backlight(bool on) { - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFE | !!on; -} - - -u32 *display_init_framebuffer(void *address) -{ - static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0}; - if(conf[0].val == 0) { - for (u32 i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) { - conf[i] = cfg_display_framebuffer[i]; - } - } - - u32 *lfb_addr = (u32 *)address; - - conf[19].val = (u32)address; - //This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). - exec_cfg((u32 *)DISPLAY_A_BASE, conf, 32); - - sleep(35000); - - return lfb_addr; -} diff --git a/fusee/fusee-primary/src/hwinit/di.h b/fusee/fusee-primary/src/hwinit/di.h deleted file mode 100644 index 9d482e072..000000000 --- a/fusee/fusee-primary/src/hwinit/di.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef _DI_H_ -#define _DI_H_ - -#include "types.h" -#include - -/*! Display registers. */ -#define _DIREG(reg) ((reg) * 4) -#define DC_CMD_DISPLAY_COMMAND 0x32 -#define DC_CMD_STATE_ACCESS 0x40 -#define DC_CMD_STATE_CONTROL 0x41 -#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42 -#define DC_DISP_DISP_WIN_OPTIONS 0x402 -#define DC_DISP_DISP_CLOCK_CONTROL 0x42E -#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4 -#define DC_WIN_AD_WIN_OPTIONS 0xB80 -#define DC_WIN_BD_WIN_OPTIONS 0xD80 -#define DC_WIN_CD_WIN_OPTIONS 0xF80 - -//The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER). -#define DC_X_WIN_XD_WIN_OPTIONS 0x700 -#define DC_X_WIN_XD_COLOR_DEPTH 0x703 -#define DC_X_WIN_XD_POSITION 0x704 -#define DC_X_WIN_XD_SIZE 0x705 -#define DC_X_WIN_XD_PRESCALED_SIZE 0x706 -#define DC_X_WIN_XD_H_INITIAL_DDA 0x707 -#define DC_X_WIN_XD_V_INITIAL_DDA 0x708 -#define DC_X_WIN_XD_DDA_INCREMENT 0x709 -#define DC_X_WIN_XD_LINE_STRIDE 0x70A - -//The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). -#define DC_X_WINBUF_XD_START_ADDR 0x800 -#define DC_X_WINBUF_XD_ADDR_H_OFFSET 0x806 -#define DC_X_WINBUF_XD_ADDR_V_OFFSET 0x808 -#define DC_X_WINBUF_XD_SURFACE_KIND 0x80B - -/*! Display serial interface registers. */ -#define _DSIREG(reg) ((reg) * 4) -#define DSI_DSI_RD_DATA 0x9 -#define DSI_DSI_WR_DATA 0xA -#define DSI_DSI_POWER_CONTROL 0xB -#define DSI_HOST_DSI_CONTROL 0xF -#define DSI_DSI_TRIGGER 0x13 -#define DSI_DSI_BTA_TIMING 0x3F -#define DSI_PAD_CONTROL 0x4B -#define DSI_DSI_VID_MODE_CONTROL 0x4E - -void display_init(); -void display_end(); - -/*! Show one single color on the display. */ -void display_color_screen(u32 color); - -/*! Init display in full 1280x720 resolution (32bpp, line stride 768, framebuffer size = 1280*768*4 bytes). */ -u32 *display_init_framebuffer(void *address); - -/*! Enable or disable the backlight. Should only be called when the screen is completely set up, to avoid flickering. */ -void display_enable_backlight(bool on); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/di.inl b/fusee/fusee-primary/src/hwinit/di.inl deleted file mode 100644 index b2e6d1533..000000000 --- a/fusee/fusee-primary/src/hwinit/di.inl +++ /dev/null @@ -1,532 +0,0 @@ -//Clock config. -static const cfg_op_t _display_config_1[4] = { - {0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 - {0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC -}; - -//Display A config. -static const cfg_op_t _display_config_2[94] = { - {0x40, 0}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0x43, 0x54}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0x42, 0x10}, - {0x42, 0x20}, - {0x42, 0x40}, - {0x480, 0}, - {0x403, 0}, - {0x404, 0}, - {0x36, 0x50155}, - {1, 0x100}, - {0x28, 0x109}, - {DC_CMD_STATE_CONTROL, 0xF00}, - {DC_CMD_STATE_CONTROL, 0xF}, - {0x40, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x10}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x10}, - {0x42, 0x10}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x20}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x20}, - {0x42, 0x20}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x42, 0x40}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x40}, - {0x42, 0x40}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x430, 8}, - {0x42F, 0}, - {0x307, 0x1000000}, - {0x309, 0}, - {0x4E4, 0}, - {0x300, 0}, - {DC_CMD_STATE_CONTROL, 0xF00}, - {DC_CMD_STATE_CONTROL, 0xF}, - {0x42, 0x10}, - {0x716, 0x10000FF}, - {0x42, 0x20}, - {0x716, 0x10000FF}, - {0x42, 0x40}, - {0x716, 0x10000FF}, - {0x31, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x402, 0}, - {0x32, 0}, - {DC_CMD_STATE_CONTROL, 0xF00}, - {DC_CMD_STATE_CONTROL, 0xF} -}; - -//DSI config. -static const cfg_op_t _display_config_3[60] = { - {0xA, 0}, - {0xC, 0}, - {0xD, 0}, - {0xE, 0}, - {0x1B, 0}, - {0x1C, 0}, - {0x1D, 0}, - {0x1E, 0}, - {0x33, 0}, - {0x23, 0}, - {0x25, 0}, - {0x27, 0}, - {0x29, 0}, - {0x2B, 0}, - {0x2D, 0}, - {0x24, 0}, - {0x26, 0}, - {0x28, 0}, - {0x2A, 0}, - {0x2C, 0}, - {0x2E, 0}, - {0x10, 0}, - {0x4C, 0}, - {0x11, 0x18}, - {0x12, 0x1E0}, - {0x13, 0}, - {0x1A, 0}, - {0x34, 0}, - {0x35, 0}, - {0x36, 0}, - {0x37, 0}, - {0x4F, 0}, - {0x3C, 0x6070601}, - {0x3D, 0x40A0E05}, - {0x3E, 0x30109}, - {0x3F, 0x190A14}, - {0x44, 0x2000FFFF}, - {0x45, 0x7652000}, - {0x46, 0}, - {0x4B, 0}, - {DSI_DSI_POWER_CONTROL, 1}, - {DSI_DSI_POWER_CONTROL, 1}, - {DSI_DSI_POWER_CONTROL, 0}, - {DSI_DSI_POWER_CONTROL, 0}, - {0x4F, 0}, - {0x3C, 0x6070601}, - {0x3D, 0x40A0E05}, - {0x3E, 0x30118}, - {0x3F, 0x190A14}, - {0x44, 0x2000FFFF}, - {0x45, 0x13432000}, - {0x46, 0}, - {0xF, 0x102003}, - {0x10, 0x31}, - {DSI_DSI_POWER_CONTROL, 1}, - {DSI_DSI_POWER_CONTROL, 1}, - {0x12, 0x40}, - {0x13, 0}, - {0x14, 0}, - {0x1A, 0} -}; - -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_4[43] = { - {DSI_DSI_WR_DATA, 0x439}, - {DSI_DSI_WR_DATA, 0x9483FFB9}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0xBD15}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x1939}, - {DSI_DSI_WR_DATA, 0xAAAAAAD8}, - {DSI_DSI_WR_DATA, 0xAAAAAAEB}, - {DSI_DSI_WR_DATA, 0xAAEBAAAA}, - {DSI_DSI_WR_DATA, 0xAAAAAAAA}, - {DSI_DSI_WR_DATA, 0xAAAAAAEB}, - {DSI_DSI_WR_DATA, 0xAAEBAAAA}, - {DSI_DSI_WR_DATA, 0xAA}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x1BD15}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x2739}, - {DSI_DSI_WR_DATA, 0xFFFFFFD8}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFF}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x2BD15}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0xF39}, - {DSI_DSI_WR_DATA, 0xFFFFFFD8}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFF}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0xBD15}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x6D915}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x439}, - {DSI_DSI_WR_DATA, 0xB9}, - {DSI_DSI_TRIGGER, 2} -}; - -//DSI config. -static const cfg_op_t _display_config_5[21] = { - {0x4F, 0}, - {0x3C, 0x6070601}, - {0x3D, 0x40A0E05}, - {0x3E, 0x30172}, - {0x3F, 0x190A14}, - {0x44, 0x20000A40}, - {0x45, 0x5A2F2000}, - {0x46, 0}, - {0x23, 0x40000208}, - {0x27, 0x40000308}, - {0x2B, 0x40000308}, - {0x25, 0x40000308}, - {0x29, 0x3F3B2B08}, - {0x2A, 0x2CC}, - {0x2D, 0x3F3B2B08}, - {0x2E, 0x2CC}, - {0x34, 0xCE0000}, - {0x35, 0x87001A2}, - {0x36, 0x190}, - {0x37, 0x190}, - {0xF, 0}, -}; - -//Clock config. -static const cfg_op_t _display_config_6[3] = { - {0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC -}; - -//DSI config. -static const cfg_op_t _display_config_7[10] = { - {0x13, 0}, - {0x10, 0}, - {0x11, 6}, - {0x12, 0x1E0}, - {DSI_DSI_POWER_CONTROL, 1}, - {0x10, 0x103032}, - {0xF, 0x33}, - {0x10, 0x103032}, - {0xF, 3}, - {0xF, 0x23} -}; - -//MIPI CAL config. -static const cfg_op_t _display_config_8[6] = { - {0x18, 0}, - {2, 0xF3F10000}, - {0x16, 1}, - {0x18, 0}, - {0x18, 0x10010}, - {0x17, 0x300} -}; - -//DSI config. -static const cfg_op_t _display_config_9[4] = { - {0x4F, 0}, - {0x50, 0}, - {0x51, 0x3333}, - {0x52, 0} -}; - -//MIPI CAL config. -static const cfg_op_t _display_config_10[16] = { - {0xE, 0x200200}, - {0xF, 0x200200}, - {0x19, 0x200002}, - {0x1A, 0x200002}, - {5, 0}, - {6, 0}, - {7, 0}, - {8, 0}, - {9, 0}, - {0xA, 0}, - {0x10, 0}, - {0x11, 0}, - {0x1A, 0}, - {0x1C, 0}, - {0x1D, 0}, - {0, 0x2A000001} -}; - -//Display A config. -static const cfg_op_t _display_config_11[113] = { - {0x40, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x10}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x10}, - {0x42, 0x10}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x20}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x20}, - {0x42, 0x20}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x42, 0x40}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x40}, - {0x42, 0x40}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x430, 8}, - {0x42F, 0}, - {0x307, 0x1000000}, - {0x309, 0}, - {0x4E4, 0}, - {0x300, 0}, - {DC_CMD_STATE_CONTROL, 0xF00}, - {DC_CMD_STATE_CONTROL, 0xF}, - {0x42, 0x10}, - {0x716, 0x10000FF}, - {0x42, 0x20}, - {0x716, 0x10000FF}, - {0x42, 0x40}, - {0x716, 0x10000FF}, - {0x31, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x402, 0}, - {0x32, 0}, - {DC_CMD_STATE_CONTROL, 0xF00}, - {DC_CMD_STATE_CONTROL, 0xF}, - {0x40, 0}, - {0x405, 0}, - {0x406, 0x10000}, - {0x407, 0x10048}, - {0x408, 0x90048}, - {0x409, 0x50002D0}, - {0x40A, 0xA0088}, - {0x431, 0x10001}, - {0x303, 0}, - {0x432, 5}, - {0x42F, 0}, - {0x42E, 0}, - {0x31, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x402, 0}, - {0x32, 0x20}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0x40, 5}, - {0x40A, 0xA0088}, - {0x40, 0}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0, 0x301}, - {0, 0x301}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0x40, 0}, - {0x42E, 4}, - {0x430, 8}, - {0x31, 0} -}; - -////Display A config. -static const cfg_op_t _display_config_12[17] = { - {0x40A, 0xA0088}, - {0x38, 0}, - {0x40, 0}, - {0x39, 0}, - {0x28, 0}, - {0x32, 0}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0, 0x301}, - {0, 0x301}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0x36, 0}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1} -}; - -//DSI config. -static const cfg_op_t _display_config_13[16] = { - {DSI_DSI_POWER_CONTROL, 0}, - {0x4F, 0}, - {0x3C, 0x6070601}, - {0x3D, 0x40A0E05}, - {0x3E, 0x30109}, - {0x3F, 0x190A14}, - {0x44, 0x2000FFFF}, - {0x45, 0x7652000}, - {0x46, 0}, - {0xF, 0x102003}, - {0x10, 0x31}, - {DSI_DSI_POWER_CONTROL, 1}, - {0x12, 0x40}, - {0x13, 0}, - {0x14, 0}, - {0x1A, 0} -}; - -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_14[22] = { - {DSI_DSI_WR_DATA, 0x439}, - {DSI_DSI_WR_DATA, 0x9483FFB9}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x2139}, - {DSI_DSI_WR_DATA, 0x191919D5}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0xB39}, - {DSI_DSI_WR_DATA, 0x4F0F41B1}, - {DSI_DSI_WR_DATA, 0xF179A433}, - {DSI_DSI_WR_DATA, 0x2D81}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x439}, - {DSI_DSI_WR_DATA, 0xB9}, - {DSI_DSI_TRIGGER, 2} -}; - -//Display A config. -static const cfg_op_t cfg_display_one_color[8] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x10}, //Enable window A. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x20}, //Enable window B. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x40}, //Enable window C. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE - {DC_CMD_DISPLAY_COMMAND, 0x20} //DISPLAY_CTRL_MODE: continuous display. -}; - -//Display A config. -static const cfg_op_t cfg_display_framebuffer[32] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x40}, //Enable window C. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x20}, //Enable window B. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x10}, //Enable window A. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE - {DC_X_WIN_XD_COLOR_DEPTH, 0xD}, //T_A8B8G8R8 - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_X_WIN_XD_POSITION, 0}, //(0,0) - {DC_X_WIN_XD_H_INITIAL_DDA, 0}, - {DC_X_WIN_XD_V_INITIAL_DDA, 0}, - {DC_X_WIN_XD_PRESCALED_SIZE, 0x5000B40}, //Pre-scaled size: 1280x2880 bytes (= 0x500 vertical lines x 0xB40 bytes). - {DC_X_WIN_XD_DDA_INCREMENT, 0x10001000}, - {DC_X_WIN_XD_SIZE, 0x50002D0}, //Window size: 1280x720 (= 0x500 vertical lines x 0x2D0 horizontal pixels). - {DC_X_WIN_XD_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. - {0x702, 0}, - {DC_X_WINBUF_XD_SURFACE_KIND, 0}, //Regular surface. - {DC_X_WINBUF_XD_START_ADDR, 0xC0000000}, //Framebuffer address. - {DC_X_WINBUF_XD_ADDR_H_OFFSET, 0}, - {DC_X_WINBUF_XD_ADDR_V_OFFSET, 0}, - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE - {DC_X_WIN_XD_WIN_OPTIONS, 0x40000000}, //Enable window AD. - {DC_CMD_DISPLAY_COMMAND, 0x20}, //DISPLAY_CTRL_MODE: continuous display. - {DC_CMD_STATE_CONTROL, 0x300}, //General update; window A update. - {DC_CMD_STATE_CONTROL, 3} //General activation request; window A activation request. -}; diff --git a/fusee/fusee-primary/src/hwinit/fuse.h b/fusee/fusee-primary/src/hwinit/fuse.h deleted file mode 100644 index 1f19f466f..000000000 --- a/fusee/fusee-primary/src/hwinit/fuse.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _FUSE_H_ -#define _FUSE_H_ - -#include "types.h" - -/*! Fuse registers. */ -#define FUSE_CTRL 0x0 -#define FUSE_ADDR 0x4 -#define FUSE_RDATA 0x8 -#define FUSE_WDATA 0xC -#define FUSE_TIME_RD1 0x10 -#define FUSE_TIME_RD2 0x14 -#define FUSE_TIME_PGM1 0x18 -#define FUSE_TIME_PGM2 0x1C -#define FUSE_PRIV2INTFC 0x20 -#define FUSE_FUSEBYPASS 0x24 -#define FUSE_PRIVATEKEYDISABLE 0x28 -#define FUSE_DISABLEREGPROGRAM 0x2C -#define FUSE_WRITE_ACCESS_SW 0x30 -#define FUSE_PWR_GOOD_SW 0x34 - -/*! Fuse cache registers. */ -#define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x)) - -void fuse_disable_program(); -u32 fuse_read_odm(u32 idx); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/hwinit.c b/fusee/fusee-primary/src/hwinit/hwinit.c deleted file mode 100644 index 467efdee5..000000000 --- a/fusee/fusee-primary/src/hwinit/hwinit.c +++ /dev/null @@ -1,280 +0,0 @@ -#include "clock.h" -#include "uart.h" -#include "i2c.h" -#include "sdram.h" -#include "di.h" -#include "mc.h" -#include "t210.h" -#include "pmc.h" -#include "pinmux.h" -#include "fuse.h" -#include "util.h" - -void config_oscillators() -{ - CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3 | 4; - SYSCTR0(SYSCTR0_CNTFID0) = 19200000; - TMR(0x14) = 0x45F; - CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; - PMC(APBDEV_PMC_OSC_EDPD_OVER) = PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81 | 0xE; - PMC(APBDEV_PMC_OSC_EDPD_OVER) = PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF | 0x400000; - PMC(APBDEV_PMC_CNTRL2) = PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF | 0x1000; - PMC(APBDEV_PMC_SCRATCH188) = PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF | 0x2000000; - CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; - PMC(APBDEV_PMC_TSC_MULT) = PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000 | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz) - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; - CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; -} - -void config_gpios() -{ - PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0; - PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0; - - PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = 0x40; - PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = 0x40; - - GPIO_2(0x8) = GPIO_2(0x8) & 0xFFFFFFFE | 1; - GPIO_1(0xC) = GPIO_1(0xC) & 0xFFFFFFFD | 2; - GPIO_2(0x0) = GPIO_2(0x0) & 0xFFFFFFBF | 0x40; - GPIO_2(0xC) = GPIO_2(0xC) & 0xFFFFFFBF | 0x40; - GPIO_2(0x18) &= 0xFFFFFFFE; - GPIO_1(0x1C) &= 0xFFFFFFFD; - GPIO_2(0x10) &= 0xFFFFFFBF; - GPIO_2(0x1C) &= 0xFFFFFFBF; - - pinmux_config_i2c(I2C_1); - pinmux_config_i2c(I2C_5); - pinmux_config_uart(UART_A); - - GPIO_6(0xC) = GPIO_6(0xC) & 0xFFFFFFBF | 0x40; - GPIO_6(0xC) = GPIO_6(0xC) & 0xFFFFFF7F | 0x80; - GPIO_6(0x1C) &= 0xFFFFFFBF; - GPIO_6(0x1C) &= 0xFFFFFF7F; -} - -void config_pmc_scratch() -{ - PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; - PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; - PMC(APBDEV_PMC_SECURE_SCRATCH21) |= 0x10; -} - -void mc_config_tsec_carveout(u32 bom, u32 size1mb, int lock) -{ - MC(0x670) = 0x90000000; - MC(0x674) = 1; - if (lock) - MC(0x678) = 1; -} - -void mc_config_carveout() -{ - *(vu32 *)0x8005FFFC = 0xC0EDBBCC; - MC(0x984) = 1; - MC(0x988) = 0; - MC(0x648) = 0; - MC(0x64C) = 0; - MC(0x650) = 1; - - //Official code disables and locks the carveout here. - //mc_config_tsec_carveout(0, 0, 1); - - MC(0x9A0) = 0; - MC(0x9A4) = 0; - MC(0x9A8) = 0; - MC(0x9AC) = 1; - MC(0xC0C) = 0; - MC(0xC10) = 0; - MC(0xC14) = 0; - MC(0xC18) = 0; - MC(0xC1C) = 0; - MC(0xC20) = 0; - MC(0xC24) = 0; - MC(0xC28) = 0; - MC(0xC2C) = 0; - MC(0xC30) = 0; - MC(0xC34) = 0; - MC(0xC38) = 0; - MC(0xC3C) = 0; - MC(0xC08) = 0x4000006; - MC(0xC5C) = 0x80020000; - MC(0xC60) = 0; - MC(0xC64) = 2; - MC(0xC68) = 0; - MC(0xC6C) = 0; - MC(0xC70) = 0x3000000; - MC(0xC74) = 0; - MC(0xC78) = 0x300; - MC(0xC7C) = 0; - MC(0xC80) = 0; - MC(0xC84) = 0; - MC(0xC88) = 0; - MC(0xC8C) = 0; - MC(0xC58) = 0x440167E; - MC(0xCAC) = 0; - MC(0xCB0) = 0; - MC(0xCB4) = 0; - MC(0xCB8) = 0; - MC(0xCBC) = 0; - MC(0xCC0) = 0x3000000; - MC(0xCC4) = 0; - MC(0xCC8) = 0x300; - MC(0xCCC) = 0; - MC(0xCD0) = 0; - MC(0xCD4) = 0; - MC(0xCD8) = 0; - MC(0xCDC) = 0; - MC(0xCA8) = 0x4401E7E; - MC(0xCFC) = 0; - MC(0xD00) = 0; - MC(0xD04) = 0; - MC(0xD08) = 0; - MC(0xD0C) = 0; - MC(0xD10) = 0; - MC(0xD14) = 0; - MC(0xD18) = 0; - MC(0xD1C) = 0; - MC(0xD20) = 0; - MC(0xD24) = 0; - MC(0xD28) = 0; - MC(0xD2C) = 0; - MC(0xCF8) = 0x8F; - MC(0xD4C) = 0; - MC(0xD50) = 0; - MC(0xD54) = 0; - MC(0xD58) = 0; - MC(0xD5C) = 0; - MC(0xD60) = 0; - MC(0xD64) = 0; - MC(0xD68) = 0; - MC(0xD6C) = 0; - MC(0xD70) = 0; - MC(0xD74) = 0; - MC(0xD78) = 0; - MC(0xD7C) = 0; - MC(0xD48) = 0x8F; -} - -void enable_clocks() -{ - CLOCK(0x410) = (CLOCK(0x410) | 0x8000) & 0xFFFFBFFF; - CLOCK(0xD0) |= 0x40800000u; - CLOCK(0x2AC) = 64; - CLOCK(0x294) = 0x40000; - CLOCK(0x304) = 0x18000000; - sleep(2); - - I2S(0x0A0) |= 0x400; - I2S(0x088) &= 0xFFFFFFFE; - I2S(0x1A0) |= 0x400; - I2S(0x188) &= 0xFFFFFFFE; - I2S(0x2A0) |= 0x400; - I2S(0x288) &= 0xFFFFFFFE; - I2S(0x3A0) |= 0x400; - I2S(0x388) &= 0xFFFFFFFE; - I2S(0x4A0) |= 0x400; - I2S(0x488) &= 0xFFFFFFFE; - DISPLAY_A(0xCF8) |= 4; - VIC(0x8C) = 0xFFFFFFFF; - sleep(2); - - CLOCK(0x2A8) = 0x40; - CLOCK(0x300) = 0x18000000; - CLOCK(0x290) = 0x40000; - CLOCK(0x14) = 0xC0; - CLOCK(0x10) = 0x80000130; - CLOCK(0x18) = 0x1F00200; - CLOCK(0x360) = 0x80400808; - CLOCK(0x364) = 0x402000FC; - CLOCK(0x280) = 0x23000780; - CLOCK(0x298) = 0x300; - CLOCK(0xF8) = 0; - CLOCK(0xFC) = 0; - CLOCK(0x3A0) = 0; - CLOCK(0x3A4) = 0; - CLOCK(0x554) = 0; - CLOCK(0xD0) &= 0x1F7FFFFFu; - CLOCK(0x410) &= 0xFFFF3FFF; - CLOCK(0x148) = CLOCK(0x148) & 0x1FFFFFFF | 0x80000000; - CLOCK(0x180) = CLOCK(0x180) & 0x1FFFFFFF | 0x80000000; - CLOCK(0x6A0) = CLOCK(0x6A0) & 0x1FFFFFFF | 0x80000000; -} - -void mc_enable_ahb_redirect() -{ - CLOCK(0x3A4) = CLOCK(0x3A4) & 0xFFF7FFFF | 0x80000; - //MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE; - MC(MC_IRAM_BOM) = 0x40000000; - MC(MC_IRAM_TOM) = 0x4003F000; -} - -void mc_disable_ahb_redirect() -{ - MC(MC_IRAM_BOM) = 0xFFFFF000; - MC(MC_IRAM_TOM) = 0; - //Disable IRAM_CFG_WRITE_ACCESS (sticky). - //MC(MC_IRAM_REG_CTRL) = MC(MC_IRAM_REG_CTRL) & 0xFFFFFFFE | 1; - CLOCK(0x3A4) &= 0xFFF7FFFF; -} - -void mc_enable() -{ - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF | 0x40000000; - //Enable MIPI CAL clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFDFFFFFF | 0x2000000; - //Enable MC clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE | 1; - //Enable EMC DLL clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF | 0x4000; - CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x2000001; //Clear EMC and MC reset. - sleep(5); -} - -clock_t clock_unk1 = { 0x358, 0x360, 0x42C, 0x1F, 0, 0 }; -clock_t clock_unk2 = { 0x358, 0x360, 0, 0x1E, 0, 0 }; - -void nx_hwinit() -{ - enable_clocks(); - clock_enable_se(); - clock_enable_fuse(1); - fuse_disable_program(); - - mc_enable(); - - config_oscillators(); - _REG(0x70000000, 0x40) = 0; - - config_gpios(); - - clock_enable_i2c(I2C_1); - clock_enable_i2c(I2C_5); - clock_enable(&clock_unk1); - clock_enable(&clock_unk2); - - i2c_init(I2C_1); - i2c_init(I2C_5); - - //Config PMIC (TODO: use max77620.h) - i2c_send_byte(I2C_5, 0x3C, 4, 0x40); - i2c_send_byte(I2C_5, 0x3C, 0x41, 0x78); - i2c_send_byte(I2C_5, 0x3C, 0x43, 0x38); - i2c_send_byte(I2C_5, 0x3C, 0x44, 0x3A); - i2c_send_byte(I2C_5, 0x3C, 0x45, 0x38); - i2c_send_byte(I2C_5, 0x3C, 0x4A, 0xF); - i2c_send_byte(I2C_5, 0x3C, 0x4E, 0xC7); - i2c_send_byte(I2C_5, 0x3C, 0x4F, 0x4F); - i2c_send_byte(I2C_5, 0x3C, 0x50, 0x29); - i2c_send_byte(I2C_5, 0x3C, 0x52, 0x1B); - i2c_send_byte(I2C_5, 0x3C, 0x16, 42); //42 = (1000 * 1125 - 600000) / 12500 - - config_pmc_scratch(); - - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888 | 0x3333; - - mc_config_carveout(); - - sdram_init(); -} diff --git a/fusee/fusee-primary/src/hwinit/hwinit.h b/fusee/fusee-primary/src/hwinit/hwinit.h deleted file mode 100644 index fda89d4f4..000000000 --- a/fusee/fusee-primary/src/hwinit/hwinit.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _HWINIT_H_ -#define _HWINIT_H_ - -void mc_config_tsec_carveout(u32 bom, u32 size1mb, int lock); -void mc_enable_ahb_redirect(); -void mc_disable_ahb_redirect(); -void nx_hwinit(); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/hwinit_fuse.c b/fusee/fusee-primary/src/hwinit/hwinit_fuse.c deleted file mode 100644 index 80fa85788..000000000 --- a/fusee/fusee-primary/src/hwinit/hwinit_fuse.c +++ /dev/null @@ -1,12 +0,0 @@ -#include "fuse.h" -#include "t210.h" - -void fuse_disable_program() -{ - FUSE(FUSE_DISABLEREGPROGRAM) = 1; -} - -u32 fuse_read_odm(u32 idx) -{ - return FUSE(FUSE_RESERVED_ODMX(idx)); -} diff --git a/fusee/fusee-primary/src/hwinit/i2c.c b/fusee/fusee-primary/src/hwinit/i2c.c deleted file mode 100644 index b44b9ffa5..000000000 --- a/fusee/fusee-primary/src/hwinit/i2c.c +++ /dev/null @@ -1,116 +0,0 @@ -#include - -#include "i2c.h" -#include "util.h" - -static u32 i2c_addrs[] = { 0x7000C000, 0x7000C400, 0x7000C500, 0x7000C700, 0x7000D000, 0x7000D100 }; - -static void _i2c_wait(vu32 *base) -{ - base[0x23] = 0x25; - for (u32 i = 0; i < 20; i++) - { - sleep(1); - if (!(base[0x23] & 1)) - break; - } -} - -static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size) -{ - if (size > 4) - return 0; - - u32 tmp = 0; - memcpy(&tmp, buf, size); - - vu32 *base = (vu32 *)i2c_addrs[idx]; - base[1] = x << 1; //Set x (send mode). - base[3] = tmp; //Set value. - base[0] = (2 * size - 2) | 0x2800; //Set size and send mode. - _i2c_wait(base); //Kick transaction. - - base[0] = base[0] & 0xFFFFFDFF | 0x200; - while (base[7] & 0x100) - ; - - if (base[7] << 28) - return 0; - - return 1; -} - -static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x) -{ - if (size > 4) - return 0; - - vu32 *base = (vu32 *)i2c_addrs[idx]; - base[1] = (x << 1) | 1; //Set x (recv mode). - base[0] = (2 * size - 2) | 0x2840; //Set size and recv mode. - _i2c_wait(base); //Kick transaction. - - base[0] = base[0] & 0xFFFFFDFF | 0x200; - while (base[7] & 0x100) - ; - - if (base[7] << 28) - return 0; - - u32 tmp = base[3]; //Get value. - memcpy(buf, &tmp, size); - - return 1; -} - -void i2c_init(u32 idx) -{ - vu32 *base = (vu32 *)i2c_addrs[idx]; - - base[0x1B] = 0x50001; - base[0x21] = 0x90003; - _i2c_wait(base); - - for (u32 i = 0; i < 10; i++) - { - sleep(20000); - if (base[0x1A] & 0x800) - break; - } - - vu32 dummy = base[0x22]; - base[0x1A] = base[0x1A]; -} - -int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size) -{ - u8 tmp[4]; - - if (size > 3) - return 0; - - tmp[0] = y; - memcpy(tmp + 1, buf, size); - - return _i2c_send_pkt(idx, x, tmp, size + 1); -} - -int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y) -{ - int res = _i2c_send_pkt(idx, x, (u8 *)&y, 1); - if (res) - res = _i2c_recv_pkt(idx, buf, size, x); - return res; -} - -void i2c_send_byte(u32 idx, u32 x, u32 y, u8 b) -{ - i2c_send_buf_small(idx, x, y, &b, 1); -} - -u8 i2c_recv_byte(u32 idx, u32 x, u32 y) -{ - u8 tmp; - i2c_recv_buf_small(&tmp, 1, idx, x, y); - return tmp; -} diff --git a/fusee/fusee-primary/src/hwinit/i2c.h b/fusee/fusee-primary/src/hwinit/i2c.h deleted file mode 100644 index 921533d6b..000000000 --- a/fusee/fusee-primary/src/hwinit/i2c.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _I2C_H_ -#define _I2C_H_ - -#include "types.h" - -#define I2C_1 0 -#define I2C_2 1 -#define I2C_3 2 -#define I2C_4 3 -#define I2C_5 4 -#define I2C_6 5 - -void i2c_init(u32 idx); -int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size); -int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y); -void i2c_send_byte(u32 idx, u32 x, u32 y, u8 b); -u8 i2c_recv_byte(u32 idx, u32 x, u32 y); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/max77620.h b/fusee/fusee-primary/src/hwinit/max77620.h deleted file mode 100644 index 7223067dc..000000000 --- a/fusee/fusee-primary/src/hwinit/max77620.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Defining registers address and its bit definitions of MAX77620 and MAX20024 - * - * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - */ - -#ifndef _MFD_MAX77620_H_ -#define _MFD_MAX77620_H_ - -/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */ -#define MAX77620_REG_CNFGGLBL1 0x00 -#define MAX77620_REG_CNFGGLBL2 0x01 -#define MAX77620_REG_CNFGGLBL3 0x02 -#define MAX77620_REG_CNFG1_32K 0x03 -#define MAX77620_REG_CNFGBBC 0x04 -#define MAX77620_REG_IRQTOP 0x05 -#define MAX77620_REG_INTLBT 0x06 -#define MAX77620_REG_IRQSD 0x07 -#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 -#define MAX77620_REG_IRQ_LVL2_L8 0x09 -#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A -#define MAX77620_REG_ONOFFIRQ 0x0B -#define MAX77620_REG_NVERC 0x0C -#define MAX77620_REG_IRQTOPM 0x0D -#define MAX77620_REG_INTENLBT 0x0E -#define MAX77620_REG_IRQMASKSD 0x0F -#define MAX77620_REG_IRQ_MSK_L0_7 0x10 -#define MAX77620_REG_IRQ_MSK_L8 0x11 -#define MAX77620_REG_ONOFFIRQM 0x12 -#define MAX77620_REG_STATLBT 0x13 -#define MAX77620_REG_STATSD 0x14 -#define MAX77620_REG_ONOFFSTAT 0x15 - -/* SD and LDO Registers */ -#define MAX77620_REG_SD0 0x16 -#define MAX77620_REG_SD1 0x17 -#define MAX77620_REG_SD2 0x18 -#define MAX77620_REG_SD3 0x19 -#define MAX77620_REG_SD4 0x1A -#define MAX77620_REG_DVSSD0 0x1B -#define MAX77620_REG_DVSSD1 0x1C -#define MAX77620_REG_SD0_CFG 0x1D -#define MAX77620_REG_SD1_CFG 0x1E -#define MAX77620_REG_SD2_CFG 0x1F -#define MAX77620_REG_SD3_CFG 0x20 -#define MAX77620_REG_SD4_CFG 0x21 -#define MAX77620_REG_SD_CFG2 0x22 -#define MAX77620_REG_LDO0_CFG 0x23 -#define MAX77620_REG_LDO0_CFG2 0x24 -#define MAX77620_REG_LDO1_CFG 0x25 -#define MAX77620_REG_LDO1_CFG2 0x26 -#define MAX77620_REG_LDO2_CFG 0x27 -#define MAX77620_REG_LDO2_CFG2 0x28 -#define MAX77620_REG_LDO3_CFG 0x29 -#define MAX77620_REG_LDO3_CFG2 0x2A -#define MAX77620_REG_LDO4_CFG 0x2B -#define MAX77620_REG_LDO4_CFG2 0x2C -#define MAX77620_REG_LDO5_CFG 0x2D -#define MAX77620_REG_LDO5_CFG2 0x2E -#define MAX77620_REG_LDO6_CFG 0x2F -#define MAX77620_REG_LDO6_CFG2 0x30 -#define MAX77620_REG_LDO7_CFG 0x31 -#define MAX77620_REG_LDO7_CFG2 0x32 -#define MAX77620_REG_LDO8_CFG 0x33 -#define MAX77620_REG_LDO8_CFG2 0x34 -#define MAX77620_REG_LDO_CFG3 0x35 - -#define MAX77620_LDO_SLEW_RATE_MASK 0x1 - -/* LDO Configuration 3 */ -#define MAX77620_TRACK4_MASK (1 << 5) -#define MAX77620_TRACK4_SHIFT 5 - -/* Voltage */ -#define MAX77620_SDX_VOLT_MASK 0xFF -#define MAX77620_SD0_VOLT_MASK 0x3F -#define MAX77620_SD1_VOLT_MASK 0x7F -#define MAX77620_LDO_VOLT_MASK 0x3F - -#define MAX77620_REG_GPIO0 0x36 -#define MAX77620_REG_GPIO1 0x37 -#define MAX77620_REG_GPIO2 0x38 -#define MAX77620_REG_GPIO3 0x39 -#define MAX77620_REG_GPIO4 0x3A -#define MAX77620_REG_GPIO5 0x3B -#define MAX77620_REG_GPIO6 0x3C -#define MAX77620_REG_GPIO7 0x3D -#define MAX77620_REG_PUE_GPIO 0x3E -#define MAX77620_REG_PDE_GPIO 0x3F -#define MAX77620_REG_AME_GPIO 0x40 -#define MAX77620_REG_ONOFFCNFG1 0x41 -#define MAX77620_REG_ONOFFCNFG2 0x42 - -/* FPS Registers */ -#define MAX77620_REG_FPS_CFG0 0x43 -#define MAX77620_REG_FPS_CFG1 0x44 -#define MAX77620_REG_FPS_CFG2 0x45 -#define MAX77620_REG_FPS_LDO0 0x46 -#define MAX77620_REG_FPS_LDO1 0x47 -#define MAX77620_REG_FPS_LDO2 0x48 -#define MAX77620_REG_FPS_LDO3 0x49 -#define MAX77620_REG_FPS_LDO4 0x4A -#define MAX77620_REG_FPS_LDO5 0x4B -#define MAX77620_REG_FPS_LDO6 0x4C -#define MAX77620_REG_FPS_LDO7 0x4D -#define MAX77620_REG_FPS_LDO8 0x4E -#define MAX77620_REG_FPS_SD0 0x4F -#define MAX77620_REG_FPS_SD1 0x50 -#define MAX77620_REG_FPS_SD2 0x51 -#define MAX77620_REG_FPS_SD3 0x52 -#define MAX77620_REG_FPS_SD4 0x53 -#define MAX77620_REG_FPS_NONE 0 - -#define MAX77620_FPS_SRC_MASK 0xC0 -#define MAX77620_FPS_SRC_SHIFT 6 -#define MAX77620_FPS_PU_PERIOD_MASK 0x38 -#define MAX77620_FPS_PU_PERIOD_SHIFT 3 -#define MAX77620_FPS_PD_PERIOD_MASK 0x07 -#define MAX77620_FPS_PD_PERIOD_SHIFT 0 -#define MAX77620_FPS_TIME_PERIOD_MASK 0x38 -#define MAX77620_FPS_TIME_PERIOD_SHIFT 3 -#define MAX77620_FPS_EN_SRC_MASK 0x06 -#define MAX77620_FPS_EN_SRC_SHIFT 1 -#define MAX77620_FPS_ENFPS_SW_MASK 0x01 -#define MAX77620_FPS_ENFPS_SW 0x01 - -/* Minimum and maximum FPS period time (in microseconds) are - * different for MAX77620 and Max20024. - */ -#define MAX77620_FPS_PERIOD_MIN_US 40 -#define MAX20024_FPS_PERIOD_MIN_US 20 - -#define MAX77620_FPS_PERIOD_MAX_US 2560 -#define MAX20024_FPS_PERIOD_MAX_US 5120 - -#define MAX77620_REG_FPS_GPIO1 0x54 -#define MAX77620_REG_FPS_GPIO2 0x55 -#define MAX77620_REG_FPS_GPIO3 0x56 -#define MAX77620_REG_FPS_RSO 0x57 -#define MAX77620_REG_CID0 0x58 -#define MAX77620_REG_CID1 0x59 -#define MAX77620_REG_CID2 0x5A -#define MAX77620_REG_CID3 0x5B -#define MAX77620_REG_CID4 0x5C -#define MAX77620_REG_CID5 0x5D - -#define MAX77620_REG_DVSSD4 0x5E -#define MAX20024_REG_MAX_ADD 0x70 - -#define MAX77620_CID_DIDM_MASK 0xF0 -#define MAX77620_CID_DIDM_SHIFT 4 - -/* CNCG2SD */ -#define MAX77620_SD_CNF2_ROVS_EN_SD1 (1 << 1) -#define MAX77620_SD_CNF2_ROVS_EN_SD0 (1 << 2) - -/* Device Identification Metal */ -#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF) -/* Device Indentification OTP */ -#define MAX77620_CID5_DIDO(n) ((n) & 0xF) - -/* SD CNFG1 */ -#define MAX77620_SD_SR_MASK 0xC0 -#define MAX77620_SD_SR_SHIFT 6 -#define MAX77620_SD_POWER_MODE_MASK 0x30 -#define MAX77620_SD_POWER_MODE_SHIFT 4 -#define MAX77620_SD_CFG1_ADE_MASK (1 << 3) -#define MAX77620_SD_CFG1_ADE_DISABLE 0 -#define MAX77620_SD_CFG1_ADE_ENABLE (1 << 3) -#define MAX77620_SD_FPWM_MASK 0x04 -#define MAX77620_SD_FPWM_SHIFT 2 -#define MAX77620_SD_FSRADE_MASK 0x01 -#define MAX77620_SD_FSRADE_SHIFT 0 -#define MAX77620_SD_CFG1_FPWM_SD_MASK (1 << 2) -#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0 -#define MAX77620_SD_CFG1_FPWM_SD_FPWM (1 << 2) -#define MAX20024_SD_CFG1_MPOK_MASK (1 << 1) -#define MAX77620_SD_CFG1_FSRADE_SD_MASK (1 << 0) -#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0 -#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0) - -/* LDO_CNFG2 */ -#define MAX77620_LDO_POWER_MODE_MASK 0xC0 -#define MAX77620_LDO_POWER_MODE_SHIFT 6 -#define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2) -#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1) -#define MAX77620_LDO_CFG2_ADE_DISABLE 0 -#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1) -#define MAX77620_LDO_CFG2_SS_MASK (1 << 0) -#define MAX77620_LDO_CFG2_SS_FAST (1 << 0) -#define MAX77620_LDO_CFG2_SS_SLOW 0 - -#define MAX77620_IRQ_TOP_GLBL_MASK (1 << 7) -#define MAX77620_IRQ_TOP_SD_MASK (1 << 6) -#define MAX77620_IRQ_TOP_LDO_MASK (1 << 5) -#define MAX77620_IRQ_TOP_GPIO_MASK (1 << 4) -#define MAX77620_IRQ_TOP_RTC_MASK (1 << 3) -#define MAX77620_IRQ_TOP_32K_MASK (1 << 2) -#define MAX77620_IRQ_TOP_ONOFF_MASK (1 << 1) - -#define MAX77620_IRQ_LBM_MASK (1 << 3) -#define MAX77620_IRQ_TJALRM1_MASK (1 << 2) -#define MAX77620_IRQ_TJALRM2_MASK (1 << 1) - -#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0 -#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1) -#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1) -#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0 -#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0 -#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4) -#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4) -#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5) -#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6) -#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6) -#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6) -#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6) -#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6) - -#define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0) -#define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1) -#define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2) -#define MAX77620_IRQ_LVL2_GPIO_EDGE3 (1 << 3) -#define MAX77620_IRQ_LVL2_GPIO_EDGE4 (1 << 4) -#define MAX77620_IRQ_LVL2_GPIO_EDGE5 (1 << 5) -#define MAX77620_IRQ_LVL2_GPIO_EDGE6 (1 << 6) -#define MAX77620_IRQ_LVL2_GPIO_EDGE7 (1 << 7) - -#define MAX77620_CNFG1_32K_OUT0_EN (1 << 2) - -#define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7) -#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38 -#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3 -#define MAX77620_ONOFFCNFG1_SLPEN (1 << 2) -#define MAX77620_ONOFFCNFG1_PWR_OFF (1 << 1) -#define MAX20024_ONOFFCNFG1_CLRSE 0x18 - -#define MAX77620_ONOFFCNFG2_SFT_RST_WK (1 << 7) -#define MAX77620_ONOFFCNFG2_WD_RST_WK (1 << 6) -#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK (1 << 5) -#define MAX77620_ONOFFCNFG2_WK_ALARM1 (1 << 2) -#define MAX77620_ONOFFCNFG2_WK_EN0 (1 << 0) - -#define MAX77620_GLBLM_MASK (1 << 0) - -#define MAX77620_WDTC_MASK 0x3 -#define MAX77620_WDTOFFC (1 << 4) -#define MAX77620_WDTSLPC (1 << 3) -#define MAX77620_WDTEN (1 << 2) - -#define MAX77620_TWD_MASK 0x3 -#define MAX77620_TWD_2s 0x0 -#define MAX77620_TWD_16s 0x1 -#define MAX77620_TWD_64s 0x2 -#define MAX77620_TWD_128s 0x3 - -#define MAX77620_CNFGGLBL1_LBDAC_EN (1 << 7) -#define MAX77620_CNFGGLBL1_MPPLD (1 << 6) -#define MAX77620_CNFGGLBL1_LBHYST ((1 << 5) | (1 << 4)) -#define MAX77620_CNFGGLBL1_LBDAC 0x0E -#define MAX77620_CNFGGLBL1_LBRSTEN (1 << 0) - -/* CNFG BBC registers */ -#define MAX77620_CNFGBBC_ENABLE (1 << 0) -#define MAX77620_CNFGBBC_CURRENT_MASK 0x06 -#define MAX77620_CNFGBBC_CURRENT_SHIFT 1 -#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18 -#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3 -#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5) -#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0 -#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6 - -#define MAX77620_FPS_COUNT 3 - -/* Interrupts */ -enum { - MAX77620_IRQ_TOP_GLBL, /* Low-Battery */ - MAX77620_IRQ_TOP_SD, /* SD power fail */ - MAX77620_IRQ_TOP_LDO, /* LDO power fail */ - MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */ - MAX77620_IRQ_TOP_RTC, /* RTC */ - MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */ - MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */ - MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */ - MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */ - MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */ -}; - -/* GPIOs */ -enum { - MAX77620_GPIO0, - MAX77620_GPIO1, - MAX77620_GPIO2, - MAX77620_GPIO3, - MAX77620_GPIO4, - MAX77620_GPIO5, - MAX77620_GPIO6, - MAX77620_GPIO7, - MAX77620_GPIO_NR, -}; - -/* FPS Source */ -enum max77620_fps_src { - MAX77620_FPS_SRC_0, - MAX77620_FPS_SRC_1, - MAX77620_FPS_SRC_2, - MAX77620_FPS_SRC_NONE, - MAX77620_FPS_SRC_DEF, -}; - -enum max77620_chip_id { - MAX77620, - MAX20024, -}; - -#endif /* _MFD_MAX77620_H_ */ diff --git a/fusee/fusee-primary/src/hwinit/max7762x.c b/fusee/fusee-primary/src/hwinit/max7762x.c deleted file mode 100755 index 67caaf230..000000000 --- a/fusee/fusee-primary/src/hwinit/max7762x.c +++ /dev/null @@ -1,136 +0,0 @@ -/* -* Copyright (c) 2018 naehrwert -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . -*/ - -#include "max7762x.h" -#include "max77620.h" -#include "i2c.h" -#include "util.h" - -#define REGULATOR_SD 0 -#define REGULATOR_LDO 1 - -typedef struct _max77620_regulator_t -{ - u8 type; - const char *name; - u8 reg_sd; - u32 mv_step; - u32 mv_min; - u32 mv_default; - u32 mv_max; - u8 volt_addr; - u8 cfg_addr; - u8 volt_mask; - u8 enable_mask; - u8 enable_shift; - u8 status_mask; - - u8 fps_addr; - u8 fps_src; - u8 pd_period; - u8 pu_period; -} max77620_regulator_t; - -static const max77620_regulator_t _pmic_regulators[] = { - { REGULATOR_SD, "sd0", 0x16, 12500, 600000, 625000, 1400000, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, 0x3F, 0x30, 4, 0x80, 0x4F, 1, 7, 1 }, - { REGULATOR_SD, "sd1", 0x17, 12500, 600000, 1125000, 1125000, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, 0x3F, 0x30, 4, 0x40, 0x50, 0, 1, 5 }, - { REGULATOR_SD, "sd2", 0x18, 12500, 600000, 1325000, 1350000, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, 0xFF, 0x30, 4, 0x20, 0x51, 1, 5, 2 }, - { REGULATOR_SD, "sd3", 0x19, 12500, 600000, 1800000, 1800000, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, 0xFF, 0x30, 4, 0x10, 0x52, 0, 3, 3 }, - { REGULATOR_LDO, "ldo0", 0x00, 25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, 0x3F, 0xC0, 6, 0x00, 0x46, 3, 7, 0 }, - { REGULATOR_LDO, "ldo1", 0x00, 25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, 0x3F, 0xC0, 6, 0x00, 0x47, 3, 7, 0 }, - { REGULATOR_LDO, "ldo2", 0x00, 50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, 0x3F, 0xC0, 6, 0x00, 0x48, 3, 7, 0 }, - { REGULATOR_LDO, "ldo3", 0x00, 50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, 0x3F, 0xC0, 6, 0x00, 0x49, 3, 7, 0 }, - { REGULATOR_LDO, "ldo4", 0x00, 12500, 800000, 850000, 850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4A, 0, 7, 1 }, - { REGULATOR_LDO, "ldo5", 0x00, 50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4B, 3, 7, 0 }, - { REGULATOR_LDO, "ldo6", 0x00, 50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4C, 3, 7, 0 }, - { REGULATOR_LDO, "ldo7", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4D, 1, 4, 3 }, - { REGULATOR_LDO, "ldo8", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4E, 3, 7, 0 } -}; - -int max77620_regulator_get_status(u32 id) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - - if (reg->type == REGULATOR_SD) - return i2c_recv_byte(I2C_5, 0x3C, MAX77620_REG_STATSD) & reg->status_mask ? 0 : 1; - return i2c_recv_byte(I2C_5, 0x3C, reg->cfg_addr) & 8 ? 1 : 0; -} - -int max77620_regulator_config_fps(u32 id) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - - i2c_send_byte(I2C_5, 0x3C, reg->fps_addr, (reg->fps_src << 6) | (reg->pu_period << 3) | (reg->pd_period)); - - return 1; -} - -int max77620_regulator_set_voltage(u32 id, u32 mv) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - - if (mv < reg->mv_default || mv > reg->mv_max) - return 0; - - u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step; - u8 val = i2c_recv_byte(I2C_5, 0x3C, reg->volt_addr); - val = (val & ~reg->volt_mask) | (mult & reg->volt_mask); - i2c_send_byte(I2C_5, 0x3C, reg->volt_addr, val); - sleep(1000); - - return 1; -} - -int max77620_regulator_enable(u32 id, int enable) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - - u32 addr = reg->type == REGULATOR_SD ? reg->cfg_addr : reg->volt_addr; - u8 val = i2c_recv_byte(I2C_5, 0x3C, addr); - if (enable) - val = (val & ~reg->enable_mask) | ((3 << reg->enable_shift) & reg->enable_mask); - else - val &= ~reg->enable_mask; - i2c_send_byte(I2C_5, 0x3C, addr, val); - sleep(1000); - - return 1; -} - -void max77620_config_default() -{ - for (u32 i = 1; i <= REGULATOR_MAX; i++) - { - i2c_recv_byte(I2C_5, 0x3C, MAX77620_REG_CID4); - max77620_regulator_config_fps(i); - max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default); - if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE) - max77620_regulator_enable(i, 1); - } - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_SD_CFG2, 4); -} diff --git a/fusee/fusee-primary/src/hwinit/pinmux.c b/fusee/fusee-primary/src/hwinit/pinmux.c deleted file mode 100644 index 269c91a57..000000000 --- a/fusee/fusee-primary/src/hwinit/pinmux.c +++ /dev/null @@ -1,16 +0,0 @@ -#include "pinmux.h" -#include "t210.h" - -void pinmux_config_uart(u32 idx) -{ - PINMUX_AUX(PINMUX_AUX_UARTX_RX(idx)) = 0; - PINMUX_AUX(PINMUX_AUX_UARTX_TX(idx)) = 0x48; - PINMUX_AUX(PINMUX_AUX_UARTX_RTS(idx)) = 0; - PINMUX_AUX(PINMUX_AUX_UARTX_CTS(idx)) = 0x44; -} - -void pinmux_config_i2c(u32 idx) -{ - PINMUX_AUX(PINMUX_AUX_X_I2C_SCL(idx)) = 0x40; - PINMUX_AUX(PINMUX_AUX_X_I2C_SDA(idx)) = 0x40; -} diff --git a/fusee/fusee-primary/src/hwinit/pinmux.h b/fusee/fusee-primary/src/hwinit/pinmux.h deleted file mode 100644 index 59bf506d8..000000000 --- a/fusee/fusee-primary/src/hwinit/pinmux.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _PINMUX_H_ -#define _PINMUX_H_ - -#include "types.h" - -/*! Pinmux registers. */ -#define PINMUX_AUX_UART2_TX 0xF4 -#define PINMUX_AUX_UART3_TX 0x104 -#define PINMUX_AUX_GPIO_PE6 0x248 -#define PINMUX_AUX_GPIO_PH6 0x250 -/*! 0:UART-A, 1:UART-B, 3:UART-C, 3:UART-D */ -#define PINMUX_AUX_UARTX_TX(x) (0xE4 + 0x10 * (x)) -#define PINMUX_AUX_UARTX_RX(x) (0xE8 + 0x10 * (x)) -#define PINMUX_AUX_UARTX_RTS(x) (0xEC + 0x10 * (x)) -#define PINMUX_AUX_UARTX_CTS(x) (0xF0 + 0x10 * (x)) -/*! 0:GEN1, 1:GEN2, 2:GEN3, 3:CAM, 4:PWR */ -#define PINMUX_AUX_X_I2C_SCL(x) (0xBC + 8 * (x)) -#define PINMUX_AUX_X_I2C_SDA(x) (0xC0 + 8 * (x)) - -void pinmux_config_uart(u32 idx); -void pinmux_config_i2c(u32 idx); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/pmc.h b/fusee/fusee-primary/src/hwinit/pmc.h deleted file mode 100644 index 4c8677239..000000000 --- a/fusee/fusee-primary/src/hwinit/pmc.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _PMC_H_ -#define _PMC_H_ - -/*! PMC registers. */ -#define APBDEV_PMC_PWRGATE_TOGGLE 0x30 -#define APBDEV_PMC_PWRGATE_STATUS 0x38 -#define APBDEV_PMC_NO_IOPOWER 0x44 -#define APBDEV_PMC_SCRATCH20 0xA0 -#define APBDEV_PMC_DDR_PWR 0xE8 -#define APBDEV_PMC_CRYPTO_OP 0xF4 -#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4 -#define APBDEV_PMC_IO_DPD_REQ 0x1B8 -#define APBDEV_PMC_IO_DPD2_REQ 0x1C0 -#define APBDEV_PMC_VDDP_SEL 0x1CC -#define APBDEV_PMC_TSC_MULT 0x2B4 -#define APBDEV_PMC_REG_SHORT 0x2CC -#define APBDEV_PMC_WEAK_BIAS 0x2C8 -#define APBDEV_PMC_SECURE_SCRATCH21 0x334 -#define APBDEV_PMC_CNTRL2 0x440 -#define APBDEV_PMC_IO_DPD4_REQ 0x464 -#define APBDEV_PMC_DDR_CNTRL 0x4E4 -#define APBDEV_PMC_SCRATCH188 0x810 -#define APBDEV_PMC_SCRATCH190 0x818 -#define APBDEV_PMC_SCRATCH200 0x840 - -#endif diff --git a/fusee/fusee-primary/src/hwinit/sdram.c b/fusee/fusee-primary/src/hwinit/sdram.c deleted file mode 100644 index a64d7b886..000000000 --- a/fusee/fusee-primary/src/hwinit/sdram.c +++ /dev/null @@ -1,488 +0,0 @@ -#include "i2c.h" -#include "t210.h" -#include "mc.h" -//#include "emc.h" -#include "pmc.h" -#include "util.h" -#include "fuse.h" - -#include "sdram.inl" - -static u32 _get_sdram_id() -{ - return (fuse_read_odm(4) & 0x38) >> 3; -} - -static void _sdram_config(const u32 *_cfg) -{ - const u32 *_cfg_120 = _cfg + 0x120; - const u32 *_cfg_100 = _cfg + 0x100; - - PMC(0x45C) = (((4 * _cfg[0x12F] >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF; - sleep(_cfg[0x111]); - - u32 req = (4 * _cfg_120[0x10] >> 2) + 0x80000000; - PMC(APBDEV_PMC_IO_DPD4_REQ) = (req ^ 0x3FFF0000) >> 16 << 16; - sleep(_cfg_100[0x12]); - PMC(APBDEV_PMC_IO_DPD4_REQ) = (req ^ 0xFFFF) & 0xC000FFFF; - sleep(_cfg_100[0x12]); - PMC(APBDEV_PMC_WEAK_BIAS) = 0; - sleep(1); - - CLOCK(0x98) = _cfg[4]; - CLOCK(0x9C) = 0; - CLOCK(0x90) = (_cfg[2] << 8) | (*((u16 *)_cfg + 0xA) << 20) | _cfg[1] | 0x40000000; - - u32 wait_end = TMR(0x10) + 300; - while (!((CLOCK(0x90) >> 27) & 1)) - { - if (TMR(0x10) >= wait_end) - goto break_nosleep; - } - sleep(10); -break_nosleep: - - CLOCK(0x19C) = _cfg[0x16] & 0xFFFEFFFF | (_cfg[0x175] >> 11) & 0x10000; - if (_cfg[0x17]) - CLOCK(0x664) = _cfg[0x17]; - if (_cfg[0x1A]) - CLOCK(0x44C) = 0x40000000; - CLOCK(0x328) = 0x2000001; - CLOCK(0x284) = 0x4000; - CLOCK(0x30C) = 0x2000001; - EMC(0xC34) = _cfg_120[0x13]; - EMC(0xC38) = _cfg_120[0x14]; - EMC(0xCF0) = _cfg_120[0x15]; - EMC(0x28) = 1; - sleep(1); - EMC(0x8) = _cfg[0xA9] | 2 * _cfg[0xAA]; - if (_cfg[0xA]) - *(vu32 *)_cfg[0xA] = _cfg[0xB]; - EMC(0x584) = _cfg[0x7B]; - EMC(0x380) = _cfg[0x7D]; - EMC(0x384) = _cfg[0x7E]; - EMC(0x388) = _cfg[0x7F]; - EMC(0x38C) = _cfg[0x80]; - EMC(0x390) = _cfg[0x81]; - EMC(0x394) = _cfg[0x82]; - EMC(0x398) = _cfg[0x83]; - EMC(0x39C) = _cfg[0x84]; - EMC(0x3A0) = _cfg[0x85]; - EMC(0x3A4) = _cfg[0x86]; - EMC(0x3A8) = _cfg[0x87]; - EMC(0x3AC) = _cfg[0x88]; - EMC(0x3B0) = _cfg[0x89]; - EMC(0xC80) = _cfg[0x14A]; - EMC(0xC84) = _cfg[0x14B]; - EMC(0xC88) = _cfg[0x14C]; - EMC(0x330) = (_cfg_120[0x16] | 0xFEEDFEED) & 0x1FFF1FFF; - EMC(0x5F0) = _cfg[0x149]; - EMC(0x5C8) = _cfg[0x7C]; - EMC(0x404) = _cfg_100[0x18]; - EMC(0x408) = _cfg_100[0x19]; - EMC(0x40C) = _cfg_100[0x1A]; - EMC(0x410) = _cfg_100[0x1B]; - EMC(0x418) = _cfg_100[0x1C]; - EMC(0x41C) = _cfg_100[0x1D]; - EMC(0x420) = _cfg_100[0x1E]; - EMC(0x424) = _cfg_100[0x1F]; - if (_cfg[0xE]) - *(vu32 *)_cfg[0xE] = _cfg[0xF]; - EMC(0x30C) = _cfg[0x31]; - EMC(0x578) = _cfg[0x32]; - EMC(0x2F4) = _cfg[0x33]; - EMC(0x458) = _cfg[0x1D]; - EMC(0x45C) = _cfg[0x1E]; - EMC(0x5B0) = _cfg[0x1F]; - EMC(0x5B4) = _cfg[0x20]; - EMC(0x5CC) = _cfg[0x21]; - EMC(0x574) = _cfg[0x22]; - EMC(0x2DC) = _cfg[0x23]; - EMC(0xC48) = _cfg[0x2A]; - EMC(0xC70) = _cfg[0x2B]; - EMC(0xC74) = _cfg[0x2C]; - EMC(0xC4C) = _cfg[0x2D]; - EMC(0xC78) = _cfg[0x2E]; - EMC(0x464) = _cfg[0x26]; - EMC(0xC44) = _cfg[0x2F]; - EMC(0x5E4) = _cfg_120[0xD]; - EMC(0x5E8) = _cfg_120[0xE]; - EMC(0x2C8) = _cfg[0xB0]; - EMC(0x588) = _cfg_120[1]; - EMC(0x58C) = _cfg_120[2]; - EMC(0x594) = _cfg_120[3]; - EMC(0x598) = _cfg_120[4]; - EMC(0x59C) = _cfg_120[5]; - EMC(0x5A0) = _cfg_120[6]; - EMC(0x5A4) = _cfg_120[7]; - EMC(0x5A8) = _cfg_120[8]; - EMC(0x5AC) = _cfg_120[9]; - EMC(0x5B8) = _cfg_120[0xA]; - EMC(0x5BC) = _cfg_120[0xB]; - EMC(0x5C4) = _cfg_120[0xC]; - EMC(0x330) = (_cfg_120[0x16] | 0xFE40FE40) & 0x1FFF1FFF; - EMC(0xC40) = _cfg_120[0x12]; - EMC(0x318) = _cfg_120[0x17]; - EMC(0x334) = _cfg_120[0x18] & 0xFF7FFF7F; - EMC(0x31C) = _cfg_120[0x19]; - EMC(0xC3C) = _cfg_120[0x1A]; - EMC(0xC54) = _cfg_120[0x1B]; - EMC(0xC50) = _cfg_120[0x1C]; - EMC(0xC64) = _cfg_120[0x1F]; - EMC(0xC5C) = _cfg_120[0x1D]; - EMC(0xC58) = _cfg_120[0x1E]; - EMC(0xC60) = _cfg[0x141]; - EMC(0x49C) = _cfg[0x142]; - EMC(0x720) = _cfg[0x143]; - EMC(0x724) = _cfg[0x144]; - EMC(0x728) = _cfg[0x145]; - EMC(0x72C) = _cfg[0x146]; - EMC(0x730) = _cfg[0x147]; - EMC(0x734) = _cfg[0x148]; - EMC(0x740) = _cfg[0x14D]; - EMC(0x744) = _cfg[0x14E]; - EMC(0x748) = _cfg[0x14F]; - EMC(0x74C) = _cfg[0x150]; - EMC(0x750) = _cfg[0x151]; - EMC(0x754) = _cfg[0x152]; - EMC(0x760) = _cfg[0x153]; - EMC(0x770) = _cfg[0x154]; - EMC(0x774) = _cfg[0x155]; - EMC(0x778) = _cfg[0x156]; - EMC(0x780) = _cfg[0x157]; - EMC(0x784) = _cfg[0x158]; - EMC(0x788) = _cfg[0x159]; - EMC(0xBE0) = _cfg[0xB6]; - EMC(0xBE4) = _cfg[0xB7]; - EMC(0xBF0) = _cfg[0xB8]; - EMC(0xBF4) = _cfg[0xB9]; - EMC(0xCF4) = _cfg[0xBA]; - EMC(0x600) = _cfg[0xBD]; - EMC(0x604) = _cfg[0xBE]; - EMC(0x608) = _cfg[0xBF]; - EMC(0x60C) = _cfg[0xC0]; - EMC(0x610) = _cfg[0xC1]; - EMC(0x614) = _cfg[0xC2]; - EMC(0x620) = _cfg[0xC3]; - EMC(0x624) = _cfg[0xC4]; - EMC(0x628) = _cfg[0xC5]; - EMC(0x62C) = _cfg[0xC6]; - EMC(0x630) = _cfg[0xC7]; - EMC(0x634) = _cfg[0xC8]; - EMC(0x330) = _cfg_120[0x16]; - EMC(0x640) = _cfg[0xC9]; - EMC(0x644) = _cfg[0xCA]; - EMC(0x648) = _cfg[0xCB]; - EMC(0x64C) = _cfg[0xCC]; - EMC(0x650) = _cfg[0xCD]; - EMC(0x654) = _cfg[0xCE]; - EMC(0x660) = _cfg[0xCF]; - EMC(0x664) = _cfg[0xD0]; - EMC(0x668) = _cfg[0xD1]; - EMC(0x66C) = _cfg[0xD2]; - EMC(0x670) = _cfg[0xD3]; - EMC(0x674) = _cfg[0xD4]; - EMC(0x680) = _cfg[0xD5]; - EMC(0x684) = _cfg[0xD6]; - EMC(0x688) = _cfg[0xD7]; - EMC(0x68C) = _cfg[0xD8]; - EMC(0x690) = _cfg[0xD9]; - EMC(0x694) = _cfg[0xDA]; - EMC(0x6A0) = _cfg[0xDB]; - EMC(0x6A4) = _cfg[0xDC]; - EMC(0x6A8) = _cfg[0xDD]; - EMC(0x6AC) = _cfg[0xDE]; - EMC(0x6B0) = _cfg[0xDF]; - EMC(0x6B4) = _cfg[0xE0]; - EMC(0x6C0) = _cfg[0xE1]; - EMC(0x6C4) = _cfg[0xE2]; - EMC(0x6C8) = _cfg[0xE3]; - EMC(0x6CC) = _cfg[0xE4]; - EMC(0x6E0) = _cfg[0xE5]; - EMC(0x6E4) = _cfg[0xE6]; - EMC(0x6E8) = _cfg[0xE7]; - EMC(0x6EC) = _cfg[0xE8]; - EMC(0xC00) = _cfg[0xE9]; - EMC(0xC04) = _cfg[0xEA]; - EMC(0xC08) = _cfg[0xEB]; - EMC(0xC0C) = _cfg[0xEC]; - EMC(0xC10) = _cfg[0xED]; - EMC(0xC20) = _cfg[0xEE]; - EMC(0xC24) = _cfg[0xEF]; - EMC(0xC28) = _cfg[0xF0]; - EMC(0xC68) = (*((u8 *)_cfg + 0x500) | 0xFFFFFFFE) & 0xF; - if (_cfg[0xC]) - *(vu32 *)_cfg[0xC] = _cfg[0xD]; - EMC(0x28) = 1; - MC(0x648) = _cfg[0x180]; - MC(0x978) = _cfg[0x181]; - MC(0x64C) = _cfg[0x182]; - MC(0x418) = _cfg[0x183]; - MC(0x590) = _cfg[0x184]; - MC(0x984) = _cfg[0x185]; - MC(0x988) = _cfg[0x186]; - MC(0x54) = _cfg[0x15A]; - MC(0x58) = _cfg[0x15B]; - MC(0x5C) = _cfg[0x15C]; - MC(0x60) = _cfg[0x15D]; - MC(0x64) = _cfg[0x15E]; - MC(0x68) = _cfg[0x15F]; - MC(0x6C) = _cfg[0x160]; - MC(0x50) = _cfg[0x161]; - MC(0x670) = _cfg[0x187]; - MC(0x9D4) = _cfg[0x188]; - MC(0x674) = _cfg[0x189]; - MC(0x9A0) = _cfg[0x1D6]; - MC(0x9A8) = _cfg[0x1D7]; - MC(0x9A4) = _cfg[0x1D8]; - MC(0x90) = _cfg[0x162]; - MC(0x94) = _cfg[0x163]; - MC(0x6F0) = _cfg[0x164]; - MC(0x6F4) = _cfg[0x165]; - MC(0x98) = _cfg[0x166]; - MC(0x9C) = _cfg[0x167]; - MC(0xA0) = _cfg[0x168]; - MC(0xA4) = _cfg[0x169]; - MC(0xA8) = _cfg[0x16A]; - MC(0xAC) = _cfg[0x16B]; - MC(0xB0) = _cfg[0x16C]; - MC(0xB4) = _cfg[0x16D]; - MC(0xB8) = _cfg[0x16E]; - MC(0xBC) = _cfg[0x16F]; - MC(0x6C4) = _cfg[0x17D]; - MC(0xC0) = _cfg[0x170]; - MC(0xC4) = _cfg[0x171]; - MC(0x6C0) = _cfg[0x172]; - MC(0xD0) = _cfg[0x173]; - MC(0xD4) = _cfg[0x174]; - MC(0xD8) = _cfg[0x175]; - MC(0xDC) = _cfg[0x176]; - MC(0xC8) = _cfg[0x177]; - MC(0xE0) = _cfg[0x178]; - MC(0xE8) = _cfg[0x179]; - MC(0x968) = _cfg[0x17A]; - MC(0xEC) = _cfg[0x17B]; - MC(0x9DC) = _cfg[0x17C]; - MC(0xFC) = 1; - MC(0xF4) = _cfg[0x17E]; - MC(0x100) = _cfg[0x17F]; - EMC(0x10) = _cfg[0x34]; - EMC(0x140) = _cfg_100[7]; - EMC(0x700) = _cfg[0x27]; - EMC(0x704) = _cfg[0x28]; - EMC(0x708) = _cfg[0x29]; - EMC(0x2F8) = _cfg[0x24]; - EMC(0x300) = _cfg[0x25]; - EMC(0x2A8) = _cfg[0x1B]; - EMC(0x2A4) = _cfg[0x1C]; - sleep(_cfg[0x30]); - if (_cfg[0x10]) - *(vu32 *)_cfg[0x10] = _cfg[0x11]; - EMC(0x2B8) = _cfg[0xA4]; - EMC(0x560) = _cfg[0xA5]; - EMC(0x55C) = _cfg[0xBB]; - EMC(0x554) = _cfg[0xBC]; - EMC(0xF0) = _cfg[0xAB]; - EMC(0xF4) = _cfg[0xAC]; - EMC(0xC8) = _cfg[0xA1]; - EMC(0xC4) = _cfg[0xA2]; - EMC(0x104) = _cfg[0x7A]; - EMC(0x2C) = _cfg[0x3A]; - EMC(0x30) = _cfg[0x3B]; - EMC(0x590) = _cfg[0x3C]; - EMC(0x580) = _cfg[0x3D]; - EMC(0xC0) = _cfg[0x3E]; - EMC(0x34) = _cfg[0x3F]; - EMC(0x38) = _cfg[0x40]; - EMC(0xAC) = _cfg[0x47]; - EMC(0x144) = _cfg[0x41]; - EMC(0x148) = _cfg[0x42]; - EMC(0x3C) = _cfg[0x43]; - EMC(0x40) = _cfg[0x44]; - EMC(0x44) = _cfg[0x45]; - EMC(0x48) = _cfg[0x46]; - EMC(0x5C0) = _cfg[0x48]; - EMC(0x4C) = _cfg[0x49]; - EMC(0x50) = _cfg[0x4A]; - EMC(0x54) = _cfg[0x4B]; - EMC(0x58) = _cfg[0x4C]; - EMC(0xB8) = _cfg[0x4D]; - EMC(0x5C) = _cfg[0x4E]; - EMC(0x4E0) = _cfg[0x4F]; - EMC(0x498) = _cfg[0x50]; - EMC(0x494) = _cfg[0x51]; - EMC(0x2D0) = _cfg[0x52]; - EMC(0x490) = _cfg[0x53]; - EMC(0x48C) = _cfg[0x54]; - EMC(0x60) = _cfg[0x55]; - EMC(0x568) = _cfg[0x56]; - EMC(0x468) = _cfg[0x57]; - EMC(0x46C) = _cfg[0x58]; - EMC(0x14C) = _cfg[0x59]; - EMC(0x150) = _cfg[0x5A]; - EMC(0x154) = _cfg[0x5B]; - EMC(0x56C) = _cfg[0x5C]; - EMC(0xC68) = _cfg[0x140]; - EMC(0x8) = _cfg[0xA9]; - EMC(0x64) = _cfg[0x5D]; - EMC(0x428) = 0; - EMC(0x68) = _cfg[0x5E]; - EMC(0x6C) = _cfg[0x5F]; - EMC(0x2CC) = _cfg[0x60]; - EMC(0x2D8) = _cfg[0x61]; - EMC(0x2D4) = _cfg[0x62]; - EMC(0x564) = _cfg[0x63]; - EMC(0x70) = _cfg[0x64]; - EMC(0x74) = _cfg[0x65]; - EMC(0x3DC) = _cfg[0x66]; - EMC(0x78) = _cfg[0x67]; - EMC(0x7C) = _cfg[0x68]; - EMC(0x80) = _cfg[0x69]; - EMC(0x84) = _cfg[0x6A]; - EMC(0x88) = _cfg[0x6B]; - EMC(0x8C) = _cfg[0x6C]; - EMC(0x11C) = _cfg[0x6D]; - EMC(0x118) = _cfg[0x6E]; - EMC(0xB4) = _cfg[0x6F]; - EMC(0x90) = _cfg[0x70]; - EMC(0x3E4) = _cfg[0x71]; - EMC(0x94) = _cfg[0x72]; - EMC(0x158) = _cfg[0x73]; - EMC(0x15C) = _cfg[0x74]; - EMC(0x98) = _cfg[0x75]; - EMC(0x9C) = _cfg[0x76]; - EMC(0xA0) = _cfg[0x77]; - EMC(0xA4) = _cfg[0x78]; - EMC(0xA8) = _cfg[0x79]; - EMC(0xB0) = _cfg[0xF2]; - EMC(0x2BC) = _cfg[0xAF]; - EMC(0x2C0) = _cfg[0xB1]; - EMC(0x100) = _cfg[0x8A] & 0xFFFFFFFD; - EMC(0x120) = _cfg[0x8B]; - EMC(0x440) = _cfg_120[0xF]; - EMC(0x444) = _cfg_120[0x10]; - EMC(0x448) = _cfg_120[0x11]; - EMC(0x124) = _cfg_100[0x17]; - EMC(0x480) = *_cfg_120; - EMC(0xC) = ((_cfg[0xA3] & 4 | 0x3C00000) & 0xFFFFFFF7 | _cfg[0xA3] & 8) & 0xFFFFFFFD | _cfg[0xA3] & 2; - if ((_cfg[0x1D4] & 0x80000000) != 0) - { - *(vu32 *)(4 * _cfg[0x1D4] + 0x70000000) = _cfg[0x1D5]; - MC(0xFC) = 1; - } - PMC(0x45C) = ((4 * _cfg_120[0xF] >> 2) + 0x40000000) & 0xCFFF0000; - sleep(_cfg_100[0x11]); - if (!_cfg[0x1B]) - EMC(0x2A4) = _cfg[0x1C] | 0x200; - EMC(0x334) = _cfg_120[0x18]; - if (_cfg[0xFA] << 31) - { - if (*_cfg == 2) - EMC(0x2E4) = 8 * _cfg[0xF4]; - if (*_cfg == 3) - { - EMC(0x2E4) = _cfg[0xF4]; - EMC(0x2E8) = _cfg[0xF5]; - } - } - EMC(0x28) = 1; - sleep(_cfg[0x39]); - PMC(0x4E4) &= 0xFFF8007F; - sleep(_cfg_100[0x15]); - if (*_cfg == 2) - { - EMC(0x24) = (_cfg[0x37] << 16) | (_cfg[0x38] << 12); - sleep(_cfg[0x36] + 200); - EMC(0x24) = ((_cfg[0x37] << 16) | (_cfg[0x38] << 12)) + 0x100; - sleep(_cfg[0x36] + 500); - } - if (*_cfg == 3) - { - EMC(0x24) = (_cfg[0x37] << 16) | (_cfg[0x38] << 12); - sleep(_cfg[0x36] + 200); - EMC(0x24) = ((_cfg[0x37] << 16) | (_cfg[0x38] << 12)) + 0x100; - sleep(_cfg[0x36] + 2000); - } - EMC(0x24) = ((_cfg[0x37] << 16) | (_cfg[0x38] << 12)) + 0x101; - sleep(_cfg[0x35]); - if (*_cfg != 3) - EMC(0xDC) = (_cfg[0xB2] << 30) + 1; - if (*_cfg == 1) - sleep(_cfg[0x36] + 200); - if (*_cfg == 3) - { - if (_cfg[0x12]) - *(vu32 *)_cfg[0x12] = _cfg[0x13]; - EMC(0x134) = _cfg[0x91]; - EMC(0xE8) = _cfg[0x90]; - EMC(0x138) = _cfg[0x92]; - EMC(0x13C) = _cfg[0x93]; - EMC(0x4A4) = _cfg[0x94]; - EMC(0x4C4) = _cfg[0x9A]; - EMC(0x4AC) = _cfg[0x95]; - EMC(0x4BC) = _cfg[0x98]; - EMC(0x4B0) = _cfg[0x96]; - EMC(0x4C0) = _cfg[0x99]; - if (_cfg[0xFA] << 31) - { - EMC(0x2EC) = _cfg[0xF7]; - sleep(_cfg[0xF9]); - EMC(0x2EC) = _cfg[0xF7] ^ 3; - if (!(_cfg[0xB2] & 2)) - { - EMC(0x2EC) = _cfg[0xF8]; - sleep(_cfg[0xF9]); - EMC(0x2EC) = _cfg[0xF8] ^ 3; - } - } - } - PMC(0x1D0) = _cfg_100[0xF]; - if (_cfg[0] == 1 || _cfg[0] == 2 || _cfg[0] == 3) - { - EMC(0x2E0) = _cfg[0xF3]; - EMC(0x2E4) = _cfg[0xF4]; - EMC(0x2E8) = _cfg[0xF5]; - } - if (_cfg[0x14]) - *(vu32 *)_cfg[0x14] = _cfg[0x15]; - EMC(0x28) = 1; - if (_cfg_100[8]) - EMC(0xD4) = ((1 << _cfg_100[8] << 8) - 0xFD) | (_cfg[0x38] << 30); - EMC(0x20) = _cfg[0xB2] | 0x80000000; - EMC(0x3E0) = _cfg[0xAD]; - EMC(0x5F4) = _cfg[0xA8]; - EMC(0xC) = _cfg[0xA3]; - EMC(0x310) = _cfg[0xB4]; - EMC(0x314) = _cfg[0xB5]; - EMC(0x3D8) = _cfg[0xB3]; - EMC(0x100) = _cfg[0x8A] | 2; - EMC(0x28) = 1; - EMC(0x558) = _cfg[0xA6]; - EMC(0x4D8) = _cfg[0xA7]; - SYSREG(AHB_ARBITRATION_XBAR_CTRL) = SYSREG(AHB_ARBITRATION_XBAR_CTRL) & 0xFFFEFFFF | (*((u16 *)_cfg + 0x15C) << 16); - MC(0x650) = _cfg[0x18A]; - MC(0x678) = _cfg[0x18B]; - MC(0x9AC) = _cfg[0x1D9]; - MC(MC_EMEM_CFG_ACCESS_CTRL) = 1; //Disable write access to a bunch of MC registers. -} - -void sdram_init() -{ - u32 sdram_id = _get_sdram_id(); - const u32 *cfg = _dram_cfgs[sdram_id]; //TODO: sdram_id should be in [0,4]. - - i2c_send_byte(I2C_5, 0x3C, 0x22, 0x05); - i2c_send_byte(I2C_5, 0x3C, 0x17, 40); //40 = (1000 * 1100 - 600000) / 12500 - - PMC(APBDEV_PMC_VDDP_SEL) = cfg[0x10C]; - sleep(cfg[0x10D]); - PMC(APBDEV_PMC_DDR_PWR) = PMC(0xE8); - PMC(APBDEV_PMC_NO_IOPOWER) = cfg[0x114]; - PMC(APBDEV_PMC_REG_SHORT) = cfg[0x113]; - PMC(APBDEV_PMC_DDR_CNTRL) = cfg[0x116]; - - if (cfg[8]) - *(vu32 *)cfg[8] = cfg[9]; - - _sdram_config(cfg); -} diff --git a/fusee/fusee-primary/src/hwinit/sdram.h b/fusee/fusee-primary/src/hwinit/sdram.h deleted file mode 100644 index 19db6da9b..000000000 --- a/fusee/fusee-primary/src/hwinit/sdram.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _SDRAM_H_ -#define _SDRAM_H_ - -void sdram_init(); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/sdram.inl b/fusee/fusee-primary/src/hwinit/sdram.inl deleted file mode 100644 index 788dcc8aa..000000000 --- a/fusee/fusee-primary/src/hwinit/sdram.inl +++ /dev/null @@ -1,812 +0,0 @@ -static const u8 _dram_cfg_0[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, - 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, - 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, - 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, - 0xA6, 0xA6, 0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - 0x1F, 0x1F, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, - 0xA1, 0x01, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, - 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x16, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, - 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0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, - 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, - 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, - 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, - 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, 0x00, 0x0D, 0x08, - 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00, 0x00, 0x0B, 0x08, - 0x72, 0x72, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x0D, 0x0C, - 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x04, 0x00, 0x01, 0x08, - 0x00, 0x00, 0x11, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0xCC, 0x00, - 0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, - 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static const u8 _dram_cfg_3[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, - 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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-static const u32 *_dram_cfgs[5] = { - (const u32 *)_dram_cfg_0, - (const u32 *)_dram_cfg_1, - (const u32 *)_dram_cfg_2, - (const u32 *)_dram_cfg_3, - (const u32 *)_dram_cfg_4 -}; diff --git a/fusee/fusee-primary/src/hwinit/t210.h b/fusee/fusee-primary/src/hwinit/t210.h deleted file mode 100644 index 578d6282b..000000000 --- a/fusee/fusee-primary/src/hwinit/t210.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef _T210_H_ -#define _T210_H_ - -#include "types.h" - -#define HOST1X_BASE 0x50000000 -#define DISPLAY_A_BASE 0x54200000 -#define DSI_BASE 0x54300000 -#define VIC_BASE 0x54340000 -#define TSEC_BASE 0x54500000 -#define SOR1_BASE 0x54580000 -#define TMR_BASE 0x60005000 -#define CLOCK_BASE 0x60006000 -#define FLOW_CTLR_BASE 0x60007000 -#define SYSREG_BASE 0x6000C000 -#define SB_BASE (SYSREG_BASE + 0x200) -#define GPIO_BASE 0x6000D000 -#define GPIO_1_BASE (GPIO_BASE) -#define GPIO_2_BASE (GPIO_BASE + 0x100) -#define GPIO_3_BASE (GPIO_BASE + 0x200) -#define GPIO_6_BASE (GPIO_BASE + 0x500) -#define EXCP_VEC_BASE 0x6000F000 -#define PINMUX_AUX_BASE 0x70003000 -#define UART_BASE 0x70006000 -#define PMC_BASE 0x7000E400 -#define SYSCTR0_BASE 0x7000F000 -#define FUSE_BASE 0x7000F800 -#define MC_BASE 0x70019000 -#define EMC_BASE 0x7001B000 -#define MIPI_CAL_BASE 0x700E3000 -#define I2S_BASE 0x702D1000 - -#define _REG(base, off) *(vu32 *)((base) + (off)) - -#define HOST1X(off) _REG(HOST1X_BASE, off) -#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off) -#define DSI(off) _REG(DSI_BASE, off) -#define VIC(off) _REG(VIC_BASE, off) -#define TSEC(off) _REG(TSEC_BASE, off) -#define SOR1(off) _REG(SOR1_BASE, off) -#define TMR(off) _REG(TMR_BASE, off) -#define CLOCK(off) _REG(CLOCK_BASE, off) -#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off) -#define SYSREG(off) _REG(SYSREG_BASE, off) -#define SB(off) _REG(SB_BASE, off) -#define GPIO_1(off) _REG(GPIO_1_BASE, off) -#define GPIO_2(off) _REG(GPIO_2_BASE, off) -#define GPIO_3(off) _REG(GPIO_3_BASE, off) -#define GPIO_6(off) _REG(GPIO_6_BASE, off) -#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off) -#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off) -#define PMC(off) _REG(PMC_BASE, off) -#define SYSCTR0(off) _REG(SYSCTR0_BASE, off) -#define FUSE(off) _REG(FUSE_BASE, off) -#define MC(off) _REG(MC_BASE, off) -#define EMC(off) _REG(EMC_BASE, off) -#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off) -#define I2S(off) _REG(I2S_BASE, off) - -/*! System registers. */ -#define AHB_ARBITRATION_XBAR_CTRL 0xE0 - -/*! Secure boot registers. */ -#define SB_CSR_0 0x0 -#define SB_AA64_RESET_LOW 0x30 -#define SB_AA64_RESET_HIGH 0x34 - -/*! SYSCTR0 registers. */ -#define SYSCTR0_CNTFID0 0x20 - -#endif diff --git a/fusee/fusee-primary/src/hwinit/tsec.c b/fusee/fusee-primary/src/hwinit/tsec.c deleted file mode 100644 index 3b229fc52..000000000 --- a/fusee/fusee-primary/src/hwinit/tsec.c +++ /dev/null @@ -1,113 +0,0 @@ -#include -#include "tsec.h" -#include "clock.h" -#include "t210.h" - -static int _tsec_dma_wait_idle() -{ - u32 timeout = TMR(0x10) + 10000000; - - while (!(TSEC(0x1118) & 2)) - if (TMR(0x10) > timeout) - return 0; - - return 1; -} - -static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offset) -{ - u32 cmd; - - if (not_imem) - cmd = 0x600; // DMA 0x100 bytes - else - cmd = 0x10; // dma imem - - TSEC(0x1114) = i_offset; // tsec_dmatrfmoffs_r - TSEC(0x111C) = pa_offset; // tsec_dmatrffboffs_r - TSEC(0x1118) = cmd; // tsec_dmatrfcmd_r - - return _tsec_dma_wait_idle(); -} - -int tsec_query(u32 carveout, u8 *dst, u32 rev) -{ - int res = 0; - - //Enable clocks. - clock_enable_host1x(); - clock_enable_tsec(); - clock_enable_sor_safe(); - clock_enable_sor0(); - clock_enable_sor1(); - clock_enable_kfuse(); - - //Configure Falcon. - TSEC(0x110C) = 0; // tsec_dmactl_r - TSEC(0x1010) = 0xFFF2; // tsec_irqmset_r - TSEC(0x101C) = 0xFFF0; // tsec_irqdest_r - TSEC(0x1048) = 3; // tsec_itfen_r - if (!_tsec_dma_wait_idle()) - { - res = -1; - goto out; - } - - //Load firmware. - TSEC(0x1110) = carveout >> 8;// tsec_dmatrfbase_r - for (u32 addr = 0; addr < 0xF00; addr += 0x100) - if (!_tsec_dma_pa_to_internal_100(0, addr, addr)) - { - res = -2; - goto out; - } - - //Execute firmware. - HOST1X(0x3300) = 0x34C2E1DA; - TSEC(0x1044) = 0; - TSEC(0x1040) = rev; - TSEC(0x1104) = 0; // tsec_bootvec_r - TSEC(0x1100) = 2; // tsec_cpuctl_r - if (!_tsec_dma_wait_idle()) - { - res = -3; - goto out; - } - u32 timeout = TMR(0x10) + 2000000; - while (!TSEC(0x1044)) - if (TMR(0x10) > timeout) - { - res = -4; - goto out; - } - if (TSEC(0x1044) != 0xB0B0B0B0) - { - res = -5; - goto out; - } - - //Fetch result. - HOST1X(0x3300) = 0; - u32 buf[4]; - buf[0] = SOR1(0x1E8); - buf[1] = SOR1(0x21C); - buf[2] = SOR1(0x208); - buf[3] = SOR1(0x20C); - SOR1(0x1E8) = 0; - SOR1(0x21C) = 0; - SOR1(0x208) = 0; - SOR1(0x20C) = 0; - memcpy(dst, &buf, 0x10); - -out:; - - //Disable clocks. - clock_disable_kfuse(); - clock_disable_sor1(); - clock_disable_sor0(); - clock_disable_sor_safe(); - clock_disable_tsec(); - clock_disable_host1x(); - - return res; -} diff --git a/fusee/fusee-primary/src/hwinit/tsec.h b/fusee/fusee-primary/src/hwinit/tsec.h deleted file mode 100644 index 03fb503d2..000000000 --- a/fusee/fusee-primary/src/hwinit/tsec.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _TSEC_H_ -#define _TSEC_H_ - -#include "types.h" - -int tsec_query(u32 carveout, u8 *dst, u32 rev); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/types.h b/fusee/fusee-primary/src/hwinit/types.h deleted file mode 100644 index dff2978da..000000000 --- a/fusee/fusee-primary/src/hwinit/types.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _TYPES_H_ -#define _TYPES_H_ - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned int u32; -typedef volatile unsigned int vu32; -typedef unsigned long long int u64; -typedef volatile unsigned long long int vu64; - -#endif diff --git a/fusee/fusee-primary/src/hwinit/uart.c b/fusee/fusee-primary/src/hwinit/uart.c deleted file mode 100644 index b9b35aa8c..000000000 --- a/fusee/fusee-primary/src/hwinit/uart.c +++ /dev/null @@ -1,62 +0,0 @@ -#include "uart.h" -#include "t210.h" -#include "util.h" - -/* UART A, B, C, D and E. */ -static const u32 uart_baseoff[5] = { 0, 0x40, 0x200, 0x300, 0x400 }; - -void uart_init(u32 idx, u32 baud) -{ - volatile uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); - - //Set baud rate. - u32 rate = (8 * baud + 408000000) / (16 * baud); - uart->UART_LCR = 0x80; //Enable DLAB. - uart->UART_THR_DLAB = (u8)rate; //Divisor latch LSB. - uart->UART_IER_DLAB = (u8)(rate >> 8); //Divisor latch MSB. - uart->UART_LCR = 0; //Diable DLAB. - - //Setup UART in fifo mode. - uart->UART_IER_DLAB = 0; - uart->UART_IIR_FCR = 7; //Enable and clear TX and RX FIFOs. - volatile u32 tmp = uart->UART_LSR; - sleep(3 * ((baud + 999999) / baud)); - uart->UART_LCR = 3; //Set word length 8. - uart->UART_MCR = 0; - uart->UART_MSR = 0; - uart->UART_IRDA_CSR = 0; - uart->UART_RX_FIFO_CFG = 1; - uart->UART_MIE = 0; - uart->UART_ASR = 0; -} - -void uart_wait_idle(u32 idx, u32 which) -{ - volatile uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); - while (!(uart->UART_VENDOR_STATUS & which)) - ; -} - -void uart_send(u32 idx, u8 *buf, u32 len) -{ - volatile uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); - - for (u32 i = 0; i != len; i++) - { - while (uart->UART_LSR & UART_TX_FIFO_FULL) - ; - uart->UART_THR_DLAB = buf[i]; - }; -} - -void uart_recv(u32 idx, u8 *buf, u32 len) -{ - volatile uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); - - for (u32 i = 0; i != len; i++) - { - while (uart->UART_LSR & UART_RX_FIFO_EMPTY) - ; - buf[i] = uart->UART_THR_DLAB; - }; -} diff --git a/fusee/fusee-primary/src/hwinit/uart.h b/fusee/fusee-primary/src/hwinit/uart.h deleted file mode 100644 index ac8222215..000000000 --- a/fusee/fusee-primary/src/hwinit/uart.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef _UART_H_ -#define _UART_H_ - -#include "types.h" - -#define UART_A 0 -#define UART_B 1 -#define UART_C 2 -//TODO: define clock inits for those. -/*#define UART_D 3 -#define UART_E 4*/ - -#define BAUD_115200 115200 - -#define UART_TX_IDLE 0x00000001 -#define UART_RX_IDLE 0x00000002 -#define UART_TX_FIFO_FULL 0x100 -#define UART_RX_FIFO_EMPTY 0x200 - -typedef struct _uart_t -{ - /* 0x00 */ u32 UART_THR_DLAB; - /* 0x04 */ u32 UART_IER_DLAB; - /* 0x08 */ u32 UART_IIR_FCR; - /* 0x0C */ u32 UART_LCR; - /* 0x10 */ u32 UART_MCR; - /* 0x14 */ u32 UART_LSR; - /* 0x18 */ u32 UART_MSR; - /* 0x1C */ u32 UART_SPR; - /* 0x20 */ u32 UART_IRDA_CSR; - /* 0x24 */ u32 UART_RX_FIFO_CFG; - /* 0x28 */ u32 UART_MIE; - /* 0x2C */ u32 UART_VENDOR_STATUS; - /* 0x30 */ u8 _pad_30[0x0C]; - /* 0x3C */ u32 UART_ASR; -} uart_t; - -void uart_init(u32 idx, u32 baud); -void uart_wait_idle(u32 idx, u32 which); -void uart_send(u32 idx, u8 *buf, u32 len); -void uart_recv(u32 idx, u8 *buf, u32 len); - -#endif diff --git a/fusee/fusee-primary/src/hwinit/util.c b/fusee/fusee-primary/src/hwinit/util.c deleted file mode 100644 index 780b31177..000000000 --- a/fusee/fusee-primary/src/hwinit/util.c +++ /dev/null @@ -1,16 +0,0 @@ -#include "util.h" -#include "t210.h" - -void sleep(u32 ticks) -{ - u32 start = TMR(0x10); - while (TMR(0x10) - start <= ticks) - ; -} - -void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops) -{ - for(u32 i = 0; i < num_ops; i++) - base[ops[i].off] = ops[i].val; -} - diff --git a/fusee/fusee-primary/src/hwinit/util.h b/fusee/fusee-primary/src/hwinit/util.h deleted file mode 100644 index 13bc8024f..000000000 --- a/fusee/fusee-primary/src/hwinit/util.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _UTIL_H_ -#define _UTIL_H_ - -#include "types.h" -#pragma GCC diagnostic ignored "-Wparentheses" -#pragma GCC diagnostic ignored "-Wunused-variable" - -typedef struct _cfg_op_t -{ - u32 off; - u32 val; -} cfg_op_t; - -void sleep(u32 ticks); -void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops); - -#endif diff --git a/fusee/fusee-primary/src/i2c.c b/fusee/fusee-primary/src/i2c.c new file mode 100644 index 000000000..a98d7fa6e --- /dev/null +++ b/fusee/fusee-primary/src/i2c.c @@ -0,0 +1,205 @@ +#include "i2c.h" +#include "utils.h" +#include "timers.h" + +/* Prototypes for internal commands. */ +volatile tegra_i2c_t *i2c_get_registers_from_id(unsigned int id); +void i2c_load_config(volatile tegra_i2c_t *regs); + +bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size); +bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size); + +bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size); +bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size); + +/* Initialize I2C based on registers. */ +void i2c_init(unsigned int id) { + volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id); + + /* Setup divisor, and clear the bus. */ + regs->I2C_I2C_CLK_DIVISOR_REGISTER_0 = 0x50001; + regs->I2C_I2C_BUS_CLEAR_CONFIG_0 = 0x90003; + + /* Load hardware configuration. */ + i2c_load_config(regs); + + /* Wait a while until BUS_CLEAR_DONE is set. */ + for (unsigned int i = 0; i < 10; i++) { + udelay(20000); + if (regs->I2C_INTERRUPT_STATUS_REGISTER_0 & 0x800) { + break; + } + } + + /* Read the BUS_CLEAR_STATUS. Result doesn't matter. */ + regs->I2C_I2C_BUS_CLEAR_STATUS_0; + + /* Read and set the Interrupt Status. */ + uint32_t int_status = regs->I2C_INTERRUPT_STATUS_REGISTER_0; + regs->I2C_INTERRUPT_STATUS_REGISTER_0 = int_status; +} + +/* Sets a bit in a PMIC register over I2C during CPU shutdown. */ +void i2c_send_pmic_cpu_shutdown_cmd(void) { + uint32_t val = 0; + /* PMIC == Device 4:3C. */ + i2c_query(4, 0x3C, 0x41, &val, 1); + val |= 4; + i2c_send(4, 0x3C, 0x41, &val, 1); +} + +/* Queries the value of TI charger bit over I2C. */ +bool i2c_query_ti_charger_bit_7(void) { + uint32_t val = 0; + /* TI Charger = Device 0:6B. */ + i2c_query(0, 0x6B, 0, &val, 1); + return (val & 0x80) != 0; +} + +/* Clears TI charger bit over I2C. */ +void i2c_clear_ti_charger_bit_7(void) { + uint32_t val = 0; + /* TI Charger = Device 0:6B. */ + i2c_query(0, 0x6B, 0, &val, 1); + val &= 0x7F; + i2c_send(0, 0x6B, 0, &val, 1); +} + +/* Sets TI charger bit over I2C. */ +void i2c_set_ti_charger_bit_7(void) { + uint32_t val = 0; + /* TI Charger = Device 0:6B. */ + i2c_query(0, 0x6B, 0, &val, 1); + val |= 0x80; + i2c_send(0, 0x6B, 0, &val, 1); +} + +/* Get registers pointer based on I2C ID. */ +volatile tegra_i2c_t *i2c_get_registers_from_id(unsigned int id) { + switch (id) { + case 0: + return I2C1_REGS; + case 1: + return I2C2_REGS; + case 2: + return I2C3_REGS; + case 3: + return I2C4_REGS; + case 4: + return I2C5_REGS; + case 5: + return I2C6_REGS; + default: + generic_panic(); + } + return NULL; +} + +/* Load hardware config for I2C4. */ +void i2c_load_config(volatile tegra_i2c_t *regs) { + /* Set MSTR_CONFIG_LOAD, TIMEOUT_CONFIG_LOAD, undocumented bit. */ + regs->I2C_I2C_CONFIG_LOAD_0 = 0x25; + + /* Wait a bit for master config to be loaded. */ + for (unsigned int i = 0; i < 20; i++) { + udelay(1); + if (!(regs->I2C_I2C_CONFIG_LOAD_0 & 1)) { + break; + } + } +} + +/* Reads a register from a device over I2C, writes result to output. */ +bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size) { + volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id); + uint32_t val = r; + + /* Write single byte register ID to device. */ + if (!i2c_write(regs, device, &val, 1)) { + return false; + } + /* Limit output size to 32-bits. */ + if (dst_size > 4) { + return false; + } + + return i2c_read(regs, device, dst, dst_size); +} + +/* Writes a value to a register over I2C. */ +bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size) { + uint32_t val = r; + if (src_size == 0) { + return true; + } else if (src_size <= 3) { + memcpy(((uint8_t *)&val) + 1, src, src_size); + return i2c_write(i2c_get_registers_from_id(id), device, &val, src_size + 1); + } else { + return false; + } +} + +/* Writes bytes to device over I2C. */ +bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size) { + if (src_size > 4) { + return false; + } else if (src_size == 0) { + return true; + } + + /* Set device for 7-bit write mode. */ + regs->I2C_I2C_CMD_ADDR0_0 = device << 1; + + /* Load in data to write. */ + regs->I2C_I2C_CMD_DATA1_0 = read32le(src, 0); + + /* Set config with LENGTH = src_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */ + regs->I2C_I2C_CNFG_0 = ((src_size << 1) - 2) | 0x2800; + + i2c_load_config(regs); + + /* Config |= SEND; */ + regs->I2C_I2C_CNFG_0 |= 0x200; + + + while (regs->I2C_I2C_STATUS_0 & 0x100) { + /* Wait until not busy. */ + } + + /* Return CMD1_STAT == SL1_XFER_SUCCESSFUL. */ + return (regs->I2C_I2C_STATUS_0 & 0xF) == 0; +} + +/* Reads bytes from device over I2C. */ +bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size) { + if (dst_size > 4) { + return false; + } else if (dst_size == 0) { + return true; + } + + /* Set device for 7-bit read mode. */ + regs->I2C_I2C_CMD_ADDR0_0 = (device << 1) | 1; + + /* Set config with LENGTH = dst_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */ + regs->I2C_I2C_CNFG_0 = ((dst_size << 1) - 2) | 0x2840; + + i2c_load_config(regs); + + /* Config |= SEND; */ + regs->I2C_I2C_CNFG_0 |= 0x200; + + + while (regs->I2C_I2C_STATUS_0 & 0x100) { + /* Wait until not busy. */ + } + + /* Ensure success. */ + if ((regs->I2C_I2C_STATUS_0 & 0xF) != 0) { + return false; + } + + uint32_t val = regs->I2C_I2C_CMD_DATA1_0; + memcpy(dst, &val, dst_size); + return true; +} diff --git a/fusee/fusee-primary/src/i2c.h b/fusee/fusee-primary/src/i2c.h new file mode 100644 index 000000000..e07ed3349 --- /dev/null +++ b/fusee/fusee-primary/src/i2c.h @@ -0,0 +1,71 @@ +#ifndef FUSEE_I2C_H +#define FUSEE_I2C_H + +#include +#include +#include + +#define I2C234_BASE 0x7000C000 +#define I2C56_BASE 0x7000D000 + +typedef struct { + uint32_t I2C_I2C_CNFG_0; + uint32_t I2C_I2C_CMD_ADDR0_0; + uint32_t I2C_I2C_CMD_ADDR1_0; + uint32_t I2C_I2C_CMD_DATA1_0; + uint32_t I2C_I2C_CMD_DATA2_0; + uint32_t _0x14; + uint32_t _0x18; + uint32_t I2C_I2C_STATUS_0; + uint32_t I2C_I2C_SL_CNFG_0; + uint32_t I2C_I2C_SL_RCVD_0; + uint32_t I2C_I2C_SL_STATUS_0; + uint32_t I2C_I2C_SL_ADDR1_0; + uint32_t I2C_I2C_SL_ADDR2_0; + uint32_t I2C_I2C_TLOW_SEXT_0; + uint32_t _0x38; + uint32_t I2C_I2C_SL_DELAY_COUNT_0; + uint32_t I2C_I2C_SL_INT_MASK_0; + uint32_t I2C_I2C_SL_INT_SOURCE_0; + uint32_t I2C_I2C_SL_INT_SET_0; + uint32_t _0x4C; + uint32_t I2C_I2C_TX_PACKET_FIFO_0; + uint32_t I2C_I2C_RX_FIFO_0; + uint32_t I2C_PACKET_TRANSFER_STATUS_0; + uint32_t I2C_FIFO_CONTROL_0; + uint32_t I2C_FIFO_STATUS_0; + uint32_t I2C_INTERRUPT_MASK_REGISTER_0; + uint32_t I2C_INTERRUPT_STATUS_REGISTER_0; + uint32_t I2C_I2C_CLK_DIVISOR_REGISTER_0; + uint32_t I2C_I2C_INTERRUPT_SOURCE_REGISTER_0; + uint32_t I2C_I2C_INTERRUPT_SET_REGISTER_0; + uint32_t I2C_I2C_SLV_TX_PACKET_FIFO_0; + uint32_t I2C_I2C_SLV_RX_FIFO_0; + uint32_t I2C_I2C_SLV_PACKET_STATUS_0; + uint32_t I2C_I2C_BUS_CLEAR_CONFIG_0; + uint32_t I2C_I2C_BUS_CLEAR_STATUS_0; + uint32_t I2C_I2C_CONFIG_LOAD_0; + uint32_t _0x90; + uint32_t I2C_I2C_INTERFACE_TIMING_0_0; + uint32_t I2C_I2C_INTERFACE_TIMING_1_0; + uint32_t I2C_I2C_HS_INTERFACE_TIMING_0_0; + uint32_t I2C_I2C_HS_INTERFACE_TIMING_1_0; +} tegra_i2c_t; + +#define I2C1_REGS ((volatile tegra_i2c_t *)(I2C234_BASE + 0x000)) +#define I2C2_REGS ((volatile tegra_i2c_t *)(I2C234_BASE + 0x400)) +#define I2C3_REGS ((volatile tegra_i2c_t *)(I2C234_BASE + 0x500)) +#define I2C4_REGS ((volatile tegra_i2c_t *)(I2C234_BASE + 0x700)) +#define I2C5_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x000)) +#define I2C6_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x100)) + +void i2c_init(unsigned int id); +bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size); +bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size); + +void i2c_send_pmic_cpu_shutdown_cmd(void); +bool i2c_query_ti_charger_bit_7(void); +void i2c_clear_ti_charger_bit_7(void); +void i2c_set_ti_charger_bit_7(void); + +#endif diff --git a/fusee/fusee-primary/src/lib/lz.c b/fusee/fusee-primary/src/lib/lz.c new file mode 100644 index 000000000..a17c6e49f --- /dev/null +++ b/fusee/fusee-primary/src/lib/lz.c @@ -0,0 +1,179 @@ +/************************************************************************* +* Name: lz.c +* Author: Marcus Geelnard +* Description: LZ77 coder/decoder implementation. +* Reentrant: Yes +* +* The LZ77 compression scheme is a substitutional compression scheme +* proposed by Abraham Lempel and Jakob Ziv in 1977. It is very simple in +* its design, and uses no fancy bit level compression. +* +* This is my first attempt at an implementation of a LZ77 code/decoder. +* +* The principle of the LZ77 compression algorithm is to store repeated +* occurrences of strings as references to previous occurrences of the same +* string. The point is that the reference consumes less space than the +* string itself, provided that the string is long enough (in this +* implementation, the string has to be at least 4 bytes long, since the +* minimum coded reference is 3 bytes long). Also note that the term +* "string" refers to any kind of byte sequence (it does not have to be +* an ASCII string, for instance). +* +* The coder uses a brute force approach to finding string matches in the +* history buffer (or "sliding window", if you wish), which is very, very +* slow. I recon the complexity is somewhere between O(n^2) and O(n^3), +* depending on the input data. +* +* There is also a faster implementation that uses a large working buffer +* in which a "jump table" is stored, which is used to quickly find +* possible string matches (see the source code for LZ_CompressFast() for +* more information). The faster method is an order of magnitude faster, +* but still quite slow compared to other compression methods. +* +* The upside is that decompression is very fast, and the compression ratio +* is often very good. +* +* The reference to a string is coded as a (length,offset) pair, where the +* length indicates the length of the string, and the offset gives the +* offset from the current data position. To distinguish between string +* references and literal strings (uncompressed bytes), a string reference +* is preceded by a marker byte, which is chosen as the least common byte +* symbol in the input data stream (this marker byte is stored in the +* output stream as the first byte). +* +* Occurrences of the marker byte in the stream are encoded as the marker +* byte followed by a zero byte, which means that occurrences of the marker +* byte have to be coded with two bytes. +* +* The lengths and offsets are coded in a variable length fashion, allowing +* values of any magnitude (up to 4294967295 in this implementation). +* +* With this compression scheme, the worst case compression result is +* (257/256)*insize + 1. +* +*------------------------------------------------------------------------- +* Copyright (c) 2003-2006 Marcus Geelnard +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would +* be appreciated but is not required. +* +* 2. Altered source versions must be plainly marked as such, and must not +* be misrepresented as being the original software. +* +* 3. This notice may not be removed or altered from any source +* distribution. +* +* Marcus Geelnard +* marcus.geelnard at home.se +*************************************************************************/ + + +/************************************************************************* +* INTERNAL FUNCTIONS * +*************************************************************************/ + + +/************************************************************************* +* _LZ_ReadVarSize() - Read unsigned integer with variable number of +* bytes depending on value. +*************************************************************************/ + +static int _LZ_ReadVarSize( unsigned int * x, const unsigned char * buf ) +{ + unsigned int y, b, num_bytes; + + /* Read complete value (stop when byte contains zero in 8:th bit) */ + y = 0; + num_bytes = 0; + do + { + b = (unsigned int) (*buf ++); + y = (y << 7) | (b & 0x0000007f); + ++ num_bytes; + } + while( b & 0x00000080 ); + + /* Store value in x */ + *x = y; + + /* Return number of bytes read */ + return num_bytes; +} + + + +/************************************************************************* +* PUBLIC FUNCTIONS * +*************************************************************************/ + + +/************************************************************************* +* LZ_Uncompress() - Uncompress a block of data using an LZ77 decoder. +* in - Input (compressed) buffer. +* out - Output (uncompressed) buffer. This buffer must be large +* enough to hold the uncompressed data. +* insize - Number of input bytes. +*************************************************************************/ + +void LZ_Uncompress( const unsigned char *in, unsigned char *out, + unsigned int insize ) +{ + unsigned char marker, symbol; + unsigned int i, inpos, outpos, length, offset; + + /* Do we have anything to uncompress? */ + if( insize < 1 ) + { + return; + } + + /* Get marker symbol from input stream */ + marker = in[ 0 ]; + inpos = 1; + + /* Main decompression loop */ + outpos = 0; + do + { + symbol = in[ inpos ++ ]; + if( symbol == marker ) + { + /* We had a marker byte */ + if( in[ inpos ] == 0 ) + { + /* It was a single occurrence of the marker byte */ + out[ outpos ++ ] = marker; + ++ inpos; + } + else + { + /* Extract true length and offset */ + inpos += _LZ_ReadVarSize( &length, &in[ inpos ] ); + inpos += _LZ_ReadVarSize( &offset, &in[ inpos ] ); + + /* Copy corresponding data from history window */ + for( i = 0; i < length; ++ i ) + { + out[ outpos ] = out[ outpos - offset ]; + ++ outpos; + } + } + } + else + { + /* No marker, plain copy */ + out[ outpos ++ ] = symbol; + } + } + while( inpos < insize ); +} diff --git a/fusee/fusee-primary/src/lib/lz.h b/fusee/fusee-primary/src/lib/lz.h new file mode 100644 index 000000000..6f31b4a14 --- /dev/null +++ b/fusee/fusee-primary/src/lib/lz.h @@ -0,0 +1,52 @@ +/************************************************************************* +* Name: lz.h +* Author: Marcus Geelnard +* Description: LZ77 coder/decoder interface. +* Reentrant: Yes +*------------------------------------------------------------------------- +* Copyright (c) 2003-2006 Marcus Geelnard +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would +* be appreciated but is not required. +* +* 2. Altered source versions must be plainly marked as such, and must not +* be misrepresented as being the original software. +* +* 3. This notice may not be removed or altered from any source +* distribution. +* +* Marcus Geelnard +* marcus.geelnard at home.se +*************************************************************************/ + +#ifndef _lz_h_ +#define _lz_h_ + +#ifdef __cplusplus +extern "C" { +#endif + + +/************************************************************************* +* Function prototypes +*************************************************************************/ + +void LZ_Uncompress( const unsigned char *in, unsigned char *out, + unsigned int insize ); + + +#ifdef __cplusplus +} +#endif + +#endif /* _lz_h_ */ diff --git a/fusee/fusee-primary/src/main.c b/fusee/fusee-primary/src/main.c index c5a5a5d3c..b1552b7cd 100644 --- a/fusee/fusee-primary/src/main.c +++ b/fusee/fusee-primary/src/main.c @@ -2,8 +2,7 @@ #include "exception_handlers.h" #include "panic.h" #include "hwinit.h" -#include "fuse.h" -#include "se.h" +#include "di.h" #include "timers.h" #include "fs_utils.h" #include "stage2.h" @@ -49,32 +48,15 @@ static const char *load_config(void) { return bct0; } -static void load_sbk(void) { - uint32_t sbk[0x4]; - /* Load the SBK into the security engine, if relevant. */ - memcpy(sbk, (void *)get_fuse_chip_regs()->FUSE_PRIVATE_KEY, 0x10); - for (unsigned int i = 0; i < 4; i++) { - if (sbk[i] != 0xFFFFFFFF) { - set_aes_keyslot(0xE, sbk, 0x10); - break; - } - } -} - static void setup_env(void) { g_framebuffer = (void *)0xC0000000; - /* Initialize DRAM. */ - /* TODO: What can be stripped out to make this minimal? */ + /* Initialize hardware. */ nx_hwinit(); /* Check for panics. */ check_and_display_panic(); - /* Try to load the SBK into the security engine, if possible. */ - /* TODO: Should this be done later? */ - load_sbk(); - /* Zero-fill the framebuffer and register it as printk provider. */ video_init(g_framebuffer); @@ -86,7 +68,7 @@ static void setup_env(void) { /* Turn on the backlight after initializing the lfb */ /* to avoid flickering. */ - display_enable_backlight(true); + display_backlight(true); /* Set up the exception handlers. */ setup_exception_handlers(); @@ -99,7 +81,7 @@ static void cleanup_env(void) { /* Unmount the SD card. */ unmount_sd(); - display_enable_backlight(false); + display_backlight(false); display_end(); } @@ -123,7 +105,7 @@ int main(void) { /* Say hello. */ printk("Welcome to Atmosph\xe8re Fus\xe9" "e!\n"); printk("Using color linear framebuffer at 0x%p!\n", g_framebuffer); - + /* Load the BCT0 configuration ini off of the SD. */ bct0 = load_config(); diff --git a/fusee/fusee-primary/src/max77620.h b/fusee/fusee-primary/src/max77620.h new file mode 100644 index 000000000..ad22a06b5 --- /dev/null +++ b/fusee/fusee-primary/src/max77620.h @@ -0,0 +1,326 @@ +/* + * Defining registers address and its bit definitions of MAX77620 and MAX20024 + * + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#ifndef _MFD_MAX77620_H_ +#define _MFD_MAX77620_H_ + +/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */ +#define MAX77620_REG_CNFGGLBL1 0x00 +#define MAX77620_REG_CNFGGLBL2 0x01 +#define MAX77620_REG_CNFGGLBL3 0x02 +#define MAX77620_REG_CNFG1_32K 0x03 +#define MAX77620_REG_CNFGBBC 0x04 +#define MAX77620_REG_IRQTOP 0x05 +#define MAX77620_REG_INTLBT 0x06 +#define MAX77620_REG_IRQSD 0x07 +#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 +#define MAX77620_REG_IRQ_LVL2_L8 0x09 +#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A +#define MAX77620_REG_ONOFFIRQ 0x0B +#define MAX77620_REG_NVERC 0x0C +#define MAX77620_REG_IRQTOPM 0x0D +#define MAX77620_REG_INTENLBT 0x0E +#define MAX77620_REG_IRQMASKSD 0x0F +#define MAX77620_REG_IRQ_MSK_L0_7 0x10 +#define MAX77620_REG_IRQ_MSK_L8 0x11 +#define MAX77620_REG_ONOFFIRQM 0x12 +#define MAX77620_REG_STATLBT 0x13 +#define MAX77620_REG_STATSD 0x14 +#define MAX77620_REG_ONOFFSTAT 0x15 + +/* SD and LDO Registers */ +#define MAX77620_REG_SD0 0x16 +#define MAX77620_REG_SD1 0x17 +#define MAX77620_REG_SD2 0x18 +#define MAX77620_REG_SD3 0x19 +#define MAX77620_REG_SD4 0x1A +#define MAX77620_REG_DVSSD0 0x1B +#define MAX77620_REG_DVSSD1 0x1C +#define MAX77620_REG_SD0_CFG 0x1D +#define MAX77620_REG_SD1_CFG 0x1E +#define MAX77620_REG_SD2_CFG 0x1F +#define MAX77620_REG_SD3_CFG 0x20 +#define MAX77620_REG_SD4_CFG 0x21 +#define MAX77620_REG_SD_CFG2 0x22 +#define MAX77620_REG_LDO0_CFG 0x23 +#define MAX77620_REG_LDO0_CFG2 0x24 +#define MAX77620_REG_LDO1_CFG 0x25 +#define MAX77620_REG_LDO1_CFG2 0x26 +#define MAX77620_REG_LDO2_CFG 0x27 +#define MAX77620_REG_LDO2_CFG2 0x28 +#define MAX77620_REG_LDO3_CFG 0x29 +#define MAX77620_REG_LDO3_CFG2 0x2A +#define MAX77620_REG_LDO4_CFG 0x2B +#define MAX77620_REG_LDO4_CFG2 0x2C +#define MAX77620_REG_LDO5_CFG 0x2D +#define MAX77620_REG_LDO5_CFG2 0x2E +#define MAX77620_REG_LDO6_CFG 0x2F +#define MAX77620_REG_LDO6_CFG2 0x30 +#define MAX77620_REG_LDO7_CFG 0x31 +#define MAX77620_REG_LDO7_CFG2 0x32 +#define MAX77620_REG_LDO8_CFG 0x33 +#define MAX77620_REG_LDO8_CFG2 0x34 +#define MAX77620_REG_LDO_CFG3 0x35 + +#define MAX77620_LDO_SLEW_RATE_MASK 0x1 + +/* LDO Configuration 3 */ +#define MAX77620_TRACK4_MASK (1 << 5) +#define MAX77620_TRACK4_SHIFT 5 + +/* Voltage */ +#define MAX77620_SDX_VOLT_MASK 0xFF +#define MAX77620_SD0_VOLT_MASK 0x3F +#define MAX77620_SD1_VOLT_MASK 0x7F +#define MAX77620_LDO_VOLT_MASK 0x3F + +#define MAX77620_REG_GPIO0 0x36 +#define MAX77620_REG_GPIO1 0x37 +#define MAX77620_REG_GPIO2 0x38 +#define MAX77620_REG_GPIO3 0x39 +#define MAX77620_REG_GPIO4 0x3A +#define MAX77620_REG_GPIO5 0x3B +#define MAX77620_REG_GPIO6 0x3C +#define MAX77620_REG_GPIO7 0x3D +#define MAX77620_REG_PUE_GPIO 0x3E +#define MAX77620_REG_PDE_GPIO 0x3F +#define MAX77620_REG_AME_GPIO 0x40 +#define MAX77620_REG_ONOFFCNFG1 0x41 +#define MAX77620_REG_ONOFFCNFG2 0x42 + +/* FPS Registers */ +#define MAX77620_REG_FPS_CFG0 0x43 +#define MAX77620_REG_FPS_CFG1 0x44 +#define MAX77620_REG_FPS_CFG2 0x45 +#define MAX77620_REG_FPS_LDO0 0x46 +#define MAX77620_REG_FPS_LDO1 0x47 +#define MAX77620_REG_FPS_LDO2 0x48 +#define MAX77620_REG_FPS_LDO3 0x49 +#define MAX77620_REG_FPS_LDO4 0x4A +#define MAX77620_REG_FPS_LDO5 0x4B +#define MAX77620_REG_FPS_LDO6 0x4C +#define MAX77620_REG_FPS_LDO7 0x4D +#define MAX77620_REG_FPS_LDO8 0x4E +#define MAX77620_REG_FPS_SD0 0x4F +#define MAX77620_REG_FPS_SD1 0x50 +#define MAX77620_REG_FPS_SD2 0x51 +#define MAX77620_REG_FPS_SD3 0x52 +#define MAX77620_REG_FPS_SD4 0x53 +#define MAX77620_REG_FPS_NONE 0 + +#define MAX77620_FPS_SRC_MASK 0xC0 +#define MAX77620_FPS_SRC_SHIFT 6 +#define MAX77620_FPS_PU_PERIOD_MASK 0x38 +#define MAX77620_FPS_PU_PERIOD_SHIFT 3 +#define MAX77620_FPS_PD_PERIOD_MASK 0x07 +#define MAX77620_FPS_PD_PERIOD_SHIFT 0 +#define MAX77620_FPS_TIME_PERIOD_MASK 0x38 +#define MAX77620_FPS_TIME_PERIOD_SHIFT 3 +#define MAX77620_FPS_EN_SRC_MASK 0x06 +#define MAX77620_FPS_EN_SRC_SHIFT 1 +#define MAX77620_FPS_ENFPS_SW_MASK 0x01 +#define MAX77620_FPS_ENFPS_SW 0x01 + +/* Minimum and maximum FPS period time (in microseconds) are + * different for MAX77620 and Max20024. + */ +#define MAX77620_FPS_PERIOD_MIN_US 40 +#define MAX20024_FPS_PERIOD_MIN_US 20 + +#define MAX77620_FPS_PERIOD_MAX_US 2560 +#define MAX20024_FPS_PERIOD_MAX_US 5120 + +#define MAX77620_REG_FPS_GPIO1 0x54 +#define MAX77620_REG_FPS_GPIO2 0x55 +#define MAX77620_REG_FPS_GPIO3 0x56 +#define MAX77620_REG_FPS_RSO 0x57 +#define MAX77620_REG_CID0 0x58 +#define MAX77620_REG_CID1 0x59 +#define MAX77620_REG_CID2 0x5A +#define MAX77620_REG_CID3 0x5B +#define MAX77620_REG_CID4 0x5C +#define MAX77620_REG_CID5 0x5D + +#define MAX77620_REG_DVSSD4 0x5E +#define MAX20024_REG_MAX_ADD 0x70 + +#define MAX77620_CID_DIDM_MASK 0xF0 +#define MAX77620_CID_DIDM_SHIFT 4 + +/* CNCG2SD */ +#define MAX77620_SD_CNF2_ROVS_EN_SD1 (1 << 1) +#define MAX77620_SD_CNF2_ROVS_EN_SD0 (1 << 2) + +/* Device Identification Metal */ +#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF) +/* Device Indentification OTP */ +#define MAX77620_CID5_DIDO(n) ((n) & 0xF) + +/* SD CNFG1 */ +#define MAX77620_SD_SR_MASK 0xC0 +#define MAX77620_SD_SR_SHIFT 6 +#define MAX77620_SD_POWER_MODE_MASK 0x30 +#define MAX77620_SD_POWER_MODE_SHIFT 4 +#define MAX77620_SD_CFG1_ADE_MASK (1 << 3) +#define MAX77620_SD_CFG1_ADE_DISABLE 0 +#define MAX77620_SD_CFG1_ADE_ENABLE (1 << 3) +#define MAX77620_SD_FPWM_MASK 0x04 +#define MAX77620_SD_FPWM_SHIFT 2 +#define MAX77620_SD_FSRADE_MASK 0x01 +#define MAX77620_SD_FSRADE_SHIFT 0 +#define MAX77620_SD_CFG1_FPWM_SD_MASK (1 << 2) +#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0 +#define MAX77620_SD_CFG1_FPWM_SD_FPWM (1 << 2) +#define MAX20024_SD_CFG1_MPOK_MASK (1 << 1) +#define MAX77620_SD_CFG1_FSRADE_SD_MASK (1 << 0) +#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0 +#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0) + +/* LDO_CNFG2 */ +#define MAX77620_LDO_POWER_MODE_MASK 0xC0 +#define MAX77620_LDO_POWER_MODE_SHIFT 6 +#define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2) +#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1) +#define MAX77620_LDO_CFG2_ADE_DISABLE 0 +#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1) +#define MAX77620_LDO_CFG2_SS_MASK (1 << 0) +#define MAX77620_LDO_CFG2_SS_FAST (1 << 0) +#define MAX77620_LDO_CFG2_SS_SLOW 0 + +#define MAX77620_IRQ_TOP_GLBL_MASK (1 << 7) +#define MAX77620_IRQ_TOP_SD_MASK (1 << 6) +#define MAX77620_IRQ_TOP_LDO_MASK (1 << 5) +#define MAX77620_IRQ_TOP_GPIO_MASK (1 << 4) +#define MAX77620_IRQ_TOP_RTC_MASK (1 << 3) +#define MAX77620_IRQ_TOP_32K_MASK (1 << 2) +#define MAX77620_IRQ_TOP_ONOFF_MASK (1 << 1) + +#define MAX77620_IRQ_LBM_MASK (1 << 3) +#define MAX77620_IRQ_TJALRM1_MASK (1 << 2) +#define MAX77620_IRQ_TJALRM2_MASK (1 << 1) + +#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0) +#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0) +#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0 +#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1) +#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1) +#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0 +#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0 +#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4) +#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4) +#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5) +#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6) +#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6) +#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6) +#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6) +#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6) + +#define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0) +#define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1) +#define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2) +#define MAX77620_IRQ_LVL2_GPIO_EDGE3 (1 << 3) +#define MAX77620_IRQ_LVL2_GPIO_EDGE4 (1 << 4) +#define MAX77620_IRQ_LVL2_GPIO_EDGE5 (1 << 5) +#define MAX77620_IRQ_LVL2_GPIO_EDGE6 (1 << 6) +#define MAX77620_IRQ_LVL2_GPIO_EDGE7 (1 << 7) + +#define MAX77620_CNFG1_32K_OUT0_EN (1 << 2) + +#define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7) +#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38 +#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3 +#define MAX77620_ONOFFCNFG1_SLPEN (1 << 2) +#define MAX77620_ONOFFCNFG1_PWR_OFF (1 << 1) +#define MAX20024_ONOFFCNFG1_CLRSE 0x18 + +#define MAX77620_ONOFFCNFG2_SFT_RST_WK (1 << 7) +#define MAX77620_ONOFFCNFG2_WD_RST_WK (1 << 6) +#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK (1 << 5) +#define MAX77620_ONOFFCNFG2_WK_ALARM1 (1 << 2) +#define MAX77620_ONOFFCNFG2_WK_EN0 (1 << 0) + +#define MAX77620_GLBLM_MASK (1 << 0) + +#define MAX77620_WDTC_MASK 0x3 +#define MAX77620_WDTOFFC (1 << 4) +#define MAX77620_WDTSLPC (1 << 3) +#define MAX77620_WDTEN (1 << 2) + +#define MAX77620_TWD_MASK 0x3 +#define MAX77620_TWD_2s 0x0 +#define MAX77620_TWD_16s 0x1 +#define MAX77620_TWD_64s 0x2 +#define MAX77620_TWD_128s 0x3 + +#define MAX77620_CNFGGLBL1_LBDAC_EN (1 << 7) +#define MAX77620_CNFGGLBL1_MPPLD (1 << 6) +#define MAX77620_CNFGGLBL1_LBHYST ((1 << 5) | (1 << 4)) +#define MAX77620_CNFGGLBL1_LBHYST_N (1 << 4) +#define MAX77620_CNFGGLBL1_LBDAC 0x0E +#define MAX77620_CNFGGLBL1_LBDAC_N (1 << 1) +#define MAX77620_CNFGGLBL1_LBRSTEN (1 << 0) + +/* CNFG BBC registers */ +#define MAX77620_CNFGBBC_ENABLE (1 << 0) +#define MAX77620_CNFGBBC_CURRENT_MASK 0x06 +#define MAX77620_CNFGBBC_CURRENT_SHIFT 1 +#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18 +#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3 +#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5) +#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0 +#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6 + +#define MAX77620_FPS_COUNT 3 + +/* Interrupts */ +enum { + MAX77620_IRQ_TOP_GLBL, /* Low-Battery */ + MAX77620_IRQ_TOP_SD, /* SD power fail */ + MAX77620_IRQ_TOP_LDO, /* LDO power fail */ + MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */ + MAX77620_IRQ_TOP_RTC, /* RTC */ + MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */ + MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */ + MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */ + MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */ + MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */ +}; + +/* GPIOs */ +enum { + MAX77620_GPIO0, + MAX77620_GPIO1, + MAX77620_GPIO2, + MAX77620_GPIO3, + MAX77620_GPIO4, + MAX77620_GPIO5, + MAX77620_GPIO6, + MAX77620_GPIO7, + MAX77620_GPIO_NR, +}; + +/* FPS Source */ +enum max77620_fps_src { + MAX77620_FPS_SRC_0, + MAX77620_FPS_SRC_1, + MAX77620_FPS_SRC_2, + MAX77620_FPS_SRC_NONE, + MAX77620_FPS_SRC_DEF, +}; + +enum max77620_chip_id { + MAX77620, + MAX20024, +}; + +#endif /* _MFD_MAX77620_H_ */ diff --git a/fusee/fusee-primary/src/max7762x.c b/fusee/fusee-primary/src/max7762x.c new file mode 100644 index 000000000..419a13bce --- /dev/null +++ b/fusee/fusee-primary/src/max7762x.c @@ -0,0 +1,161 @@ +#include + +#include "max7762x.h" +#include "max77620.h" +#include "i2c.h" +#include "timers.h" + +#define REGULATOR_SD 0 +#define REGULATOR_LDO 1 + +typedef struct _max77620_regulator_t +{ + uint8_t type; + const char *name; + uint8_t reg_sd; + uint32_t mv_step; + uint32_t mv_min; + uint32_t mv_default; + uint32_t mv_max; + uint8_t volt_addr; + uint8_t cfg_addr; + uint8_t volt_mask; + uint8_t enable_mask; + uint8_t enable_shift; + uint8_t status_mask; + + uint8_t fps_addr; + uint8_t fps_src; + uint8_t pd_period; + uint8_t pu_period; +} max77620_regulator_t; + +static const max77620_regulator_t _pmic_regulators[] = { + { REGULATOR_SD, "sd0", 0x16, 12500, 600000, 625000, 1400000, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, 0x3F, 0x30, 4, 0x80, 0x4F, 1, 7, 1 }, + { REGULATOR_SD, "sd1", 0x17, 12500, 600000, 1125000, 1125000, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, 0x3F, 0x30, 4, 0x40, 0x50, 0, 1, 5 }, + { REGULATOR_SD, "sd2", 0x18, 12500, 600000, 1325000, 1350000, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, 0xFF, 0x30, 4, 0x20, 0x51, 1, 5, 2 }, + { REGULATOR_SD, "sd3", 0x19, 12500, 600000, 1800000, 1800000, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, 0xFF, 0x30, 4, 0x10, 0x52, 0, 3, 3 }, + { REGULATOR_LDO, "ldo0", 0x00, 25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, 0x3F, 0xC0, 6, 0x00, 0x46, 3, 7, 0 }, + { REGULATOR_LDO, "ldo1", 0x00, 25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, 0x3F, 0xC0, 6, 0x00, 0x47, 3, 7, 0 }, + { REGULATOR_LDO, "ldo2", 0x00, 50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, 0x3F, 0xC0, 6, 0x00, 0x48, 3, 7, 0 }, + { REGULATOR_LDO, "ldo3", 0x00, 50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, 0x3F, 0xC0, 6, 0x00, 0x49, 3, 7, 0 }, + { REGULATOR_LDO, "ldo4", 0x00, 12500, 800000, 850000, 850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4A, 0, 7, 1 }, + { REGULATOR_LDO, "ldo5", 0x00, 50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4B, 3, 7, 0 }, + { REGULATOR_LDO, "ldo6", 0x00, 50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4C, 3, 7, 0 }, + { REGULATOR_LDO, "ldo7", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4D, 1, 4, 3 }, + { REGULATOR_LDO, "ldo8", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4E, 3, 7, 0 } +}; + +int max77620_regulator_get_status(uint32_t id) +{ + if (id > REGULATOR_MAX) + return 0; + + const max77620_regulator_t *reg = &_pmic_regulators[id]; + uint8_t val = 0; + + if (reg->type == REGULATOR_SD) { + if (i2c_query(4, 0x3C, MAX77620_REG_STATSD, &val, 1)) + return (val & reg->status_mask) ? 0 : 1; + } + + if (i2c_query(4, 0x3C, reg->cfg_addr, &val, 1)) + return (val & 8) ? 0 : 1; + + return 0; +} + +int max77620_regulator_config_fps(uint32_t id) +{ + if (id > REGULATOR_MAX) + return 0; + + const max77620_regulator_t *reg = &_pmic_regulators[id]; + uint8_t val = ((reg->fps_src << 6) | (reg->pu_period << 3) | (reg->pd_period)); + + if (i2c_send(4, 0x3C, reg->fps_addr, &val, 1)) { + return 1; + } + + return 0; +} + +int max77620_regulator_set_voltage(uint32_t id, uint32_t mv) +{ + if (id > REGULATOR_MAX) + return 0; + + const max77620_regulator_t *reg = &_pmic_regulators[id]; + + if ((mv < reg->mv_default) || (mv > reg->mv_max)) + return 0; + + uint32_t mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step; + uint8_t val = 0; + + if (i2c_query(4, 0x3C, reg->volt_addr, &val, 1)) + { + val = ((val & ~reg->volt_mask) | (mult & reg->volt_mask)); + + if (i2c_send(4, 0x3C, reg->volt_addr, &val, 1)) + { + udelay(1000); + return 1; + } + } + + return 0; +} + +int max77620_regulator_enable(uint32_t id, int enable) +{ + if (id > REGULATOR_MAX) + return 0; + + const max77620_regulator_t *reg = &_pmic_regulators[id]; + + uint32_t addr = (reg->type == REGULATOR_SD) ? reg->cfg_addr : reg->volt_addr; + uint8_t val = 0; + + if (i2c_query(4, 0x3C, addr, &val, 1)) + { + if (enable) + val = ((val & ~reg->enable_mask) | ((3 << reg->enable_shift) & reg->enable_mask)); + else + val &= ~reg->enable_mask; + + if (i2c_send(4, 0x3C, addr, &val, 1)) + { + udelay(1000); + return 1; + } + } + + return 0; +} + +void max77620_config_default() +{ + for (uint32_t i = 1; i <= REGULATOR_MAX; i++) + { + uint8_t val = 0; + if (i2c_query(4, 0x3C, MAX77620_REG_CID4, &val, 1)) + { + max77620_regulator_config_fps(i); + max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default); + + if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE) { + max77620_regulator_enable(i, 1); + } + } + } + + uint8_t val = 4; + i2c_send(4, 0x3C, MAX77620_REG_SD_CFG2, &val, 1); +} + +void max77620_low_battery_monitor_config() +{ + uint8_t val = (MAX77620_CNFGGLBL1_LBDAC_EN | MAX77620_CNFGGLBL1_LBHYST_N | MAX77620_CNFGGLBL1_LBDAC_N); + i2c_send(4, 0x3C, MAX77620_REG_CNFGGLBL1, &val, 1); +} diff --git a/fusee/fusee-primary/src/hwinit/max7762x.h b/fusee/fusee-primary/src/max7762x.h old mode 100755 new mode 100644 similarity index 62% rename from fusee/fusee-primary/src/hwinit/max7762x.h rename to fusee/fusee-primary/src/max7762x.h index 05434956e..c106a27d4 --- a/fusee/fusee-primary/src/hwinit/max7762x.h +++ b/fusee/fusee-primary/src/max7762x.h @@ -1,34 +1,16 @@ -/* -* Copyright (c) 2018 naehrwert -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . -*/ - -#ifndef _MAX7762X_H_ -#define _MAX7762X_H_ - -#include "types.h" +#ifndef FUSEE_MAX7762X_H_ +#define FUSEE_MAX7762X_H_ /* * Switch Power domains (max77620): * Name | Usage | uV step | uV min | uV default | uV max | Init *-------+---------------+---------+--------+------------+---------+------------------ * sd0 | core | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1) -* sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1) +* sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1) * sd2 | ldo{0-1, 7-8} | 12500 | 600000 | 1325000 | 1350000 | 1.325V (pcv) * sd3 | 1.8V general | 12500 | 600000 | 1800000 | 1800000 | -* ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1) -* ldo1 | XUSB | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv) +* ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1) +* ldo1 | XUSB, PCIE | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv) * ldo2 | SDMMC1 | 50000 | 800000 | 1800000 | 3300000 | * ldo3 | | 50000 | 800000 | 3100000 | 3100000 | * ldo4 | RTC | 12500 | 800000 | 850000 | 850000 | @@ -59,10 +41,11 @@ #define REGULATOR_LDO8 12 #define REGULATOR_MAX 12 -int max77620_regulator_get_status(u32 id); -int max77620_regulator_config_fps(u32 id); -int max77620_regulator_set_voltage(u32 id, u32 mv); -int max77620_regulator_enable(u32 id, int enable); +int max77620_regulator_get_status(uint32_t id); +int max77620_regulator_config_fps(uint32_t id); +int max77620_regulator_set_voltage(uint32_t id, uint32_t mv); +int max77620_regulator_enable(uint32_t id, int enable); void max77620_config_default(); +void max77620_low_battery_monitor_config(); #endif diff --git a/fusee/fusee-primary/src/mc.c b/fusee/fusee-primary/src/mc.c new file mode 100644 index 000000000..a98b6fbf7 --- /dev/null +++ b/fusee/fusee-primary/src/mc.c @@ -0,0 +1,146 @@ +#include "mc.h" +#include "car.h" +#include "timers.h" + +void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock) +{ + MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = bom; + MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = size1mb; + + if (lock) + MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = 1; +} + +void mc_config_carveout() +{ + *(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0; + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0; + MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0; + MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1; + + mc_config_tsec_carveout(0, 0, 1); + + MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0; + MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0; + MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0; + MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006; + + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM_HI) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0x3000000; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0x300; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F; +} + +void mc_config_carveout_finalize() +{ + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM_HI) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = 0x3000000; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = 0x300; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E; +} + +void mc_enable_ahb_redirect() +{ + volatile tegra_car_t *car = car_get_regs(); + car->lvl2_clk_gate_ovrd = ((car->lvl2_clk_gate_ovrd & 0xFFF7FFFF) | 0x80000); + + MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000; + MAKE_MC_REG(MC_IRAM_TOM) = 0x4003F000; +} + +void mc_disable_ahb_redirect() +{ + volatile tegra_car_t *car = car_get_regs(); + + MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000; + MAKE_MC_REG(MC_IRAM_TOM) = 0; + + car->lvl2_clk_gate_ovrd &= 0xFFF7FFFF; +} + +void mc_enable() +{ + volatile tegra_car_t *car = car_get_regs(); + + /* Set EMC clock source. */ + car->clk_source_emc = ((car->clk_source_emc & 0x1FFFFFFF) | 0x40000000); + + /* Enable MIPI CAL clock. */ + car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFDFFFFFF) | 0x2000000); + + /* Enable MC clock. */ + car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFFFFFFFE) | 1); + + /* Enable EMC DLL clock. */ + car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000); + + /* Clear EMC and MC reset. */ + car->rst_dev_h_set = 0x2000001; + udelay(5); + + mc_disable_ahb_redirect(); +} \ No newline at end of file diff --git a/fusee/fusee-primary/src/hwinit/mc.h b/fusee/fusee-primary/src/mc.h similarity index 98% rename from fusee/fusee-primary/src/hwinit/mc.h rename to fusee/fusee-primary/src/mc.h index 7eebdf4e0..e93bfc7bf 100644 --- a/fusee/fusee-primary/src/hwinit/mc.h +++ b/fusee/fusee-primary/src/mc.h @@ -1,18 +1,11 @@ -/* -* Copyright (c) 2014, NVIDIA Corporation. All rights reserved. -* -* This software is licensed under the terms of the GNU General Public -* License version 2, as published by the Free Software Foundation, and -* may be copied, distributed, and modified under those terms. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -*/ +#ifndef FUSEE_MC_H_ +#define FUSEE_MC_H_ -#ifndef _MC_H_ -#define _MC_ +#include +#include + +#define MC_BASE 0x70019000 +#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n) #define MC_INTSTATUS 0x0 #define MC_INTMASK 0x4 @@ -463,4 +456,11 @@ #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_DA_CONFIG0 0x9dc -#endif +void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock); +void mc_config_carveout(); +void mc_config_carveout_finalize(); +void mc_enable_ahb_redirect(); +void mc_disable_ahb_redirect(); +void mc_enable(); + +#endif \ No newline at end of file diff --git a/fusee/fusee-primary/src/panic.c b/fusee/fusee-primary/src/panic.c index b5c4591b6..ce0b54747 100644 --- a/fusee/fusee-primary/src/panic.c +++ b/fusee/fusee-primary/src/panic.c @@ -1,8 +1,8 @@ #include "panic.h" +#include "di.h" #include "pmc.h" #include "fuse.h" #include "utils.h" -#include "hwinit.h" static uint32_t g_panic_code = 0; diff --git a/fusee/fusee-primary/src/pinmux.h b/fusee/fusee-primary/src/pinmux.h index d7131d1d5..80fc3a37c 100644 --- a/fusee/fusee-primary/src/pinmux.h +++ b/fusee/fusee-primary/src/pinmux.h @@ -1,6 +1,9 @@ #ifndef FUSEE_PINMUX_H #define FUSEE_PINMUX_H +#define PINMUX_BASE 0x70003000 +#define MAKE_PINMUX_REG(n) MAKE_REG32(PINMUX_BASE + n) + #define PINMUX_TRISTATE (1 << 4) #define PINMUX_PARKED (1 << 5) #define PINMUX_INPUT (1 << 6) @@ -186,7 +189,7 @@ typedef struct { static inline volatile tegra_pinmux_t *pinmux_get_regs(void) { - return (volatile tegra_pinmux_t *)0x70003000; + return (volatile tegra_pinmux_t *)PINMUX_BASE; } #endif diff --git a/fusee/fusee-primary/src/pmc.h b/fusee/fusee-primary/src/pmc.h index 4c10d1a0e..0c851eb47 100644 --- a/fusee/fusee-primary/src/pmc.h +++ b/fusee/fusee-primary/src/pmc.h @@ -1,25 +1,49 @@ #ifndef FUSEE_PMC_H #define FUSEE_PMC_H -/* TODO: get rid of these defines; use the struct instead */ +#include + #define PMC_BASE 0x7000E400 +#define MAKE_PMC_REG(n) MAKE_REG32(PMC_BASE + n) #define PMC_CONTROL_SDMMC1 (1 << 12) #define PMC_CONTROL_SDMMC3 (1 << 13) #define PMC_CONTROL_SDMMC4 (1 << 14) -#define APBDEV_PMC_CONTROL MAKE_REG32(PMC_BASE + 0x00) -#define APBDEV_PMC_DPD_ENABLE_0 MAKE_REG32(PMC_BASE + 0x24) -#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_REG32(PMC_BASE + 0x30) -#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_REG32(PMC_BASE + 0x38) -#define APBDEV_PMC_SCRATCH0_0 MAKE_REG32(PMC_BASE + 0x50) -#define APBDEV_PMC_CRYPTO_OP_0 MAKE_REG32(PMC_BASE + 0xF4) -#define APBDEV_PM_0 MAKE_REG32(PMC_BASE + 0x14) -#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_REG32(PMC_BASE + 0x168) -#define APBDEV_PMC_RST_STATUS_0 MAKE_REG32(PMC_BASE + 0x1B4) -#define APBDEV_PMC_CNTRL2_0 MAKE_REG32(PMC_BASE + 0x440) -#define APBDEV_PMC_SCRATCH43_0 MAKE_REG32(PMC_BASE + 0x22C) -#define APBDEV_PMC_SCRATCH200_0 MAKE_REG32(PMC_BASE + 0x840) +#define APBDEV_PMC_CONTROL MAKE_PMC_REG(0x00) +#define APBDEV_PM_0 MAKE_PMC_REG(0x14) +#define APBDEV_PMC_DPD_ENABLE_0 MAKE_PMC_REG(0x24) +#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x30) +#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x38) +#define APBDEV_PMC_NO_IOPOWER_0 MAKE_PMC_REG(0x44) +#define APBDEV_PMC_SCRATCH0_0 MAKE_PMC_REG(0x50) +#define APBDEV_PMC_SCRATCH1_0 MAKE_PMC_REG(0x54) +#define APBDEV_PMC_SCRATCH20_0 MAKE_PMC_REG(0xA0) +#define APBDEV_PMC_PWR_DET_VAL_0 MAKE_PMC_REG(0xE4) +#define APBDEV_PMC_DDR_PWR_0 MAKE_PMC_REG(0xE8) +#define APBDEV_PMC_CRYPTO_OP_0 MAKE_PMC_REG(0xF4) +#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_PMC_REG(0x168) +#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4) +#define APBDEV_PMC_RST_STATUS_0 MAKE_PMC_REG(0x1B4) +#define APBDEV_PMC_IO_DPD_REQ_0 MAKE_PMC_REG(0x1B8) +#define APBDEV_PMC_IO_DPD2_REQ_0 MAKE_PMC_REG(0x1C0) +#define APBDEV_PMC_VDDP_SEL_0 MAKE_PMC_REG(0x1CC) +#define APBDEV_PMC_SCRATCH49_0 MAKE_PMC_REG(0x244) +#define APBDEV_PMC_TSC_MULT_0 MAKE_PMC_REG(0x2B4) +#define APBDEV_PMC_REG_SHORT_0 MAKE_PMC_REG(0x2CC) +#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8) +#define APBDEV_PMC_SECURE_SCRATCH21_0 MAKE_PMC_REG(0x334) +#define APBDEV_PMC_SECURE_SCRATCH32_0 MAKE_PMC_REG(0x360) +#define APBDEV_PMC_SECURE_SCRATCH49_0 MAKE_PMC_REG(0x3A4) +#define APBDEV_PMC_CNTRL2_0 MAKE_PMC_REG(0x440) +#define APBDEV_PMC_IO_DPD4_REQ_0 MAKE_PMC_REG(0x464) +#define APBDEV_PMC_UTMIP_PAD_CFG1_0 MAKE_PMC_REG(0x4C4) +#define APBDEV_PMC_UTMIP_PAD_CFG3_0 MAKE_PMC_REG(0x4CC) +#define APBDEV_PMC_DDR_CNTRL_0 MAKE_PMC_REG(0x4E4) +#define APBDEV_PMC_SCRATCH43_0 MAKE_PMC_REG(0x22C) +#define APBDEV_PMC_SCRATCH188_0 MAKE_PMC_REG(0x810) +#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818) +#define APBDEV_PMC_SCRATCH200_0 MAKE_PMC_REG(0x840) typedef struct { uint32_t cntrl; @@ -42,7 +66,6 @@ typedef struct { uint32_t no_iopower; uint32_t pwr_det; uint32_t pwr_det_latch; - uint32_t scratch0; uint32_t scratch1; uint32_t scratch2; @@ -67,14 +90,12 @@ typedef struct { uint32_t scratch21; uint32_t scratch22; uint32_t scratch23; - uint32_t secure_scratch0; uint32_t secure_scratch1; uint32_t secure_scratch2; uint32_t secure_scratch3; uint32_t secure_scratch4; uint32_t secure_scratch5; - uint32_t cpupwrgood_timer; uint32_t cpupwroff_timer; uint32_t pg_mask; @@ -88,7 +109,6 @@ typedef struct { uint32_t usb_ao; uint32_t crypto_op; uint32_t pllp_wb0_override; - uint32_t scratch24; uint32_t scratch25; uint32_t scratch26; @@ -108,7 +128,6 @@ typedef struct { uint32_t scratch40; uint32_t scratch41; uint32_t scratch42; - uint32_t bo_mirror0; uint32_t bo_mirror1; uint32_t bo_mirror2; @@ -143,10 +162,9 @@ typedef struct { uint32_t io_dpd2_stat; uint32_t sel_dpd_tim; uint32_t vddp_sel; - uint32_t ddr_cfg; uint32_t e_no_vttgen; - uint32_t reserved0; + uint32_t _reserved0; uint32_t pllm_wb0_ovrride_frq; uint32_t test_pwrgate; uint32_t pwrgate_timer_mult; @@ -156,8 +174,12 @@ typedef struct { uint32_t utmip_pad_cfg; uint32_t utmip_term_pad_cfg; uint32_t utmip_uhsic_sleep_cfg; - - uint32_t todo_0[9]; + uint32_t utmip_uhsic_sleepwalk_cfg; + uint32_t utmip_sleepwalk_p[3]; + uint32_t uhsic_sleepwalk_p0; + uint32_t utmip_uhsic_status; + uint32_t utmip_uhsic_fake; + uint32_t bo_mirror3[2]; uint32_t secure_scratch6; uint32_t secure_scratch7; uint32_t scratch43; @@ -176,7 +198,22 @@ typedef struct { uint32_t scratch0_eco; uint32_t por_dpd_ctrl; uint32_t scratch2_eco; - uint32_t todo_1[17]; + uint32_t utmip_uhsic_line_wakeup; + uint32_t utmip_bias_master_cntrl; + uint32_t utmip_master_config; + uint32_t td_pwrgate_inter_part_timer; + uint32_t utmip_uhsic2_triggers; + uint32_t utmip_uhsic2_saved_state; + uint32_t utmip_uhsic2_sleep_cfg; + uint32_t utmip_uhsic2_sleepwalk_cfg; + uint32_t uhsic2_sleepwalk_p1; + uint32_t utmip_uhsic2_status; + uint32_t utmip_uhsic2_fake; + uint32_t utmip_uhsic2_line_wakeup; + uint32_t utmip_master2_config; + uint32_t utmip_uhsic_rpd_cfg; + uint32_t pg_mask_ce0; + uint32_t pg_mask3[2]; uint32_t pllm_wb0_override2; uint32_t tsc_mult; uint32_t cpu_vsense_override; @@ -184,7 +221,9 @@ typedef struct { uint32_t sticky_bits; uint32_t sec_disable2; uint32_t weak_bias; - uint32_t todo_3[13]; + uint32_t reg_short; + uint32_t pg_mask_andor; + uint32_t _reserved1[11]; uint32_t secure_scratch8; uint32_t secure_scratch9; uint32_t secure_scratch10; @@ -213,15 +252,64 @@ typedef struct { uint32_t secure_scratch33; uint32_t secure_scratch34; uint32_t secure_scratch35; - - uint32_t reserved1[52]; + uint32_t secure_scratch36; + uint32_t secure_scratch37; + uint32_t secure_scratch38; + uint32_t secure_scratch39; + uint32_t secure_scratch40; + uint32_t secure_scratch41; + uint32_t secure_scratch42; + uint32_t secure_scratch43; + uint32_t secure_scratch44; + uint32_t secure_scratch45; + uint32_t secure_scratch46; + uint32_t secure_scratch47; + uint32_t secure_scratch48; + uint32_t secure_scratch49; + uint32_t secure_scratch50; + uint32_t secure_scratch51; + uint32_t secure_scratch52; + uint32_t secure_scratch53; + uint32_t secure_scratch54; + uint32_t secure_scratch55; + uint32_t secure_scratch56; + uint32_t secure_scratch57; + uint32_t secure_scratch58; + uint32_t secure_scratch59; + uint32_t secure_scratch60; + uint32_t secure_scratch61; + uint32_t secure_scratch62; + uint32_t secure_scratch63; + uint32_t secure_scratch64; + uint32_t secure_scratch65; + uint32_t secure_scratch66; + uint32_t secure_scratch67; + uint32_t secure_scratch68; + uint32_t secure_scratch69; + uint32_t secure_scratch70; + uint32_t secure_scratch71; + uint32_t secure_scratch72; + uint32_t secure_scratch73; + uint32_t secure_scratch74; + uint32_t secure_scratch75; + uint32_t secure_scratch76; + uint32_t secure_scratch77; + uint32_t secure_scratch78; + uint32_t secure_scratch79; + uint32_t _reserved2[8]; uint32_t cntrl2; - uint32_t reserved2[6]; + uint32_t _reserved3[2]; + uint32_t event_counter; + uint32_t fuse_control; + uint32_t scratch1_eco; + uint32_t _reserved4; uint32_t io_dpd3_req; - uint32_t io_dpd3_stat; - uint32_t strap_opt_a; - uint32_t reserved3[102]; - + uint32_t io_dpd3_status; + uint32_t io_dpd4_req; + uint32_t io_dpd4_status; + uint32_t _reserved5[30]; + uint32_t ddr_cntrl; + uint32_t _reserved6[70]; uint32_t scratch56; uint32_t scratch57; uint32_t scratch58; @@ -286,12 +374,232 @@ typedef struct { uint32_t scratch117; uint32_t scratch118; uint32_t scratch119; - uint32_t scratch1_eco; + uint32_t scratch120; + uint32_t scratch121; + uint32_t scratch122; + uint32_t scratch123; + uint32_t scratch124; + uint32_t scratch125; + uint32_t scratch126; + uint32_t scratch127; + uint32_t scratch128; + uint32_t scratch129; + uint32_t scratch130; + uint32_t scratch131; + uint32_t scratch132; + uint32_t scratch133; + uint32_t scratch134; + uint32_t scratch135; + uint32_t scratch136; + uint32_t scratch137; + uint32_t scratch138; + uint32_t scratch139; + uint32_t scratch140; + uint32_t scratch141; + uint32_t scratch142; + uint32_t scratch143; + uint32_t scratch144; + uint32_t scratch145; + uint32_t scratch146; + uint32_t scratch147; + uint32_t scratch148; + uint32_t scratch149; + uint32_t scratch150; + uint32_t scratch151; + uint32_t scratch152; + uint32_t scratch153; + uint32_t scratch154; + uint32_t scratch155; + uint32_t scratch156; + uint32_t scratch157; + uint32_t scratch158; + uint32_t scratch159; + uint32_t scratch160; + uint32_t scratch161; + uint32_t scratch162; + uint32_t scratch163; + uint32_t scratch164; + uint32_t scratch165; + uint32_t scratch166; + uint32_t scratch167; + uint32_t scratch168; + uint32_t scratch169; + uint32_t scratch170; + uint32_t scratch171; + uint32_t scratch172; + uint32_t scratch173; + uint32_t scratch174; + uint32_t scratch175; + uint32_t scratch176; + uint32_t scratch177; + uint32_t scratch178; + uint32_t scratch179; + uint32_t scratch180; + uint32_t scratch181; + uint32_t scratch182; + uint32_t scratch183; + uint32_t scratch184; + uint32_t scratch185; + uint32_t scratch186; + uint32_t scratch187; + uint32_t scratch188; + uint32_t scratch189; + uint32_t scratch190; + uint32_t scratch191; + uint32_t scratch192; + uint32_t scratch193; + uint32_t scratch194; + uint32_t scratch195; + uint32_t scratch196; + uint32_t scratch197; + uint32_t scratch198; + uint32_t scratch199; + uint32_t scratch200; + uint32_t scratch201; + uint32_t scratch202; + uint32_t scratch203; + uint32_t scratch204; + uint32_t scratch205; + uint32_t scratch206; + uint32_t scratch207; + uint32_t scratch208; + uint32_t scratch209; + uint32_t scratch210; + uint32_t scratch211; + uint32_t scratch212; + uint32_t scratch213; + uint32_t scratch214; + uint32_t scratch215; + uint32_t scratch216; + uint32_t scratch217; + uint32_t scratch218; + uint32_t scratch219; + uint32_t scratch220; + uint32_t scratch221; + uint32_t scratch222; + uint32_t scratch223; + uint32_t scratch224; + uint32_t scratch225; + uint32_t scratch226; + uint32_t scratch227; + uint32_t scratch228; + uint32_t scratch229; + uint32_t scratch230; + uint32_t scratch231; + uint32_t scratch232; + uint32_t scratch233; + uint32_t scratch234; + uint32_t scratch235; + uint32_t scratch236; + uint32_t scratch237; + uint32_t scratch238; + uint32_t scratch239; + uint32_t scratch240; + uint32_t scratch241; + uint32_t scratch242; + uint32_t scratch243; + uint32_t scratch244; + uint32_t scratch245; + uint32_t scratch246; + uint32_t scratch247; + uint32_t scratch248; + uint32_t scratch249; + uint32_t scratch250; + uint32_t scratch251; + uint32_t scratch252; + uint32_t scratch253; + uint32_t scratch254; + uint32_t scratch255; + uint32_t scratch256; + uint32_t scratch257; + uint32_t scratch258; + uint32_t scratch259; + uint32_t scratch260; + uint32_t scratch261; + uint32_t scratch262; + uint32_t scratch263; + uint32_t scratch264; + uint32_t scratch265; + uint32_t scratch266; + uint32_t scratch267; + uint32_t scratch268; + uint32_t scratch269; + uint32_t scratch270; + uint32_t scratch271; + uint32_t scratch272; + uint32_t scratch273; + uint32_t scratch274; + uint32_t scratch275; + uint32_t scratch276; + uint32_t scratch277; + uint32_t scratch278; + uint32_t scratch279; + uint32_t scratch280; + uint32_t scratch281; + uint32_t scratch282; + uint32_t scratch283; + uint32_t scratch284; + uint32_t scratch285; + uint32_t scratch286; + uint32_t scratch287; + uint32_t scratch288; + uint32_t scratch289; + uint32_t scratch290; + uint32_t scratch291; + uint32_t scratch292; + uint32_t scratch293; + uint32_t scratch294; + uint32_t scratch295; + uint32_t scratch296; + uint32_t scratch297; + uint32_t scratch298; + uint32_t scratch299; + uint32_t _reserved7[50]; + uint32_t secure_scratch80; + uint32_t secure_scratch81; + uint32_t secure_scratch82; + uint32_t secure_scratch83; + uint32_t secure_scratch84; + uint32_t secure_scratch85; + uint32_t secure_scratch86; + uint32_t secure_scratch87; + uint32_t secure_scratch88; + uint32_t secure_scratch89; + uint32_t secure_scratch90; + uint32_t secure_scratch91; + uint32_t secure_scratch92; + uint32_t secure_scratch93; + uint32_t secure_scratch94; + uint32_t secure_scratch95; + uint32_t secure_scratch96; + uint32_t secure_scratch97; + uint32_t secure_scratch98; + uint32_t secure_scratch99; + uint32_t secure_scratch100; + uint32_t secure_scratch101; + uint32_t secure_scratch102; + uint32_t secure_scratch103; + uint32_t secure_scratch104; + uint32_t secure_scratch105; + uint32_t secure_scratch106; + uint32_t secure_scratch107; + uint32_t secure_scratch108; + uint32_t secure_scratch109; + uint32_t secure_scratch110; + uint32_t secure_scratch111; + uint32_t secure_scratch112; + uint32_t secure_scratch113; + uint32_t secure_scratch114; + uint32_t secure_scratch115; + uint32_t secure_scratch116; + uint32_t secure_scratch117; + uint32_t secure_scratch118; + uint32_t secure_scratch119; } tegra_pmc_t; static inline volatile tegra_pmc_t *pmc_get_regs(void) { - return (volatile tegra_pmc_t *)0x7000E400; + return (volatile tegra_pmc_t *)PMC_BASE; } #endif diff --git a/fusee/fusee-primary/src/sdmmc/sdmmc_core.c b/fusee/fusee-primary/src/sdmmc/sdmmc_core.c index 85cab87ba..c30a1f837 100644 --- a/fusee/fusee-primary/src/sdmmc/sdmmc_core.c +++ b/fusee/fusee-primary/src/sdmmc/sdmmc_core.c @@ -11,8 +11,8 @@ #include "../apb_misc.h" #include "../gpio.h" #include "../pmc.h" +#include "../max7762x.h" #include "../lib/driver_utils.h" -#include "../hwinit/max7762x.h" static SdmmcLogLevel g_sdmmc_log_level = SDMMC_LOG_NONE; @@ -399,16 +399,16 @@ static int sdmmc_clk_set_source(SdmmcControllerNum controller, uint32_t clk_freq switch (controller) { case SDMMC_1: - car->clk_src[CLK_SOURCE_SDMMC1] = (CLK_SOURCE_FIRST | car_div); + car->clk_source_sdmmc1 = (CLK_SOURCE_FIRST | car_div); break; case SDMMC_2: - car->clk_src[CLK_SOURCE_SDMMC2] = (CLK_SOURCE_FIRST | car_div); + car->clk_source_sdmmc2 = (CLK_SOURCE_FIRST | car_div); break; case SDMMC_3: - car->clk_src[CLK_SOURCE_SDMMC3] = (CLK_SOURCE_FIRST | car_div); + car->clk_source_sdmmc3 = (CLK_SOURCE_FIRST | car_div); break; case SDMMC_4: - car->clk_src[CLK_SOURCE_SDMMC4] = (CLK_SOURCE_FIRST | car_div); + car->clk_source_sdmmc4 = (CLK_SOURCE_FIRST | car_div); break; } diff --git a/fusee/fusee-primary/src/sdram.c b/fusee/fusee-primary/src/sdram.c new file mode 100644 index 000000000..eb941f235 --- /dev/null +++ b/fusee/fusee-primary/src/sdram.c @@ -0,0 +1,561 @@ +#include "i2c.h" +#include "mc.h" +#include "emc.h" +#include "pmc.h" +#include "timers.h" +#include "sysreg.h" +#include "fuse.h" +#include "max77620.h" +#include "sdram_param_t210.h" +#include "car.h" + +#define CONFIG_SDRAM_COMPRESS_CFG + +#ifdef CONFIG_SDRAM_COMPRESS_CFG +#include "lib/lz.h" +#include "sdram_lz.inl" +#else +#include "sdram.inl" +#endif + +static uint32_t _get_sdram_id() +{ + return ((fuse_get_reserved_odm(4) & 0x38) >> 3); +} + +static void _sdram_config(const sdram_params_t *params) +{ + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pmc_t *pmc = pmc_get_regs(); + + pmc->io_dpd3_req = (((4 * params->emc_pmc_scratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF; + udelay(params->pmc_io_dpd3_req_wait); + + uint32_t req = (4 * params->emc_pmc_scratch2 >> 2) + 0x80000000; + pmc->io_dpd4_req = (req >> 16 << 16) ^ 0x3FFF0000; + + udelay(params->pmc_io_dpd4_req_wait); + pmc->io_dpd4_req = (req ^ 0xFFFF) & 0xC000FFFF; + udelay(params->pmc_io_dpd4_req_wait); + + pmc->weak_bias = 0; + udelay(1); + + car->pllm_misc1 = params->pllm_setup_control; + car->pllm_misc2 = 0; + car->pllm_base = ((params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20)); + + bool timeout = false; + uint32_t wait_end = get_time_us() + 300; + + while (!(car->pllm_base & 0x8000000) && !timeout) + { + if (get_time_us() >= wait_end) + timeout = true; + } + + if (!timeout) { + udelay(10); + } + + car->clk_source_emc = (((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF)); + + if (params->emc_clock_source_dll) + car->clk_source_emc_dll = params->emc_clock_source_dll; + + if (params->clear_clock2_mc1) + car->clk_enb_w_clr = 0x40000000; + + car->clk_enb_h_set = 0x2000001; + car->clk_enb_x_set = 0x4000; + car->rst_dev_h_clr = 0x2000001; + + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_0) = params->emc_pmacro_vttgen_ctrl0; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_1) = params->emc_pmacro_vttgen_ctrl1; + MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_2) = params->emc_pmacro_vttgen_ctrl2; + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + udelay(1); + + MAKE_EMC_REG(EMC_DBG) = (params->emc_dbg_write_mux << 1) | params->emc_dbg; + + if (params->emc_bct_spare2) + *(volatile uint32_t *)params->emc_bct_spare2 = params->emc_bct_spare3; + + MAKE_EMC_REG(EMC_FBIO_CFG7) = params->emc_fbio_cfg7; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_0) = params->emc_cmd_mapping_cmd1_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_1) = params->emc_cmd_mapping_cmd1_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_2) = params->emc_cmd_mapping_cmd1_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_0) = params->emc_cmd_mapping_cmd2_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_1) = params->emc_cmd_mapping_cmd2_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_2) = params->emc_cmd_mapping_cmd2_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1; + MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2; + MAKE_EMC_REG(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_1) = params->emc_pmacro_brick_mapping1; + MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_2) = params->emc_pmacro_brick_mapping2; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->emc_pmacro_brick_ctrl_rfu1 & 0x1120112) | 0x1EED1EED); + MAKE_EMC_REG(EMC_CONFIG_SAMPLE_DELAY) = params->emc_config_sample_delay; + MAKE_EMC_REG(EMC_FBIO_CFG8) = params->emc_fbio_cfg8; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE0) = params->emc_swizzle_rank0_byte0; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE1) = params->emc_swizzle_rank0_byte1; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE2) = params->emc_swizzle_rank0_byte2; + MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE3) = params->emc_swizzle_rank0_byte3; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE0) = params->emc_swizzle_rank1_byte0; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE1) = params->emc_swizzle_rank1_byte1; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE2) = params->emc_swizzle_rank1_byte2; + MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE3) = params->emc_swizzle_rank1_byte3; + + if (params->emc_bct_spare6) + *(volatile uint32_t *)params->emc_bct_spare6 = params->emc_bct_spare7; + + MAKE_EMC_REG(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; + MAKE_EMC_REG(EMC_XM2COMPPADCTRL2) = params->emc_xm2_comp_pad_ctrl2; + MAKE_EMC_REG(EMC_XM2COMPPADCTRL3) = params->emc_xm2_comp_pad_ctrl3; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG2) = params->emc_auto_cal_config2; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG3) = params->emc_auto_cal_config3; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG4) = params->emc_auto_cal_config4; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG5) = params->emc_auto_cal_config5; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG6) = params->emc_auto_cal_config6; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8; + MAKE_EMC_REG(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; + MAKE_EMC_REG(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; + MAKE_EMC_REG(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; + MAKE_EMC_REG(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common; + MAKE_EMC_REG(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; + MAKE_EMC_REG(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; + MAKE_EMC_REG(EMC_DLL_CFG_0) = params->emc_dll_cfg0; + MAKE_EMC_REG(EMC_DLL_CFG_1) = params->emc_dll_cfg1; + MAKE_EMC_REG(EMC_CFG_DIG_DLL_1) = params->emc_cfg_dig_dll_1; + MAKE_EMC_REG(EMC_DATA_BRLSHFT_0) = params->emc_data_brlshft0; + MAKE_EMC_REG(EMC_DATA_BRLSHFT_1) = params->emc_data_brlshft1; + MAKE_EMC_REG(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; + MAKE_EMC_REG(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; + MAKE_EMC_REG(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_0) = params->emc_quse_brlshft0; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2; + MAKE_EMC_REG(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->emc_pmacro_brick_ctrl_rfu1 & 0x1BF01BF) | 0x1E401E40); + MAKE_EMC_REG(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = (params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F); + MAKE_EMC_REG(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd; + MAKE_EMC_REG(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0; + MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; + MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; + MAKE_EMC_REG(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; + MAKE_EMC_REG(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; + MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl; + MAKE_EMC_REG(EMC_CFG_3) = params->emc_cfg3; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; + MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->emc_pmacro_tx_sel_clk_src0; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->emc_pmacro_tx_sel_clk_src1; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->emc_pmacro_tx_sel_clk_src2; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->emc_pmacro_tx_sel_clk_src3; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->emc_pmacro_tx_sel_clk_src4; + MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->emc_pmacro_tx_sel_clk_src5; + MAKE_EMC_REG(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; + MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0; + MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1; + MAKE_EMC_REG(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->emc_pmacro_quse_ddll_rank0_0; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->emc_pmacro_quse_ddll_rank0_1; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->emc_pmacro_quse_ddll_rank0_2; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->emc_pmacro_quse_ddll_rank0_3; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->emc_pmacro_quse_ddll_rank0_4; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->emc_pmacro_quse_ddll_rank0_5; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->emc_pmacro_quse_ddll_rank1_0; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->emc_pmacro_quse_ddll_rank1_1; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->emc_pmacro_quse_ddll_rank1_2; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->emc_pmacro_quse_ddll_rank1_3; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->emc_pmacro_quse_ddll_rank1_4; + MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->emc_pmacro_quse_ddll_rank1_5; + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->emc_pmacro_ob_ddll_long_dq_rank0_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->emc_pmacro_ob_ddll_long_dq_rank0_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->emc_pmacro_ob_ddll_long_dq_rank0_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->emc_pmacro_ob_ddll_long_dq_rank0_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->emc_pmacro_ob_ddll_long_dq_rank0_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->emc_pmacro_ob_ddll_long_dq_rank0_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->emc_pmacro_ob_ddll_long_dq_rank1_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->emc_pmacro_ob_ddll_long_dq_rank1_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->emc_pmacro_ob_ddll_long_dq_rank1_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->emc_pmacro_ob_ddll_long_dq_rank1_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->emc_pmacro_ob_ddll_long_dq_rank1_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->emc_pmacro_ob_ddll_long_dq_rank1_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ob_ddll_long_dqs_rank0_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ob_ddll_long_dqs_rank0_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ob_ddll_long_dqs_rank0_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ob_ddll_long_dqs_rank0_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->emc_pmacro_ob_ddll_long_dqs_rank0_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->emc_pmacro_ob_ddll_long_dqs_rank0_5; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ob_ddll_long_dqs_rank1_0; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ob_ddll_long_dqs_rank1_1; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ob_ddll_long_dqs_rank1_2; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ob_ddll_long_dqs_rank1_3; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->emc_pmacro_ob_ddll_long_dqs_rank1_4; + MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->emc_pmacro_ob_ddll_long_dqs_rank1_5; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->emc_pmacro_ib_ddll_long_dqs_rank0_0; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->emc_pmacro_ib_ddll_long_dqs_rank0_1; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->emc_pmacro_ib_ddll_long_dqs_rank0_2; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->emc_pmacro_ib_ddll_long_dqs_rank0_3; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->emc_pmacro_ib_ddll_long_dqs_rank1_0; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->emc_pmacro_ib_ddll_long_dqs_rank1_1; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ib_ddll_long_dqs_rank1_2; + MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ib_ddll_long_dqs_rank1_3; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; + MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1; + MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2; + MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = ((params->emc_pmacro_common_pad_tx_ctrl & 1) | 0xE); + + if (params->emc_bct_spare4) + *(volatile uint32_t *)params->emc_bct_spare4 = params->emc_bct_spare5; + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; + MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; + MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; + MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->mc_video_protect_gpu_override0; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->mc_video_protect_gpu_override1; + MAKE_MC_REG(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; + MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; + MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; + MAKE_MC_REG(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->mc_emem_adr_cfg_channel_mask; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->mc_emem_adr_cfg_bank_mask0; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->mc_emem_adr_cfg_bank_mask1; + MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->mc_emem_adr_cfg_bank_mask2; + MAKE_MC_REG(MC_EMEM_CFG) = params->mc_emem_cfg; + MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; + MAKE_MC_REG(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; + MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = params->mc_sec_carveout_size_mb; + MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; + MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; + MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = params->mc_mts_carveout_size_mb; + MAKE_MC_REG(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; + MAKE_MC_REG(MC_EMEM_ARB_OUTSTANDING_REQ) = params->mc_emem_arb_outstanding_req; + MAKE_MC_REG(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; + MAKE_MC_REG(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->emc_emem_arb_refpb_bank_ctrl; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; + MAKE_MC_REG(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; + MAKE_MC_REG(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; + MAKE_MC_REG(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; + MAKE_MC_REG(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; + MAKE_MC_REG(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; + MAKE_MC_REG(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; + MAKE_MC_REG(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; + MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; + MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; + MAKE_MC_REG(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; + MAKE_MC_REG(MC_DA_CONFIG0) = params->mc_da_cfg0; + MAKE_MC_REG(MC_TIMING_CONTROL) = 1; + MAKE_MC_REG(MC_CLKEN_OVERRIDE) = params->mc_clken_override; + MAKE_MC_REG(MC_STAT_CONTROL) = params->mc_stat_control; + + MAKE_EMC_REG(EMC_ADR_CFG) = params->emc_adr_cfg; + MAKE_EMC_REG(EMC_CLKEN_OVERRIDE) = params->emc_clken_override; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_0) = params->emc_pmacro_auto_cal_cfg0; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_1) = params->emc_pmacro_auto_cal_cfg1; + MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_2) = params->emc_pmacro_auto_cal_cfg2; + MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_0) = params->emc_auto_cal_vref_sel0; + MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1; + MAKE_EMC_REG(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval; + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; + udelay(params->emc_auto_cal_wait); + + if (params->emc_bct_spare8) + *(volatile uint32_t *)params->emc_bct_spare8 = params->emc_bct_spare9; + + MAKE_EMC_REG(EMC_CFG_2) = params->emc_cfg2; + MAKE_EMC_REG(EMC_CFG_PIPE) = params->emc_cfg_pipe; + MAKE_EMC_REG(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; + MAKE_EMC_REG(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; + MAKE_EMC_REG(EMC_CMDQ) = params->emc_cmd_q; + MAKE_EMC_REG(EMC_MC2EMCQ) = params->emc_mc2emc_q; + MAKE_EMC_REG(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; + MAKE_EMC_REG(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; + MAKE_EMC_REG(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; + MAKE_EMC_REG(EMC_RC) = params->emc_rc; + MAKE_EMC_REG(EMC_RFC) = params->emc_rfc; + MAKE_EMC_REG(EMC_RFCPB) = params->emc_rfc_pb; + MAKE_EMC_REG(EMC_REFCTRL2) = params->emc_ref_ctrl2; + MAKE_EMC_REG(EMC_RFC_SLR) = params->emc_rfc_slr; + MAKE_EMC_REG(EMC_RAS) = params->emc_ras; + MAKE_EMC_REG(EMC_RP) = params->emc_rp; + MAKE_EMC_REG(EMC_TPPD) = params->emc_tppd; + MAKE_EMC_REG(EMC_R2R) = params->emc_r2r; + MAKE_EMC_REG(EMC_W2W) = params->emc_w2w; + MAKE_EMC_REG(EMC_R2W) = params->emc_r2w; + MAKE_EMC_REG(EMC_W2R) = params->emc_w2r; + MAKE_EMC_REG(EMC_R2P) = params->emc_r2p; + MAKE_EMC_REG(EMC_W2P) = params->emc_w2p; + MAKE_EMC_REG(EMC_CCDMW) = params->emc_ccdmw; + MAKE_EMC_REG(EMC_RD_RCD) = params->emc_rd_rcd; + MAKE_EMC_REG(EMC_WR_RCD) = params->emc_wr_rcd; + MAKE_EMC_REG(EMC_RRD) = params->emc_rrd; + MAKE_EMC_REG(EMC_REXT) = params->emc_rext; + MAKE_EMC_REG(EMC_WEXT) = params->emc_wext; + MAKE_EMC_REG(EMC_WDV) = params->emc_wdv; + MAKE_EMC_REG(EMC_WDV_CHK) = params->emc_wdv_chk; + MAKE_EMC_REG(EMC_WSV) = params->emc_wsv; + MAKE_EMC_REG(EMC_WEV) = params->emc_wev; + MAKE_EMC_REG(EMC_WDV_MASK) = params->emc_wdv_mask; + MAKE_EMC_REG(EMC_WS_DURATION) = params->emc_ws_duration; + MAKE_EMC_REG(EMC_WE_DURATION) = params->emc_we_duration; + MAKE_EMC_REG(EMC_QUSE) = params->emc_quse; + MAKE_EMC_REG(EMC_QUSE_WIDTH) = params->emc_quse_width; + MAKE_EMC_REG(EMC_IBDLY) = params->emc_ibdly; + MAKE_EMC_REG(EMC_OBDLY) = params->emc_obdly; + MAKE_EMC_REG(EMC_EINPUT) = params->emc_einput; + MAKE_EMC_REG(EMC_EINPUT_DURATION) = params->emc_einput_duration; + MAKE_EMC_REG(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; + MAKE_EMC_REG(EMC_PUTERM_WIDTH) = params->emc_puterm_width; + MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->emc_pmacro_common_pad_tx_ctrl; + MAKE_EMC_REG(EMC_DBG) = params->emc_dbg; + MAKE_EMC_REG(EMC_QRST) = params->emc_qrst; + MAKE_EMC_REG(EMC_ISSUE_QRST) = 0; + MAKE_EMC_REG(EMC_QSAFE) = params->emc_qsafe; + MAKE_EMC_REG(EMC_RDV) = params->emc_rdv; + MAKE_EMC_REG(EMC_RDV_MASK) = params->emc_rdv_mask; + MAKE_EMC_REG(EMC_RDV_EARLY) = params->emc_rdv_early; + MAKE_EMC_REG(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; + MAKE_EMC_REG(EMC_QPOP) = params->emc_qpop; + MAKE_EMC_REG(EMC_REFRESH) = params->emc_refresh; + MAKE_EMC_REG(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; + MAKE_EMC_REG(EMC_PRE_REFRESH_REQ_CNT) = params->emc_prerefresh_req_cnt; + MAKE_EMC_REG(EMC_PDEX2WR) = params->emc_pdex2wr; + MAKE_EMC_REG(EMC_PDEX2RD) = params->emc_pdex2rd; + MAKE_EMC_REG(EMC_PCHG2PDEN) = params->emc_pchg2pden; + MAKE_EMC_REG(EMC_ACT2PDEN) = params->emc_act2pden; + MAKE_EMC_REG(EMC_AR2PDEN) = params->emc_ar2pden; + MAKE_EMC_REG(EMC_RW2PDEN) = params->emc_rw2pden; + MAKE_EMC_REG(EMC_CKE2PDEN) = params->emc_cke2pden; + MAKE_EMC_REG(EMC_PDEX2CKE) = params->emc_pdex2che; + MAKE_EMC_REG(EMC_PDEX2MRR) = params->emc_pdex2mrr; + MAKE_EMC_REG(EMC_TXSR) = params->emc_txsr; + MAKE_EMC_REG(EMC_TXSRDLL) = params->emc_txsr_dll; + MAKE_EMC_REG(EMC_TCKE) = params->emc_tcke; + MAKE_EMC_REG(EMC_TCKESR) = params->emc_tckesr; + MAKE_EMC_REG(EMC_TPD) = params->emc_tpd; + MAKE_EMC_REG(EMC_TFAW) = params->emc_tfaw; + MAKE_EMC_REG(EMC_TRPAB) = params->emc_trpab; + MAKE_EMC_REG(EMC_TCLKSTABLE) = params->emc_tclkstable; + MAKE_EMC_REG(EMC_TCLKSTOP) = params->emc_tclkstop; + MAKE_EMC_REG(EMC_TREFBW) = params->emc_trefbw; + MAKE_EMC_REG(EMC_ODT_WRITE) = params->emc_odt_write; + MAKE_EMC_REG(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; + MAKE_EMC_REG(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; + MAKE_EMC_REG(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; + MAKE_EMC_REG(EMC_CFG_RSV) = params->emc_cfg_rsv; + MAKE_EMC_REG(EMC_PMC_SCRATCH1) = params->emc_pmc_scratch1; + MAKE_EMC_REG(EMC_PMC_SCRATCH2) = params->emc_pmc_scratch2; + MAKE_EMC_REG(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3; + MAKE_EMC_REG(EMC_ACPD_CONTROL) = params->emc_acpd_control; + MAKE_EMC_REG(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; + MAKE_EMC_REG(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000; + + if (params->boot_rom_patch_control & 0x80000000) + { + *(volatile uint32_t *)(4 * (params->boot_rom_patch_control + 0x1C000000)) = params->boot_rom_patch_data; + MAKE_MC_REG(MC_TIMING_CONTROL) = 1; + } + + pmc->io_dpd3_req = (((4 * params->emc_pmc_scratch1 >> 2) + 0x40000000) & 0xCFFF0000); + udelay(params->pmc_io_dpd3_req_wait); + + if (!params->emc_auto_cal_interval) + MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = (params->emc_auto_cal_config | 0x200); + + MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2; + + if (params->emc_zcal_warm_cold_boot_enables & 1) + { + if (params->memory_type == 2) + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = (8 * params->emc_zcal_wait_cnt); + + if (params->memory_type == 3) + { + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; + MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; + } + } + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + udelay(params->emc_timing_control_wait); + + pmc->ddr_cntrl &= 0xFFF8007F; + udelay(params->pmc_ddr_ctrl_wait); + + if (params->memory_type == 2) + { + MAKE_EMC_REG(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)); + udelay(params->emc_pin_extra_wait + 200); + MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256); + udelay(params->emc_pin_extra_wait + 500); + } + + if (params->memory_type == 3) + { + MAKE_EMC_REG(EMC_PIN) = ((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)); + udelay(params->emc_pin_extra_wait + 200); + MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 256); + udelay(params->emc_pin_extra_wait + 2000); + } + + MAKE_EMC_REG(EMC_PIN) = (((params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12)) + 0x101); + udelay(params->emc_pin_program_wait); + + if (params->memory_type != 3) + MAKE_EMC_REG(EMC_NOP) = ((params->emc_dev_select << 30) + 1); + + if (params->memory_type == 1) + udelay(params->emc_pin_extra_wait + 200); + + if (params->memory_type == 3) + { + if (params->emc_bct_spare10) + *(volatile uint32_t *)params->emc_bct_spare10 = params->emc_bct_spare11; + + MAKE_EMC_REG(EMC_MRW2) = params->emc_mrw2; + MAKE_EMC_REG(EMC_MRW) = params->emc_mrw1; + MAKE_EMC_REG(EMC_MRW3) = params->emc_mrw3; + MAKE_EMC_REG(EMC_MRW4) = params->emc_mrw4; + MAKE_EMC_REG(EMC_MRW6) = params->emc_mrw6; + MAKE_EMC_REG(EMC_MRW14) = params->emc_mrw14; + MAKE_EMC_REG(EMC_MRW8) = params->emc_mrw8; + MAKE_EMC_REG(EMC_MRW12) = params->emc_mrw12; + MAKE_EMC_REG(EMC_MRW9) = params->emc_mrw9; + MAKE_EMC_REG(EMC_MRW13) = params->emc_mrw13; + + if (params->emc_zcal_warm_cold_boot_enables & 1) + { + MAKE_EMC_REG(EMC_ZQ_CAL) = params->emc_zcal_init_dev0; + udelay(params->emc_zcal_init_wait); + MAKE_EMC_REG(EMC_ZQ_CAL) = (params->emc_zcal_init_dev0 ^ 3); + + if (!(params->emc_dev_select & 2)) + { + MAKE_EMC_REG(EMC_ZQ_CAL) = params->emc_zcal_init_dev1; + udelay(params->emc_zcal_init_wait); + MAKE_EMC_REG(EMC_ZQ_CAL) = (params->emc_zcal_init_dev1 ^ 3); + } + } + } + + pmc->ddr_cfg = params->pmc_ddr_cfg; + if ((params->memory_type - 1) <= 2) + { + MAKE_EMC_REG(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval; + MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; + MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; + } + + if (params->emc_bct_spare12) + *(volatile uint32_t *)params->emc_bct_spare12 = params->emc_bct_spare13; + + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + + if (params->emc_extra_refresh_num) + MAKE_EMC_REG(EMC_REF) = (((1 << params->emc_extra_refresh_num << 8) - 0xFD) | (params->emc_pin_gpio << 30)); + + MAKE_EMC_REG(EMC_REFCTRL) = (params->emc_dev_select | 0x80000000); + MAKE_EMC_REG(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control; + MAKE_EMC_REG(EMC_CFG_UPDATE) = params->emc_cfg_update; + MAKE_EMC_REG(EMC_CFG) = params->emc_cfg; + MAKE_EMC_REG(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; + MAKE_EMC_REG(EMC_FDPD_CTRL_CMD) = params->emc_fdpd_ctrl_cmd; + MAKE_EMC_REG(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; + MAKE_EMC_REG(EMC_FBIO_SPARE) = (params->emc_fbio_spare | 2); + MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; + MAKE_EMC_REG(EMC_CFG_PIPE_CLK) = params->emc_cfg_pipe_clk; + MAKE_EMC_REG(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->emc_fdpd_ctrl_cmd_no_ramp; + + AHB_ARBITRATION_XBAR_CTRL_0 = ((AHB_ARBITRATION_XBAR_CTRL_0 & 0xFFFEFFFF) | ((params->ahb_arbitration_xbar_ctrl_meminit_done & 0xFFFF) << 16)); + + MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access; + MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; + MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; + MAKE_MC_REG(MC_EMEM_CFG_ACCESS_CTRL) = 1; /* Disable write access to a bunch of MC registers. */ +} + +const void *sdram_get_params() +{ + /* TODO: sdram_id should be in [0, 7]. */ + +#ifdef CONFIG_SDRAM_COMPRESS_CFG + uint8_t *buf = (uint8_t *)0x40030000; + LZ_Uncompress(_dram_cfg_lz, buf, sizeof(_dram_cfg_lz)); + return (const void *)&buf[sizeof(sdram_params_t) * _get_sdram_id()]; +#else + return _dram_cfgs[_get_sdram_id()]; +#endif +} + +void sdram_init() +{ + volatile tegra_pmc_t *pmc = pmc_get_regs(); + + /* TODO: sdram_id should be in [0,4]. */ + const sdram_params_t *params = (const sdram_params_t *)sdram_get_params(); + + uint8_t val = 5; + i2c_send(4, 0x3C, MAX77620_REG_SD_CFG2, &val, 1); + val = 40; /* 40 = (1000 * 1100 - 600000) / 12500 -> 1.1V */ + i2c_send(4, 0x3C, MAX77620_REG_SD1, &val, 1); + + pmc->vddp_sel = params->pmc_vddp_sel; + udelay(params->pmc_vddp_sel_wait); + + pmc->ddr_pwr = pmc->ddr_pwr; + pmc->no_iopower = params->pmc_no_io_power; + pmc->reg_short = params->pmc_reg_short; + pmc->ddr_cntrl = params->pmc_ddr_ctrl; + + if (params->emc_bct_spare0) + *(volatile uint32_t *)params->emc_bct_spare0 = params->emc_bct_spare1; + + _sdram_config(params); +} diff --git a/fusee/fusee-primary/src/sdram.h b/fusee/fusee-primary/src/sdram.h new file mode 100644 index 000000000..1ccc07f0c --- /dev/null +++ b/fusee/fusee-primary/src/sdram.h @@ -0,0 +1,8 @@ +#ifndef FUSEE_SDRAM_H_ +#define FUSEE_SDRAM_H_ + +void sdram_init(); +const void *sdram_get_params(); +void sdram_lp0_save_params(const void *params); + +#endif diff --git a/fusee/fusee-primary/src/sdram.inl b/fusee/fusee-primary/src/sdram.inl new file mode 100644 index 000000000..187355c4c --- /dev/null +++ b/fusee/fusee-primary/src/sdram.inl @@ -0,0 +1,1136 @@ +static const uint8_t _dram_cfg_0[1896] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, + 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, + 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, + 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, + 0xA6, 0xA6, 0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, + 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, + 0xA1, 0x01, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, + 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, + 0x16, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, + 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, + 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, + 0xBF, 0x3B, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, + 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, + 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, + 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, + 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, + 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, 0x00, 0x0D, 0x08, + 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00, 0x00, 0x0B, 0x08, + 0x72, 0x72, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x0D, 0x0C, + 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x04, 0x00, 0x01, 0x08, + 0x00, 0x00, 0x11, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0xCC, 0x00, + 0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, + 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, + 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x00, 0x80, + 0x01, 0x00, 0x00, 0x00, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, + 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28, 0x28, 0x28, + 0x28, 0x28, 0x28, 0x28, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, + 0xBE, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x12, 0x00, 0x10, 0x00, 0x14, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x12, 0x00, 0x10, 0x00, 0x14, 0x00, + 0x30, 0x00, 0x2E, 0x00, 0x33, 0x00, 0x30, 0x00, 0x33, 0x00, 0x35, 0x00, + 0x30, 0x00, 0x32, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x30, 0x00, 0x2E, 0x00, 0x33, 0x00, 0x30, 0x00, 0x33, 0x00, 0x35, 0x00, + 0x30, 0x00, 0x32, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, + 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, + 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x14, 0x00, 0x14, 0x00, + 0x12, 0x00, 0x12, 0x00, 0x10, 0x00, 0x10, 0x00, 0x14, 0x00, 0x14, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, 0x00, 0x51, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x40, + 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0xAB, 0x00, 0x0A, 0x04, + 0x11, 0x00, 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0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t _dram_cfg_1[1896] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, + 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x76, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7E, 0x16, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t _dram_cfg_2[1896] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, + 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 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0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t _dram_cfg_3[1896] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, + 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, + 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, + 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, + 0xA6, 0xA6, 0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, + 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, + 0xA1, 0x01, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, + 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, + 0xBF, 0x3B, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, + 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, + 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, + 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, + 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, + 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, 0x00, 0x0D, 0x08, + 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00, 0x00, 0x0B, 0x08, + 0x72, 0x72, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x0D, 0x0C, + 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x04, 0x00, 0x01, 0x08, + 0x00, 0x00, 0x11, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t _dram_cfg_4[1896] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, + 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, + 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, + 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, + 0xA6, 0xA6, 0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, + 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, + 0xA1, 0x01, 0x00, 0x00, 0x32, 0x00, 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0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, + 0x16, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, + 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, + 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, + 0xBF, 0x3B, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, + 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, + 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 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0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x00, 0x80, + 0x01, 0x00, 0x00, 0x00, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, + 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28, 0x28, 0x28, + 0x28, 0x28, 0x28, 0x28, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, + 0xBE, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x12, 0x00, 0x10, 0x00, 0x14, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 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0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x22, 0x04, 0xFF, 0xFF, 0xAF, 0x4F, + 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0xFF, 0x07, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x54, 0x76, 0x10, 0x47, 0x32, 0x65, + 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75, 0x64, 0x32, + 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45, 0x32, 0x67, + 0x00, 0x00, 0x00, 0x00, 0x49, 0x92, 0x24, 0x00, 0x49, 0x92, 0x24, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0xC3, 0x71, 0x0F, 0x0F, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x76, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7E, 0x16, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t _dram_cfg_5[1896] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, + 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, + 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, + 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, + 0xA6, 0xA6, 0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, + 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, + 0xA1, 0x01, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, + 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, + 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, + 0x16, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, + 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0D, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, + 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, + 0xBF, 0x3B, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, + 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, + 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, + 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, + 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, + 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 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0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28, 0x28, 0x28, + 0x28, 0x28, 0x28, 0x28, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, + 0xBE, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0x12, 0x00, 0x12, 0x00, 0x16, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0x12, 0x00, 0x12, 0x00, 0x16, 0x00, + 0x32, 0x00, 0x2F, 0x00, 0x32, 0x00, 0x31, 0x00, 0x34, 0x00, 0x36, 0x00, + 0x2F, 0x00, 0x33, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x32, 0x00, 0x2F, 0x00, 0x32, 0x00, 0x31, 0x00, 0x34, 0x00, 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0x00, 0x00, + 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static const uint8_t _dram_cfg_6[1896] = { + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, + 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 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0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x0D, 0x0C, + 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x04, 0x00, 0x01, 0x08, + 0x00, 0x00, 0x11, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0xCC, 0x00, + 0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, + 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, + 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x00, 0x80, + 0x01, 0x00, 0x00, 0x00, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, + 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28, 0x28, 0x28, + 0x28, 0x28, 0x28, 0x28, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, + 0xBE, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0x12, 0x00, 0x12, 0x00, 0x16, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0x12, 0x00, 0x12, 0x00, 0x16, 0x00, + 0x32, 0x00, 0x2F, 0x00, 0x32, 0x00, 0x31, 0x00, 0x34, 0x00, 0x36, 0x00, + 0x2F, 0x00, 0x33, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x32, 0x00, 0x2F, 0x00, 0x32, 0x00, 0x31, 0x00, 0x34, 0x00, 0x36, 0x00, + 0x2F, 0x00, 0x33, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, + 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, + 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x15, 0x00, 0x15, 0x00, + 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x16, 0x00, 0x16, 0x00, + 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, 0x00, 0x51, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x40, + 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0xAB, 0x00, 0x0A, 0x04, + 0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x22, 0x04, 0xFF, 0xFF, 0xAF, 0x4F, + 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0xFF, 0x07, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x54, 0x76, 0x10, 0x47, 0x32, 0x65, + 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75, 0x64, 0x32, + 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45, 0x32, 0x67, + 0x00, 0x00, 0x00, 0x00, 0x49, 0x92, 0x24, 0x00, 0x49, 0x92, 0x24, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x2F, 0x41, 0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, + 0xFF, 0xFF, 0xAF, 0x4F, 0xFF, 0xFF, 0xFF, 0x7F, 0x0B, 0xD7, 0x06, 0x40, + 0x00, 0x00, 0x02, 0x00, 0x08, 0x08, 0x03, 0x00, 0x00, 0x5C, 0x01, 0x00, + 0x10, 0x10, 0x10, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, + 0x37, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x30, 0x00, 0x00, 0x11, 0x01, 0x00, 0x02, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0A, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, + 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, + 0x81, 0x10, 0x09, 0x28, 0x93, 0x32, 0xA5, 0x44, 0x5B, 0x8A, 0x67, 0x76, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xEF, 0xFF, 0xEF, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, + 0xDC, 0xDC, 0xDC, 0xDC, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, + 0x0A, 0x0A, 0x0A, 0x0A, 0x01, 0x00, 0x00, 0x00, 0x02, 0x03, 0x07, 0x00, + 0x02, 0x03, 0x07, 0x00, 0x00, 0x24, 0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, + 0x00, 0x28, 0x72, 0x39, 0x00, 0x10, 0x9C, 0x4B, 0x00, 0x10, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x08, 0x4C, 0x00, 0x00, 0x80, 0x20, 0x10, 0x0A, 0x00, + 0x28, 0x10, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x05, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x02, + 0x01, 0x02, 0x03, 0x00, 0x04, 0x05, 0xA3, 0x72, 0x0F, 0x0F, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x76, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7E, 0x16, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static const uint32_t *_dram_cfgs[7] = { + (const uint32_t *)_dram_cfg_0, + (const uint32_t *)_dram_cfg_1, + (const uint32_t *)_dram_cfg_2, + (const uint32_t *)_dram_cfg_3, + (const uint32_t *)_dram_cfg_4, + (const uint32_t *)_dram_cfg_5, + (const uint32_t *)_dram_cfg_6 +}; diff --git a/fusee/fusee-primary/src/sdram_lp0.c b/fusee/fusee-primary/src/sdram_lp0.c new file mode 100644 index 000000000..36bcc6bef --- /dev/null +++ b/fusee/fusee-primary/src/sdram_lp0.c @@ -0,0 +1,1109 @@ +#include "pmc.h" +#include "sdram_param_t210_lp0.h" + +/* + * This function reads SDRAM parameters from the common BCT format and + * writes them into PMC scratch registers (where the BootROM expects them + * on LP0 resume). + */ +void sdram_lp0_save_params(const void *params) +{ + struct sdram_params *sdram = (struct sdram_params *)params; + volatile tegra_pmc_t *pmc = pmc_get_regs(); + +#define pack(src, src_bits, dst, dst_bits) { \ + uint32_t mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ + dst &= ~(mask << (0 ? dst_bits)); \ + dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ +} + +#define s(param, src_bits, pmcreg, dst_bits) \ + pack(sdram->param, src_bits, pmc->pmcreg, dst_bits) + +#define c(value, pmcreg, dst_bits) \ + pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) + +/* 32 bits version of s macro */ +#define s32(param, pmcreg) pmc->pmcreg = sdram->param + +/* 32 bits version c macro */ +#define c32(value, pmcreg) pmc->pmcreg = value + + //TODO: pkg1.1 (1.X - 3.X) reads them from MC. + // Patch carveout parameters. + /*sdram->McGeneralizedCarveout1Bom = 0; + sdram->McGeneralizedCarveout1BomHi = 0; + sdram->McGeneralizedCarveout1Size128kb = 0; + sdram->McGeneralizedCarveout1Access0 = 0; + sdram->McGeneralizedCarveout1Access1 = 0; + sdram->McGeneralizedCarveout1Access2 = 0; + sdram->McGeneralizedCarveout1Access3 = 0; + sdram->McGeneralizedCarveout1Access4 = 0; + sdram->McGeneralizedCarveout1ForceInternalAccess0 = 0; + sdram->McGeneralizedCarveout1ForceInternalAccess1 = 0; + sdram->McGeneralizedCarveout1ForceInternalAccess2 = 0; + sdram->McGeneralizedCarveout1ForceInternalAccess3 = 0; + sdram->McGeneralizedCarveout1ForceInternalAccess4 = 0; + sdram->McGeneralizedCarveout1Cfg0 = 0; + sdram->McGeneralizedCarveout2Bom = 0x80020000; + sdram->McGeneralizedCarveout2BomHi = 0; + sdram->McGeneralizedCarveout2Size128kb = 2; + sdram->McGeneralizedCarveout2Access0 = 0; + sdram->McGeneralizedCarveout2Access1 = 0; + sdram->McGeneralizedCarveout2Access2 = 0x3000000; + sdram->McGeneralizedCarveout2Access3 = 0; + sdram->McGeneralizedCarveout2Access4 = 0x300; + sdram->McGeneralizedCarveout2ForceInternalAccess0 = 0; + sdram->McGeneralizedCarveout2ForceInternalAccess1 = 0; + sdram->McGeneralizedCarveout2ForceInternalAccess2 = 0; + sdram->McGeneralizedCarveout2ForceInternalAccess3 = 0; + sdram->McGeneralizedCarveout2ForceInternalAccess4 = 0; + sdram->McGeneralizedCarveout2Cfg0 = 0x440167E; + sdram->McGeneralizedCarveout3Bom = 0; + sdram->McGeneralizedCarveout3BomHi = 0; + sdram->McGeneralizedCarveout3Size128kb = 0; + sdram->McGeneralizedCarveout3Access0 = 0; + sdram->McGeneralizedCarveout3Access1 = 0; + sdram->McGeneralizedCarveout3Access2 = 0x3000000; + sdram->McGeneralizedCarveout3Access3 = 0; + sdram->McGeneralizedCarveout3Access4 = 0x300; + sdram->McGeneralizedCarveout3ForceInternalAccess0 = 0; + sdram->McGeneralizedCarveout3ForceInternalAccess1 = 0; + sdram->McGeneralizedCarveout3ForceInternalAccess2 = 0; + sdram->McGeneralizedCarveout3ForceInternalAccess3 = 0; + sdram->McGeneralizedCarveout3ForceInternalAccess4 = 0; + sdram->McGeneralizedCarveout3Cfg0 = 0x4401E7E; + sdram->McGeneralizedCarveout4Bom = 0; + sdram->McGeneralizedCarveout4BomHi = 0; + sdram->McGeneralizedCarveout4Size128kb = 0; + sdram->McGeneralizedCarveout4Access0 = 0; + sdram->McGeneralizedCarveout4Access1 = 0; + sdram->McGeneralizedCarveout4Access2 = 0; + sdram->McGeneralizedCarveout4Access3 = 0; + sdram->McGeneralizedCarveout4Access4 = 0; + sdram->McGeneralizedCarveout4ForceInternalAccess0 = 0; + sdram->McGeneralizedCarveout4ForceInternalAccess1 = 0; + sdram->McGeneralizedCarveout4ForceInternalAccess2 = 0; + sdram->McGeneralizedCarveout4ForceInternalAccess3 = 0; + sdram->McGeneralizedCarveout4ForceInternalAccess4 = 0; + sdram->McGeneralizedCarveout4Cfg0 = 0x8F; + sdram->McGeneralizedCarveout5Bom = 0; + sdram->McGeneralizedCarveout5BomHi = 0; + sdram->McGeneralizedCarveout5Size128kb = 0; + sdram->McGeneralizedCarveout5Access0 = 0; + sdram->McGeneralizedCarveout5Access1 = 0; + sdram->McGeneralizedCarveout5Access2 = 0; + sdram->McGeneralizedCarveout5Access3 = 0; + sdram->McGeneralizedCarveout5Access4 = 0; + sdram->McGeneralizedCarveout5ForceInternalAccess0 = 0; + sdram->McGeneralizedCarveout5ForceInternalAccess1 = 0; + sdram->McGeneralizedCarveout5ForceInternalAccess2 = 0; + sdram->McGeneralizedCarveout5ForceInternalAccess3 = 0; + sdram->McGeneralizedCarveout5ForceInternalAccess4 = 0; + sdram->McGeneralizedCarveout5Cfg0 = 0x8F;*/ + + //TODO: this is 4.X+ behaviour which seems to work fine for < 4.X. + // Patch carveout parameters. + sdram->McGeneralizedCarveout1Cfg0 = 0; + sdram->McGeneralizedCarveout2Cfg0 = 0; + sdram->McGeneralizedCarveout3Cfg0 = 0; + sdram->McGeneralizedCarveout4Cfg0 = 0; + sdram->McGeneralizedCarveout5Cfg0 = 0; + + // Patch SDRAM parameters. + uint32_t t0 = sdram->EmcSwizzleRank0Byte0 << 5 >> 29 > sdram->EmcSwizzleRank0Byte0 << 1 >> 29; + uint32_t t1 = (t0 & 0xFFFFFFEF) | ((sdram->EmcSwizzleRank1Byte0 << 5 >> 29 > sdram->EmcSwizzleRank1Byte0 << 1 >> 29) << 4); + uint32_t t2 = (t1 & 0xFFFFFFFD) | ((sdram->EmcSwizzleRank0Byte1 << 5 >> 29 > sdram->EmcSwizzleRank0Byte1 << 1 >> 29) << 1); + uint32_t t3 = (t2 & 0xFFFFFFDF) | ((sdram->EmcSwizzleRank1Byte1 << 5 >> 29 > sdram->EmcSwizzleRank1Byte1 << 1 >> 29) << 5); + uint32_t t4 = (t3 & 0xFFFFFFFB) | ((sdram->EmcSwizzleRank0Byte2 << 5 >> 29 > sdram->EmcSwizzleRank0Byte2 << 1 >> 29) << 2); + uint32_t t5 = (t4 & 0xFFFFFFBF) | ((sdram->EmcSwizzleRank1Byte2 << 5 >> 29 > sdram->EmcSwizzleRank1Byte2 << 1 >> 29) << 6); + uint32_t t6 = (t5 & 0xFFFFFFF7) | ((sdram->EmcSwizzleRank0Byte3 << 5 >> 29 > sdram->EmcSwizzleRank0Byte3 << 1 >> 29) << 3); + uint32_t t7 = (t6 & 0xFFFFFF7F) | ((sdram->EmcSwizzleRank1Byte3 << 5 >> 29 > sdram->EmcSwizzleRank1Byte3 << 1 >> 29) << 7); + sdram->SwizzleRankByteEncode = t7; + sdram->EmcBctSpare2 = 0x40000DD8; + sdram->EmcBctSpare3 = t7; + + s(EmcClockSource, 7:0, scratch6, 15:8); + s(EmcClockSourceDll, 7:0, scratch6, 23:16); + s(EmcClockSource, 31:29, scratch6, 26:24); + s(EmcClockSourceDll, 31:29, scratch6, 29:27); + s(EmcClockSourceDll, 11:10, scratch6, 31:30); + s(ClkRstControllerPllmMisc2Override, 9:8, scratch7, 1:0); + s(ClkRstControllerPllmMisc2Override, 2:1, scratch7, 3:2); + s(EmcZqCalLpDdr4WarmBoot, 31:30, scratch7, 5:4); + s(EmcClockSource, 15:15, scratch7, 6:6); + s(EmcClockSource, 26:26, scratch7, 7:7); + s(EmcClockSource, 20:20, scratch7, 8:8); + s(EmcClockSource, 19:19, scratch7, 9:9); + s(ClkRstControllerPllmMisc2Override, 13:13, scratch7, 10:10); + s(ClkRstControllerPllmMisc2Override, 12:12, scratch7, 11:11); + s(ClkRstControllerPllmMisc2Override, 11:11, scratch7, 12:12); + s(ClkRstControllerPllmMisc2Override, 10:10, scratch7, 13:13); + s(ClkRstControllerPllmMisc2Override, 5:5, scratch7, 14:14); + s(ClkRstControllerPllmMisc2Override, 4:4, scratch7, 15:15); + s(ClkRstControllerPllmMisc2Override, 3:3, scratch7, 16:16); + s(ClkRstControllerPllmMisc2Override, 0:0, scratch7, 17:17); + s(EmcZqCalLpDdr4WarmBoot, 1:0, scratch7, 19:18); + s(EmcZqCalLpDdr4WarmBoot, 4:4, scratch7, 20:20); + s(EmcOdtWrite, 5:0, scratch7, 26:21); + s(EmcOdtWrite, 11:8, scratch7, 30:27); + s(EmcOdtWrite, 31:31, scratch7, 31:31); + s(EmcFdpdCtrlCmdNoRamp, 0:0, scratch13, 30:30); + s(EmcCfgPipeClk, 0:0, scratch13, 31:31); + s(McEmemArbMisc2, 0:0, scratch14, 30:30); + s(McDaCfg0, 0:0, scratch14, 31:31); + s(EmcQRst, 6:0, scratch15, 26:20); + s(EmcQRst, 20:16, scratch15, 31:27); + s(EmcPmacroCmdTxDrv, 5:0, scratch16, 25:20); + s(EmcPmacroCmdTxDrv, 13:8, scratch16, 31:26); + s(EmcPmacroAutocalCfg0, 2:0, scratch17, 22:20); + s(EmcPmacroAutocalCfg0, 10:8, scratch17, 25:23); + s(EmcPmacroAutocalCfg0, 18:16, scratch17, 28:26); + s(EmcPmacroAutocalCfg0, 26:24, scratch17, 31:29); + s(EmcPmacroAutocalCfg1, 2:0, scratch18, 22:20); + s(EmcPmacroAutocalCfg1, 10:8, scratch18, 25:23); + s(EmcPmacroAutocalCfg1, 18:16, scratch18, 28:26); + s(EmcPmacroAutocalCfg1, 26:24, scratch18, 31:29); + s(EmcPmacroAutocalCfg2, 2:0, scratch19, 22:20); + s(EmcPmacroAutocalCfg2, 10:8, scratch19, 25:23); + s(EmcPmacroAutocalCfg2, 18:16, scratch19, 28:26); + s(EmcPmacroAutocalCfg2, 26:24, scratch19, 31:29); + s32(EmcCfgRsv,scratch22); + s32(EmcAutoCalConfig, scratch23); + s32(EmcAutoCalVrefSel0, scratch24); + s32(EmcPmacroBrickCtrlRfu1, scratch25); + s32(EmcPmacroBrickCtrlRfu2, scratch26); + s32(EmcPmcScratch1, scratch27); + s32(EmcPmcScratch2, scratch28); + s32(EmcPmcScratch3, scratch29); + s32(McEmemArbDaTurns, scratch30); + s(EmcFbioSpare, 31:24, scratch58, 7:0); + s(EmcFbioSpare, 23:16, scratch58, 15:8); + s(EmcFbioSpare, 15:8, scratch58, 23:16); + s(EmcFbioSpare, 7:2, scratch58, 29:24); + s(EmcFbioSpare, 0:0, scratch58, 30:30); + s(EmcDllCfg0, 29:0, scratch59, 29:0); + s(EmcPmacroDdllBypass, 11:0, scratch60, 11:0); + s(EmcPmacroDdllBypass, 27:13, scratch60, 26:12); + s(EmcPmacroDdllBypass, 31:29, scratch60, 29:27); + s(McEmemArbMisc0, 14:0, scratch61, 14:0); + s(McEmemArbMisc0, 30:16, scratch61, 29:15); + s(EmcFdpdCtrlCmd, 16:0, scratch62, 16:0); + s(EmcFdpdCtrlCmd, 31:20, scratch62, 28:17); + s(EmcAutoCalConfig2, 27:0, scratch63, 27:0); + s(EmcBurstRefreshNum, 3:0, scratch63, 31:28); + s(EmcPmacroZctrl, 27:0, scratch64, 27:0); + s(EmcTppd, 3:0, scratch64, 31:28); + s(EmcCfgDigDll, 10:0, scratch65, 10:0); + s(EmcCfgDigDll, 25:12, scratch65, 24:11); + s(EmcCfgDigDll, 27:27, scratch65, 25:25); + s(EmcCfgDigDll, 31:30, scratch65, 27:26); + s(EmcR2r, 3:0, scratch65, 31:28); + s(EmcFdpdCtrlDq, 16:0, scratch66, 16:0); + s(EmcFdpdCtrlDq, 28:20, scratch66, 25:17); + s(EmcFdpdCtrlDq, 31:30, scratch66, 27:26); + s(EmcW2w, 3:0, scratch66, 31:28); + s(EmcPmacroTxPwrd4, 13:0, scratch67, 13:0); + s(EmcPmacroTxPwrd4, 29:16, scratch67, 27:14); + s(EmcPmacroCommonPadTxCtrl, 3:0, scratch67, 31:28); + s(EmcPmacroTxPwrd5, 13:0, scratch68, 13:0); + s(EmcPmacroTxPwrd5, 29:16, scratch68, 27:14); + s(EmcPmacroDdllPwrd0, 4:0, scratch69, 4:0); + s(EmcPmacroDdllPwrd0, 12:6, scratch69, 11:5); + s(EmcPmacroDdllPwrd0, 20:14, scratch69, 18:12); + s(EmcPmacroDdllPwrd0, 28:22, scratch69, 25:19); + s(EmcPmacroDdllPwrd0, 31:30, scratch69, 27:26); + s(EmcCfg, 4:4, scratch69, 31:31); + s(EmcPmacroDdllPwrd1, 4:0, scratch70, 4:0); + s(EmcPmacroDdllPwrd1, 12:6, scratch70, 11:5); + s(EmcPmacroDdllPwrd1, 20:14, scratch70, 18:12); + s(EmcPmacroDdllPwrd1, 28:22, scratch70, 25:19); + s(EmcPmacroDdllPwrd1, 31:30, scratch70, 27:26); + s(EmcCfg, 5:5, scratch70, 31:31); + s(EmcPmacroDdllPwrd2, 4:0, scratch71, 4:0); + s(EmcPmacroDdllPwrd2, 12:6, scratch71, 11:5); + s(EmcPmacroDdllPwrd2, 20:14, scratch71, 18:12); + s(EmcPmacroDdllPwrd2, 28:22, scratch71, 25:19); + s(EmcPmacroDdllPwrd2, 31:30, scratch71, 27:26); + s(EmcFbioCfg5, 23:20, scratch71, 31:28); + s(EmcPmacroIbVrefDq_0, 6:0, scratch72, 6:0); + s(EmcPmacroIbVrefDq_0, 14:8, scratch72, 13:7); + s(EmcPmacroIbVrefDq_0, 22:16, scratch72, 20:14); + s(EmcPmacroIbVrefDq_0, 30:24, scratch72, 27:21); + s(EmcFbioCfg5, 15:13, scratch72, 30:28); + s(EmcCfg, 6:6, scratch72, 31:31); + s(EmcPmacroIbVrefDq_1, 6:0, scratch73, 6:0); + s(EmcPmacroIbVrefDq_1, 14:8, scratch73, 13:7); + s(EmcPmacroIbVrefDq_1, 22:16, scratch73, 20:14); + s(EmcPmacroIbVrefDq_1, 30:24, scratch73, 27:21); + s(EmcCfg2, 5:3, scratch73, 30:28); + s(EmcCfg, 7:7, scratch73, 31:31); + s(EmcPmacroIbVrefDqs_0, 6:0, scratch74, 6:0); + s(EmcPmacroIbVrefDqs_0, 14:8, scratch74, 13:7); + s(EmcPmacroIbVrefDqs_0, 22:16, scratch74, 20:14); + s(EmcPmacroIbVrefDqs_0, 30:24, scratch74, 27:21); + s(EmcCfg, 17:16, scratch74, 29:28); + s(EmcFbioCfg5, 1:0, scratch74, 31:30); + s(EmcPmacroIbVrefDqs_1, 6:0, scratch75, 6:0); + s(EmcPmacroIbVrefDqs_1, 14:8, scratch75, 13:7); + s(EmcPmacroIbVrefDqs_1, 22:16, scratch75, 20:14); + s(EmcPmacroIbVrefDqs_1, 30:24, scratch75, 27:21); + s(EmcFbioCfg5, 3:2, scratch75, 29:28); + s(EmcCfg2, 27:26, scratch75, 31:30); + s(EmcPmacroDdllShortCmd_0, 6:0, scratch76, 6:0); + s(EmcPmacroDdllShortCmd_0, 14:8, scratch76, 13:7); + s(EmcPmacroDdllShortCmd_0, 22:16, scratch76, 20:14); + s(EmcPmacroDdllShortCmd_0, 30:24, scratch76, 27:21); + s(EmcPmacroCmdPadTxCtrl, 3:2, scratch76, 29:28); + s(EmcPmacroCmdPadTxCtrl, 7:6, scratch76, 31:30); + s(EmcPmacroDdllShortCmd_1, 6:0, scratch77, 6:0); + s(EmcPmacroDdllShortCmd_1, 14:8, scratch77, 13:7); + s(EmcPmacroDdllShortCmd_1, 22:16, scratch77, 20:14); + s(EmcPmacroDdllShortCmd_1, 30:24, scratch77, 27:21); + s(EmcPmacroCmdPadTxCtrl, 11:10, scratch77, 29:28); + s(EmcPmacroCmdPadTxCtrl, 15:14, scratch77, 31:30); + s(EmcAutoCalChannel, 5:0, scratch78, 5:0); + s(EmcAutoCalChannel, 11:8, scratch78, 9:6); + s(EmcAutoCalChannel, 27:16, scratch78, 21:10); + s(EmcAutoCalChannel, 31:29, scratch78, 24:22); + s(EmcConfigSampleDelay, 6:0, scratch78, 31:25); + s(EmcPmacroRxTerm, 5:0, scratch79, 5:0); + s(EmcPmacroRxTerm, 13:8, scratch79, 11:6); + s(EmcPmacroRxTerm, 21:16, scratch79, 17:12); + s(EmcPmacroRxTerm, 29:24, scratch79, 23:18); + s(EmcRc, 7:0, scratch79, 31:24); + s(EmcPmacroDqTxDrv, 5:0, scratch80, 5:0); + s(EmcPmacroDqTxDrv, 13:8, scratch80, 11:6); + s(EmcPmacroDqTxDrv, 21:16, scratch80, 17:12); + s(EmcPmacroDqTxDrv, 29:24, scratch80, 23:18); + s(EmcSelDpdCtrl, 5:2, scratch80, 27:24); + s(EmcSelDpdCtrl, 8:8, scratch80, 28:28); + s(EmcSelDpdCtrl, 18:16, scratch80, 31:29); + s(EmcPmacroCaTxDrv, 5:0, scratch81, 5:0); + s(EmcPmacroCaTxDrv, 13:8, scratch81, 11:6); + s(EmcPmacroCaTxDrv, 21:16, scratch81, 17:12); + s(EmcPmacroCaTxDrv, 29:24, scratch81, 23:18); + s(EmcObdly, 5:0, scratch81, 29:24); + s(EmcObdly, 29:28, scratch81, 31:30); + s(EmcZcalInterval, 23:10, scratch82, 13:0); + s(EmcZcalInterval, 9:0, scratch82, 23:14); + s(EmcPmacroCmdRxTermMode, 1:0, scratch82, 25:24); + s(EmcPmacroCmdRxTermMode, 5:4, scratch82, 27:26); + s(EmcPmacroCmdRxTermMode, 9:8, scratch82, 29:28); + s(EmcPmacroCmdRxTermMode, 13:12, scratch82, 31:30); + s(EmcDataBrlshft0, 23:0, scratch83, 23:0); + s(EmcPmacroDataRxTermMode, 1:0, scratch83, 25:24); + s(EmcPmacroDataRxTermMode, 5:4, scratch83, 27:26); + s(EmcPmacroDataRxTermMode, 9:8, scratch83, 29:28); + s(EmcPmacroDataRxTermMode, 13:12, scratch83, 31:30); + s(EmcDataBrlshft1, 23:0, scratch84, 23:0); + s(McEmemArbTimingRc, 7:0, scratch84, 31:24); + s(EmcDqsBrlshft0, 23:0, scratch85, 23:0); + s(McEmemArbRsv, 7:0, scratch85, 31:24); + s(EmcDqsBrlshft1, 23:0, scratch86, 23:0); + s(EmcCfgPipe2, 11:0, scratch87, 11:0); + s(EmcCfgPipe2, 27:16, scratch87, 23:12); + s(EmcCfgPipe1, 11:0, scratch88, 11:0); + s(EmcCfgPipe1, 27:16, scratch88, 23:12); + s(EmcPmacroCmdCtrl0, 5:0, scratch89, 5:0); + s(EmcPmacroCmdCtrl0, 13:8, scratch89, 11:6); + s(EmcPmacroCmdCtrl0, 21:16, scratch89, 17:12); + s(EmcPmacroCmdCtrl0, 29:24, scratch89, 23:18); + s(EmcPmacroCmdCtrl1, 5:0, scratch90, 5:0); + s(EmcPmacroCmdCtrl1, 13:8, scratch90, 11:6); + s(EmcPmacroCmdCtrl1, 21:16, scratch90, 17:12); + s(EmcPmacroCmdCtrl1, 29:24, scratch90, 23:18); + s(EmcRas, 6:0, scratch90, 30:24); + s(EmcCfg, 8:8, scratch90, 31:31); + s(EmcPmacroVttgenCtrl2, 23:0, scratch91, 23:0); + s(EmcW2p, 6:0, scratch91, 30:24); + s(EmcCfg, 9:9, scratch91, 31:31); + s(EmcPmacroCmdPadRxCtrl, 2:0, scratch92, 2:0); + s(EmcPmacroCmdPadRxCtrl, 5:4, scratch92, 4:3); + s(EmcPmacroCmdPadRxCtrl, 10:8, scratch92, 7:5); + s(EmcPmacroCmdPadRxCtrl, 22:12, scratch92, 18:8); + s(EmcPmacroCmdPadRxCtrl, 28:24, scratch92, 23:19); + s(EmcQSafe, 6:0, scratch92, 30:24); + s(EmcCfg, 18:18, scratch92, 31:31); + s(EmcPmacroDataPadRxCtrl, 2:0, scratch93, 2:0); + s(EmcPmacroDataPadRxCtrl, 5:4, scratch93, 4:3); + s(EmcPmacroDataPadRxCtrl, 10:8, scratch93, 7:5); + s(EmcPmacroDataPadRxCtrl, 22:12, scratch93, 18:8); + s(EmcPmacroDataPadRxCtrl, 28:24, scratch93, 23:19); + s(EmcRdv, 6:0, scratch93, 30:24); + s(EmcCfg, 21:21, scratch93, 31:31); + s(McEmemArbDaCovers, 23:0, scratch94, 23:0); + s(EmcRw2Pden, 6:0, scratch94, 30:24); + s(EmcCfg, 22:22, scratch94, 31:31); + s(EmcPmacroCmdCtrl2, 5:0, scratch95, 5:0); + s(EmcPmacroCmdCtrl2, 13:9, scratch95, 10:6); + s(EmcPmacroCmdCtrl2, 21:16, scratch95, 16:11); + s(EmcPmacroCmdCtrl2, 29:24, scratch95, 22:17); + s(EmcRfcPb, 8:0, scratch95, 31:23); + s(EmcPmacroQuseDdllRank0_0, 10:0, scratch96, 10:0); + s(EmcPmacroQuseDdllRank0_0, 26:16, scratch96, 21:11); + s(EmcCfgUpdate, 2:0, scratch96, 24:22); + s(EmcCfgUpdate, 10:8, scratch96, 27:25); + s(EmcCfgUpdate, 31:28, scratch96, 31:28); + s(EmcPmacroQuseDdllRank0_1, 10:0, scratch97, 10:0); + s(EmcPmacroQuseDdllRank0_1, 26:16, scratch97, 21:11); + s(EmcRfc, 9:0, scratch97, 31:22); + s(EmcPmacroQuseDdllRank0_2, 10:0, scratch98, 10:0); + s(EmcPmacroQuseDdllRank0_2, 26:16, scratch98, 21:11); + s(EmcTxsr, 9:0, scratch98, 31:22); + s(EmcPmacroQuseDdllRank0_3, 10:0, scratch99, 10:0); + s(EmcPmacroQuseDdllRank0_3, 26:16, scratch99, 21:11); + s(EmcMc2EmcQ, 2:0, scratch99, 24:22); + s(EmcMc2EmcQ, 10:8, scratch99, 27:25); + s(EmcMc2EmcQ, 27:24, scratch99, 31:28); + s(EmcPmacroQuseDdllRank0_4, 10:0, scratch100, 10:0); + s(EmcPmacroQuseDdllRank0_4, 26:16, scratch100, 21:11); + s(McEmemArbRing1Throttle, 4:0, scratch100, 26:22); + s(McEmemArbRing1Throttle, 20:16, scratch100, 31:27); + s(EmcPmacroQuseDdllRank0_5, 10:0, scratch101, 10:0); + s(EmcPmacroQuseDdllRank0_5, 26:16, scratch101, 21:11); + s(EmcPmacroQuseDdllRank1_0, 10:0, scratch102, 10:0); + s(EmcPmacroQuseDdllRank1_0, 26:16, scratch102, 21:11); + s(EmcAr2Pden, 8:0, scratch102, 30:22); + s(EmcCfg, 23:23, scratch102, 31:31); + s(EmcPmacroQuseDdllRank1_1, 10:0, scratch103, 10:0); + s(EmcPmacroQuseDdllRank1_1, 26:16, scratch103, 21:11); + s(EmcRfcSlr, 8:0, scratch103, 30:22); + s(EmcCfg, 24:24, scratch103, 31:31); + s(EmcPmacroQuseDdllRank1_2, 10:0, scratch104, 10:0); + s(EmcPmacroQuseDdllRank1_2, 26:16, scratch104, 21:11); + s(EmcIbdly, 6:0, scratch104, 28:22); + s(EmcIbdly, 29:28, scratch104, 30:29); + s(EmcCfg, 25:25, scratch104, 31:31); + s(EmcPmacroQuseDdllRank1_3, 10:0, scratch105, 10:0); + s(EmcPmacroQuseDdllRank1_3, 26:16, scratch105, 21:11); + s(McEmemArbTimingRFCPB, 8:0, scratch105, 30:22); + s(EmcCfg, 26:26, scratch105, 31:31); + s(EmcPmacroQuseDdllRank1_4, 10:0, scratch106, 10:0); + s(EmcPmacroQuseDdllRank1_4, 26:16, scratch106, 21:11); + s(EmcTfaw, 6:0, scratch106, 28:22); + s(EmcPmacroDataPadTxCtrl, 3:2, scratch106, 30:29); + s(EmcCfg, 28:28, scratch106, 31:31); + s(EmcPmacroQuseDdllRank1_5, 10:0, scratch107, 10:0); + s(EmcPmacroQuseDdllRank1_5, 26:16, scratch107, 21:11); + s(EmcTClkStable, 6:0, scratch107, 28:22); + s(EmcPmacroDataPadTxCtrl, 7:6, scratch107, 30:29); + s(EmcCfg, 29:29, scratch107, 31:31); + s(EmcPmacroObDdllLongDqRank0_0, 10:0, scratch108, 10:0); + s(EmcPmacroObDdllLongDqRank0_0, 26:16, scratch108, 21:11); + s(EmcPdex2Mrr, 6:0, scratch108, 28:22); + s(EmcPmacroDataPadTxCtrl, 11:10, scratch108, 30:29); + s(EmcCfg, 30:30, scratch108, 31:31); + s(EmcPmacroObDdllLongDqRank0_1, 10:0, scratch109, 10:0); + s(EmcPmacroObDdllLongDqRank0_1, 26:16, scratch109, 21:11); + s(EmcRdvMask, 6:0, scratch109, 28:22); + s(EmcPmacroDataPadTxCtrl, 15:14, scratch109, 30:29); + s(EmcCfg, 31:31, scratch109, 31:31); + s(EmcPmacroObDdllLongDqRank0_2, 10:0, scratch110, 10:0); + s(EmcPmacroObDdllLongDqRank0_2, 26:16, scratch110, 21:11); + s(EmcRdvEarlyMask, 6:0, scratch110, 28:22); + s(EmcFbioCfg5, 4:4, scratch110, 29:29); + s(EmcFbioCfg5, 8:8, scratch110, 30:30); + s(EmcFbioCfg5, 10:10, scratch110, 31:31); + s(EmcPmacroObDdllLongDqRank0_3, 10:0, scratch111, 10:0); + s(EmcPmacroObDdllLongDqRank0_3, 26:16, scratch111, 21:11); + s(EmcRdvEarly, 6:0, scratch111, 28:22); + s(EmcFbioCfg5, 12:12, scratch111, 29:29); + s(EmcFbioCfg5, 25:24, scratch111, 31:30); + s(EmcPmacroObDdllLongDqRank0_4, 10:0, scratch112, 10:0); + s(EmcPmacroObDdllLongDqRank0_4, 26:16, scratch112, 21:11); + s(EmcPmacroDdllShortCmd_2, 6:0, scratch112, 28:22); + s(EmcFbioCfg5, 28:26, scratch112, 31:29); + s(EmcPmacroObDdllLongDqRank0_5, 10:0, scratch113, 10:0); + s(EmcPmacroObDdllLongDqRank0_5, 26:16, scratch113, 21:11); + s(McEmemArbTimingRp, 6:0, scratch113, 28:22); + s(EmcFbioCfg5, 31:30, scratch113, 30:29); + s(EmcCfg2, 0:0, scratch113, 31:31); + s(EmcPmacroObDdllLongDqRank1_0, 10:0, scratch114, 10:0); + s(EmcPmacroObDdllLongDqRank1_0, 26:16, scratch114, 21:11); + s(McEmemArbTimingRas, 6:0, scratch114, 28:22); + s(EmcCfg2, 2:1, scratch114, 30:29); + s(EmcCfg2, 7:7, scratch114, 31:31); + s(EmcPmacroObDdllLongDqRank1_1, 10:0, scratch115, 10:0); + s(EmcPmacroObDdllLongDqRank1_1, 26:16, scratch115, 21:11); + s(McEmemArbTimingFaw, 6:0, scratch115, 28:22); + s(EmcCfg2, 11:10, scratch115, 30:29); + s(EmcCfg2, 14:14, scratch115, 31:31); + s(EmcPmacroObDdllLongDqRank1_2, 10:0, scratch123, 10:0); + s(EmcPmacroObDdllLongDqRank1_2, 26:16, scratch123, 21:11); + s(McEmemArbTimingRap2Pre, 6:0, scratch123, 28:22); + s(EmcCfg2, 16:15, scratch123, 30:29); + s(EmcCfg2, 20:20, scratch123, 31:31); + s(EmcPmacroObDdllLongDqRank1_3, 10:0, scratch124, 10:0); + s(EmcPmacroObDdllLongDqRank1_3, 26:16, scratch124, 21:11); + s(McEmemArbTimingWap2Pre, 6:0, scratch124, 28:22); + s(EmcCfg2, 24:22, scratch124, 31:29); + s(EmcPmacroObDdllLongDqRank1_4, 10:0, scratch125, 10:0); + s(EmcPmacroObDdllLongDqRank1_4, 26:16, scratch125, 21:11); + s(McEmemArbTimingR2W, 6:0, scratch125, 28:22); + s(EmcCfg2, 25:25, scratch125, 29:29); + s(EmcCfg2, 29:28, scratch125, 31:30); + s(EmcPmacroObDdllLongDqRank1_5, 10:0, scratch126, 10:0); + s(EmcPmacroObDdllLongDqRank1_5, 26:16, scratch126, 21:11); + s(McEmemArbTimingW2R, 6:0, scratch126, 28:22); + s(EmcCfg2, 31:30, scratch126, 30:29); + s(EmcCfgPipe, 0:0, scratch126, 31:31); + s(EmcPmacroObDdllLongDqsRank0_0, 10:0, scratch127, 10:0); + s(EmcPmacroObDdllLongDqsRank0_0, 26:16, scratch127, 21:11); + s(EmcRp, 5:0, scratch127, 27:22); + s(EmcCfgPipe, 4:1, scratch127, 31:28); + s(EmcPmacroObDdllLongDqsRank0_1, 10:0, scratch128, 10:0); + s(EmcPmacroObDdllLongDqsRank0_1, 26:16, scratch128, 21:11); + s(EmcR2w, 5:0, scratch128, 27:22); + s(EmcCfgPipe, 8:5, scratch128, 31:28); + s(EmcPmacroObDdllLongDqsRank0_2, 10:0, scratch129, 10:0); + s(EmcPmacroObDdllLongDqsRank0_2, 26:16, scratch129, 21:11); + s(EmcW2r, 5:0, scratch129, 27:22); + s(EmcCfgPipe, 11:9, scratch129, 30:28); + s(EmcCfgPipe, 16:16, scratch129, 31:31); + s(EmcPmacroObDdllLongDqsRank0_3, 10:0, scratch130, 10:0); + s(EmcPmacroObDdllLongDqsRank0_3, 26:16, scratch130, 21:11); + s(EmcR2p, 5:0, scratch130, 27:22); + s(EmcCfgPipe, 20:17, scratch130, 31:28); + s(EmcPmacroObDdllLongDqsRank0_4, 10:0, scratch131, 10:0); + s(EmcPmacroObDdllLongDqsRank0_4, 26:16, scratch131, 21:11); + s(EmcCcdmw, 5:0, scratch131, 27:22); + s(EmcCfgPipe, 24:21, scratch131, 31:28); + s(EmcPmacroObDdllLongDqsRank0_5, 10:0, scratch132, 10:0); + s(EmcPmacroObDdllLongDqsRank0_5, 26:16, scratch132, 21:11); + s(EmcRdRcd, 5:0, scratch132, 27:22); + s(EmcCfgPipe, 27:25, scratch132, 30:28); + s(EmcPmacroTxPwrd0, 0:0, scratch132, 31:31); + s(EmcPmacroObDdllLongDqsRank1_0, 10:0, scratch133, 10:0); + s(EmcPmacroObDdllLongDqsRank1_0, 26:16, scratch133, 21:11); + s(EmcWrRcd, 5:0, scratch133, 27:22); + s(EmcPmacroTxPwrd0, 4:1, scratch133, 31:28); + s(EmcPmacroObDdllLongDqsRank1_1, 10:0, scratch134, 10:0); + s(EmcPmacroObDdllLongDqsRank1_1, 26:16, scratch134, 21:11); + s(EmcWdv, 5:0, scratch134, 27:22); + s(EmcPmacroTxPwrd0, 8:5, scratch134, 31:28); + s(EmcPmacroObDdllLongDqsRank1_2, 10:0, scratch135, 10:0); + s(EmcPmacroObDdllLongDqsRank1_2, 26:16, scratch135, 21:11); + s(EmcQUse, 5:0, scratch135, 27:22); + s(EmcPmacroTxPwrd0, 12:9, scratch135, 31:28); + s(EmcPmacroObDdllLongDqsRank1_3, 10:0, scratch136, 10:0); + s(EmcPmacroObDdllLongDqsRank1_3, 26:16, scratch136, 21:11); + s(EmcPdEx2Wr, 5:0, scratch136, 27:22); + s(EmcPmacroTxPwrd0, 13:13, scratch136, 28:28); + s(EmcPmacroTxPwrd0, 18:16, scratch136, 31:29); + s(EmcPmacroObDdllLongDqsRank1_4, 10:0, scratch137, 10:0); + s(EmcPmacroObDdllLongDqsRank1_4, 26:16, scratch137, 21:11); + s(EmcPdEx2Rd, 5:0, scratch137, 27:22); + s(EmcPmacroTxPwrd0, 22:19, scratch137, 31:28); + s(EmcPmacroObDdllLongDqsRank1_5, 10:0, scratch138, 10:0); + s(EmcPmacroObDdllLongDqsRank1_5, 26:16, scratch138, 21:11); + s(EmcPdex2Cke, 5:0, scratch138, 27:22); + s(EmcPmacroTxPwrd0, 26:23, scratch138, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_0, 10:0, scratch139, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_0, 26:16, scratch139, 21:11); + s(EmcPChg2Pden, 5:0, scratch139, 27:22); + s(EmcPmacroTxPwrd0, 29:27, scratch139, 30:28); + s(EmcPmacroTxPwrd1, 0:0, scratch139, 31:31); + s(EmcPmacroIbDdllLongDqsRank0_1, 10:0, scratch140, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_1, 26:16, scratch140, 21:11); + s(EmcAct2Pden, 5:0, scratch140, 27:22); + s(EmcPmacroTxPwrd1, 4:1, scratch140, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_2, 10:0, scratch141, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_2, 26:16, scratch141, 21:11); + s(EmcCke2Pden, 5:0, scratch141, 27:22); + s(EmcPmacroTxPwrd1, 8:5, scratch141, 31:28); + s(EmcPmacroIbDdllLongDqsRank0_3, 10:0, scratch142, 10:0); + s(EmcPmacroIbDdllLongDqsRank0_3, 26:16, scratch142, 21:11); + s(EmcTcke, 5:0, scratch142, 27:22); + s(EmcPmacroTxPwrd1, 12:9, scratch142, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_0, 10:0, scratch143, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_0, 26:16, scratch143, 21:11); + s(EmcTrpab, 5:0, scratch143, 27:22); + s(EmcPmacroTxPwrd1, 13:13, scratch143, 28:28); + s(EmcPmacroTxPwrd1, 18:16, scratch143, 31:29); + s(EmcPmacroIbDdllLongDqsRank1_1, 10:0, scratch144, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_1, 26:16, scratch144, 21:11); + s(EmcClkenOverride, 3:1, scratch144, 24:22); + s(EmcClkenOverride, 8:6, scratch144, 27:25); + s(EmcPmacroTxPwrd1, 22:19, scratch144, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_2, 10:0, scratch145, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_2, 26:16, scratch145, 21:11); + s(EmcEInput, 5:0, scratch145, 27:22); + s(EmcPmacroTxPwrd1, 26:23, scratch145, 31:28); + s(EmcPmacroIbDdllLongDqsRank1_3, 10:0, scratch146, 10:0); + s(EmcPmacroIbDdllLongDqsRank1_3, 26:16, scratch146, 21:11); + s(EmcEInputDuration, 5:0, scratch146, 27:22); + s(EmcPmacroTxPwrd1, 29:27, scratch146, 30:28); + s(EmcPmacroTxPwrd2, 0:0, scratch146, 31:31); + s(EmcPmacroDdllLongCmd_0, 10:0, scratch147, 10:0); + s(EmcPmacroDdllLongCmd_0, 26:16, scratch147, 21:11); + s(EmcPutermExtra, 5:0, scratch147, 27:22); + s(EmcPmacroTxPwrd2, 4:1, scratch147, 31:28); + s(EmcPmacroDdllLongCmd_1, 10:0, scratch148, 10:0); + s(EmcPmacroDdllLongCmd_1, 26:16, scratch148, 21:11); + s(EmcTckesr, 5:0, scratch148, 27:22); + s(EmcPmacroTxPwrd2, 8:5, scratch148, 31:28); + s(EmcPmacroDdllLongCmd_2, 10:0, scratch149, 10:0); + s(EmcPmacroDdllLongCmd_2, 26:16, scratch149, 21:11); + s(EmcTpd, 5:0, scratch149, 27:22); + s(EmcPmacroTxPwrd2, 12:9, scratch149, 31:28); + s(EmcPmacroDdllLongCmd_3, 10:0, scratch150, 10:0); + s(EmcPmacroDdllLongCmd_3, 26:16, scratch150, 21:11); + s(EmcWdvMask, 5:0, scratch150, 27:22); + s(EmcPmacroTxPwrd2, 13:13, scratch150, 28:28); + s(EmcPmacroTxPwrd2, 18:16, scratch150, 31:29); + s(McEmemArbCfg, 8:0, scratch151, 8:0); + s(McEmemArbCfg, 20:16, scratch151, 13:9); + s(McEmemArbCfg, 31:24, scratch151, 21:14); + s(EmcWdvChk, 5:0, scratch151, 27:22); + s(EmcPmacroTxPwrd2, 22:19, scratch151, 31:28); + s(McEmemArbMisc1, 12:0, scratch152, 12:0); + s(McEmemArbMisc1, 25:21, scratch152, 17:13); + s(McEmemArbMisc1, 31:28, scratch152, 21:18); + s(EmcCmdBrlshft0, 5:0, scratch152, 27:22); + s(EmcPmacroTxPwrd2, 26:23, scratch152, 31:28); + s(EmcMrsWaitCnt2, 9:0, scratch153, 9:0); + s(EmcMrsWaitCnt2, 26:16, scratch153, 20:10); + s(EmcPmacroIbRxrt, 10:0, scratch153, 31:21); + s(EmcMrsWaitCnt, 9:0, scratch154, 9:0); + s(EmcMrsWaitCnt, 26:16, scratch154, 20:10); + s(EmcPmacroDdllLongCmd_4, 10:0, scratch154, 31:21); + s(EmcAutoCalInterval, 20:0, scratch155, 20:0); + s(McEmemArbOutstandingReq, 8:0, scratch155, 29:21); + s(McEmemArbOutstandingReq, 31:30, scratch155, 31:30); + s(McEmemArbRefpbHpCtrl, 6:0, scratch156, 6:0); + s(McEmemArbRefpbHpCtrl, 14:8, scratch156, 13:7); + s(McEmemArbRefpbHpCtrl, 22:16, scratch156, 20:14); + s(EmcCmdBrlshft1, 5:0, scratch156, 26:21); + s(EmcRrd, 4:0, scratch156, 31:27); + s(EmcQuseBrlshft0, 19:0, scratch157, 19:0); + s(EmcFbioCfg8, 27:16, scratch157, 31:20); + s(EmcQuseBrlshft1, 19:0, scratch158, 19:0); + s(EmcTxsrDll, 11:0, scratch158, 31:20); + s(EmcQuseBrlshft2, 19:0, scratch159, 19:0); + s(EmcTxdsrvttgen, 11:0, scratch159, 31:20); + s(EmcQuseBrlshft3, 19:0, scratch160, 19:0); + s(EmcPmacroVttgenCtrl0, 3:0, scratch160, 23:20); + s(EmcPmacroVttgenCtrl0, 11:8, scratch160, 27:24); + s(EmcPmacroVttgenCtrl0, 19:16, scratch160, 31:28); + s(EmcPmacroVttgenCtrl1, 19:0, scratch161, 19:0); + s(EmcCmdBrlshft2, 5:0, scratch161, 25:20); + s(EmcCmdBrlshft3, 5:0, scratch161, 31:26); + s(EmcAutoCalConfig3, 5:0, scratch162, 5:0); + s(EmcAutoCalConfig3, 13:8, scratch162, 11:6); + s(EmcAutoCalConfig3, 18:16, scratch162, 14:12); + s(EmcAutoCalConfig3, 22:20, scratch162, 17:15); + s(EmcTRefBw, 13:0, scratch162, 31:18); + s(EmcAutoCalConfig4, 5:0, scratch163, 5:0); + s(EmcAutoCalConfig4, 13:8, scratch163, 11:6); + s(EmcAutoCalConfig4, 18:16, scratch163, 14:12); + s(EmcAutoCalConfig4, 22:20, scratch163, 17:15); + s(EmcQpop, 6:0, scratch163, 24:18); + s(EmcQpop, 22:16, scratch163, 31:25); + s(EmcAutoCalConfig5, 5:0, scratch164, 5:0); + s(EmcAutoCalConfig5, 13:8, scratch164, 11:6); + s(EmcAutoCalConfig5, 18:16, scratch164, 14:12); + s(EmcAutoCalConfig5, 22:20, scratch164, 17:15); + s(EmcPmacroAutocalCfgCommon, 5:0, scratch164, 23:18); + s(EmcPmacroAutocalCfgCommon, 13:8, scratch164, 29:24); + s(EmcPmacroAutocalCfgCommon, 16:16, scratch164, 30:30); + s(EmcPmacroTxPwrd2, 27:27, scratch164, 31:31); + s(EmcAutoCalConfig6, 5:0, scratch165, 5:0); + s(EmcAutoCalConfig6, 13:8, scratch165, 11:6); + s(EmcAutoCalConfig6, 18:16, scratch165, 14:12); + s(EmcAutoCalConfig6, 22:20, scratch165, 17:15); + s(EmcWev, 5:0, scratch165, 23:18); + s(EmcWsv, 5:0, scratch165, 29:24); + s(EmcPmacroTxPwrd2, 29:28, scratch165, 31:30); + s(EmcAutoCalConfig7, 5:0, scratch166, 5:0); + s(EmcAutoCalConfig7, 13:8, scratch166, 11:6); + s(EmcAutoCalConfig7, 18:16, scratch166, 14:12); + s(EmcAutoCalConfig7, 22:20, scratch166, 17:15); + s(EmcCfg3, 2:0, scratch166, 20:18); + s(EmcCfg3, 6:4, scratch166, 23:21); + s(EmcQuseWidth, 3:0, scratch166, 27:24); + s(EmcQuseWidth, 29:28, scratch166, 29:28); + s(EmcPmacroTxPwrd3, 1:0, scratch166, 31:30); + s(EmcAutoCalConfig8, 5:0, scratch167, 5:0); + s(EmcAutoCalConfig8, 13:8, scratch167, 11:6); + s(EmcAutoCalConfig8, 18:16, scratch167, 14:12); + s(EmcAutoCalConfig8, 22:20, scratch167, 17:15); + s(EmcPmacroBgBiasCtrl0, 2:0, scratch167, 20:18); + s(EmcPmacroBgBiasCtrl0, 6:4, scratch167, 23:21); + s(McEmemArbTimingRcd, 5:0, scratch167, 29:24); + s(EmcPmacroTxPwrd3, 3:2, scratch167, 31:30); + s(EmcXm2CompPadCtrl2, 17:0, scratch168, 17:0); + s(McEmemArbTimingCcdmw, 5:0, scratch168, 23:18); + s(McEmemArbOverride, 27:27, scratch168, 24:24); + s(McEmemArbOverride, 26:26, scratch168, 25:25); + s(McEmemArbOverride, 16:16, scratch168, 26:26); + s(McEmemArbOverride, 10:10, scratch168, 27:27); + s(McEmemArbOverride, 4:4, scratch168, 28:28); + s(McEmemArbOverride, 3:3, scratch168, 29:29); + s(EmcPmacroTxPwrd3, 5:4, scratch168, 31:30); + s(EmcXm2CompPadCtrl3, 17:0, scratch169, 17:0); + s(EmcRext, 4:0, scratch169, 22:18); + s(EmcTClkStop, 4:0, scratch169, 27:23); + s(EmcPmacroTxPwrd3, 9:6, scratch169, 31:28); + s(EmcZcalWaitCnt, 10:0, scratch170, 10:0); + s(EmcZcalWaitCnt, 21:16, scratch170, 16:11); + s(EmcZcalWaitCnt, 31:31, scratch170, 17:17); + s(EmcWext, 4:0, scratch170, 22:18); + s(EmcRefctrl2, 0:0, scratch170, 23:23); + s(EmcRefctrl2, 26:24, scratch170, 26:24); + s(EmcRefctrl2, 31:31, scratch170, 27:27); + s(EmcPmacroTxPwrd3, 13:10, scratch170, 31:28); + s(EmcZcalMrwCmd, 7:0, scratch171, 7:0); + s(EmcZcalMrwCmd, 23:16, scratch171, 15:8); + s(EmcZcalMrwCmd, 31:30, scratch171, 17:16); + s(EmcWeDuration, 4:0, scratch171, 22:18); + s(EmcWsDuration, 4:0, scratch171, 27:23); + s(EmcPmacroTxPwrd3, 19:16, scratch171, 31:28); + s(EmcSwizzleRank0Byte0, 2:0, scratch172, 2:0); + s(EmcSwizzleRank0Byte0, 6:4, scratch172, 5:3); + s(EmcSwizzleRank0Byte0, 10:8, scratch172, 8:6); + s(EmcSwizzleRank0Byte0, 14:12, scratch172, 11:9); + s(EmcSwizzleRank0Byte0, 18:16, scratch172, 14:12); + s(EmcSwizzleRank0Byte0, 22:20, scratch172, 17:15); + s(EmcPutermWidth, 31:31, scratch172, 18:18); + s(EmcPutermWidth, 3:0, scratch172, 22:19); + s(McEmemArbTimingRrd, 4:0, scratch172, 27:23); + s(EmcPmacroTxPwrd3, 23:20, scratch172, 31:28); + s(EmcSwizzleRank0Byte1, 2:0, scratch173, 2:0); + s(EmcSwizzleRank0Byte1, 6:4, scratch173, 5:3); + s(EmcSwizzleRank0Byte1, 10:8, scratch173, 8:6); + s(EmcSwizzleRank0Byte1, 14:12, scratch173, 11:9); + s(EmcSwizzleRank0Byte1, 18:16, scratch173, 14:12); + s(EmcSwizzleRank0Byte1, 22:20, scratch173, 17:15); + s(McEmemArbTimingR2R, 4:0, scratch173, 22:18); + s(McEmemArbTimingW2W, 4:0, scratch173, 27:23); + s(EmcPmacroTxPwrd3, 27:24, scratch173, 31:28); + s(EmcSwizzleRank0Byte2, 2:0, scratch174, 2:0); + s(EmcSwizzleRank0Byte2, 6:4, scratch174, 5:3); + s(EmcSwizzleRank0Byte2, 10:8, scratch174, 8:6); + s(EmcSwizzleRank0Byte2, 14:12, scratch174, 11:9); + s(EmcSwizzleRank0Byte2, 18:16, scratch174, 14:12); + s(EmcSwizzleRank0Byte2, 22:20, scratch174, 17:15); + s(EmcPmacroTxPwrd3, 29:28, scratch174, 19:18); + s(EmcPmacroTxSelClkSrc0, 11:0, scratch174, 31:20); + s(EmcSwizzleRank0Byte3, 2:0, scratch175, 2:0); + s(EmcSwizzleRank0Byte3, 6:4, scratch175, 5:3); + s(EmcSwizzleRank0Byte3, 10:8, scratch175, 8:6); + s(EmcSwizzleRank0Byte3, 14:12, scratch175, 11:9); + s(EmcSwizzleRank0Byte3, 18:16, scratch175, 14:12); + s(EmcSwizzleRank0Byte3, 22:20, scratch175, 17:15); + s(EmcPmacroTxSelClkSrc0, 27:16, scratch175, 29:18); + s(EmcPmacroTxSelClkSrc1, 1:0, scratch175, 31:30); + s(EmcSwizzleRank1Byte0, 2:0, scratch176, 2:0); + s(EmcSwizzleRank1Byte0, 6:4, scratch176, 5:3); + s(EmcSwizzleRank1Byte0, 10:8, scratch176, 8:6); + s(EmcSwizzleRank1Byte0, 14:12, scratch176, 11:9); + s(EmcSwizzleRank1Byte0, 18:16, scratch176, 14:12); + s(EmcSwizzleRank1Byte0, 22:20, scratch176, 17:15); + s(EmcPmacroTxSelClkSrc1, 11:2, scratch176, 27:18); + s(EmcPmacroTxSelClkSrc1, 19:16, scratch176, 31:28); + s(EmcSwizzleRank1Byte1, 2:0, scratch177, 2:0); + s(EmcSwizzleRank1Byte1, 6:4, scratch177, 5:3); + s(EmcSwizzleRank1Byte1, 10:8, scratch177, 8:6); + s(EmcSwizzleRank1Byte1, 14:12, scratch177, 11:9); + s(EmcSwizzleRank1Byte1, 18:16, scratch177, 14:12); + s(EmcSwizzleRank1Byte1, 22:20, scratch177, 17:15); + s(EmcPmacroTxSelClkSrc1, 27:20, scratch177, 25:18); + s(EmcPmacroTxSelClkSrc3, 5:0, scratch177, 31:26); + s(EmcSwizzleRank1Byte2, 2:0, scratch178, 2:0); + s(EmcSwizzleRank1Byte2, 6:4, scratch178, 5:3); + s(EmcSwizzleRank1Byte2, 10:8, scratch178, 8:6); + s(EmcSwizzleRank1Byte2, 14:12, scratch178, 11:9); + s(EmcSwizzleRank1Byte2, 18:16, scratch178, 14:12); + s(EmcSwizzleRank1Byte2, 22:20, scratch178, 17:15); + s(EmcPmacroTxSelClkSrc3, 11:6, scratch178, 23:18); + s(EmcPmacroTxSelClkSrc3, 23:16, scratch178, 31:24); + s(EmcSwizzleRank1Byte3, 2:0, scratch179, 2:0); + s(EmcSwizzleRank1Byte3, 6:4, scratch179, 5:3); + s(EmcSwizzleRank1Byte3, 10:8, scratch179, 8:6); + s(EmcSwizzleRank1Byte3, 14:12, scratch179, 11:9); + s(EmcSwizzleRank1Byte3, 18:16, scratch179, 14:12); + s(EmcSwizzleRank1Byte3, 22:20, scratch179, 17:15); + s(EmcPmacroTxSelClkSrc3, 27:24, scratch179, 21:18); + s(EmcPmacroTxSelClkSrc2, 9:0, scratch179, 31:22); + s(EmcPmacroCmdBrickCtrlFdpd, 17:0, scratch180, 17:0); + s(EmcPmacroTxSelClkSrc2, 11:10, scratch180, 19:18); + s(EmcPmacroTxSelClkSrc2, 27:16, scratch180, 31:20); + s(EmcPmacroDataBrickCtrlFdpd, 17:0, scratch181, 17:0); + s(EmcPmacroTxSelClkSrc4, 11:0, scratch181, 29:18); + s(EmcPmacroTxSelClkSrc4, 17:16, scratch181, 31:30); + s(EmcFbioCfg7, 16:0, scratch182, 16:0); + s(McEmemArbRefpbBankCtrl, 6:0, scratch182, 23:17); + s(McEmemArbRefpbBankCtrl, 14:8, scratch182, 30:24); + s(McEmemArbRefpbBankCtrl, 31:31, scratch182, 31:31); + s(EmcDynSelfRefControl, 15:0, scratch183, 15:0); + s(EmcDynSelfRefControl, 31:31, scratch183, 16:16); + s(EmcPmacroTxSelClkSrc4, 27:18, scratch183, 26:17); + s(EmcPmacroTxSelClkSrc5, 4:0, scratch183, 31:27); + s(EmcDllCfg1, 16:0, scratch184, 16:0); + s(EmcPmacroTxSelClkSrc5, 11:5, scratch184, 23:17); + s(EmcPmacroTxSelClkSrc5, 23:16, scratch184, 31:24); + s(EmcPmacroPadCfgCtrl, 1:0, scratch185, 1:0); + s(EmcPmacroPadCfgCtrl, 6:5, scratch185, 3:2); + s(EmcPmacroPadCfgCtrl, 11:9, scratch185, 6:4); + s(EmcPmacroPadCfgCtrl, 13:13, scratch185, 7:7); + s(EmcPmacroPadCfgCtrl, 17:16, scratch185, 9:8); + s(EmcPmacroPadCfgCtrl, 21:20, scratch185, 11:10); + s(EmcPmacroPadCfgCtrl, 25:24, scratch185, 13:12); + s(EmcPmacroPadCfgCtrl, 30:28, scratch185, 16:14); + s(EmcPmacroTxSelClkSrc5, 27:24, scratch185, 20:17); + s(EmcPmacroCmdPadTxCtrl, 1:0, scratch185, 22:21); + s(EmcPmacroCmdPadTxCtrl, 5:4, scratch185, 24:23); + s(EmcPmacroCmdPadTxCtrl, 9:8, scratch185, 26:25); + s(EmcPmacroCmdPadTxCtrl, 13:12, scratch185, 28:27); + s(EmcPmacroCmdPadTxCtrl, 16:16, scratch185, 29:29); + s(EmcPmacroCmdPadTxCtrl, 21:20, scratch185, 31:30); + s(EmcRefresh, 15:0, scratch186, 15:0); + s(EmcCmdQ, 4:0, scratch186, 20:16); + s(EmcCmdQ, 10:8, scratch186, 23:21); + s(EmcCmdQ, 14:12, scratch186, 26:24); + s(EmcCmdQ, 28:24, scratch186, 31:27); + s(EmcAcpdControl, 15:0, scratch187, 15:0); + s(EmcAutoCalVrefSel1, 15:0, scratch187, 31:16); + s(EmcXm2CompPadCtrl, 1:0, scratch188, 1:0); + s(EmcXm2CompPadCtrl, 6:3, scratch188, 5:2); + s(EmcXm2CompPadCtrl, 9:9, scratch188, 6:6); + s(EmcXm2CompPadCtrl, 19:11, scratch188, 15:7); + s(EmcCfgDigDllPeriod, 15:0, scratch188, 31:16); + s(EmcCfgDigDll_1, 15:0, scratch189, 15:0); + s(EmcPreRefreshReqCnt, 15:0, scratch189, 31:16); + s(EmcPmacroCmdPadTxCtrl, 27:24, scratch190, 19:16); + s(EmcPmacroDataPadTxCtrl, 1:0, scratch190, 21:20); + s(EmcPmacroDataPadTxCtrl, 5:4, scratch190, 23:22); + s(EmcPmacroDataPadTxCtrl, 9:8, scratch190, 25:24); + s(EmcPmacroDataPadTxCtrl, 13:12, scratch190, 27:26); + s(EmcPmacroDataPadTxCtrl, 16:16, scratch190, 28:28); + s(EmcPmacroDataPadTxCtrl, 21:20, scratch190, 30:29); + s(EmcPmacroDataPadTxCtrl, 24:24, scratch190, 31:31); + s(EmcPmacroDataPadTxCtrl, 27:25, scratch191, 2:0); + + s(EmcPinGpio, 1:0, scratch8, 31:30); + s(EmcPinGpioEn, 1:0, scratch9, 31:30); + s(EmcDevSelect, 1:0, scratch10, 31:30); + s(EmcZcalWarmColdBootEnables, 1:0, scratch11, 31:30); + s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch12, 31:30); + s32(EmcBctSpare13, scratch31); + s32(EmcBctSpare12, scratch32); + s32(EmcBctSpare7, scratch33); + s32(EmcBctSpare6, scratch40); + s32(EmcBctSpare5, scratch42); + s32(EmcBctSpare4, scratch44); + s32(EmcBctSpare3, scratch45); + s32(EmcBctSpare2, scratch46); + s32(EmcBctSpare1, scratch47); + s32(EmcBctSpare0, scratch48); + s32(EmcBctSpare9, scratch50); + s32(EmcBctSpare8, scratch51); + s32(BootRomPatchData, scratch56); + s32(BootRomPatchControl, scratch57); + s(McClkenOverrideAllWarmBoot, 0:0, scratch58, 31:31); + s(EmcClkenOverrideAllWarmBoot, 0:0, scratch59, 30:30); + s(EmcMrsWarmBootEnable, 0:0, scratch59, 31:31); + s(ClearClk2Mc1, 0:0, scratch60, 30:30); + s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch60, 31:31); + s(ClkRstControllerPllmMisc2OverrideEnable, 0:0, scratch61, 30:30); + s(EmcDbgWriteMux, 0:0, scratch61, 31:31); + s(EmcExtraRefreshNum, 2:0, scratch62, 31:29); + s(PmcIoDpd3ReqWait, 2:0, scratch68, 30:28); + s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch68, 31:31); + s(MemoryType, 2:0, scratch69, 30:28); + s(PmcIoDpd4ReqWait, 2:0, scratch70, 30:28); + s(EmcTimingControlWait, 7:0, scratch86, 31:24); + s(EmcZcalWarmBootWait, 7:0, scratch87, 31:24); + s(WarmBootWait, 7:0, scratch88, 31:24); + s(EmcPinProgramWait, 7:0, scratch89, 31:24); + s(EmcAutoCalWait, 9:0, scratch101, 31:22); + s(SwizzleRankByteEncode, 15:0, scratch190, 15:0); + + switch (sdram->MemoryType) + { + case NvBootMemoryType_LpDdr2: + case NvBootMemoryType_LpDdr4: + s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); + s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); + s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); + s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24); + s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0); + s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); + s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); + s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); + s(EmcMrw6, 27:0, scratch8, 27:0); + s(EmcMrw6, 31:30, scratch8, 29:28); + s(EmcMrw8, 27:0, scratch9, 27:0); + s(EmcMrw8, 31:30, scratch9, 29:28); + s(EmcMrw9, 27:0, scratch10, 27:0); + s(EmcMrw9, 31:30, scratch10, 29:28); + s(EmcMrw10, 27:0, scratch11, 27:0); + s(EmcMrw10, 31:30, scratch11, 29:28); + s(EmcMrw12, 27:0, scratch12, 27:0); + s(EmcMrw12, 31:30, scratch12, 29:28); + s(EmcMrw13, 27:0, scratch13, 27:0); + s(EmcMrw13, 31:30, scratch13, 29:28); + s(EmcMrw14, 27:0, scratch14, 27:0); + s(EmcMrw14, 31:30, scratch14, 29:28); + s(EmcMrw1, 7:0, scratch15, 7:0); + s(EmcMrw1, 23:16, scratch15, 15:8); + s(EmcMrw1, 27:26, scratch15, 17:16); + s(EmcMrw1, 31:30, scratch15, 19:18); + s(EmcWarmBootMrwExtra, 7:0, scratch16, 7:0); + s(EmcWarmBootMrwExtra, 23:16, scratch16, 15:8); + s(EmcWarmBootMrwExtra, 27:26, scratch16, 17:16); + s(EmcWarmBootMrwExtra, 31:30, scratch16, 19:18); + s(EmcMrw2, 7:0, scratch17, 7:0); + s(EmcMrw2, 23:16, scratch17, 15:8); + s(EmcMrw2, 27:26, scratch17, 17:16); + s(EmcMrw2, 31:30, scratch17, 19:18); + s(EmcMrw3, 7:0, scratch18, 7:0); + s(EmcMrw3, 23:16, scratch18, 15:8); + s(EmcMrw3, 27:26, scratch18, 17:16); + s(EmcMrw3, 31:30, scratch18, 19:18); + s(EmcMrw4, 7:0, scratch19, 7:0); + s(EmcMrw4, 23:16, scratch19, 15:8); + s(EmcMrw4, 27:26, scratch19, 17:16); + s(EmcMrw4, 31:30, scratch19, 19:18); + break; + case NvBootMemoryType_Ddr3: + s(EmcMrs, 13:0, scratch5, 13:0); + s(EmcEmrs, 13:0, scratch5, 27:14); + s(EmcMrs, 21:20, scratch5, 29:28); + s(EmcMrs, 31:30, scratch5, 31:30); + s(EmcEmrs2, 13:0, scratch8, 13:0); + s(EmcEmrs3, 13:0, scratch8, 27:14); + s(EmcEmrs, 21:20, scratch8, 29:28); + s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); + s(EmcEmrs, 31:30, scratch9, 15:14); + s(EmcEmrs2, 21:20, scratch9, 17:16); + s(EmcEmrs2, 31:30, scratch9, 19:18); + s(EmcEmrs3, 21:20, scratch9, 21:20); + s(EmcEmrs3, 31:30, scratch9, 23:22); + s(EmcWarmBootMrsExtra, 31:30, scratch9, 25:24); + s(EmcWarmBootMrsExtra, 21:20, scratch9, 27:26); + s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 29:28); + s(EmcMrs, 27:26, scratch10, 1:0); + s(EmcEmrs, 27:26, scratch10, 3:2); + s(EmcEmrs2, 27:26, scratch10, 5:4); + s(EmcEmrs3, 27:26, scratch10, 7:6); + s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8); + s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); + s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); + s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); + break; + } + + s32(EmcCmdMappingByte, secure_scratch8); + s32(EmcPmacroBrickMapping0, secure_scratch9); + s32(EmcPmacroBrickMapping1, secure_scratch10); + s32(EmcPmacroBrickMapping2, secure_scratch11); + s32(McVideoProtectGpuOverride0, secure_scratch12); + s(EmcCmdMappingCmd0_0, 6:0, secure_scratch13, 6:0); + s(EmcCmdMappingCmd0_0, 14:8, secure_scratch13, 13:7); + s(EmcCmdMappingCmd0_0, 22:16, secure_scratch13, 20:14); + s(EmcCmdMappingCmd0_0, 30:24, secure_scratch13, 27:21); + s(McVideoProtectBomAdrHi, 1:0, secure_scratch13, 29:28); + s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 31:30); + s(EmcCmdMappingCmd0_1, 6:0, secure_scratch14, 6:0); + s(EmcCmdMappingCmd0_1, 14:8, secure_scratch14, 13:7); + s(EmcCmdMappingCmd0_1, 22:16, secure_scratch14, 20:14); + s(EmcCmdMappingCmd0_1, 30:24, secure_scratch14, 27:21); + s(McSecCarveoutAdrHi, 1:0, secure_scratch14, 29:28); + s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 31:30); + s(EmcCmdMappingCmd1_0, 6:0, secure_scratch15, 6:0); + s(EmcCmdMappingCmd1_0, 14:8, secure_scratch15, 13:7); + s(EmcCmdMappingCmd1_0, 22:16, secure_scratch15, 20:14); + s(EmcCmdMappingCmd1_0, 30:24, secure_scratch15, 27:21); + s(McGeneralizedCarveout5BomHi, 1:0, secure_scratch15, 29:28); + s(McGeneralizedCarveout3BomHi, 1:0, secure_scratch15, 31:30); + s(EmcCmdMappingCmd1_1, 6:0, secure_scratch16, 6:0); + s(EmcCmdMappingCmd1_1, 14:8, secure_scratch16, 13:7); + s(EmcCmdMappingCmd1_1, 22:16, secure_scratch16, 20:14); + s(EmcCmdMappingCmd1_1, 30:24, secure_scratch16, 27:21); + s(McGeneralizedCarveout2BomHi, 1:0, secure_scratch16, 29:28); + s(McGeneralizedCarveout4BomHi, 1:0, secure_scratch16, 31:30); + s(EmcCmdMappingCmd2_0, 6:0, secure_scratch17, 6:0); + s(EmcCmdMappingCmd2_0, 14:8, secure_scratch17, 13:7); + s(EmcCmdMappingCmd2_0, 22:16, secure_scratch17, 20:14); + s(EmcCmdMappingCmd2_0, 30:24, secure_scratch17, 27:21); + s(McGeneralizedCarveout1BomHi, 1:0, secure_scratch17, 29:28); + s(EmcAdrCfg, 0:0, secure_scratch17, 30:30); + s(EmcFbioSpare, 1:1, secure_scratch17, 31:31); + s(EmcCmdMappingCmd2_1, 6:0, secure_scratch18, 6:0); + s(EmcCmdMappingCmd2_1, 14:8, secure_scratch18, 13:7); + s(EmcCmdMappingCmd2_1, 22:16, secure_scratch18, 20:14); + s(EmcCmdMappingCmd2_1, 30:24, secure_scratch18, 27:21); + s(EmcFbioCfg8, 15:15, secure_scratch18, 28:28); + s(McEmemAdrCfg, 0:0, secure_scratch18, 29:29); + s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch18, 30:30); + s(McMtsCarveoutRegCtrl, 0:0, secure_scratch18, 31:31); + s(EmcCmdMappingCmd3_0, 6:0, secure_scratch19, 6:0); + s(EmcCmdMappingCmd3_0, 14:8, secure_scratch19, 13:7); + s(EmcCmdMappingCmd3_0, 22:16, secure_scratch19, 20:14); + s(EmcCmdMappingCmd3_0, 30:24, secure_scratch19, 27:21); + s(McGeneralizedCarveout2Cfg0, 6:3, secure_scratch19, 31:28); + s(EmcCmdMappingCmd3_1, 6:0, secure_scratch20, 6:0); + s(EmcCmdMappingCmd3_1, 14:8, secure_scratch20, 13:7); + s(EmcCmdMappingCmd3_1, 22:16, secure_scratch20, 20:14); + s(EmcCmdMappingCmd3_1, 30:24, secure_scratch20, 27:21); + s(McGeneralizedCarveout2Cfg0, 10:7, secure_scratch20, 31:28); + s(McGeneralizedCarveout4Cfg0, 26:0, secure_scratch39, 26:0); + s(McGeneralizedCarveout2Cfg0, 17:14, secure_scratch39, 30:27); + s(McVideoProtectVprOverride, 0:0, secure_scratch39, 31:31); + s(McGeneralizedCarveout5Cfg0, 26:0, secure_scratch40, 26:0); + s(McGeneralizedCarveout2Cfg0, 21:18, secure_scratch40, 30:27); + s(McVideoProtectVprOverride, 1:1, secure_scratch40, 31:31); + s(EmcCmdMappingCmd0_2, 6:0, secure_scratch41, 6:0); + s(EmcCmdMappingCmd0_2, 14:8, secure_scratch41, 13:7); + s(EmcCmdMappingCmd0_2, 22:16, secure_scratch41, 20:14); + s(EmcCmdMappingCmd0_2, 27:24, secure_scratch41, 24:21); + s(McGeneralizedCarveout1Cfg0, 6:3, secure_scratch41, 28:25); + s(McGeneralizedCarveout2Cfg0, 13:11, secure_scratch41, 31:29); + s(EmcCmdMappingCmd1_2, 6:0, secure_scratch42, 6:0); + s(EmcCmdMappingCmd1_2, 14:8, secure_scratch42, 13:7); + s(EmcCmdMappingCmd1_2, 22:16, secure_scratch42, 20:14); + s(EmcCmdMappingCmd1_2, 27:24, secure_scratch42, 24:21); + s(McGeneralizedCarveout1Cfg0, 13:7, secure_scratch42, 31:25); + s(EmcCmdMappingCmd2_2, 6:0, secure_scratch43, 6:0); + s(EmcCmdMappingCmd2_2, 14:8, secure_scratch43, 13:7); + s(EmcCmdMappingCmd2_2, 22:16, secure_scratch43, 20:14); + s(EmcCmdMappingCmd2_2, 27:24, secure_scratch43, 24:21); + s(McGeneralizedCarveout1Cfg0, 17:14, secure_scratch43, 28:25); + s(McGeneralizedCarveout3Cfg0, 13:11, secure_scratch43, 31:29); + s(EmcCmdMappingCmd3_2, 6:0, secure_scratch44, 6:0); + s(EmcCmdMappingCmd3_2, 14:8, secure_scratch44, 13:7); + s(EmcCmdMappingCmd3_2, 22:16, secure_scratch44, 20:14); + s(EmcCmdMappingCmd3_2, 27:24, secure_scratch44, 24:21); + s(McGeneralizedCarveout1Cfg0, 21:18, secure_scratch44, 28:25); + s(McVideoProtectVprOverride, 3:2, secure_scratch44, 30:29); + s(McVideoProtectVprOverride, 6:6, secure_scratch44, 31:31); + s(McEmemAdrCfgChannelMask, 31:9, secure_scratch45, 22:0); + s(McEmemAdrCfgDev0, 2:0, secure_scratch45, 25:23); + s(McEmemAdrCfgDev0, 9:8, secure_scratch45, 27:26); + s(McEmemAdrCfgDev0, 19:16, secure_scratch45, 31:28); + s(McEmemAdrCfgBankMask0, 31:10, secure_scratch46, 21:0); + s(McEmemAdrCfgDev1, 2:0, secure_scratch46, 24:22); + s(McEmemAdrCfgDev1, 9:8, secure_scratch46, 26:25); + s(McEmemAdrCfgDev1, 19:16, secure_scratch46, 30:27); + s(McVideoProtectVprOverride, 7:7, secure_scratch46, 31:31); + s(McEmemAdrCfgBankMask1, 31:10, secure_scratch47, 21:0); + s(McGeneralizedCarveout3Cfg0, 10:3, secure_scratch47, 29:22); + s(McVideoProtectVprOverride, 9:8, secure_scratch47, 31:30); + s(McEmemAdrCfgBankMask2, 31:10, secure_scratch48, 21:0); + s(McGeneralizedCarveout3Cfg0, 21:14, secure_scratch48, 29:22); + s(McVideoProtectVprOverride, 11:11, secure_scratch48, 30:30); + s(McVideoProtectVprOverride, 14:14, secure_scratch48, 31:31); + s(McVideoProtectGpuOverride1, 15:0, secure_scratch49, 15:0); + s(McEmemCfg, 13:0, secure_scratch49, 29:16); + s(McEmemCfg, 31:31, secure_scratch49, 30:30); + s(McVideoProtectVprOverride, 15:15, secure_scratch49, 31:31); + s(McGeneralizedCarveout3Bom, 31:17, secure_scratch50, 14:0); + s(McGeneralizedCarveout1Bom, 31:17, secure_scratch50, 29:15); + s(McVideoProtectVprOverride, 18:17, secure_scratch50, 31:30); + s(McGeneralizedCarveout4Bom, 31:17, secure_scratch51, 14:0); + s(McGeneralizedCarveout2Bom, 31:17, secure_scratch51, 29:15); + s(McVideoProtectVprOverride, 20:19, secure_scratch51, 31:30); + s(McGeneralizedCarveout5Bom, 31:17, secure_scratch52, 14:0); + s(McVideoProtectBom, 31:20, secure_scratch52, 26:15); + s(McVideoProtectVprOverride, 23:21, secure_scratch52, 29:27); + s(McVideoProtectVprOverride, 26:26, secure_scratch52, 30:30); + s(McVideoProtectVprOverride, 29:29, secure_scratch52, 31:31); + s(McVideoProtectSizeMb, 11:0, secure_scratch53, 11:0); + s(McSecCarveoutBom, 31:20, secure_scratch53, 23:12); + s(McVideoProtectVprOverride, 31:30, secure_scratch53, 25:24); + s(McVideoProtectVprOverride1, 1:0, secure_scratch53, 27:26); + s(McVideoProtectVprOverride1, 7:4, secure_scratch53, 31:28); + s(McSecCarveoutSizeMb, 11:0, secure_scratch54, 11:0); + s(McMtsCarveoutBom, 31:20, secure_scratch54, 23:12); + s(McVideoProtectVprOverride1, 15:8, secure_scratch54, 31:24); + s(McMtsCarveoutSizeMb, 11:0, secure_scratch55, 11:0); + s(McGeneralizedCarveout4Size128kb, 11:0, secure_scratch55, 23:12); + s(McVideoProtectVprOverride1, 16:16, secure_scratch55, 24:24); + s(McGeneralizedCarveout2Cfg0, 2:0, secure_scratch55, 27:25); + s(McGeneralizedCarveout2Cfg0, 25:22, secure_scratch55, 31:28); + s(McGeneralizedCarveout3Size128kb, 11:0, secure_scratch56, 11:0); + s(McGeneralizedCarveout2Size128kb, 11:0, secure_scratch56, 23:12); + s(McGeneralizedCarveout2Cfg0, 26:26, secure_scratch56, 24:24); + s(McGeneralizedCarveout1Cfg0, 2:0, secure_scratch56, 27:25); + s(McGeneralizedCarveout1Cfg0, 25:22, secure_scratch56, 31:28); + s(McGeneralizedCarveout1Size128kb, 11:0, secure_scratch57, 11:0); + s(McGeneralizedCarveout5Size128kb, 11:0, secure_scratch57, 23:12); + s(McGeneralizedCarveout1Cfg0, 26:26, secure_scratch57, 24:24); + s(McGeneralizedCarveout3Cfg0, 2:0, secure_scratch57, 27:25); + s(McGeneralizedCarveout3Cfg0, 25:22, secure_scratch57, 31:28); + s(McGeneralizedCarveout3Cfg0, 26:26, secure_scratch58, 0:0); + + s32(McGeneralizedCarveout1Access0, secure_scratch59); + s32(McGeneralizedCarveout1Access1, secure_scratch60); + s32(McGeneralizedCarveout1Access2, secure_scratch61); + s32(McGeneralizedCarveout1Access3, secure_scratch62); + s32(McGeneralizedCarveout1Access4, secure_scratch63); + s32(McGeneralizedCarveout2Access0, secure_scratch64); + s32(McGeneralizedCarveout2Access1, secure_scratch65); + s32(McGeneralizedCarveout2Access2, secure_scratch66); + s32(McGeneralizedCarveout2Access3, secure_scratch67); + s32(McGeneralizedCarveout2Access4, secure_scratch68); + s32(McGeneralizedCarveout3Access0, secure_scratch69); + s32(McGeneralizedCarveout3Access1, secure_scratch70); + s32(McGeneralizedCarveout3Access2, secure_scratch71); + s32(McGeneralizedCarveout3Access3, secure_scratch72); + s32(McGeneralizedCarveout3Access4, secure_scratch73); + s32(McGeneralizedCarveout4Access0, secure_scratch74); + s32(McGeneralizedCarveout4Access1, secure_scratch75); + s32(McGeneralizedCarveout4Access2, secure_scratch76); + s32(McGeneralizedCarveout4Access3, secure_scratch77); + s32(McGeneralizedCarveout4Access4, secure_scratch78); + s32(McGeneralizedCarveout5Access0, secure_scratch79); + s32(McGeneralizedCarveout5Access1, secure_scratch80); + s32(McGeneralizedCarveout5Access2, secure_scratch81); + s32(McGeneralizedCarveout5Access3, secure_scratch82); + s32(McGeneralizedCarveout1ForceInternalAccess0, secure_scratch84); + s32(McGeneralizedCarveout1ForceInternalAccess1, secure_scratch85); + s32(McGeneralizedCarveout1ForceInternalAccess2, secure_scratch86); + s32(McGeneralizedCarveout1ForceInternalAccess3, secure_scratch87); + s32(McGeneralizedCarveout1ForceInternalAccess4, secure_scratch88); + s32(McGeneralizedCarveout2ForceInternalAccess0, secure_scratch89); + s32(McGeneralizedCarveout2ForceInternalAccess1, secure_scratch90); + s32(McGeneralizedCarveout2ForceInternalAccess2, secure_scratch91); + s32(McGeneralizedCarveout2ForceInternalAccess3, secure_scratch92); + s32(McGeneralizedCarveout2ForceInternalAccess4, secure_scratch93); + s32(McGeneralizedCarveout3ForceInternalAccess0, secure_scratch94); + s32(McGeneralizedCarveout3ForceInternalAccess1, secure_scratch95); + s32(McGeneralizedCarveout3ForceInternalAccess2, secure_scratch96); + s32(McGeneralizedCarveout3ForceInternalAccess3, secure_scratch97); + s32(McGeneralizedCarveout3ForceInternalAccess4, secure_scratch98); + s32(McGeneralizedCarveout4ForceInternalAccess0, secure_scratch99); + s32(McGeneralizedCarveout4ForceInternalAccess1, secure_scratch100); + s32(McGeneralizedCarveout4ForceInternalAccess2, secure_scratch101); + s32(McGeneralizedCarveout4ForceInternalAccess3, secure_scratch102); + s32(McGeneralizedCarveout4ForceInternalAccess4, secure_scratch103); + s32(McGeneralizedCarveout5ForceInternalAccess0, secure_scratch104); + s32(McGeneralizedCarveout5ForceInternalAccess1, secure_scratch105); + s32(McGeneralizedCarveout5ForceInternalAccess2, secure_scratch106); + s32(McGeneralizedCarveout5ForceInternalAccess3, secure_scratch107); + + c32(0, scratch2); + s(PllMInputDivider, 7:0, scratch2, 7:0); + s(PllMFeedbackDivider, 7:0, scratch2, 15:8); + s(PllMPostDivider, 4:0, scratch2, 20:16); + s(PllMKVCO, 0:0, scratch2, 21:21); + s(PllMKCP, 1:0, scratch2, 23:22); + + c32(0, scratch35); + s(PllMSetupControl, 15:0, scratch35, 15:0); + + c32(0, scratch3); + s(PllMInputDivider, 7:0, scratch3, 7:0); + c(0x3e, scratch3, 15:8); + c(0, scratch3, 20:16); + s(PllMKVCO, 0:0, scratch3, 21:21); + s(PllMKCP, 1:0, scratch3, 23:22); + + c32(0, scratch36); + s(PllMSetupControl, 23:0, scratch36, 23:0); + + c32(0, scratch4); + s(PllMStableTime, 9:0, scratch4, 9:0); +} diff --git a/fusee/fusee-primary/src/sdram_lz.inl b/fusee/fusee-primary/src/sdram_lz.inl new file mode 100644 index 000000000..d16470fe6 --- /dev/null +++ b/fusee/fusee-primary/src/sdram_lz.inl @@ -0,0 +1,108 @@ +static const uint8_t _dram_cfg_lz[1262] = { + 0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, + 0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, + 0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, + 0x00, 0x04, 0xB4, 0x01, 0x70, 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, + 0x70, 0x17, 0x10, 0x24, 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, + 0x00, 0x00, 0x00, 0x17, 0x04, 0x04, 0x17, 0x09, 0x18, 0xFF, 0xFF, 0x1F, + 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, 0x77, + 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, 0x17, 0x08, 0x08, 0xA6, 0xA6, + 0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, 0x04, 0x04, + 0x04, 0x04, 0x17, 0x04, 0x04, 0x17, 0x04, 0x3C, 0x1F, 0x1F, 0x1F, 0x1F, + 0x17, 0x04, 0x04, 0x17, 0x06, 0x06, 0x00, 0x00, 0x04, 0x08, 0x17, 0x06, + 0x46, 0xA1, 0x01, 0x00, 0x00, 0x32, 0x17, 0x0B, 0x64, 0x01, 0x17, 0x04, + 0x7C, 0x17, 0x07, 0x0C, 0x03, 0x17, 0x04, 0x04, 0x00, 0x00, 0x00, 0x1E, + 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x13, + 0x17, 0x0B, 0x2C, 0x09, 0x00, 0x00, 0x00, 0x17, 0x05, 0x5D, 0x17, 0x07, + 0x10, 0x0B, 0x17, 0x07, 0x28, 0x08, 0x17, 0x07, 0x0C, 0x17, 0x04, 0x1C, + 0x20, 0x00, 0x00, 0x00, 0x06, 0x17, 0x04, 0x04, 0x17, 0x07, 0x08, 0x17, + 0x04, 0x50, 0x17, 0x04, 0x2C, 0x17, 0x04, 0x1C, 0x17, 0x04, 0x10, 0x17, + 0x08, 0x6C, 0x17, 0x04, 0x10, 0x17, 0x04, 0x38, 0x17, 0x04, 0x40, 0x05, + 0x17, 0x07, 0x1C, 0x17, 0x08, 0x58, 0x17, 0x04, 0x24, 0x17, 0x04, 0x18, + 0x17, 0x08, 0x64, 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, + 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x17, 0x09, 0x0C, 0x17, 0x05, 0x82, + 0x58, 0x17, 0x07, 0x61, 0xC1, 0x17, 0x07, 0x50, 0x17, 0x04, 0x04, 0x17, + 0x08, 0x81, 0x48, 0x17, 0x04, 0x04, 0x17, 0x04, 0x28, 0x17, 0x04, 0x60, + 0x17, 0x08, 0x54, 0x27, 0x17, 0x04, 0x04, 0x17, 0x07, 0x14, 0x17, 0x04, + 0x04, 0x04, 0x17, 0x07, 0x81, 0x58, 0x17, 0x0C, 0x0C, 0x1C, 0x03, 0x00, + 0x00, 0x0D, 0xA0, 0x60, 0x91, 0xBF, 0x3B, 0x17, 0x04, 0x5A, 0xF3, 0x0C, + 0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, + 0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, + 0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, + 0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, + 0x24, 0x06, 0x07, 0x9A, 0x12, 0x17, 0x05, 0x83, 0x41, 0x00, 0xFF, 0x17, + 0x10, 0x83, 0x6C, 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, + 0x00, 0x0D, 0x08, 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00, + 0x00, 0x0B, 0x08, 0x72, 0x72, 0x0E, 0x0C, 0x17, 0x04, 0x20, 0x08, 0x08, + 0x0D, 0x0C, 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x17, 0x06, + 0x2C, 0x11, 0x08, 0x17, 0x10, 0x84, 0x67, 0x15, 0x00, 0xCC, 0x00, 0x0A, + 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, 0xFF, + 0x0F, 0xFF, 0x0F, 0x17, 0x08, 0x83, 0x4C, 0x01, 0x03, 0x00, 0x70, 0x00, + 0x0C, 0x00, 0x01, 0x17, 0x04, 0x0C, 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, + 0x00, 0x06, 0x13, 0x07, 0x00, 0x80, 0x17, 0x04, 0x10, 0xA0, 0x00, 0x2C, + 0x00, 0x01, 0x37, 0x00, 0x00, 0x00, 0x80, 0x17, 0x06, 0x48, 0x08, 0x00, + 0x04, 0x00, 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28, + 0x28, 0x28, 0x17, 0x04, 0x04, 0x11, 0x11, 0x11, 0x11, 0x17, 0x04, 0x04, + 0xBE, 0x00, 0x00, 0x17, 0x05, 0x58, 0x17, 0x08, 0x5C, 0x17, 0x22, 0x85, + 0x6A, 0x17, 0x1A, 0x1A, 0x14, 0x00, 0x12, 0x00, 0x10, 0x17, 0x05, 0x83, + 0x0A, 0x17, 0x16, 0x18, 0x30, 0x00, 0x2E, 0x00, 0x33, 0x00, 0x30, 0x00, + 0x33, 0x00, 0x35, 0x00, 0x30, 0x00, 0x32, 0x17, 0x05, 0x83, 0x0C, 0x17, + 0x04, 0x20, 0x17, 0x18, 0x18, 0x28, 0x00, 0x28, 0x17, 0x04, 0x04, 0x17, + 0x08, 0x08, 0x17, 0x10, 0x10, 0x00, 0x14, 0x17, 0x05, 0x5A, 0x17, 0x04, + 0x5C, 0x17, 0x04, 0x5E, 0x17, 0x04, 0x0E, 0x17, 0x0E, 0x78, 0x17, 0x09, + 0x82, 0x50, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, 0x00, 0x51, + 0x17, 0x08, 0x18, 0x80, 0x01, 0x00, 0x00, 0x40, 0x17, 0x04, 0x20, 0x03, + 0x00, 0x00, 0x00, 0xAB, 0x00, 0x0A, 0x04, 0x11, 0x17, 0x08, 0x82, 0x58, + 0x17, 0x0C, 0x38, 0x17, 0x1B, 0x81, 0x6C, 0x17, 0x08, 0x85, 0x60, 0x17, + 0x08, 0x86, 0x50, 0x17, 0x08, 0x86, 0x60, 0x17, 0x06, 0x83, 0x21, 0x22, + 0x04, 0xFF, 0xFF, 0xAF, 0x4F, 0x17, 0x0C, 0x86, 0x74, 0x17, 0x08, 0x2C, + 0x8B, 0xFF, 0x07, 0x17, 0x06, 0x81, 0x04, 0x32, 0x54, 0x76, 0x10, 0x47, + 0x32, 0x65, 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75, + 0x64, 0x32, 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45, + 0x32, 0x67, 0x17, 0x04, 0x24, 0x49, 0x92, 0x24, 0x17, 0x04, 0x04, 0x17, + 0x11, 0x7C, 0x1B, 0x17, 0x04, 0x04, 0x17, 0x13, 0x81, 0x14, 0x2F, 0x41, + 0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, 0x17, 0x04, 0x7C, 0xFF, 0xFF, 0xFF, + 0x7F, 0x0B, 0xD7, 0x06, 0x40, 0x00, 0x00, 0x02, 0x00, 0x08, 0x08, 0x03, + 0x00, 0x00, 0x5C, 0x01, 0x00, 0x10, 0x10, 0x10, 0x17, 0x06, 0x86, 0x59, + 0x17, 0x0F, 0x89, 0x14, 0x37, 0x17, 0x07, 0x82, 0x72, 0x10, 0x17, 0x06, + 0x83, 0x0D, 0x00, 0x11, 0x01, 0x17, 0x05, 0x85, 0x39, 0x17, 0x04, 0x0E, + 0x0A, 0x17, 0x07, 0x89, 0x29, 0x17, 0x04, 0x1B, 0x17, 0x08, 0x86, 0x77, + 0x17, 0x09, 0x12, 0x20, 0x00, 0x00, 0x00, 0x81, 0x10, 0x09, 0x28, 0x93, + 0x32, 0xA5, 0x44, 0x5B, 0x8A, 0x67, 0x76, 0x17, 0x18, 0x82, 0x2C, 0xFF, + 0xEF, 0xFF, 0xEF, 0xC0, 0xC0, 0xC0, 0xC0, 0x17, 0x04, 0x04, 0xDC, 0xDC, + 0xDC, 0xDC, 0x0A, 0x0A, 0x0A, 0x0A, 0x17, 0x04, 0x04, 0x17, 0x04, 0x04, + 0x17, 0x05, 0x82, 0x24, 0x03, 0x07, 0x17, 0x04, 0x04, 0x00, 0x00, 0x24, + 0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39, 0x00, 0x10, + 0x9C, 0x4B, 0x17, 0x04, 0x64, 0x01, 0x00, 0x00, 0x08, 0x4C, 0x00, 0x00, + 0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x17, 0x06, 0x85, 0x60, 0x17, + 0x10, 0x82, 0x74, 0x17, 0x08, 0x08, 0x17, 0x08, 0x88, 0x00, 0x17, 0x04, + 0x10, 0x04, 0x17, 0x0B, 0x87, 0x6C, 0x01, 0x00, 0x02, 0x02, 0x01, 0x02, + 0x03, 0x00, 0x04, 0x05, 0xC3, 0x71, 0x0F, 0x0F, 0x17, 0x08, 0x8B, 0x18, + 0x1F, 0x17, 0x09, 0x81, 0x73, 0x00, 0xFF, 0x00, 0xFF, 0x17, 0x05, 0x86, + 0x48, 0x17, 0x04, 0x0C, 0x17, 0x07, 0x86, 0x34, 0x00, 0x00, 0xF0, 0x17, + 0x09, 0x87, 0x54, 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x17, 0x0C, 0x81, + 0x52, 0x17, 0x0A, 0x1C, 0x17, 0x10, 0x81, 0x6C, 0x17, 0x0A, 0x82, 0x21, + 0x17, 0x07, 0x82, 0x4D, 0x17, 0x0A, 0x8A, 0x1B, 0x17, 0x11, 0x2C, 0x76, + 0x0C, 0x17, 0x0A, 0x8A, 0x67, 0x17, 0x0F, 0x84, 0x28, 0x17, 0x06, 0x34, + 0x17, 0x17, 0x3A, 0x7E, 0x16, 0x40, 0x17, 0x0C, 0x8B, 0x1F, 0x17, 0x2A, + 0x38, 0x1E, 0x17, 0x0A, 0x38, 0x17, 0x13, 0x81, 0x28, 0x00, 0xC0, 0x17, + 0x17, 0x55, 0x46, 0x24, 0x17, 0x0A, 0x81, 0x28, 0x17, 0x14, 0x38, 0x17, + 0x18, 0x81, 0x60, 0x46, 0x2C, 0x17, 0x06, 0x38, 0xEC, 0x17, 0x0D, 0x16, + 0x17, 0x0E, 0x82, 0x3C, 0x17, 0x82, 0x0C, 0x8E, 0x68, 0x17, 0x04, 0x24, + 0x17, 0x5C, 0x8E, 0x68, 0x17, 0x07, 0x82, 0x5F, 0x80, 0x17, 0x87, 0x01, + 0x8E, 0x68, 0x02, 0x17, 0x81, 0x4A, 0x8E, 0x68, 0x17, 0x0C, 0x87, 0x78, + 0x17, 0x85, 0x28, 0x8E, 0x68, 0x17, 0x8E, 0x68, 0x9D, 0x50, 0x17, 0x81, + 0x24, 0x8E, 0x68, 0x17, 0x04, 0x2C, 0x17, 0x28, 0x8E, 0x68, 0x17, 0x04, + 0x30, 0x17, 0x85, 0x3C, 0x8E, 0x68, 0x12, 0x17, 0x07, 0x85, 0x70, 0x17, + 0x88, 0x74, 0x8E, 0x68, 0x17, 0x87, 0x3E, 0x9D, 0x50, 0x0C, 0x17, 0x04, + 0x04, 0x17, 0x12, 0x8E, 0x68, 0x18, 0x17, 0x87, 0x12, 0xBB, 0x20, 0x17, + 0x83, 0x04, 0x9D, 0x50, 0x15, 0x17, 0x05, 0x8D, 0x76, 0x17, 0x0F, 0x8B, + 0x49, 0x17, 0x0B, 0x18, 0x32, 0x00, 0x2F, 0x00, 0x32, 0x00, 0x31, 0x00, + 0x34, 0x00, 0x36, 0x00, 0x2F, 0x00, 0x33, 0x17, 0x09, 0x84, 0x0C, 0x17, + 0x18, 0x18, 0x17, 0x20, 0x8E, 0x68, 0x15, 0x17, 0x07, 0x5A, 0x17, 0x06, + 0x5E, 0x16, 0x00, 0x15, 0x17, 0x82, 0x40, 0x9D, 0x50, 0x17, 0x86, 0x5F, + 0xBB, 0x20, 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x17, 0x81, 0x4F, 0xAC, 0x38, + 0x3B, 0x17, 0x04, 0x04, 0x17, 0x86, 0x30, 0x8E, 0x68, 0x17, 0x81, 0x53, + 0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10, + 0x8E, 0x68 +}; diff --git a/fusee/fusee-primary/src/sdram_param_t210.h b/fusee/fusee-primary/src/sdram_param_t210.h new file mode 100644 index 000000000..328ee5109 --- /dev/null +++ b/fusee/fusee-primary/src/sdram_param_t210.h @@ -0,0 +1,933 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. + */ + +#ifndef _SDRAM_PARAM_T210_H_ +#define _SDRAM_PARAM_T210_H_ + +#include + +#define MEMORY_TYPE_NONE 0 +#define MEMORY_TYPE_DDR 0 +#define MEMORY_TYPE_LPDDR 0 +#define MEMORY_TYPE_DDR2 0 +#define MEMORY_TYPE_LPDDR2 1 +#define MEMORY_TYPE_DDR3 2 +#define MEMORY_TYPE_LPDDR4 3 + +/** + * Defines the SDRAM parameter structure + */ +typedef struct _sdram_params +{ + /* Specifies the type of memory device */ + uint32_t memory_type; + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + uint32_t pllm_input_divider; + /* Specifies the N value for PllM */ + uint32_t pllm_feedback_divider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t pllm_stable_time; + /* Specifies misc. control bits */ + uint32_t pllm_setup_control; + /* Specifies the P value for PLLM */ + uint32_t pllm_post_divider; + /* Specifies value for Charge Pump Gain Control */ + uint32_t pllm_kcp; + /* Specifies VCO gain */ + uint32_t pllm_kvco; + /* Spare BCT param */ + uint32_t emc_bct_spare0; + /* Spare BCT param */ + uint32_t emc_bct_spare1; + /* Spare BCT param */ + uint32_t emc_bct_spare2; + /* Spare BCT param */ + uint32_t emc_bct_spare3; + /* Spare BCT param */ + uint32_t emc_bct_spare4; + /* Spare BCT param */ + uint32_t emc_bct_spare5; + /* Spare BCT param */ + uint32_t emc_bct_spare6; + /* Spare BCT param */ + uint32_t emc_bct_spare7; + /* Spare BCT param */ + uint32_t emc_bct_spare8; + /* Spare BCT param */ + uint32_t emc_bct_spare9; + /* Spare BCT param */ + uint32_t emc_bct_spare10; + /* Spare BCT param */ + uint32_t emc_bct_spare11; + /* Spare BCT param */ + uint32_t emc_bct_spare12; + /* Spare BCT param */ + uint32_t emc_bct_spare13; + + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + uint32_t emc_clock_source; + uint32_t emc_clock_source_dll; + + /* Defines possible override for PLLLM_MISC2 */ + uint32_t clk_rst_pllm_misc20_override; + /* enables override for PLLLM_MISC2 */ + uint32_t clk_rst_pllm_misc20_override_enable; + /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ + uint32_t clear_clock2_mc1; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t emc_auto_cal_interval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t emc_auto_cal_config; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t emc_auto_cal_config2; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t emc_auto_cal_config3; + + uint32_t emc_auto_cal_config4; + uint32_t emc_auto_cal_config5; + uint32_t emc_auto_cal_config6; + uint32_t emc_auto_cal_config7; + uint32_t emc_auto_cal_config8; + /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ + uint32_t emc_auto_cal_vref_sel0; + uint32_t emc_auto_cal_vref_sel1; + + /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ + uint32_t emc_auto_cal_channel; + + /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ + uint32_t emc_pmacro_auto_cal_cfg0; + uint32_t emc_pmacro_auto_cal_cfg1; + uint32_t emc_pmacro_auto_cal_cfg2; + + uint32_t emc_pmacro_rx_term; + uint32_t emc_pmacro_dq_tx_drive; + uint32_t emc_pmacro_ca_tx_drive; + uint32_t emc_pmacro_cmd_tx_drive; + uint32_t emc_pmacro_auto_cal_common; + uint32_t emc_pmacro_zcrtl; + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t emc_auto_cal_wait; + + uint32_t emc_xm2_comp_pad_ctrl; + uint32_t emc_xm2_comp_pad_ctrl2; + uint32_t emc_xm2_comp_pad_ctrl3; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t emc_adr_cfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t emc_pin_program_wait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t emc_pin_extra_wait; + + uint32_t emc_pin_gpio_enable; + uint32_t emc_pin_gpio; + + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t emc_timing_control_wait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t emc_rc; + /* Specifies the value for EMC_RFC */ + uint32_t emc_rfc; + + uint32_t emc_rfc_pb; + uint32_t emc_ref_ctrl2; + + /* Specifies the value for EMC_RFC_SLR */ + uint32_t emc_rfc_slr; + /* Specifies the value for EMC_RAS */ + uint32_t emc_ras; + /* Specifies the value for EMC_RP */ + uint32_t emc_rp; + /* Specifies the value for EMC_R2R */ + uint32_t emc_r2r; + /* Specifies the value for EMC_W2W */ + uint32_t emc_w2w; + /* Specifies the value for EMC_R2W */ + uint32_t emc_r2w; + /* Specifies the value for EMC_W2R */ + uint32_t emc_w2r; + /* Specifies the value for EMC_R2P */ + uint32_t emc_r2p; + /* Specifies the value for EMC_W2P */ + uint32_t emc_w2p; + /* Specifies the value for EMC_RD_RCD */ + + uint32_t emc_tppd; + uint32_t emc_ccdmw; + + uint32_t emc_rd_rcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t emc_wr_rcd; + /* Specifies the value for EMC_RRD */ + uint32_t emc_rrd; + /* Specifies the value for EMC_REXT */ + uint32_t emc_rext; + /* Specifies the value for EMC_WEXT */ + uint32_t emc_wext; + /* Specifies the value for EMC_WDV */ + uint32_t emc_wdv; + + uint32_t emc_wdv_chk; + uint32_t emc_wsv; + uint32_t emc_wev; + + /* Specifies the value for EMC_WDV_MASK */ + uint32_t emc_wdv_mask; + + uint32_t emc_ws_duration; + uint32_t emc_we_duration; + + /* Specifies the value for EMC_QUSE */ + uint32_t emc_quse; + /* Specifies the value for EMC_QUSE_WIDTH */ + uint32_t emc_quse_width; + /* Specifies the value for EMC_IBDLY */ + uint32_t emc_ibdly; + + uint32_t emc_obdly; + + /* Specifies the value for EMC_EINPUT */ + uint32_t emc_einput; + /* Specifies the value for EMC_EINPUT_DURATION */ + uint32_t emc_einput_duration; + /* Specifies the value for EMC_PUTERM_EXTRA */ + uint32_t emc_puterm_extra; + /* Specifies the value for EMC_PUTERM_WIDTH */ + uint32_t emc_puterm_width; + + uint32_t emc_qrst; + uint32_t emc_qsafe; + uint32_t emc_rdv; + uint32_t emc_rdv_mask; + + uint32_t emc_rdv_early; + uint32_t emc_rdv_early_mask; + + /* Specifies the value for EMC_QPOP */ + uint32_t emc_qpop; + + /* Specifies the value for EMC_REFRESH */ + uint32_t emc_refresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t emc_burst_refresh_num; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t emc_prerefresh_req_cnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t emc_pdex2wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t emc_pdex2rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t emc_pchg2pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t emc_act2pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t emc_ar2pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t emc_rw2pden; + + uint32_t emc_cke2pden; + uint32_t emc_pdex2che; + uint32_t emc_pdex2mrr; + + /* Specifies the value for EMC_TXSR */ + uint32_t emc_txsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t emc_txsr_dll; + /* Specifies the value for EMC_TCKE */ + uint32_t emc_tcke; + /* Specifies the value for EMC_TCKESR */ + uint32_t emc_tckesr; + /* Specifies the value for EMC_TPD */ + uint32_t emc_tpd; + /* Specifies the value for EMC_TFAW */ + uint32_t emc_tfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t emc_trpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t emc_tclkstable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t emc_tclkstop; + /* Specifies the value for EMC_TREFBW */ + uint32_t emc_trefbw; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t emc_fbio_cfg5; + /* Specifies the value for EMC_FBIO_CFG7 */ + uint32_t emc_fbio_cfg7; + uint32_t emc_fbio_cfg8; + + /* Command mapping for CMD brick 0 */ + uint32_t emc_cmd_mapping_cmd0_0; + uint32_t emc_cmd_mapping_cmd0_1; + uint32_t emc_cmd_mapping_cmd0_2; + uint32_t emc_cmd_mapping_cmd1_0; + uint32_t emc_cmd_mapping_cmd1_1; + uint32_t emc_cmd_mapping_cmd1_2; + uint32_t emc_cmd_mapping_cmd2_0; + uint32_t emc_cmd_mapping_cmd2_1; + uint32_t emc_cmd_mapping_cmd2_2; + uint32_t emc_cmd_mapping_cmd3_0; + uint32_t emc_cmd_mapping_cmd3_1; + uint32_t emc_cmd_mapping_cmd3_2; + uint32_t emc_cmd_mapping_byte; + + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t emc_fbio_spare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t emc_cfg_rsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t emc_mrs; + /* Specifies the MP0 command to initialize mode registers */ + uint32_t emc_emrs; + /* Specifies the MP2 command to initialize mode registers */ + uint32_t emc_emrs2; + /* Specifies the MP3 command to initialize mode registers */ + uint32_t emc_emrs3; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t emc_mrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t emc_mrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t emc_mrw3; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t emc_mrw4; + + /* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */ + uint32_t emc_mrw6; + /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ + uint32_t emc_mrw8; + /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ + uint32_t emc_mrw9; + /* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */ + uint32_t emc_mrw10; + /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ + uint32_t emc_mrw12; + /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ + uint32_t emc_mrw13; + /* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */ + uint32_t emc_mrw14; + + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t emc_mrw_extra; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t emc_warm_boot_mrw_extra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t emc_warm_boot_extramode_reg_write_enable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t emc_extramode_reg_write_enable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t emc_mrw_reset_command; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t emc_mrw_reset_ninit_wait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t emc_mrs_wait_cnt; + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + uint32_t emc_mrs_wait_cnt2; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t emc_cfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t emc_cfg2; + /* Specifies the pipe bypass controls */ + uint32_t emc_cfg_pipe; + + uint32_t emc_cfg_pipe_clk; + uint32_t emc_fdpd_ctrl_cmd_no_ramp; + uint32_t emc_cfg_update; + + /* Specifies the value for EMC_DBG */ + uint32_t emc_dbg; + + uint32_t emc_dbg_write_mux; + + /* Specifies the value for EMC_CMDQ */ + uint32_t emc_cmd_q; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t emc_mc2emc_q; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t emc_dyn_self_ref_control; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t ahb_arbitration_xbar_ctrl_meminit_done; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll_1; + + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t emc_cfg_dig_dll_period; + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + uint32_t emc_dev_select; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t emc_sel_dpd_ctrl; + + /* Pads trimmer delays */ + uint32_t emc_fdpd_ctrl_dq; + uint32_t emc_fdpd_ctrl_cmd; + uint32_t emc_pmacro_ib_vref_dq_0; + uint32_t emc_pmacro_ib_vref_dq_1; + uint32_t emc_pmacro_ib_vref_dqs_0; + uint32_t emc_pmacro_ib_vref_dqs_1; + uint32_t emc_pmacro_ib_rxrt; + uint32_t emc_cfg_pipe1; + uint32_t emc_cfg_pipe2; + + /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ + uint32_t emc_pmacro_quse_ddll_rank0_0; + uint32_t emc_pmacro_quse_ddll_rank0_1; + uint32_t emc_pmacro_quse_ddll_rank0_2; + uint32_t emc_pmacro_quse_ddll_rank0_3; + uint32_t emc_pmacro_quse_ddll_rank0_4; + uint32_t emc_pmacro_quse_ddll_rank0_5; + uint32_t emc_pmacro_quse_ddll_rank1_0; + uint32_t emc_pmacro_quse_ddll_rank1_1; + uint32_t emc_pmacro_quse_ddll_rank1_2; + uint32_t emc_pmacro_quse_ddll_rank1_3; + uint32_t emc_pmacro_quse_ddll_rank1_4; + uint32_t emc_pmacro_quse_ddll_rank1_5; + + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; + + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; + + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3; + + uint32_t emc_pmacro_ddll_long_cmd_0; + uint32_t emc_pmacro_ddll_long_cmd_1; + uint32_t emc_pmacro_ddll_long_cmd_2; + uint32_t emc_pmacro_ddll_long_cmd_3; + uint32_t emc_pmacro_ddll_long_cmd_4; + uint32_t emc_pmacro_ddll_short_cmd_0; + uint32_t emc_pmacro_ddll_short_cmd_1; + uint32_t emc_pmacro_ddll_short_cmd_2; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t warm_boot_wait; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t emc_odt_write; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t emc_zcal_interval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t emc_zcal_wait_cnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t emc_zcal_mrw_cmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t emc_mrs_reset_dll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t emc_zcal_init_dev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t emc_zcal_init_dev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t emc_zcal_init_wait; + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + uint32_t emc_zcal_warm_cold_boot_enables; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + uint32_t emc_mrw_lpddr2zcal_warm_boot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t emc_zqcal_ddr3_warm_boot; + + uint32_t emc_zqcal_lpddr4_warm_boot; + + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t emc_zcal_warm_boot_wait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t emc_mrs_warm_boot_enable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t emc_mrs_reset_dll_wait; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t emc_mrs_extra; + /* Specifies the extra MRS command at warm boot */ + uint32_t emc_warm_boot_mrs_extra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t emc_emrs_ddr2_dll_enable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t emc_mrs_ddr2_dll_reset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t emc_emrs_ddr2_ocd_calib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t emc_ddr2_wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t emc_clken_override; + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t emc_extra_refresh_num; + /* Specifies the master override for all EMC clocks */ + uint32_t emc_clken_override_allwarm_boot; + /* Specifies the master override for all MC clocks */ + uint32_t mc_clken_override_allwarm_boot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t emc_cfg_dig_dll_period_warm_boot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t pmc_vddp_sel; + /* Specifies the wait time after programming PMC_VDDP_SEL */ + uint32_t pmc_vddp_sel_wait; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t pmc_ddr_pwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t pmc_ddr_cfg; + /* Specifies the value for PMC_IO_DPD3_REQ */ + uint32_t pmc_io_dpd3_req; + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + uint32_t pmc_io_dpd3_req_wait; + + uint32_t pmc_io_dpd4_req_wait; + + /* Specifies the value for PMC_REG_SHORT */ + uint32_t pmc_reg_short; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t pmc_no_io_power; + + uint32_t pmc_ddr_ctrl_wait; + uint32_t pmc_ddr_ctrl; + + /* Specifies the value for EMC_ACPD_CONTROL */ + uint32_t emc_acpd_control; + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t emc_swizzle_rank0_byte0; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t emc_swizzle_rank0_byte1; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t emc_swizzle_rank0_byte2; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t emc_swizzle_rank0_byte3; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t emc_swizzle_rank1_byte0; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t emc_swizzle_rank1_byte1; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t emc_swizzle_rank1_byte2; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t emc_swizzle_rank1_byte3; + + /* Specifies the value for EMC_TXDSRVTTGEN */ + uint32_t emc_txdsrvttgen; + + /* Specifies the value for EMC_DATA_BRLSHFT_0 */ + uint32_t emc_data_brlshft0; + uint32_t emc_data_brlshft1; + + uint32_t emc_dqs_brlshft0; + uint32_t emc_dqs_brlshft1; + + uint32_t emc_cmd_brlshft0; + uint32_t emc_cmd_brlshft1; + uint32_t emc_cmd_brlshft2; + uint32_t emc_cmd_brlshft3; + + uint32_t emc_quse_brlshft0; + uint32_t emc_quse_brlshft1; + uint32_t emc_quse_brlshft2; + uint32_t emc_quse_brlshft3; + + uint32_t emc_dll_cfg0; + uint32_t emc_dll_cfg1; + + uint32_t emc_pmc_scratch1; + uint32_t emc_pmc_scratch2; + uint32_t emc_pmc_scratch3; + + uint32_t emc_pmacro_pad_cfg_ctrl; + + uint32_t emc_pmacro_vttgen_ctrl0; + uint32_t emc_pmacro_vttgen_ctrl1; + uint32_t emc_pmacro_vttgen_ctrl2; + + uint32_t emc_pmacro_brick_ctrl_rfu1; + uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; + uint32_t emc_pmacro_brick_ctrl_rfu2; + uint32_t emc_pmacro_data_brick_ctrl_fdpd; + uint32_t emc_pmacro_bg_bias_ctrl0; + uint32_t emc_pmacro_data_pad_rx_ctrl; + uint32_t emc_pmacro_cmd_pad_rx_ctrl; + uint32_t emc_pmacro_data_rx_term_mode; + uint32_t emc_pmacro_cmd_rx_term_mode; + uint32_t emc_pmacro_data_pad_tx_ctrl; + uint32_t emc_pmacro_common_pad_tx_ctrl; + uint32_t emc_pmacro_cmd_pad_tx_ctrl; + uint32_t emc_cfg3; + + uint32_t emc_pmacro_tx_pwrd0; + uint32_t emc_pmacro_tx_pwrd1; + uint32_t emc_pmacro_tx_pwrd2; + uint32_t emc_pmacro_tx_pwrd3; + uint32_t emc_pmacro_tx_pwrd4; + uint32_t emc_pmacro_tx_pwrd5; + + uint32_t emc_config_sample_delay; + + uint32_t emc_pmacro_brick_mapping0; + uint32_t emc_pmacro_brick_mapping1; + uint32_t emc_pmacro_brick_mapping2; + + uint32_t emc_pmacro_tx_sel_clk_src0; + uint32_t emc_pmacro_tx_sel_clk_src1; + uint32_t emc_pmacro_tx_sel_clk_src2; + uint32_t emc_pmacro_tx_sel_clk_src3; + uint32_t emc_pmacro_tx_sel_clk_src4; + uint32_t emc_pmacro_tx_sel_clk_src5; + + uint32_t emc_pmacro_ddll_bypass; + + uint32_t emc_pmacro_ddll_pwrd0; + uint32_t emc_pmacro_ddll_pwrd1; + uint32_t emc_pmacro_ddll_pwrd2; + + uint32_t emc_pmacro_cmd_ctrl0; + uint32_t emc_pmacro_cmd_ctrl1; + uint32_t emc_pmacro_cmd_ctrl2; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t mc_emem_adr_cfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t mc_emem_adr_cfg_dev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t mc_emem_adr_cfg_dev1; + + uint32_t mc_emem_adr_cfg_channel_mask; + + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ + uint32_t mc_emem_adr_cfg_bank_mask0; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + uint32_t mc_emem_adr_cfg_bank_mask1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + uint32_t mc_emem_adr_cfg_bank_mask2; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t mc_emem_cfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t mc_emem_arb_cfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t mc_emem_arb_outstanding_req; + + uint32_t emc_emem_arb_refpb_hp_ctrl; + uint32_t emc_emem_arb_refpb_bank_ctrl; + + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t mc_emem_arb_timing_rcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t mc_emem_arb_timing_rp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t mc_emem_arb_timing_rc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t mc_emem_arb_timing_ras; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t mc_emem_arb_timing_faw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t mc_emem_arb_timing_rrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t mc_emem_arb_timing_rap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t mc_emem_arb_timing_wap2pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t mc_emem_arb_timing_r2r; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t mc_emem_arb_timing_w2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t mc_emem_arb_timing_r2w; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t mc_emem_arb_timing_w2r; + + uint32_t mc_emem_arb_timing_rfcpb; + + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t mc_emem_arb_da_turns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t mc_emem_arb_da_covers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t mc_emem_arb_misc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t mc_emem_arb_misc1; + uint32_t mc_emem_arb_misc2; + + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t mc_emem_arb_ring1_throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t mc_emem_arb_override; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + uint32_t mc_emem_arb_override1; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t mc_emem_arb_rsv; + + uint32_t mc_da_cfg0; + uint32_t mc_emem_arb_timing_ccdmw; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t mc_clken_override; + + /* Specifies the value for MC_STAT_CONTROL */ + uint32_t mc_stat_control; + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + uint32_t mc_video_protect_bom; + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + uint32_t mc_video_protect_bom_adr_hi; + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + uint32_t mc_video_protect_size_mb; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + uint32_t mc_video_protect_vpr_override; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + uint32_t mc_video_protect_vpr_override1; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + uint32_t mc_video_protect_gpu_override0; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + uint32_t mc_video_protect_gpu_override1; + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + uint32_t mc_sec_carveout_bom; + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + uint32_t mc_sec_carveout_adr_hi; + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + uint32_t mc_sec_carveout_size_mb; + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ + uint32_t mc_video_protect_write_access; + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ + uint32_t mc_sec_carveout_protect_write_access; + + uint32_t mc_generalized_carveout1_bom; + uint32_t mc_generalized_carveout1_bom_hi; + uint32_t mc_generalized_carveout1_size_128kb; + uint32_t mc_generalized_carveout1_access0; + uint32_t mc_generalized_carveout1_access1; + uint32_t mc_generalized_carveout1_access2; + uint32_t mc_generalized_carveout1_access3; + uint32_t mc_generalized_carveout1_access4; + uint32_t mc_generalized_carveout1_force_internal_access0; + uint32_t mc_generalized_carveout1_force_internal_access1; + uint32_t mc_generalized_carveout1_force_internal_access2; + uint32_t mc_generalized_carveout1_force_internal_access3; + uint32_t mc_generalized_carveout1_force_internal_access4; + uint32_t mc_generalized_carveout1_cfg0; + + uint32_t mc_generalized_carveout2_bom; + uint32_t mc_generalized_carveout2_bom_hi; + uint32_t mc_generalized_carveout2_size_128kb; + uint32_t mc_generalized_carveout2_access0; + uint32_t mc_generalized_carveout2_access1; + uint32_t mc_generalized_carveout2_access2; + uint32_t mc_generalized_carveout2_access3; + uint32_t mc_generalized_carveout2_access4; + uint32_t mc_generalized_carveout2_force_internal_access0; + uint32_t mc_generalized_carveout2_force_internal_access1; + uint32_t mc_generalized_carveout2_force_internal_access2; + uint32_t mc_generalized_carveout2_force_internal_access3; + uint32_t mc_generalized_carveout2_force_internal_access4; + uint32_t mc_generalized_carveout2_cfg0; + + uint32_t mc_generalized_carveout3_bom; + uint32_t mc_generalized_carveout3_bom_hi; + uint32_t mc_generalized_carveout3_size_128kb; + uint32_t mc_generalized_carveout3_access0; + uint32_t mc_generalized_carveout3_access1; + uint32_t mc_generalized_carveout3_access2; + uint32_t mc_generalized_carveout3_access3; + uint32_t mc_generalized_carveout3_access4; + uint32_t mc_generalized_carveout3_force_internal_access0; + uint32_t mc_generalized_carveout3_force_internal_access1; + uint32_t mc_generalized_carveout3_force_internal_access2; + uint32_t mc_generalized_carveout3_force_internal_access3; + uint32_t mc_generalized_carveout3_force_internal_access4; + uint32_t mc_generalized_carveout3_cfg0; + + uint32_t mc_generalized_carveout4_bom; + uint32_t mc_generalized_carveout4_bom_hi; + uint32_t mc_generalized_carveout4_size_128kb; + uint32_t mc_generalized_carveout4_access0; + uint32_t mc_generalized_carveout4_access1; + uint32_t mc_generalized_carveout4_access2; + uint32_t mc_generalized_carveout4_access3; + uint32_t mc_generalized_carveout4_access4; + uint32_t mc_generalized_carveout4_force_internal_access0; + uint32_t mc_generalized_carveout4_force_internal_access1; + uint32_t mc_generalized_carveout4_force_internal_access2; + uint32_t mc_generalized_carveout4_force_internal_access3; + uint32_t mc_generalized_carveout4_force_internal_access4; + uint32_t mc_generalized_carveout4_cfg0; + + uint32_t mc_generalized_carveout5_bom; + uint32_t mc_generalized_carveout5_bom_hi; + uint32_t mc_generalized_carveout5_size_128kb; + uint32_t mc_generalized_carveout5_access0; + uint32_t mc_generalized_carveout5_access1; + uint32_t mc_generalized_carveout5_access2; + uint32_t mc_generalized_carveout5_access3; + uint32_t mc_generalized_carveout5_access4; + uint32_t mc_generalized_carveout5_force_internal_access0; + uint32_t mc_generalized_carveout5_force_internal_access1; + uint32_t mc_generalized_carveout5_force_internal_access2; + uint32_t mc_generalized_carveout5_force_internal_access3; + uint32_t mc_generalized_carveout5_force_internal_access4; + uint32_t mc_generalized_carveout5_cfg0; + + /* Specifies enable for CA training */ + uint32_t emc_ca_training_enable; + /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ + uint32_t swizzle_rank_byte_encode; + /* Specifies enable and offset for patched boot rom write */ + uint32_t boot_rom_patch_control; + /* Specifies data for patched boot rom write */ + uint32_t boot_rom_patch_data; + + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + uint32_t mc_mts_carveout_bom; + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + uint32_t mc_mts_carveout_adr_hi; + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + uint32_t mc_mts_carveout_size_mb; + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + uint32_t mc_mts_carveout_reg_ctrl; +} sdram_params_t; + +#endif diff --git a/fusee/fusee-primary/src/sdram_param_t210_lp0.h b/fusee/fusee-primary/src/sdram_param_t210_lp0.h new file mode 100644 index 000000000..6702ea2c9 --- /dev/null +++ b/fusee/fusee-primary/src/sdram_param_t210_lp0.h @@ -0,0 +1,964 @@ +/* + * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * Copyright (C) 2018 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. The field names are in camel case to ease + * directly converting BCT config files (*.cfg) into C structure. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ +#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ + +#include + +enum +{ + /* Specifies the memory type to be undefined */ + NvBootMemoryType_None = 0, + + /* Specifies the memory type to be DDR SDRAM */ + NvBootMemoryType_Ddr = 0, + + /* Specifies the memory type to be LPDDR SDRAM */ + NvBootMemoryType_LpDdr = 0, + + /* Specifies the memory type to be DDR2 SDRAM */ + NvBootMemoryType_Ddr2 = 0, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + NvBootMemoryType_LpDdr2, + + /* Specifies the memory type to be DDR3 SDRAM */ + NvBootMemoryType_Ddr3, + + /* Specifies the memory type to be LPDDR4 SDRAM */ + NvBootMemoryType_LpDdr4, + + NvBootMemoryType_Num, + + /* Specifies an entry in the ram_code table that's not in use */ + NvBootMemoryType_Unused = 0X7FFFFFF, +}; + +/** + * Defines the SDRAM parameter structure + */ +struct sdram_params +{ + + /* Specifies the type of memory device */ + uint32_t MemoryType; + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + uint32_t PllMInputDivider; + /* Specifies the N value for PllM */ + uint32_t PllMFeedbackDivider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t PllMStableTime; + /* Specifies misc. control bits */ + uint32_t PllMSetupControl; + /* Specifies the P value for PLLM */ + uint32_t PllMPostDivider; + /* Specifies value for Charge Pump Gain Control */ + uint32_t PllMKCP; + /* Specifies VCO gain */ + uint32_t PllMKVCO; + /* Spare BCT param */ + uint32_t EmcBctSpare0; + /* Spare BCT param */ + uint32_t EmcBctSpare1; + /* Spare BCT param */ + uint32_t EmcBctSpare2; + /* Spare BCT param */ + uint32_t EmcBctSpare3; + /* Spare BCT param */ + uint32_t EmcBctSpare4; + /* Spare BCT param */ + uint32_t EmcBctSpare5; + /* Spare BCT param */ + uint32_t EmcBctSpare6; + /* Spare BCT param */ + uint32_t EmcBctSpare7; + /* Spare BCT param */ + uint32_t EmcBctSpare8; + /* Spare BCT param */ + uint32_t EmcBctSpare9; + /* Spare BCT param */ + uint32_t EmcBctSpare10; + /* Spare BCT param */ + uint32_t EmcBctSpare11; + /* Spare BCT param */ + uint32_t EmcBctSpare12; + /* Spare BCT param */ + uint32_t EmcBctSpare13; + + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + uint32_t EmcClockSource; + uint32_t EmcClockSourceDll; + + /* Defines possible override for PLLLM_MISC2 */ + uint32_t ClkRstControllerPllmMisc2Override; + /* enables override for PLLLM_MISC2 */ + uint32_t ClkRstControllerPllmMisc2OverrideEnable; + /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ + uint32_t ClearClk2Mc1; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t EmcAutoCalInterval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t EmcAutoCalConfig; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t EmcAutoCalConfig2; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t EmcAutoCalConfig3; + + /* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */ + uint32_t EmcAutoCalConfig4; + uint32_t EmcAutoCalConfig5; + uint32_t EmcAutoCalConfig6; + uint32_t EmcAutoCalConfig7; + uint32_t EmcAutoCalConfig8; + + /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ + uint32_t EmcAutoCalVrefSel0; + uint32_t EmcAutoCalVrefSel1; + + /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ + uint32_t EmcAutoCalChannel; + + /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ + uint32_t EmcPmacroAutocalCfg0; + uint32_t EmcPmacroAutocalCfg1; + uint32_t EmcPmacroAutocalCfg2; + uint32_t EmcPmacroRxTerm; + uint32_t EmcPmacroDqTxDrv; + uint32_t EmcPmacroCaTxDrv; + uint32_t EmcPmacroCmdTxDrv; + uint32_t EmcPmacroAutocalCfgCommon; + uint32_t EmcPmacroZctrl; + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t EmcAutoCalWait; + + uint32_t EmcXm2CompPadCtrl; + uint32_t EmcXm2CompPadCtrl2; + uint32_t EmcXm2CompPadCtrl3; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t EmcAdrCfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t EmcPinProgramWait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t EmcPinExtraWait; + + uint32_t EmcPinGpioEn; + uint32_t EmcPinGpio; + + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t EmcTimingControlWait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t EmcRc; + /* Specifies the value for EMC_RFC */ + uint32_t EmcRfc; + /* Specifies the value for EMC_RFC_PB */ + uint32_t EmcRfcPb; + /* Specifies the value for EMC_RFC_CTRL2 */ + uint32_t EmcRefctrl2; + /* Specifies the value for EMC_RFC_SLR */ + uint32_t EmcRfcSlr; + /* Specifies the value for EMC_RAS */ + uint32_t EmcRas; + /* Specifies the value for EMC_RP */ + uint32_t EmcRp; + /* Specifies the value for EMC_R2R */ + uint32_t EmcR2r; + /* Specifies the value for EMC_W2W */ + uint32_t EmcW2w; + /* Specifies the value for EMC_R2W */ + uint32_t EmcR2w; + /* Specifies the value for EMC_W2R */ + uint32_t EmcW2r; + /* Specifies the value for EMC_R2P */ + uint32_t EmcR2p; + /* Specifies the value for EMC_W2P */ + uint32_t EmcW2p; + + uint32_t EmcTppd; + uint32_t EmcCcdmw; + + /* Specifies the value for EMC_RD_RCD */ + uint32_t EmcRdRcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t EmcWrRcd; + /* Specifies the value for EMC_RRD */ + uint32_t EmcRrd; + /* Specifies the value for EMC_REXT */ + uint32_t EmcRext; + /* Specifies the value for EMC_WEXT */ + uint32_t EmcWext; + /* Specifies the value for EMC_WDV */ + uint32_t EmcWdv; + + uint32_t EmcWdvChk; + uint32_t EmcWsv; + uint32_t EmcWev; + + /* Specifies the value for EMC_WDV_MASK */ + uint32_t EmcWdvMask; + + uint32_t EmcWsDuration; + uint32_t EmcWeDuration; + + /* Specifies the value for EMC_QUSE */ + uint32_t EmcQUse; + /* Specifies the value for EMC_QUSE_WIDTH */ + uint32_t EmcQuseWidth; + /* Specifies the value for EMC_IBDLY */ + uint32_t EmcIbdly; + /* Specifies the value for EMC_OBDLY */ + uint32_t EmcObdly; + /* Specifies the value for EMC_EINPUT */ + uint32_t EmcEInput; + /* Specifies the value for EMC_EINPUT_DURATION */ + uint32_t EmcEInputDuration; + /* Specifies the value for EMC_PUTERM_EXTRA */ + uint32_t EmcPutermExtra; + /* Specifies the value for EMC_PUTERM_WIDTH */ + uint32_t EmcPutermWidth; + /* Specifies the value for EMC_PUTERM_ADJ */ + ////uint32_t EmcPutermAdj; + + /* Specifies the value for EMC_QRST */ + uint32_t EmcQRst; + /* Specifies the value for EMC_QSAFE */ + uint32_t EmcQSafe; + /* Specifies the value for EMC_RDV */ + uint32_t EmcRdv; + /* Specifies the value for EMC_RDV_MASK */ + uint32_t EmcRdvMask; + /* Specifies the value for EMC_RDV_EARLY */ + uint32_t EmcRdvEarly; + /* Specifies the value for EMC_RDV_EARLY_MASK */ + uint32_t EmcRdvEarlyMask; + /* Specifies the value for EMC_QPOP */ + uint32_t EmcQpop; + + /* Specifies the value for EMC_REFRESH */ + uint32_t EmcRefresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t EmcBurstRefreshNum; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t EmcPreRefreshReqCnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t EmcPdEx2Wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t EmcPdEx2Rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t EmcPChg2Pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t EmcAct2Pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t EmcAr2Pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t EmcRw2Pden; + /* Specifies the value for EMC_CKE2PDEN */ + uint32_t EmcCke2Pden; + /* Specifies the value for EMC_PDEX2CKE */ + uint32_t EmcPdex2Cke; + /* Specifies the value for EMC_PDEX2MRR */ + uint32_t EmcPdex2Mrr; + /* Specifies the value for EMC_TXSR */ + uint32_t EmcTxsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t EmcTxsrDll; + /* Specifies the value for EMC_TCKE */ + uint32_t EmcTcke; + /* Specifies the value for EMC_TCKESR */ + uint32_t EmcTckesr; + /* Specifies the value for EMC_TPD */ + uint32_t EmcTpd; + /* Specifies the value for EMC_TFAW */ + uint32_t EmcTfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t EmcTrpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t EmcTClkStable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t EmcTClkStop; + /* Specifies the value for EMC_TREFBW */ + uint32_t EmcTRefBw; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t EmcFbioCfg5; + /* Specifies the value for EMC_FBIO_CFG7 */ + uint32_t EmcFbioCfg7; + /* Specifies the value for EMC_FBIO_CFG8 */ + uint32_t EmcFbioCfg8; + + /* Command mapping for CMD brick 0 */ + uint32_t EmcCmdMappingCmd0_0; + uint32_t EmcCmdMappingCmd0_1; + uint32_t EmcCmdMappingCmd0_2; + uint32_t EmcCmdMappingCmd1_0; + uint32_t EmcCmdMappingCmd1_1; + uint32_t EmcCmdMappingCmd1_2; + uint32_t EmcCmdMappingCmd2_0; + uint32_t EmcCmdMappingCmd2_1; + uint32_t EmcCmdMappingCmd2_2; + uint32_t EmcCmdMappingCmd3_0; + uint32_t EmcCmdMappingCmd3_1; + uint32_t EmcCmdMappingCmd3_2; + uint32_t EmcCmdMappingByte; + + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t EmcFbioSpare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t EmcCfgRsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t EmcMrs; + /* Specifies the MP0 command to initialize mode registers */ + uint32_t EmcEmrs; + /* Specifies the MP2 command to initialize mode registers */ + uint32_t EmcEmrs2; + /* Specifies the MP3 command to initialize mode registers */ + uint32_t EmcEmrs3; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t EmcMrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t EmcMrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t EmcMrw3; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t EmcMrw4; + /* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */ + uint32_t EmcMrw6; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t EmcMrw8; + /* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */ + uint32_t EmcMrw9; + /* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */ + uint32_t EmcMrw10; + /* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */ + uint32_t EmcMrw12; + /* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */ + uint32_t EmcMrw13; + /* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */ + uint32_t EmcMrw14; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t EmcMrwExtra; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t EmcWarmBootMrwExtra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t EmcWarmBootExtraModeRegWriteEnable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t EmcExtraModeRegWriteEnable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t EmcMrwResetCommand; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t EmcMrwResetNInitWait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t EmcMrsWaitCnt; + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + uint32_t EmcMrsWaitCnt2; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t EmcCfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t EmcCfg2; + /* Specifies the pipe bypass controls */ + uint32_t EmcCfgPipe; + uint32_t EmcCfgPipeClk; + uint32_t EmcFdpdCtrlCmdNoRamp; + uint32_t EmcCfgUpdate; + + /* Specifies the value for EMC_DBG */ + uint32_t EmcDbg; + uint32_t EmcDbgWriteMux; + + /* Specifies the value for EMC_CMDQ */ + uint32_t EmcCmdQ; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t EmcMc2EmcQ; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t EmcDynSelfRefControl; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t AhbArbitrationXbarCtrlMemInitDone; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t EmcCfgDigDll; + uint32_t EmcCfgDigDll_1; + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t EmcCfgDigDllPeriod; + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + uint32_t EmcDevSelect; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t EmcSelDpdCtrl; + + /* Pads trimmer delays */ + uint32_t EmcFdpdCtrlDq; + uint32_t EmcFdpdCtrlCmd; + uint32_t EmcPmacroIbVrefDq_0; + uint32_t EmcPmacroIbVrefDq_1; + uint32_t EmcPmacroIbVrefDqs_0; + uint32_t EmcPmacroIbVrefDqs_1; + uint32_t EmcPmacroIbRxrt; + uint32_t EmcCfgPipe1; + uint32_t EmcCfgPipe2; + + /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ + uint32_t EmcPmacroQuseDdllRank0_0; + uint32_t EmcPmacroQuseDdllRank0_1; + uint32_t EmcPmacroQuseDdllRank0_2; + uint32_t EmcPmacroQuseDdllRank0_3; + uint32_t EmcPmacroQuseDdllRank0_4; + uint32_t EmcPmacroQuseDdllRank0_5; + uint32_t EmcPmacroQuseDdllRank1_0; + uint32_t EmcPmacroQuseDdllRank1_1; + uint32_t EmcPmacroQuseDdllRank1_2; + uint32_t EmcPmacroQuseDdllRank1_3; + uint32_t EmcPmacroQuseDdllRank1_4; + uint32_t EmcPmacroQuseDdllRank1_5; + + uint32_t EmcPmacroObDdllLongDqRank0_0; + uint32_t EmcPmacroObDdllLongDqRank0_1; + uint32_t EmcPmacroObDdllLongDqRank0_2; + uint32_t EmcPmacroObDdllLongDqRank0_3; + uint32_t EmcPmacroObDdllLongDqRank0_4; + uint32_t EmcPmacroObDdllLongDqRank0_5; + uint32_t EmcPmacroObDdllLongDqRank1_0; + uint32_t EmcPmacroObDdllLongDqRank1_1; + uint32_t EmcPmacroObDdllLongDqRank1_2; + uint32_t EmcPmacroObDdllLongDqRank1_3; + uint32_t EmcPmacroObDdllLongDqRank1_4; + uint32_t EmcPmacroObDdllLongDqRank1_5; + + uint32_t EmcPmacroObDdllLongDqsRank0_0; + uint32_t EmcPmacroObDdllLongDqsRank0_1; + uint32_t EmcPmacroObDdllLongDqsRank0_2; + uint32_t EmcPmacroObDdllLongDqsRank0_3; + uint32_t EmcPmacroObDdllLongDqsRank0_4; + uint32_t EmcPmacroObDdllLongDqsRank0_5; + uint32_t EmcPmacroObDdllLongDqsRank1_0; + uint32_t EmcPmacroObDdllLongDqsRank1_1; + uint32_t EmcPmacroObDdllLongDqsRank1_2; + uint32_t EmcPmacroObDdllLongDqsRank1_3; + uint32_t EmcPmacroObDdllLongDqsRank1_4; + uint32_t EmcPmacroObDdllLongDqsRank1_5; + + uint32_t EmcPmacroIbDdllLongDqsRank0_0; + uint32_t EmcPmacroIbDdllLongDqsRank0_1; + uint32_t EmcPmacroIbDdllLongDqsRank0_2; + uint32_t EmcPmacroIbDdllLongDqsRank0_3; + uint32_t EmcPmacroIbDdllLongDqsRank1_0; + uint32_t EmcPmacroIbDdllLongDqsRank1_1; + uint32_t EmcPmacroIbDdllLongDqsRank1_2; + uint32_t EmcPmacroIbDdllLongDqsRank1_3; + + uint32_t EmcPmacroDdllLongCmd_0; + uint32_t EmcPmacroDdllLongCmd_1; + uint32_t EmcPmacroDdllLongCmd_2; + uint32_t EmcPmacroDdllLongCmd_3; + uint32_t EmcPmacroDdllLongCmd_4; + uint32_t EmcPmacroDdllShortCmd_0; + uint32_t EmcPmacroDdllShortCmd_1; + uint32_t EmcPmacroDdllShortCmd_2; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t WarmBootWait; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t EmcOdtWrite; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t EmcZcalInterval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t EmcZcalWaitCnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t EmcZcalMrwCmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t EmcMrsResetDll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t EmcZcalInitDev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t EmcZcalInitDev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t EmcZcalInitWait; + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + uint32_t EmcZcalWarmColdBootEnables; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + uint32_t EmcMrwLpddr2ZcalWarmBoot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t EmcZqCalDdr3WarmBoot; + uint32_t EmcZqCalLpDdr4WarmBoot; + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t EmcZcalWarmBootWait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t EmcMrsWarmBootEnable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t EmcMrsResetDllWait; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t EmcMrsExtra; + /* Specifies the extra MRS command at warm boot */ + uint32_t EmcWarmBootMrsExtra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t EmcEmrsDdr2DllEnable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t EmcMrsDdr2DllReset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t EmcEmrsDdr2OcdCalib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t EmcDdr2Wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t EmcClkenOverride; + + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t EmcExtraRefreshNum; + /* Specifies the master override for all EMC clocks */ + uint32_t EmcClkenOverrideAllWarmBoot; + /* Specifies the master override for all MC clocks */ + uint32_t McClkenOverrideAllWarmBoot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t EmcCfgDigDllPeriodWarmBoot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t PmcVddpSel; + /* Specifies the wait time after programming PMC_VDDP_SEL */ + uint32_t PmcVddpSelWait; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t PmcDdrPwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t PmcDdrCfg; + /* Specifies the value for PMC_IO_DPD3_REQ */ + uint32_t PmcIoDpd3Req; + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + uint32_t PmcIoDpd3ReqWait; + uint32_t PmcIoDpd4ReqWait; + + /* Specifies the value for PMC_REG_SHORT */ + uint32_t PmcRegShort; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t PmcNoIoPower; + + uint32_t PmcDdrCntrlWait; + uint32_t PmcDdrCntrl; + + /* Specifies the value for EMC_ACPD_CONTROL */ + uint32_t EmcAcpdControl; + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ + ////uint32_t EmcSwizzleRank0ByteCfg; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t EmcSwizzleRank0Byte0; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t EmcSwizzleRank0Byte1; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t EmcSwizzleRank0Byte2; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t EmcSwizzleRank0Byte3; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ + ////uint32_t EmcSwizzleRank1ByteCfg; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t EmcSwizzleRank1Byte0; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t EmcSwizzleRank1Byte1; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t EmcSwizzleRank1Byte2; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t EmcSwizzleRank1Byte3; + + /* Specifies the value for EMC_TXDSRVTTGEN */ + uint32_t EmcTxdsrvttgen; + + /* Specifies the value for EMC_DATA_BRLSHFT_0 */ + uint32_t EmcDataBrlshft0; + uint32_t EmcDataBrlshft1; + + uint32_t EmcDqsBrlshft0; + uint32_t EmcDqsBrlshft1; + + uint32_t EmcCmdBrlshft0; + uint32_t EmcCmdBrlshft1; + uint32_t EmcCmdBrlshft2; + uint32_t EmcCmdBrlshft3; + + uint32_t EmcQuseBrlshft0; + uint32_t EmcQuseBrlshft1; + uint32_t EmcQuseBrlshft2; + uint32_t EmcQuseBrlshft3; + + uint32_t EmcDllCfg0; + uint32_t EmcDllCfg1; + + uint32_t EmcPmcScratch1; + uint32_t EmcPmcScratch2; + uint32_t EmcPmcScratch3; + + uint32_t EmcPmacroPadCfgCtrl; + + uint32_t EmcPmacroVttgenCtrl0; + uint32_t EmcPmacroVttgenCtrl1; + uint32_t EmcPmacroVttgenCtrl2; + + uint32_t EmcPmacroBrickCtrlRfu1; + uint32_t EmcPmacroCmdBrickCtrlFdpd; + uint32_t EmcPmacroBrickCtrlRfu2; + uint32_t EmcPmacroDataBrickCtrlFdpd; + uint32_t EmcPmacroBgBiasCtrl0; + uint32_t EmcPmacroDataPadRxCtrl; + uint32_t EmcPmacroCmdPadRxCtrl; + uint32_t EmcPmacroDataRxTermMode; + uint32_t EmcPmacroCmdRxTermMode; + uint32_t EmcPmacroDataPadTxCtrl; + uint32_t EmcPmacroCommonPadTxCtrl; + uint32_t EmcPmacroCmdPadTxCtrl; + uint32_t EmcCfg3; + + uint32_t EmcPmacroTxPwrd0; + uint32_t EmcPmacroTxPwrd1; + uint32_t EmcPmacroTxPwrd2; + uint32_t EmcPmacroTxPwrd3; + uint32_t EmcPmacroTxPwrd4; + uint32_t EmcPmacroTxPwrd5; + + uint32_t EmcConfigSampleDelay; + + uint32_t EmcPmacroBrickMapping0; + uint32_t EmcPmacroBrickMapping1; + uint32_t EmcPmacroBrickMapping2; + + uint32_t EmcPmacroTxSelClkSrc0; + uint32_t EmcPmacroTxSelClkSrc1; + uint32_t EmcPmacroTxSelClkSrc2; + uint32_t EmcPmacroTxSelClkSrc3; + uint32_t EmcPmacroTxSelClkSrc4; + uint32_t EmcPmacroTxSelClkSrc5; + + uint32_t EmcPmacroDdllBypass; + + uint32_t EmcPmacroDdllPwrd0; + uint32_t EmcPmacroDdllPwrd1; + uint32_t EmcPmacroDdllPwrd2; + + uint32_t EmcPmacroCmdCtrl0; + uint32_t EmcPmacroCmdCtrl1; + uint32_t EmcPmacroCmdCtrl2; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t McEmemAdrCfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t McEmemAdrCfgDev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t McEmemAdrCfgDev1; + uint32_t McEmemAdrCfgChannelMask; + + /* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */ + uint32_t McEmemAdrCfgBankMask0; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + uint32_t McEmemAdrCfgBankMask1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + uint32_t McEmemAdrCfgBankMask2; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t McEmemCfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t McEmemArbCfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t McEmemArbOutstandingReq; + + uint32_t McEmemArbRefpbHpCtrl; + uint32_t McEmemArbRefpbBankCtrl; + + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t McEmemArbTimingRcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t McEmemArbTimingRp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t McEmemArbTimingRc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t McEmemArbTimingRas; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t McEmemArbTimingFaw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t McEmemArbTimingRrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t McEmemArbTimingRap2Pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t McEmemArbTimingWap2Pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t McEmemArbTimingR2R; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t McEmemArbTimingW2W; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t McEmemArbTimingR2W; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t McEmemArbTimingW2R; + + uint32_t McEmemArbTimingRFCPB; + + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t McEmemArbDaTurns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t McEmemArbDaCovers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t McEmemArbMisc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t McEmemArbMisc1; + uint32_t McEmemArbMisc2; + + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t McEmemArbRing1Throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t McEmemArbOverride; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + uint32_t McEmemArbOverride1; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t McEmemArbRsv; + + uint32_t McDaCfg0; + uint32_t McEmemArbTimingCcdmw; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t McClkenOverride; + + /* Specifies the value for MC_STAT_CONTROL */ + uint32_t McStatControl; + + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + uint32_t McVideoProtectBom; + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + uint32_t McVideoProtectBomAdrHi; + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + uint32_t McVideoProtectSizeMb; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + uint32_t McVideoProtectVprOverride; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + uint32_t McVideoProtectVprOverride1; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + uint32_t McVideoProtectGpuOverride0; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + uint32_t McVideoProtectGpuOverride1; + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + uint32_t McSecCarveoutBom; + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + uint32_t McSecCarveoutAdrHi; + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + uint32_t McSecCarveoutSizeMb; + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL. + VIDEO_PROTECT_WRITEAccess */ + uint32_t McVideoProtectWriteAccess; + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL. + SEC_CARVEOUT_WRITEAccess */ + uint32_t McSecCarveoutProtectWriteAccess; + + /* Write-Protect Regions (WPR) */ + uint32_t McGeneralizedCarveout1Bom; + uint32_t McGeneralizedCarveout1BomHi; + uint32_t McGeneralizedCarveout1Size128kb; + uint32_t McGeneralizedCarveout1Access0; + uint32_t McGeneralizedCarveout1Access1; + uint32_t McGeneralizedCarveout1Access2; + uint32_t McGeneralizedCarveout1Access3; + uint32_t McGeneralizedCarveout1Access4; + uint32_t McGeneralizedCarveout1ForceInternalAccess0; + uint32_t McGeneralizedCarveout1ForceInternalAccess1; + uint32_t McGeneralizedCarveout1ForceInternalAccess2; + uint32_t McGeneralizedCarveout1ForceInternalAccess3; + uint32_t McGeneralizedCarveout1ForceInternalAccess4; + uint32_t McGeneralizedCarveout1Cfg0; + + uint32_t McGeneralizedCarveout2Bom; + uint32_t McGeneralizedCarveout2BomHi; + uint32_t McGeneralizedCarveout2Size128kb; + uint32_t McGeneralizedCarveout2Access0; + uint32_t McGeneralizedCarveout2Access1; + uint32_t McGeneralizedCarveout2Access2; + uint32_t McGeneralizedCarveout2Access3; + uint32_t McGeneralizedCarveout2Access4; + uint32_t McGeneralizedCarveout2ForceInternalAccess0; + uint32_t McGeneralizedCarveout2ForceInternalAccess1; + uint32_t McGeneralizedCarveout2ForceInternalAccess2; + uint32_t McGeneralizedCarveout2ForceInternalAccess3; + uint32_t McGeneralizedCarveout2ForceInternalAccess4; + uint32_t McGeneralizedCarveout2Cfg0; + + uint32_t McGeneralizedCarveout3Bom; + uint32_t McGeneralizedCarveout3BomHi; + uint32_t McGeneralizedCarveout3Size128kb; + uint32_t McGeneralizedCarveout3Access0; + uint32_t McGeneralizedCarveout3Access1; + uint32_t McGeneralizedCarveout3Access2; + uint32_t McGeneralizedCarveout3Access3; + uint32_t McGeneralizedCarveout3Access4; + uint32_t McGeneralizedCarveout3ForceInternalAccess0; + uint32_t McGeneralizedCarveout3ForceInternalAccess1; + uint32_t McGeneralizedCarveout3ForceInternalAccess2; + uint32_t McGeneralizedCarveout3ForceInternalAccess3; + uint32_t McGeneralizedCarveout3ForceInternalAccess4; + uint32_t McGeneralizedCarveout3Cfg0; + + uint32_t McGeneralizedCarveout4Bom; + uint32_t McGeneralizedCarveout4BomHi; + uint32_t McGeneralizedCarveout4Size128kb; + uint32_t McGeneralizedCarveout4Access0; + uint32_t McGeneralizedCarveout4Access1; + uint32_t McGeneralizedCarveout4Access2; + uint32_t McGeneralizedCarveout4Access3; + uint32_t McGeneralizedCarveout4Access4; + uint32_t McGeneralizedCarveout4ForceInternalAccess0; + uint32_t McGeneralizedCarveout4ForceInternalAccess1; + uint32_t McGeneralizedCarveout4ForceInternalAccess2; + uint32_t McGeneralizedCarveout4ForceInternalAccess3; + uint32_t McGeneralizedCarveout4ForceInternalAccess4; + uint32_t McGeneralizedCarveout4Cfg0; + + uint32_t McGeneralizedCarveout5Bom; + uint32_t McGeneralizedCarveout5BomHi; + uint32_t McGeneralizedCarveout5Size128kb; + uint32_t McGeneralizedCarveout5Access0; + uint32_t McGeneralizedCarveout5Access1; + uint32_t McGeneralizedCarveout5Access2; + uint32_t McGeneralizedCarveout5Access3; + uint32_t McGeneralizedCarveout5Access4; + uint32_t McGeneralizedCarveout5ForceInternalAccess0; + uint32_t McGeneralizedCarveout5ForceInternalAccess1; + uint32_t McGeneralizedCarveout5ForceInternalAccess2; + uint32_t McGeneralizedCarveout5ForceInternalAccess3; + uint32_t McGeneralizedCarveout5ForceInternalAccess4; + uint32_t McGeneralizedCarveout5Cfg0; + + /* Specifies enable for CA training */ + uint32_t EmcCaTrainingEnable; + + /* Set if bit 6 select is greater than bit 7 select; uses aremc. + spec packet SWIZZLE_BIT6_GT_BIT7 */ + uint32_t SwizzleRankByteEncode; + /* Specifies enable and offset for patched boot ROM write */ + uint32_t BootRomPatchControl; + /* Specifies data for patched boot ROM write */ + uint32_t BootRomPatchData; + + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + uint32_t McMtsCarveoutBom; + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + uint32_t McMtsCarveoutAdrHi; + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + uint32_t McMtsCarveoutSizeMb; + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + uint32_t McMtsCarveoutRegCtrl; + + /* End */ +}; + +#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */ diff --git a/fusee/fusee-primary/src/se.c b/fusee/fusee-primary/src/se.c index 18e16bd99..af86980b3 100644 --- a/fusee/fusee-primary/src/se.c +++ b/fusee/fusee-primary/src/se.c @@ -1,7 +1,6 @@ #include #include "utils.h" -/*#include "interrupt.h"*/ #include "se.h" void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size); @@ -24,42 +23,49 @@ void NOINLINE ll_init(volatile se_ll_t *ll, void *buffer, size_t size) { } void se_check_error_status_reg(void) { - if (SECURITY_ENGINE->ERR_STATUS_REG) { + volatile tegra_se_t *se = se_get_regs(); + if (se->ERR_STATUS_REG) { generic_panic(); } } void se_check_for_error(void) { - if (SECURITY_ENGINE->INT_STATUS_REG & 0x10000 || SECURITY_ENGINE->FLAGS_REG & 3 || SECURITY_ENGINE->ERR_STATUS_REG) { + volatile tegra_se_t *se = se_get_regs(); + if (se->INT_STATUS_REG & 0x10000 || se->FLAGS_REG & 3 || se->ERR_STATUS_REG) { generic_panic(); } } void se_verify_flags_cleared(void) { - if (SECURITY_ENGINE->FLAGS_REG & 3) { + volatile tegra_se_t *se = se_get_regs(); + if (se->FLAGS_REG & 3) { generic_panic(); } } /* Set the flags for an AES keyslot. */ void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } /* Misc flags. */ if (flags & ~0x80) { - SECURITY_ENGINE->AES_KEYSLOT_FLAGS[keyslot] = ~flags; + se->AES_KEYSLOT_FLAGS[keyslot] = ~flags; } /* Disable keyslot reads. */ if (flags & 0x80) { - SECURITY_ENGINE->AES_KEY_READ_DISABLE_REG &= ~(1 << keyslot); + se->AES_KEY_READ_DISABLE_REG &= ~(1 << keyslot); } } /* Set the flags for an RSA keyslot. */ void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_RSA_MAX) { generic_panic(); } @@ -67,28 +73,32 @@ void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags) { /* Misc flags. */ if (flags & ~0x80) { /* TODO: Why are flags assigned this way? */ - SECURITY_ENGINE->RSA_KEYSLOT_FLAGS[keyslot] = (((flags >> 4) & 4) | (flags & 3)) ^ 7; + se->RSA_KEYSLOT_FLAGS[keyslot] = (((flags >> 4) & 4) | (flags & 3)) ^ 7; } /* Disable keyslot reads. */ if (flags & 0x80) { - SECURITY_ENGINE->RSA_KEY_READ_DISABLE_REG &= ~(1 << keyslot); + se->RSA_KEY_READ_DISABLE_REG &= ~(1 << keyslot); } } void clear_aes_keyslot(unsigned int keyslot) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } /* Zero out the whole keyslot and IV. */ for (unsigned int i = 0; i < 0x10; i++) { - SECURITY_ENGINE->AES_KEYTABLE_ADDR = (keyslot << 4) | i; - SECURITY_ENGINE->AES_KEYTABLE_DATA = 0; + se->AES_KEYTABLE_ADDR = (keyslot << 4) | i; + se->AES_KEYTABLE_DATA = 0; } } void clear_rsa_keyslot(unsigned int keyslot) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_RSA_MAX) { generic_panic(); } @@ -96,40 +106,44 @@ void clear_rsa_keyslot(unsigned int keyslot) { /* Zero out the whole keyslot. */ for (unsigned int i = 0; i < 0x40; i++) { /* Select Keyslot Modulus[i] */ - SECURITY_ENGINE->RSA_KEYTABLE_ADDR = (keyslot << 7) | i | 0x40; - SECURITY_ENGINE->RSA_KEYTABLE_DATA = 0; + se->RSA_KEYTABLE_ADDR = (keyslot << 7) | i | 0x40; + se->RSA_KEYTABLE_DATA = 0; } for (unsigned int i = 0; i < 0x40; i++) { /* Select Keyslot Expontent[i] */ - SECURITY_ENGINE->RSA_KEYTABLE_ADDR = (keyslot << 7) | i; - SECURITY_ENGINE->RSA_KEYTABLE_DATA = 0; + se->RSA_KEYTABLE_ADDR = (keyslot << 7) | i; + se->RSA_KEYTABLE_DATA = 0; } } void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || key_size > KEYSIZE_AES_MAX) { generic_panic(); } for (size_t i = 0; i < (key_size >> 2); i++) { - SECURITY_ENGINE->AES_KEYTABLE_ADDR = (keyslot << 4) | i; - SECURITY_ENGINE->AES_KEYTABLE_DATA = read32le(key, 4 * i); + se->AES_KEYTABLE_ADDR = (keyslot << 4) | i; + se->AES_KEYTABLE_DATA = read32le(key, 4 * i); } } void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_RSA_MAX || modulus_size > KEYSIZE_RSA_MAX || exp_size > KEYSIZE_RSA_MAX) { generic_panic(); } for (size_t i = 0; i < (modulus_size >> 2); i++) { - SECURITY_ENGINE->RSA_KEYTABLE_ADDR = (keyslot << 7) | 0x40 | i; - SECURITY_ENGINE->RSA_KEYTABLE_DATA = read32be(modulus, (4 * (modulus_size >> 2)) - (4 * i) - 4); + se->RSA_KEYTABLE_ADDR = (keyslot << 7) | 0x40 | i; + se->RSA_KEYTABLE_DATA = read32be(modulus, (4 * (modulus_size >> 2)) - (4 * i) - 4); } for (size_t i = 0; i < (exp_size >> 2); i++) { - SECURITY_ENGINE->RSA_KEYTABLE_ADDR = (keyslot << 7) | i; - SECURITY_ENGINE->RSA_KEYTABLE_DATA = read32be(exponent, (4 * (exp_size >> 2)) - (4 * i) - 4); + se->RSA_KEYTABLE_ADDR = (keyslot << 7) | i; + se->RSA_KEYTABLE_DATA = read32be(exponent, (4 * (exp_size >> 2)) - (4 * i) - 4); } g_se_modulus_sizes[keyslot] = modulus_size; @@ -137,47 +151,55 @@ void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_ } void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || iv_size > 0x10) { generic_panic(); } for (size_t i = 0; i < (iv_size >> 2); i++) { - SECURITY_ENGINE->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; - SECURITY_ENGINE->AES_KEYTABLE_DATA = read32le(iv, 4 * i); + se->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; + se->AES_KEYTABLE_DATA = read32le(iv, 4 * i); } } void clear_aes_keyslot_iv(unsigned int keyslot) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } for (size_t i = 0; i < (0x10 >> 2); i++) { - SECURITY_ENGINE->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; - SECURITY_ENGINE->AES_KEYTABLE_DATA = 0; + se->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; + se->AES_KEYTABLE_DATA = 0; } } void set_se_ctr(const void *ctr) { + volatile tegra_se_t *se = se_get_regs(); for (unsigned int i = 0; i < 4; i++) { - SECURITY_ENGINE->CRYPTO_CTR_REG[i] = read32le(ctr, i * 4); + se->CRYPTO_CTR_REG[i] = read32le(ctr, i * 4); } } void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot_dst >= KEYSLOT_AES_MAX || keyslot_src >= KEYSLOT_AES_MAX || wrapped_key_size > KEYSIZE_AES_MAX) { generic_panic(); } - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_DEC | DST_KEYTAB); - SECURITY_ENGINE->CRYPTO_REG = keyslot_src << 24; - SECURITY_ENGINE->BLOCK_COUNT_REG = 0; - SECURITY_ENGINE->CRYPTO_KEYTABLE_DST_REG = keyslot_dst << 8; + se->CONFIG_REG = (ALG_AES_DEC | DST_KEYTAB); + se->CRYPTO_REG = keyslot_src << 24; + se->BLOCK_COUNT_REG = 0; + se->CRYPTO_KEYTABLE_DST_REG = keyslot_dst << 8; trigger_se_blocking_op(OP_START, NULL, 0, wrapped_key, wrapped_key_size); } void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { + volatile tegra_se_t *se = se_get_regs(); uint8_t ALIGN(16) stack_buf[KEYSIZE_RSA_MAX]; if (keyslot >= KEYSLOT_RSA_MAX || src_size > KEYSIZE_RSA_MAX || dst_size > KEYSIZE_RSA_MAX) { @@ -189,18 +211,19 @@ void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, co stack_buf[i] = *((uint8_t *)src + src_size - i - 1); } - SECURITY_ENGINE->CONFIG_REG = (ALG_RSA | DST_RSAREG); - SECURITY_ENGINE->RSA_CONFIG = keyslot << 24; - SECURITY_ENGINE->RSA_KEY_SIZE_REG = (g_se_modulus_sizes[keyslot] >> 6) - 1; - SECURITY_ENGINE->RSA_EXP_SIZE_REG = g_se_exp_sizes[keyslot] >> 2; - + se->CONFIG_REG = (ALG_RSA | DST_RSAREG); + se->RSA_CONFIG = keyslot << 24; + se->RSA_KEY_SIZE_REG = (g_se_modulus_sizes[keyslot] >> 6) - 1; + se->RSA_EXP_SIZE_REG = g_se_exp_sizes[keyslot] >> 2; trigger_se_blocking_op(OP_START, NULL, 0, stack_buf, src_size); se_get_exp_mod_output(dst, dst_size); } void se_get_exp_mod_output(void *buf, size_t size) { + volatile tegra_se_t *se = se_get_regs(); size_t num_dwords = (size >> 2); + if (num_dwords < 1) { return; } @@ -210,7 +233,7 @@ void se_get_exp_mod_output(void *buf, size_t size) { /* Copy endian swapped output. */ while (num_dwords) { - *p_out = read32be(SECURITY_ENGINE->RSA_OUTPUT, offset); + *p_out = read32be(se->RSA_OUTPUT, offset); offset += 4; p_out--; num_dwords--; @@ -271,6 +294,7 @@ bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const v } void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size) { + volatile tegra_se_t *se = se_get_regs(); se_ll_t in_ll; se_ll_t out_ll; @@ -278,21 +302,22 @@ void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const v ll_init(&out_ll, dst, dst_size); /* Set the LLs. */ - SECURITY_ENGINE->IN_LL_ADDR_REG = (uint32_t) get_physical_address(&in_ll); - SECURITY_ENGINE->OUT_LL_ADDR_REG = (uint32_t) get_physical_address(&out_ll); + se->IN_LL_ADDR_REG = (uint32_t) get_physical_address(&in_ll); + se->OUT_LL_ADDR_REG = (uint32_t) get_physical_address(&out_ll); /* Set registers for operation. */ - SECURITY_ENGINE->ERR_STATUS_REG = SECURITY_ENGINE->ERR_STATUS_REG; - SECURITY_ENGINE->INT_STATUS_REG = SECURITY_ENGINE->INT_STATUS_REG; - SECURITY_ENGINE->OPERATION_REG = op; + se->ERR_STATUS_REG = se->ERR_STATUS_REG; + se->INT_STATUS_REG = se->INT_STATUS_REG; + se->OPERATION_REG = op; - while (!(SECURITY_ENGINE->INT_STATUS_REG & 0x10)) { /* Wait a while */ } + while (!(se->INT_STATUS_REG & 0x10)) { /* Wait a while */ } se_check_for_error(); } /* Secure AES Functionality. */ void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, size_t src_size) { + volatile tegra_se_t *se = se_get_regs(); uint8_t block[0x10] = {0}; if (src_size > sizeof(block) || dst_size > sizeof(block)) { @@ -305,7 +330,7 @@ void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, } /* Trigger AES operation. */ - SECURITY_ENGINE->BLOCK_COUNT_REG = 0; + se->BLOCK_COUNT_REG = 0; trigger_se_blocking_op(OP_START, block, sizeof(block), block, sizeof(block)); /* Copy output data into dst. */ @@ -315,21 +340,23 @@ void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, } void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || ctr_size != 0x10) { generic_panic(); } unsigned int num_blocks = src_size >> 4; /* Unknown what this write does, but official code writes it for CTR mode. */ - SECURITY_ENGINE->_0x80C = 1; - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | 0x91E; + se->SPARE_0 = 1; + se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY); + se->CRYPTO_REG = (keyslot << 24) | 0x91E; set_se_ctr(ctr); /* Handle any aligned blocks. */ size_t aligned_size = (size_t)num_blocks << 4; if (aligned_size) { - SECURITY_ENGINE->BLOCK_COUNT_REG = num_blocks - 1; + se->BLOCK_COUNT_REG = num_blocks - 1; trigger_se_blocking_op(OP_START, dst, dst_size, src, aligned_size); } @@ -344,15 +371,16 @@ void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const vo } void se_aes_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, unsigned int config_high) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) { generic_panic(); } /* Set configuration high (256-bit vs 128-bit) based on parameter. */ - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (config_high << 16); - SECURITY_ENGINE->CRYPTO_REG = keyslot << 24 | 0x100; + se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (config_high << 16); + se->CRYPTO_REG = keyslot << 24 | 0x100; se_perform_aes_block_operation(dst, 0x10, src, 0x10); - } void se_aes_128_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { @@ -365,12 +393,14 @@ void se_aes_256_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_si void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) { generic_panic(); } - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = keyslot << 24; + se->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY); + se->CRYPTO_REG = keyslot << 24; se_perform_aes_block_operation(dst, 0x10, src, 0x10); } @@ -422,6 +452,8 @@ void aes_128_xts_nintendo_xor_with_tweak(unsigned int keyslot, size_t sector, ui } void aes_128_xts_nintendo_crypt_sector(unsigned int keyslot_1, unsigned int keyslot_2, size_t sector, bool encrypt, void *dst, const void *src, size_t size) { + volatile tegra_se_t *se = se_get_regs(); + if ((size & 0xF) || size == 0) { generic_panic(); } @@ -431,13 +463,13 @@ void aes_128_xts_nintendo_crypt_sector(unsigned int keyslot_1, unsigned int keys /* Encrypt/Decrypt. */ if (encrypt) { - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = keyslot_1 << 24 | 0x100; + se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY); + se->CRYPTO_REG = keyslot_1 << 24 | 0x100; } else { - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = keyslot_1 << 24; + se->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY); + se->CRYPTO_REG = keyslot_1 << 24; } - SECURITY_ENGINE->BLOCK_COUNT_REG = (size >> 4) - 1; + se->BLOCK_COUNT_REG = (size >> 4) - 1; trigger_se_blocking_op(OP_START, dst, size, src, size); /* XOR. */ @@ -469,6 +501,8 @@ void se_aes_128_xts_nintendo_decrypt(unsigned int keyslot_1, unsigned int keyslo } void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size, unsigned int config_high) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } @@ -481,17 +515,17 @@ void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, con shift_left_xor_rb(derived_key); } - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_HASHREG) | (config_high << 16); - SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | (0x145); + se->CONFIG_REG = (ALG_AES_ENC | DST_HASHREG) | (config_high << 16); + se->CRYPTO_REG = (keyslot << 24) | (0x145); clear_aes_keyslot_iv(keyslot); unsigned int num_blocks = (data_size + 0xF) >> 4; /* Handle aligned blocks. */ if (num_blocks > 1) { - SECURITY_ENGINE->BLOCK_COUNT_REG = num_blocks - 2; + se->BLOCK_COUNT_REG = num_blocks - 2; trigger_se_blocking_op(OP_START, NULL, 0, data, data_size); - SECURITY_ENGINE->CRYPTO_REG |= 0x80; + se->CRYPTO_REG |= 0x80; } /* Create final block. */ @@ -508,12 +542,12 @@ void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, con } /* Perform last operation. */ - SECURITY_ENGINE->BLOCK_COUNT_REG = 0; + se->BLOCK_COUNT_REG = 0; trigger_se_blocking_op(OP_START, NULL, 0, last_block, sizeof(last_block)); /* Copy output CMAC. */ for (unsigned int i = 0; i < (cmac_size >> 2); i++) { - ((uint32_t *)cmac)[i] = read32le(SECURITY_ENGINE->HASH_RESULT_REG, i << 2); + ((uint32_t *)cmac)[i] = read32le(se->HASH_RESULT_REG, i << 2); } } @@ -525,42 +559,48 @@ void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, } void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || src_size < 0x10) { generic_panic(); } - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (0x202 << 16); - SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | 0x144; + se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (0x202 << 16); + se->CRYPTO_REG = (keyslot << 24) | 0x144; set_aes_keyslot_iv(keyslot, iv, 0x10); - SECURITY_ENGINE->BLOCK_COUNT_REG = (src_size >> 4) - 1; + se->BLOCK_COUNT_REG = (src_size >> 4) - 1; trigger_se_blocking_op(OP_START, dst, dst_size, src, src_size); } /* SHA256 Implementation. */ void se_calculate_sha256(void *dst, const void *src, size_t src_size) { + volatile tegra_se_t *se = se_get_regs(); + /* Setup config for SHA256, size = BITS(src_size) */ - SECURITY_ENGINE->CONFIG_REG = (ENCMODE_SHA256 | ALG_SHA | DST_HASHREG); - SECURITY_ENGINE->SHA_CONFIG_REG = 1; - SECURITY_ENGINE->SHA_MSG_LENGTH_REG = (uint32_t)(src_size << 3); - SECURITY_ENGINE->_0x208 = 0; - SECURITY_ENGINE->_0x20C = 0; - SECURITY_ENGINE->_0x210 = 0; - SECURITY_ENGINE->SHA_MSG_LEFT_REG = (uint32_t)(src_size << 3); - SECURITY_ENGINE->_0x218 = 0; - SECURITY_ENGINE->_0x21C = 0; - SECURITY_ENGINE->_0x220 = 0; + se->CONFIG_REG = (ENCMODE_SHA256 | ALG_SHA | DST_HASHREG); + se->SHA_CONFIG_REG = 1; + se->SHA_MSG_LENGTH_REG = (uint32_t)(src_size << 3); + se->_0x208 = 0; + se->_0x20C = 0; + se->_0x210 = 0; + se->SHA_MSG_LEFT_REG = (uint32_t)(src_size << 3); + se->_0x218 = 0; + se->_0x21C = 0; + se->_0x220 = 0; /* Trigger the operation. */ trigger_se_blocking_op(OP_START, NULL, 0, src, src_size); /* Copy output hash. */ for (unsigned int i = 0; i < (0x20 >> 2); i++) { - ((uint32_t *)dst)[i] = read32be(SECURITY_ENGINE->HASH_RESULT_REG, i << 2); + ((uint32_t *)dst)[i] = read32be(se->HASH_RESULT_REG, i << 2); } } /* RNG API */ void se_initialize_rng(unsigned int keyslot) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } @@ -569,32 +609,33 @@ void se_initialize_rng(unsigned int keyslot) { /* This will be discarded, when done. */ uint8_t ALIGN(16) output_buf[0x10]; - SECURITY_ENGINE->RNG_SRC_CONFIG_REG = 3; /* Entropy enable + Entropy lock enable */ - SECURITY_ENGINE->RNG_RESEED_INTERVAL_REG = 70001; - SECURITY_ENGINE->CONFIG_REG = (ALG_RNG | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | 0x108; - SECURITY_ENGINE->RNG_CONFIG_REG = 5; - SECURITY_ENGINE->BLOCK_COUNT_REG = 0; + se->RNG_SRC_CONFIG_REG = 3; /* Entropy enable + Entropy lock enable */ + se->RNG_RESEED_INTERVAL_REG = 70001; + se->CONFIG_REG = (ALG_RNG | DST_MEMORY); + se->CRYPTO_REG = (keyslot << 24) | 0x108; + se->RNG_CONFIG_REG = 5; + se->BLOCK_COUNT_REG = 0; trigger_se_blocking_op(OP_START, output_buf, 0x10, NULL, 0); } void se_generate_random(unsigned int keyslot, void *dst, size_t size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } uint32_t num_blocks = size >> 4; size_t aligned_size = num_blocks << 4; - SECURITY_ENGINE->CONFIG_REG = (ALG_RNG | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | 0x108; - SECURITY_ENGINE->RNG_CONFIG_REG = 4; + se->CONFIG_REG = (ALG_RNG | DST_MEMORY); + se->CRYPTO_REG = (keyslot << 24) | 0x108; + se->RNG_CONFIG_REG = 4; if (num_blocks >= 1) { - SECURITY_ENGINE->BLOCK_COUNT_REG = num_blocks - 1; + se->BLOCK_COUNT_REG = num_blocks - 1; trigger_se_blocking_op(OP_START, dst, aligned_size, NULL, 0); } if (size > aligned_size) { se_perform_aes_block_operation(dst + aligned_size, size - aligned_size, NULL, 0); } - } diff --git a/fusee/fusee-primary/src/se.h b/fusee/fusee-primary/src/se.h index a1ef7fa84..311567261 100644 --- a/fusee/fusee-primary/src/se.h +++ b/fusee/fusee-primary/src/se.h @@ -1,7 +1,8 @@ #ifndef FUSEE_SE_H #define FUSEE_SE_H -#include +#define SE_BASE 0x70012000 +#define MAKE_SE_REG(n) MAKE_REG32(SE_BASE + n) #define KEYSLOT_SWITCH_LP0TZRAMKEY 0x2 #define KEYSLOT_SWITCH_SRKGENKEY 0x8 @@ -98,10 +99,10 @@ typedef struct security_engine { uint32_t _0x21C; uint32_t _0x220; uint32_t _0x224; - uint8_t _0x228[0x5C]; + uint8_t _0x228[0x58]; uint32_t AES_KEY_READ_DISABLE_REG; uint32_t AES_KEYSLOT_FLAGS[0x10]; - uint8_t _0x2C8[0x38]; + uint8_t _0x2C4[0x3C]; uint32_t _0x300; uint32_t CRYPTO_REG; uint32_t CRYPTO_CTR_REG[4]; @@ -131,15 +132,13 @@ typedef struct security_engine { uint32_t FLAGS_REG; uint32_t ERR_STATUS_REG; uint32_t _0x808; - uint32_t _0x80C; + uint32_t SPARE_0; uint32_t _0x810; uint32_t _0x814; uint32_t _0x818; uint32_t _0x81C; uint8_t _0x820[0x17E0]; -} security_engine_t; - -static_assert(sizeof(security_engine_t) == 0x2000, "Mis-defined Security Engine Registers!"); +} tegra_se_t; typedef struct { uint32_t address; @@ -151,15 +150,10 @@ typedef struct { se_addr_info_t addr_info; /* This should really be an array...but for our use case it works. */ } se_ll_t; - -/* WIP, API subject to change. */ - -static inline volatile security_engine_t *get_security_engine(void) { - return (volatile security_engine_t *)0x70012000; +static inline volatile tegra_se_t *se_get_regs(void) { + return (volatile tegra_se_t *)SE_BASE; } -#define SECURITY_ENGINE (get_security_engine()) - /* This function MUST be registered to fire on the appropriate interrupt. */ void se_check_error_status_reg(void); diff --git a/fusee/fusee-primary/src/sysctr0.h b/fusee/fusee-primary/src/sysctr0.h new file mode 100644 index 000000000..60c645bdd --- /dev/null +++ b/fusee/fusee-primary/src/sysctr0.h @@ -0,0 +1,11 @@ +#ifndef FUSEE_SYSCTR0_H +#define FUSEE_SYSCTR0_H + +#include + +#define SYSCTR0_BASE 0x7000F000 +#define MAKE_SYSCTR0_REG(n) MAKE_REG32(SYSCTR0_BASE + n) + +#define SYSCTR0_CNTFID0_0 MAKE_SYSCTR0_REG(0x00) + +#endif diff --git a/fusee/fusee-primary/src/sysreg.h b/fusee/fusee-primary/src/sysreg.h new file mode 100644 index 000000000..d69cf8897 --- /dev/null +++ b/fusee/fusee-primary/src/sysreg.h @@ -0,0 +1,32 @@ +#ifndef FUSEE_SYSREG_H +#define FUSEE_SYSREG_H + +#include + +#define SYSREG_BASE 0x6000C000 +#define SB_BASE (SYSREG_BASE + 0x200) +#define EXCP_VEC_BASE 0x6000F000 + +#define MAKE_SYSREG(n) MAKE_REG32(SYSREG_BASE + n) +#define MAKE_SB_REG(n) MAKE_REG32(SB_BASE + n) +#define MAKE_EXCP_VEC_REG(n) MAKE_REG32(EXCP_VEC_BASE + n) + +#define AHB_ARBITRATION_DISABLE_0 MAKE_SYSREG(0x004) +#define AHB_ARBITRATION_XBAR_CTRL_0 MAKE_SYSREG(0x0E0) +#define AHB_AHB_SPARE_REG_0 MAKE_SYSREG(0x110) + +#define SB_CSR_0 MAKE_SB_REG(0x00) +#define SB_PIROM_START_0 MAKE_SB_REG(0x04) +#define SB_PFCFG_0 MAKE_SB_REG(0x08) +#define SB_SECURE_SPAREREG_0_0 MAKE_SB_REG(0x0C) +#define SB_SECURE_SPAREREG_1_0 MAKE_SB_REG(0x10) +#define SB_SECURE_SPAREREG_2_0 MAKE_SB_REG(0x14) +#define SB_SECURE_SPAREREG_3_0 MAKE_SB_REG(0x18) +#define SB_SECURE_SPAREREG_4_0 MAKE_SB_REG(0x1C) +#define SB_SECURE_SPAREREG_5_0 MAKE_SB_REG(0x20) +#define SB_SECURE_SPAREREG_6_0 MAKE_SB_REG(0x24) +#define SB_SECURE_SPAREREG_7_0 MAKE_SB_REG(0x28) +#define SB_AA64_RESET_LOW_0 MAKE_SB_REG(0x30) +#define SB_AA64_RESET_HIGH_0 MAKE_SB_REG(0x34) + +#endif diff --git a/fusee/fusee-primary/src/timers.h b/fusee/fusee-primary/src/timers.h index 519c0292f..8c9569c19 100644 --- a/fusee/fusee-primary/src/timers.h +++ b/fusee/fusee-primary/src/timers.h @@ -8,6 +8,7 @@ #define TIMERUS_CNTR_1US_0 MAKE_REG32(TIMERS_BASE + 0x10) #define RTC_BASE 0x7000E000 +#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n) #define RTC_SECONDS MAKE_REG32(RTC_BASE + 0x08) #define RTC_SHADOW_SECONDS MAKE_REG32(RTC_BASE + 0x0C) #define RTC_MILLI_SECONDS MAKE_REG32(RTC_BASE + 0x10) diff --git a/fusee/fusee-primary/src/uart.c b/fusee/fusee-primary/src/uart.c new file mode 100644 index 000000000..3d9865983 --- /dev/null +++ b/fusee/fusee-primary/src/uart.c @@ -0,0 +1,55 @@ +#include "uart.h" +#include "timers.h" + +void uart_init(UartDevice dev, uint32_t baud) { + volatile tegra_uart_t *uart = uart_get_regs(dev); + + /* Set baud rate. */ + uint32_t rate = (8 * baud + 408000000) / (16 * baud); + uart->UART_LCR = UART_LCR_DLAB; /* Enable DLAB. */ + uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */ + uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */ + uart->UART_LCR = 0; /* Diable DLAB. */ + + /* Setup UART in fifo mode. */ + uart->UART_IER_DLAB = 0; + uart->UART_IIR_FCR = UART_FCR_FCR_EN_FIFO | UART_FCR_RX_CLR | UART_FCR_TX_CLR; /* Enable and clear TX and RX FIFOs. */ + (void)uart->UART_LSR; + udelay(3 * ((baud + 999999) / baud)); + uart->UART_LCR = UART_LCR_WD_LENGTH_8; /* Set word length 8. */ + uart->UART_MCR = 0; + uart->UART_MSR = 0; + uart->UART_IRDA_CSR = 0; + uart->UART_RX_FIFO_CFG = 1; /* Set RX_FIFO trigger level */ + uart->UART_MIE = 0; + uart->UART_ASR = 0; +} + +/* This function blocks until the UART device (dev) is in the desired state (status). Make sure the desired state can be reached! */ +void uart_wait_idle(UartDevice dev, UartVendorStatus status) { + while (!(uart_get_regs(dev)->UART_VENDOR_STATUS & status)) { + /* Wait */ + } +} + +void uart_send(UartDevice dev, const void *buf, size_t len) { + volatile tegra_uart_t *uart = uart_get_regs(dev); + + for (size_t i = 0; i < len; i++) { + while (uart->UART_LSR & UART_LSR_TX_FIFO_FULL) { + /* Wait until the TX FIFO isn't full */ + } + uart->UART_THR_DLAB = *((const uint8_t *)buf + i); + } +} + +void uart_recv(UartDevice dev, void *buf, size_t len) { + volatile tegra_uart_t *uart = uart_get_regs(dev); + + for (size_t i = 0; i < len; i++) { + while (uart->UART_LSR & UART_LSR_RX_FIFO_EMPTY) { + /* Wait until the RX FIFO isn't empty */ + } + *((uint8_t *)buf + i) = uart->UART_THR_DLAB; + } +} diff --git a/fusee/fusee-primary/src/uart.h b/fusee/fusee-primary/src/uart.h new file mode 100644 index 000000000..3ba2ccad2 --- /dev/null +++ b/fusee/fusee-primary/src/uart.h @@ -0,0 +1,153 @@ +#ifndef FUSEE_UART_H +#define FUSEE_UART_H + +#include + +#define UART_BASE 0x70006000 + +#define BAUD_115200 115200 + +/* UART devices */ +typedef enum { + UART_A = 0, + UART_B = 1, + UART_C = 2, + UART_D = 3, + UART_E = 4, +} UartDevice; + +/* 36.3.12 UART_VENDOR_STATUS_0_0 */ +typedef enum { + UART_VENDOR_STATE_TX_IDLE = 1 << 0, + UART_VENDOR_STATE_RX_IDLE = 1 << 1, + + /* This bit is set to 1 when a read is issued to an empty FIFO and gets cleared on register read (sticky bit until read) + 0 = NO_UNDERRUN + 1 = UNDERRUN + */ + UART_VENDOR_STATE_RX_UNDERRUN = 1 << 2, + + /* This bit is set to 1 when write data is issued to the TX FIFO when it is already full and gets cleared on register read (sticky bit until read) + 0 = NO_OVERRUN + 1 = OVERRUN + */ + UART_VENDOR_STATE_TX_OVERRUN = 1 << 3, + + UART_VENDOR_STATE_RX_FIFO_COUNTER = 0b111111 << 16, /* reflects number of current entries in RX FIFO */ + UART_VENDOR_STATE_TX_FIFO_COUNTER = 0b111111 << 24 /* reflects number of current entries in TX FIFO */ +} UartVendorStatus; + +/* 36.3.6 UART_LSR_0 */ +typedef enum { + UART_LSR_RDR = 1 << 0, /* Receiver Data Ready */ + UART_LSR_OVRF = 1 << 1, /* Receiver Overrun Error */ + UART_LSR_PERR = 1 << 2, /* Parity Error */ + UART_LSR_FERR = 1 << 3, /* Framing Error */ + UART_LSR_BRK = 1 << 4, /* BREAK condition detected on line */ + UART_LSR_THRE = 1 << 5, /* Transmit Holding Register is Empty -- OK to write data */ + UART_LSR_TMTY = 1 << 6, /* Transmit Shift Register empty status */ + UART_LSR_FIFOE = 1 << 7, /* Receive FIFO Error */ + UART_LSR_TX_FIFO_FULL = 1 << 8, /* Transmitter FIFO full status */ + UART_LSR_RX_FIFO_EMPTY = 1 << 9, /* Receiver FIFO empty status */ +} UartLineStatus; + +/* 36.3.4 UART_LCR_0 */ +typedef enum { + UART_LCR_WD_LENGTH_5 = 0, /* word length 5 */ + UART_LCR_WD_LENGTH_6 = 1, /* word length 6 */ + UART_LCR_WD_LENGTH_7 = 2, /* word length 7 */ + UART_LCR_WD_LENGTH_8 = 3, /* word length 8 */ + + /* STOP: + 0 = Transmit 1 stop bit + 1 = Transmit 2 stop bits (receiver always checks for 1 stop bit) + */ + UART_LCR_STOP = 1 << 2, + UART_LCR_PAR = 1 << 3, /* Parity enabled */ + UART_LCR_EVEN = 1 << 4, /* Even parity format. There will always be an even number of 1s in the binary representation (PAR = 1) */ + UART_LCR_SET_P = 1 << 5, /* Set (force) parity to value in LCR[4] */ + UART_LCR_SET_B = 1 << 6, /* Set BREAK condition -- Transmitter sends all zeroes to indicate BREAK */ + UART_LCR_DLAB = 1 << 7, /* Divisor Latch Access Bit (set to allow programming of the DLH, DLM Divisors) */ +} UartLineControl; + +/* 36.3.3 UART_IIR_FCR_0 */ +typedef enum { + UART_FCR_FCR_EN_FIFO = 1 << 0, /* Enable the transmit and receive FIFOs. This bit should be enabled */ + UART_FCR_RX_CLR = 1 << 1, /* Clears the contents of the receive FIFO and resets its counter logic to 0 (the receive shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */ + UART_FCR_TX_CLR = 1 << 2, /* Clears the contents of the transmit FIFO and resets its counter logic to 0 (the transmit shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */ + + /* DMA: + 0 = DMA_MODE_0 + 1 = DMA_MODE_1 + */ + UART_FCR_DMA = 1 << 3, + + /* TX_TRIG + 0 = FIFO_COUNT_GREATER_16 + 1 = FIFO_COUNT_GREATER_8 + 2 = FIFO_COUNT_GREATER_4 + 3 = FIFO_COUNT_GREATER_1 + */ + UART_FCR_TX_TRIG = 3 << 4, + UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_16 = 0 << 4, + UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_8 = 1 << 4, + UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_4 = 2 << 4, + UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_1 = 3 << 4, + + /* RX_TRIG + 0 = FIFO_COUNT_GREATER_1 + 1 = FIFO_COUNT_GREATER_4 + 2 = FIFO_COUNT_GREATER_8 + 3 = FIFO_COUNT_GREATER_16 + */ + UART_FCR_RX_TRIG = 3 << 6, + UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_1 = 0 << 6, + UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_4 = 1 << 6, + UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_8 = 2 << 6, + UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_16 = 3 << 6, +} UartFifoControl; + +/* 36.3.3 UART_IIR_FCR_0 */ +typedef enum { + UART_IIR_IS_STA = 1 << 0, /* Interrupt Pending if ZERO */ + UART_IIR_IS_PRI0 = 1 << 1, /* Encoded Interrupt ID Refer to IIR[3:0] table [36.3.3] */ + UART_IIR_IS_PRI1 = 1 << 2, /* Encoded Interrupt ID Refer to IIR[3:0] table */ + UART_IIR_IS_PRI2 = 1 << 3, /* Encoded Interrupt ID Refer to IIR[3:0] table */ + + /* FIFO Mode Status + 0 = 16450 mode (no FIFO) + 1 = 16550 mode (FIFO) + */ + UART_IIR_EN_FIFO = 3 << 6, + UART_IIR_MODE_16450 = 0 << 6, + UART_IIR_MODE_16550 = 1 << 6, +} UartInterruptIdentification; + +typedef struct { + uint32_t UART_THR_DLAB; + uint32_t UART_IER_DLAB; + uint32_t UART_IIR_FCR; + uint32_t UART_LCR; + uint32_t UART_MCR; + uint32_t UART_LSR; + uint32_t UART_MSR; + uint32_t UART_SPR; + uint32_t UART_IRDA_CSR; + uint32_t UART_RX_FIFO_CFG; + uint32_t UART_MIE; + uint32_t UART_VENDOR_STATUS; + uint8_t _0x30[0x0C]; + uint32_t UART_ASR; +} tegra_uart_t; + +void uart_init(UartDevice dev, uint32_t baud); +void uart_wait_idle(UartDevice dev, UartVendorStatus status); +void uart_send(UartDevice dev, const void *buf, size_t len); +void uart_recv(UartDevice dev, void *buf, size_t len); + +static inline volatile tegra_uart_t *uart_get_regs(UartDevice dev) { + static const size_t offsets[] = {0, 0x40, 0x200, 0x300, 0x400}; + return (volatile tegra_uart_t *)(UART_BASE + offsets[dev]); +} + +#endif diff --git a/fusee/fusee-primary/src/utils.c b/fusee/fusee-primary/src/utils.c index 823e4ea00..6929ec0c0 100644 --- a/fusee/fusee-primary/src/utils.c +++ b/fusee/fusee-primary/src/utils.c @@ -7,9 +7,9 @@ #include "timers.h" #include "panic.h" #include "car.h" +#include "btn.h" #include "lib/printk.h" -#include "hwinit/btn.h" #include diff --git a/fusee/fusee-secondary/Makefile b/fusee/fusee-secondary/Makefile index 477dd52d0..bad10f017 100644 --- a/fusee/fusee-secondary/Makefile +++ b/fusee/fusee-secondary/Makefile @@ -21,7 +21,7 @@ include $(DEVKITARM)/base_rules #--------------------------------------------------------------------------------- TARGET := $(notdir $(CURDIR)) BUILD := build -SOURCES := src src/sdmmc src/hwinit src/lib src/lib/fatfs src/display +SOURCES := src src/sdmmc src/lib src/lib/fatfs src/display DATA := data INCLUDES := include diff --git a/fusee/fusee-secondary/src/apb_misc.h b/fusee/fusee-secondary/src/apb_misc.h index 114b7496a..4552a61b5 100644 --- a/fusee/fusee-secondary/src/apb_misc.h +++ b/fusee/fusee-secondary/src/apb_misc.h @@ -1,6 +1,17 @@ #ifndef FUSEE_APB_MISC_H #define FUSEE_APB_MISC_H +#include + +#define APB_MISC_BASE 0x70000000 +#define APB_PADCTL_BASE 0x70000810 +#define MAKE_APB_MISC_REG(n) MAKE_REG32(APB_MISC_BASE + n) +#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n) + +#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40) +#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64) +#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68) + #define SDMMC1_PAD_CAL_DRVUP_SHIFT (20) #define SDMMC1_PAD_CAL_DRVDN_SHIFT (12) #define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT) @@ -48,7 +59,7 @@ typedef struct { static inline volatile tegra_padctl_t *padctl_get_regs(void) { - return (volatile tegra_padctl_t *)0x70000810; + return (volatile tegra_padctl_t *)APB_PADCTL_BASE; } #endif diff --git a/fusee/fusee-secondary/src/btn.c b/fusee/fusee-secondary/src/btn.c new file mode 100644 index 000000000..bffc8e79d --- /dev/null +++ b/fusee/fusee-secondary/src/btn.c @@ -0,0 +1,64 @@ +#include + +#include "btn.h" +#include "i2c.h" +#include "gpio.h" +#include "timers.h" + +uint32_t btn_read() +{ + uint32_t res = 0; + + if (!gpio_read(GPIO_BUTTON_VOL_DOWN)) + res |= BTN_VOL_DOWN; + + if (!gpio_read(GPIO_BUTTON_VOL_UP)) + res |= BTN_VOL_UP; + + uint32_t val = 0; + if (i2c_query(4, 0x3C, 0x15, &val, 1)) + { + if (val & 0x4) + res |= BTN_POWER; + } + + return res; +} + +uint32_t btn_wait() +{ + uint32_t res = 0, btn = btn_read(); + int pwr = 0; + + if (btn & BTN_POWER) + { + pwr = 1; + btn &= ~BTN_POWER; + } + + do + { + res = btn_read(); + + if (!(res & BTN_POWER) && pwr) + pwr = 0; + else if (pwr) + res &= ~BTN_POWER; + } while (btn == res); + + return res; +} + +uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask) +{ + uint32_t timeout = get_time_ms() + time_ms; + uint32_t res = btn_read() & mask; + + do + { + if (!(res & mask)) + res = btn_read() & mask; + } while (get_time_ms() < timeout); + + return res; +} \ No newline at end of file diff --git a/fusee/fusee-secondary/src/btn.h b/fusee/fusee-secondary/src/btn.h new file mode 100644 index 000000000..08f6f6921 --- /dev/null +++ b/fusee/fusee-secondary/src/btn.h @@ -0,0 +1,12 @@ +#ifndef FUSEE_BTN_H_ +#define FUSEE_BTN_H_ + +#define BTN_POWER 0x1 +#define BTN_VOL_DOWN 0x2 +#define BTN_VOL_UP 0x4 + +uint32_t btn_read(); +uint32_t btn_wait(); +uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask); + +#endif \ No newline at end of file diff --git a/fusee/fusee-secondary/src/car.c b/fusee/fusee-secondary/src/car.c new file mode 100644 index 000000000..bc79be9a6 --- /dev/null +++ b/fusee/fusee-secondary/src/car.c @@ -0,0 +1,114 @@ +#include "car.h" +#include "utils.h" + +static inline uint32_t get_clk_source_reg(CarDevice dev) { + switch (dev) { + case CARDEVICE_UARTA: return 0x178; + case CARDEVICE_UARTB: return 0x17C; + case CARDEVICE_UARTC: return 0x1A0; + case CARDEVICE_I2C1: return 0x124; + case CARDEVICE_I2C5: return 0x128; + case CARDEVICE_UNK: return 0; + case CARDEVICE_SE: return 0x42C; + case CARDEVICE_HOST1X: return 0x180; + case CARDEVICE_TSEC: return 0x1F4; + case CARDEVICE_SOR_SAFE: return 0; + case CARDEVICE_SOR0: return 0; + case CARDEVICE_SOR1: return 0x410; + case CARDEVICE_KFUSE: return 0; + case CARDEVICE_CL_DVFS: return 0; + case CARDEVICE_CORESIGHT: return 0x1D4; + case CARDEVICE_ACTMON: return 0x3E8; + case CARDEVICE_BPMP: return 0; + default: generic_panic(); + } +} + +static inline uint32_t get_clk_source_val(CarDevice dev) { + switch (dev) { + case CARDEVICE_UARTA: return 0; + case CARDEVICE_UARTB: return 0; + case CARDEVICE_UARTC: return 0; + case CARDEVICE_I2C1: return 6; + case CARDEVICE_I2C5: return 6; + case CARDEVICE_UNK: return 0; + case CARDEVICE_SE: return 0; + case CARDEVICE_HOST1X: return 4; + case CARDEVICE_TSEC: return 0; + case CARDEVICE_SOR_SAFE: return 0; + case CARDEVICE_SOR0: return 0; + case CARDEVICE_SOR1: return 0; + case CARDEVICE_KFUSE: return 0; + case CARDEVICE_CL_DVFS: return 0; + case CARDEVICE_CORESIGHT: return 0; + case CARDEVICE_ACTMON: return 6; + case CARDEVICE_BPMP: return 0; + default: generic_panic(); + } +} + +static inline uint32_t get_clk_source_div(CarDevice dev) { + switch (dev) { + case CARDEVICE_UARTA: return 0; + case CARDEVICE_UARTB: return 0; + case CARDEVICE_UARTC: return 0; + case CARDEVICE_I2C1: return 0; + case CARDEVICE_I2C5: return 0; + case CARDEVICE_UNK: return 0; + case CARDEVICE_SE: return 0; + case CARDEVICE_HOST1X: return 3; + case CARDEVICE_TSEC: return 2; + case CARDEVICE_SOR_SAFE: return 0; + case CARDEVICE_SOR0: return 0; + case CARDEVICE_SOR1: return 2; + case CARDEVICE_KFUSE: return 0; + case CARDEVICE_CL_DVFS: return 0; + case CARDEVICE_CORESIGHT: return 4; + case CARDEVICE_ACTMON: return 0; + case CARDEVICE_BPMP: return 0; + default: generic_panic(); + } +} + +static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298}; +static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4}; + +void clk_enable(CarDevice dev) { + uint32_t clk_source_reg; + if ((clk_source_reg = get_clk_source_reg(dev))) { + MAKE_CAR_REG(clk_source_reg) = (get_clk_source_val(dev) << 29) | get_clk_source_div(dev); + } + MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F); +} + +void clk_disable(CarDevice dev) { + MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F)); +} + +void rst_enable(CarDevice dev) { + MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F); +} + +void rst_disable(CarDevice dev) { + MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F)); +} + +void clkrst_enable(CarDevice dev) { + clk_enable(dev); + rst_disable(dev); +} + +void clkrst_disable(CarDevice dev) { + rst_enable(dev); + clk_disable(dev); +} + +void clkrst_reboot(CarDevice dev) { + clkrst_disable(dev); + clkrst_enable(dev); +} + +void clkrst_enable_fuse_regs(bool enable) { + volatile tegra_car_t *car = car_get_regs(); + car->misc_clk_enb = ((car->misc_clk_enb & 0xEFFFFFFF) | ((enable & 1) << 28)); +} diff --git a/fusee/fusee-secondary/src/car.h b/fusee/fusee-secondary/src/car.h index 8cc0fb139..6ec42e744 100644 --- a/fusee/fusee-secondary/src/car.h +++ b/fusee/fusee-secondary/src/car.h @@ -1,121 +1,202 @@ #ifndef FUSEE_CAR_H #define FUSEE_CAR_H -#define CLK_SOURCE_SDMMC1 20 -#define CLK_SOURCE_SDMMC2 21 -#define CLK_SOURCE_SDMMC3 47 -#define CLK_SOURCE_SDMMC4 25 -#define CLK_SOURCE_SDMMC_LEGACY 0 +#include +#include + +#define CAR_BASE 0x60006000 +#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n) #define CLK_L_SDMMC1 (1 << 14) #define CLK_L_SDMMC2 (1 << 9) #define CLK_U_SDMMC3 (1 << 5) #define CLK_L_SDMMC4 (1 << 15) -#define TEGRA_CLK_PLLS 6 /* Number of normal PLLs */ -#define TEGRA_CLK_SIMPLE_PLLS 3 /* Number of simple PLLs */ -#define TEGRA_CLK_SOURCES 64 /* Number of ppl clock sources L/H/U */ -#define TEGRA_CLK_SOURCES_VW 32 /* Number of ppl clock sources V/W */ -#define TEGRA_CLK_SOURCES_X 32 /* Number of ppl clock sources X */ -#define TEGRA_CLK_SOURCES_Y 18 /* Number of ppl clock sources Y */ - #define CLK_SOURCE_MASK (0b111 << 29) #define CLK_SOURCE_FIRST (0b000 << 29) #define CLK_DIVIDER_MASK (0xff << 0) #define CLK_DIVIDER_UNITY (0x00 << 0) -#define CAR_CONTROL_SDMMC1 (1 << 14) -#define CAR_CONTROL_SDMMC4 (1 << 15) -#define CAR_CONTROL_SDMMC_LEGACY (1 << 1) +#define NUM_CAR_BANKS 7 -/* PLL registers - there are several PLLs in the clock controller */ -typedef struct { - uint32_t pll_base; /* the control register */ - - /* pll_out[0] is output A control, pll_out[1] is output B control */ - uint32_t pll_out[2]; - uint32_t pll_misc; /* other misc things */ -} clk_pll_t; - -/* PLL registers - there are several PLLs in the clock controller */ -typedef struct { - uint32_t pll_base; /* the control register */ - uint32_t pll_misc; /* other misc things */ -} clk_pll_simple_t; - -typedef struct { - uint32_t pllm_base; /* the control register */ - uint32_t pllm_out; /* output control */ - uint32_t pllm_misc1; /* misc1 */ - uint32_t pllm_misc2; /* misc2 */ -} clk_pllm_t; +/* Clock and reset devices. */ +typedef enum { + CARDEVICE_UARTA = ((0 << 5) | 0x6), + CARDEVICE_UARTB = ((0 << 5) | 0x7), + CARDEVICE_UARTC = ((1 << 5) | 0x17), + CARDEVICE_I2C1 = ((0 << 5) | 0xC), + CARDEVICE_I2C5 = ((1 << 5) | 0xF), + CARDEVICE_UNK = ((3 << 5) | 0x1E), + CARDEVICE_SE = ((3 << 5) | 0x1F), + CARDEVICE_HOST1X = ((0 << 5) | 0x1C), + CARDEVICE_TSEC = ((2 << 5) | 0x13), + CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E), + CARDEVICE_SOR0 = ((5 << 5) | 0x16), + CARDEVICE_SOR1 = ((5 << 5) | 0x17), + CARDEVICE_KFUSE = ((1 << 5) | 0x8), + CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B), + CARDEVICE_CORESIGHT = ((2 << 5) | 0x9), + CARDEVICE_ACTMON = ((3 << 5) | 0x17), + CARDEVICE_BPMP = ((0 << 5) | 0x1) +} CarDevice; /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ typedef struct { - uint32_t rst_src; /* _RST_SOURCE_0,0x00 */ + uint32_t rst_src; /* _RST_SOURCE_0, 0x00 */ + /* _RST_DEVICES_L/H/U_0 0x4-0xc */ uint32_t rst_dev_l; uint32_t rst_dev_h; uint32_t rst_dev_u; + /* _CLK_OUT_ENB_L/H/U_0 0x10-0x18 */ uint32_t clk_out_enb_l; uint32_t clk_out_enb_h; uint32_t clk_out_enb_u; - uint32_t reserved0; /* reserved_0, 0x1C */ - uint32_t cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ - uint32_t super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ - uint32_t sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ - uint32_t super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ - uint32_t clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ - uint32_t prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ - uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ - uint32_t reserved1; /* reserved_1, 0x3C */ - uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ - uint32_t clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ - uint32_t misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ - uint32_t clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ - uint32_t osc_ctrl; /* _OSC_CTRL_0, 0x50 */ - uint32_t pll_lfsr; /* _PLL_LFSR_0, 0x54 */ - uint32_t osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ - uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ - uint32_t reserved2[8]; /* reserved_2[8], 0x60-7C */ + uint32_t _0x1C; + uint32_t cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ + uint32_t super_cclk_div; /* _SUPER_CCLK_DIVIDER_0, 0x24 */ + uint32_t sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ + uint32_t super_sclk_div; /* _SUPER_SCLK_DIVIDER_0, 0x2c */ + uint32_t clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ + uint32_t prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ + uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0, 0x38 */ + uint32_t _0x3C; + uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0, 0x40 */ + uint32_t clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ + uint32_t misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ + uint32_t clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4c */ + uint32_t osc_ctrl; /* _OSC_CTRL_0, 0x50 */ + uint32_t pll_lfsr; /* _PLL_LFSR_0, 0x54 */ + uint32_t osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ + uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0, 0x5c */ + uint32_t _0x60[2]; + uint32_t plle_ss_cntl; /* _PLLE_SS_CNTL_0, 0x68 */ + uint32_t plle_misc1; /* _PLLE_MISC1_0, 0x6c */ + uint32_t _0x70[4]; - clk_pll_t pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ + /* PLLC 0x80-0x8c */ + uint32_t pllc_base; + uint32_t pllc_out; + uint32_t pllc_misc0; + uint32_t pllc_misc1; + + /* PLLM 0x90-0x9c */ + uint32_t pllm_base; + uint32_t pllm_out; + uint32_t pllm_misc1; + uint32_t pllm_misc2; + + /* PLLP 0xa0-0xac */ + uint32_t pllp_base; + uint32_t pllp_outa; + uint32_t pllp_outb; + uint32_t pllp_misc; + + /* PLLA 0xb0-0xbc */ + uint32_t plla_base; + uint32_t plla_out; + uint32_t plla_misc0; + uint32_t plla_misc1; + + /* PLLU 0xc0-0xcc */ + uint32_t pllu_base; + uint32_t pllu_out; + uint32_t pllu_misc1; + uint32_t pllu_misc2; + + /* PLLD 0xd0-0xdc */ + uint32_t plld_base; + uint32_t plld_out; + uint32_t plld_misc1; + uint32_t plld_misc2; - /* PLLs from 0xe0 to 0xf4 */ - clk_pll_simple_t pll_simple[TEGRA_CLK_SIMPLE_PLLS]; + /* PLLX 0xe0-0xe4 */ + uint32_t pllx_base; + uint32_t pllx_misc; + + /* PLLE 0xe8-0xf4 */ + uint32_t plle_base; + uint32_t plle_misc; + uint32_t plle_ss_cntl1; + uint32_t plle_ss_cntl2; + + uint32_t lvl2_clk_gate_ovra; /* _LVL2_CLK_GATE_OVRA_0, 0xf8 */ + uint32_t lvl2_clk_gate_ovrb; /* _LVL2_CLK_GATE_OVRB_0, 0xfc */ - uint32_t reserved10; /* _reserved_10, 0xF8 */ - uint32_t reserved11; /* _reserved_11, 0xFC */ + uint32_t clk_source_i2s2; /* _CLK_SOURCE_I2S2_0, 0x100 */ + uint32_t clk_source_i2s3; /* _CLK_SOURCE_I2S3_0, 0x104 */ + uint32_t clk_source_spdif_out; /* _CLK_SOURCE_SPDIF_OUT_0, 0x108 */ + uint32_t clk_source_spdif_in; /* _CLK_SOURCE_SPDIF_IN_0, 0x10c */ + uint32_t clk_source_pwm; /* _CLK_SOURCE_PWM_0, 0x110 */ + uint32_t _0x114; + uint32_t clk_source_spi2; /* _CLK_SOURCE_SPI2_0, 0x118 */ + uint32_t clk_source_spi3; /* _CLK_SOURCE_SPI3_0, 0x11c */ + uint32_t _0x120; + uint32_t clk_source_i2c1; /* _CLK_SOURCE_I2C1_0, 0x124 */ + uint32_t clk_source_i2c5; /* _CLK_SOURCE_I2C5_0, 0x128 */ + uint32_t _0x12c[2]; + uint32_t clk_source_spi1; /* _CLK_SOURCE_SPI1_0, 0x134 */ + uint32_t clk_source_disp1; /* _CLK_SOURCE_DISP1_0, 0x138 */ + uint32_t clk_source_disp2; /* _CLK_SOURCE_DISP2_0, 0x13c */ + uint32_t _0x140; + uint32_t clk_source_isp; /* _CLK_SOURCE_ISP_0, 0x144 */ + uint32_t clk_source_vi; /* _CLK_SOURCE_VI_0, 0x148 */ + uint32_t _0x14c; + uint32_t clk_source_sdmmc1; /* _CLK_SOURCE_SDMMC1_0, 0x150 */ + uint32_t clk_source_sdmmc2; /* _CLK_SOURCE_SDMMC2_0, 0x154 */ + uint32_t _0x158[3]; + uint32_t clk_source_sdmmc4; /* _CLK_SOURCE_SDMMC4_0, 0x164 */ + uint32_t _0x168[4]; + uint32_t clk_source_uarta; /* _CLK_SOURCE_UARTA_0, 0x178 */ + uint32_t clk_source_uartb; /* _CLK_SOURCE_UARTB_0, 0x17c */ + uint32_t clk_source_host1x; /* _CLK_SOURCE_HOST1X_0, 0x180 */ + uint32_t _0x184[5]; + uint32_t clk_source_i2c2; /* _CLK_SOURCE_I2C2_0, 0x198 */ + uint32_t clk_source_emc; /* _CLK_SOURCE_EMC_0, 0x19c */ + uint32_t clk_source_uartc; /* _CLK_SOURCE_UARTC_0, 0x1a0 */ + uint32_t _0x1a4; + uint32_t clk_source_vi_sensor; /* _CLK_SOURCE_VI_SENSOR_0, 0x1a8 */ + uint32_t _0x1ac[2]; + uint32_t clk_source_spi4; /* _CLK_SOURCE_SPI4_0, 0x1b4 */ + uint32_t clk_source_i2c3; /* _CLK_SOURCE_I2C3_0, 0x1b8 */ + uint32_t clk_source_sdmmc3; /* _CLK_SOURCE_SDMMC3_0, 0x1bc */ + uint32_t clk_source_uartd; /* _CLK_SOURCE_UARTD_0, 0x1c0 */ + uint32_t _0x1c4[2]; + uint32_t clk_source_owr; /* _CLK_SOURCE_OWR_0, 0x1cc */ + uint32_t _0x1d0; + uint32_t clk_source_csite; /* _CLK_SOURCE_CSITE_0, 0x1d4 */ + uint32_t clk_source_i2s1; /* _CLK_SOURCE_I2S1_0, 0x1d8 */ + uint32_t clk_source_dtv; /* _CLK_SOURCE_DTV_0, 0x1dc */ + uint32_t _0x1e0[5]; + uint32_t clk_source_tsec; /* _CLK_SOURCE_TSEC_0, 0x1f4 */ + uint32_t _0x1f8; + + uint32_t clk_spare2; /* _CLK_SPARE2_0, 0x1fc */ + uint32_t _0x200[32]; - uint32_t clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ + uint32_t clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + uint32_t clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + uint32_t clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ - uint32_t reserved20[32]; /* _reserved_20, 0x200-27c */ + uint32_t rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ + uint32_t rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + uint32_t rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - uint32_t clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ - uint32_t clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ - uint32_t clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + uint32_t clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ + uint32_t clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */ + uint32_t clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */ - uint32_t rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ - uint32_t rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ - uint32_t rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + uint32_t rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */ + uint32_t rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */ + uint32_t rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */ - uint32_t clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ - uint32_t clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */ - uint32_t clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */ + uint32_t _0x2b0[17]; + uint32_t dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + uint32_t _0x2f8[2]; - uint32_t rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */ - uint32_t rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */ - uint32_t rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */ - - uint32_t reserved21[17]; /* _reserved_21, 0x2b0-2f0 */ - - uint32_t dfll_base; /* _DFLL_BASE_0, 0x2f4 */ - - uint32_t reserved22[2]; /* _reserved_22, 0x2f8-2fc */ - - /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ + /* _RST_DEV_L/H/U_SET_0 0x300-0x314 */ uint32_t rst_dev_l_set; uint32_t rst_dev_l_clr; uint32_t rst_dev_h_set; @@ -123,9 +204,9 @@ typedef struct { uint32_t rst_dev_u_set; uint32_t rst_dev_u_clr; - uint32_t reserved30[2]; /* _reserved_30, 0x318, 0x31c */ + uint32_t _0x318[2]; - /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */ + /* _CLK_ENB_L/H/U_CLR_0 0x320-0x334 */ uint32_t clk_enb_l_set; uint32_t clk_enb_l_clr; uint32_t clk_enb_h_set; @@ -133,136 +214,275 @@ typedef struct { uint32_t clk_enb_u_set; uint32_t clk_enb_u_clr; - uint32_t reserved31[2]; /* _reserved_31, 0x338, 0x33c */ - - uint32_t cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ - uint32_t cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ + uint32_t _0x338; + uint32_t ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD_0, 0x33c */ + uint32_t rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ + uint32_t rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ /* Additional (T30) registers */ - uint32_t clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ - uint32_t clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ + uint32_t clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ + uint32_t clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ - uint32_t reserved32[2]; /* _reserved_32, 0x350,0x354 */ + uint32_t _0x350[2]; + uint32_t rst_dev_v; /* _RST_DEVICES_V/W_0 */ + uint32_t rst_dev_w; /* _RST_DEVICES_V/W_0 */ + uint32_t clk_out_enb_v; /* _CLK_OUT_ENB_V/W_0 */ + uint32_t clk_out_enb_w; /* _CLK_OUT_ENB_V/W_0 */ + uint32_t cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ + uint32_t super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ + uint32_t cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ + uint32_t super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ + uint32_t clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ + uint32_t clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ + uint32_t cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ + uint32_t cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ + uint32_t cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ + uint32_t _0x38c[5]; + uint32_t lvl2_clk_gate_ovrc; /* _LVL2_CLK_GATE_OVRC, 0x3a0 */ + uint32_t lvl2_clk_gate_ovrd; /* _LVL2_CLK_GATE_OVRD, 0x3a4 */ + uint32_t _0x3a8[2]; + + uint32_t _0x3b0; + uint32_t clk_source_mselect; /* _CLK_SOURCE_MSELECT_0, 0x3b4 */ + uint32_t clk_source_tsensor; /* _CLK_SOURCE_TSENSOR_0, 0x3b8 */ + uint32_t clk_source_i2s4; /* _CLK_SOURCE_I2S4_0, 0x3bc */ + uint32_t clk_source_i2s5; /* _CLK_SOURCE_I2S5_0, 0x3c0 */ + uint32_t clk_source_i2c4; /* _CLK_SOURCE_I2C4_0, 0x3c4 */ + uint32_t _0x3c8[2]; + uint32_t clk_source_ahub; /* _CLK_SOURCE_AHUB_0, 0x3d0 */ + uint32_t _0x3d4[4]; + uint32_t clk_source_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X_0, 0x3e4 */ + uint32_t clk_source_actmon; /* _CLK_SOURCE_ACTMON_0, 0x3e8 */ + uint32_t clk_source_extperiph1; /* _CLK_SOURCE_EXTPERIPH1_0, 0x3ec */ + uint32_t clk_source_extperiph2; /* _CLK_SOURCE_EXTPERIPH2_0, 0x3f0 */ + uint32_t clk_source_extperiph3; /* _CLK_SOURCE_EXTPERIPH3_0, 0x3f4 */ + uint32_t _0x3f8; + uint32_t clk_source_i2c_slow; /* _CLK_SOURCE_I2C_SLOW_0, 0x3fc */ + uint32_t clk_source_sys; /* _CLK_SOURCE_SYS_0, 0x400 */ + uint32_t clk_source_ispb; /* _CLK_SOURCE_ISPB_0, 0x404 */ + uint32_t _0x408[2]; + uint32_t clk_source_sor1; /* _CLK_SOURCE_SOR1_0, 0x410 */ + uint32_t clk_source_sor0; /* _CLK_SOURCE_SOR0_0, 0x414 */ + uint32_t _0x418[2]; + uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */ + uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */ + uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */ + uint32_t _0x42c; - uint32_t rst_dev_v; /* _RST_DEVICES_V/W_0 */ - uint32_t rst_dev_w; /* _RST_DEVICES_V/W_0 */ - - uint32_t clk_out_enb_v; /* _CLK_OUT_ENB_V/W_0 */ - uint32_t clk_out_enb_w; /* _CLK_OUT_ENB_V/W_0 */ - uint32_t cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ - uint32_t super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ - uint32_t cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ - uint32_t super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ - uint32_t clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ - uint32_t clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ - uint32_t cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - uint32_t cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ - uint32_t cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ - uint32_t reserved33[9]; /* _reserved_33, 0x38c-3ac */ - uint32_t clk_src_v; /* 0x3B0-0x42C */ - uint32_t clk_src_w; /* 0x3B0-0x42C */ - - /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ + /* _RST_DEV_V/W_SET_0 0x430-0x43c */ uint32_t rst_dev_v_set; uint32_t rst_dev_v_clr; uint32_t rst_dev_w_set; uint32_t rst_dev_w_clr; - /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ - uint32_t rst_clk_v_set; - uint32_t rst_clk_v_clr; - uint32_t rst_clk_w_set; - uint32_t rst_clk_w_clr; + /* _CLK_ENB_V/W_CLR_0 0x440-0x44c */ + uint32_t clk_enb_v_set; + uint32_t clk_enb_v_clr; + uint32_t clk_enb_w_set; + uint32_t clk_enb_w_clr; /* Additional (T114+) registers */ - uint32_t rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ - uint32_t rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ - uint32_t rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ - uint32_t rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */ - uint32_t clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ - uint32_t clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ - uint32_t clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ - uint32_t clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */ - uint32_t cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ - uint32_t reserved40[1]; /* _reserved_40, 0x474 */ - uint32_t intstatus; /* __INTSTATUS_0, 0x478 */ - uint32_t intmask; /* __INTMASK_0, 0x47C */ - uint32_t utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ - uint32_t utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ - uint32_t utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ + uint32_t rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ + uint32_t rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ + uint32_t rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ + uint32_t rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45c */ + uint32_t clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ + uint32_t clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ + uint32_t clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ + uint32_t clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46c */ + uint32_t cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ + uint32_t _0x474; + uint32_t intstatus; /* _INTSTATUS_0, 0x478 */ + uint32_t intmask; /* _INTMASK_0, 0x47c */ + uint32_t utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ + uint32_t utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ + uint32_t utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ - uint32_t plle_aux; /* _PLLE_AUX_0, 0x48C */ - uint32_t sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ - uint32_t sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ - uint32_t pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ + uint32_t plle_aux; /* _PLLE_AUX_0, 0x48c */ + uint32_t sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ + uint32_t sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ + uint32_t pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ - uint32_t prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */ - uint32_t audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */ - uint32_t audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */ - uint32_t audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */ - uint32_t audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ - uint32_t audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ - uint32_t audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ + uint32_t prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49c */ + uint32_t audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4a0 */ + uint32_t audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4a4 */ + uint32_t audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4a8 */ + uint32_t audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4ac */ + uint32_t audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4b0 */ + uint32_t audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4b4 */ - uint32_t plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ - uint32_t plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ - uint32_t utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ - uint32_t pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ - uint32_t pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ - uint32_t crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ - uint32_t pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ - uint32_t pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ - uint32_t pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ - uint32_t pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ - uint32_t pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ - uint32_t pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ + uint32_t plld2_base; /* _PLLD2_BASE_0, 0x4b8 */ + uint32_t plld2_misc; /* _PLLD2_MISC_0, 0x4bc */ + uint32_t utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4c0 */ + uint32_t pllrefe_base; /* _PLLREFE_BASE_0, 0x4c4 */ + uint32_t pllrefe_misc; /* _PLLREFE_MISC_0, 0x4c8 */ + uint32_t pllrefe_out; /* _PLLREFE_OUT_0, 0x4cc */ + uint32_t cpu_finetrim_byp; /* _CPU_FINETRIM_BYP_0, 0x4d0 */ + uint32_t cpu_finetrim_select; /* _CPU_FINETRIM_SELECT_0, 0x4d4 */ + uint32_t cpu_finetrim_dr; /* _CPU_FINETRIM_DR_0, 0x4d8 */ + uint32_t cpu_finetrim_df; /* _CPU_FINETRIM_DF_0, 0x4dc */ + uint32_t cpu_finetrim_f; /* _CPU_FINETRIM_F_0, 0x4e0 */ + uint32_t cpu_finetrim_r; /* _CPU_FINETRIM_R_0, 0x4e4 */ + uint32_t pllc2_base; /* _PLLC2_BASE_0, 0x4e8 */ + uint32_t pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4ec */ + uint32_t pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4f0 */ + uint32_t pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4f4 */ + uint32_t pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4f8 */ + uint32_t pllc3_base; /* _PLLC3_BASE_0, 0x4fc */ uint32_t pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ uint32_t pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ uint32_t pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ - uint32_t pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ + uint32_t pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50c */ uint32_t pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ uint32_t pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ uint32_t pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ - uint32_t xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ + uint32_t xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51c */ uint32_t xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ uint32_t plle_aux1; /* _PLLE_AUX1_0, 0x524 */ uint32_t pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ - uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ + uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52c */ uint32_t pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ uint32_t xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ - uint32_t reserved51[1]; /* _reserved_51, 0x538 */ - uint32_t clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ + uint32_t _0x538; + uint32_t clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53c */ uint32_t clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ uint32_t clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ uint32_t pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ - uint32_t pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ + uint32_t pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54c */ uint32_t pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ - uint32_t reserved52[1]; /* _reserved_52, 0x554 */ + uint32_t lvl2_clk_gate_ovre; /* _LVL2_CLK_GATE_OVRE, 0x554 */ uint32_t super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ - uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55C */ - uint32_t _rsv32[4]; /* 0x560-0x56c */ - uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ - uint32_t _rsv32_1[7]; /* 0x574-58c */ - clk_pll_simple_t plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */ - uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ - - /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */ - uint32_t _rsrv32_2[25]; /* _0x59C - 0x5FC */ - uint32_t clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */ - - /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */ - uint32_t reserved61[5]; /* _reserved_61, 0x680 - 0x690 */ + uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55c */ + uint32_t audio_sync_clk_dmic1; /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */ + uint32_t audio_sync_clk_dmic2; /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */ - /* - * NOTE: PLLA1 regs are in the middle of this Y region. Break this in - * two later if PLLA1 is needed, but for now this is cleaner. - */ - uint32_t clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */ + uint32_t _0x568[2]; + uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG, 0x570 */ + uint32_t plld2_ss_ctrl1; /* _PLLD2_SS_CTRL1_0, 0x574 */ + uint32_t plld2_ss_ctrl2; /* _PLLD2_SS_CTRL2_0, 0x578 */ + uint32_t _0x57c[5]; + + uint32_t plldp_base; /* _PLLDP_BASE, 0x590*/ + uint32_t plldp_misc; /* _PLLDP_MISC, 0x594 */ + uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ + uint32_t plldp_ss_ctrl1; /* _PLLDP_SS_CTRL1_0, 0x59c */ + uint32_t plldp_ss_ctrl2; /* _PLLDP_SS_CTRL2_0, 0x5a0 */ + uint32_t pllc4_base; /* _PLLC4_BASE_0, 0x5a4 */ + uint32_t pllc4_misc; /* _PLLC4_MISC_0, 0x5a8 */ + uint32_t _0x5ac[6]; + uint32_t clk_spare0; /* _CLK_SPARE0_0, 0x5c4 */ + uint32_t clk_spare1; /* _CLK_SPARE1_0, 0x5c8 */ + uint32_t gpu_isob_ctrl; /* _GPU_ISOB_CTRL_0, 0x5cc */ + uint32_t pllc_misc2; /* _PLLC_MISC_2_0, 0x5d0 */ + uint32_t pllc_misc3; /* _PLLC_MISC_3_0, 0x5d4 */ + uint32_t plla_misc2; /* _PLLA_MISC2_0, 0x5d8 */ + uint32_t _0x5dc[2]; + uint32_t pllc4_out; /* _PLLC4_OUT_0, 0x5e4 */ + uint32_t pllmb_base; /* _PLLMB_BASE_0, 0x5e8 */ + uint32_t pllmb_misc1; /* _PLLMB_MISC1_0, 0x5ec */ + uint32_t pllx_misc4; /* _PLLX_MISC_4_0, 0x5f0 */ + uint32_t pllx_misc5; /* _PLLX_MISC_5_0, 0x5f4 */ + uint32_t _0x5f8[2]; + + uint32_t clk_source_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST_0, 0x600 */ + uint32_t clk_source_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON_0, 0x604 */ + uint32_t clk_source_xusb_fs; /* _CLK_SOURCE_XUSB_FS_0, 0x608 */ + uint32_t clk_source_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV_0, 0x60c */ + uint32_t clk_source_xusb_ss; /* _CLK_SOURCE_XUSB_SS_0, 0x610 */ + uint32_t clk_source_cilab; /* _CLK_SOURCE_CILAB_0, 0x614 */ + uint32_t clk_source_cilcd; /* _CLK_SOURCE_CILCD_0, 0x618 */ + uint32_t clk_source_cilef; /* _CLK_SOURCE_CILEF_0, 0x61c */ + uint32_t clk_source_dsia_lp; /* _CLK_SOURCE_DSIA_LP_0, 0x620 */ + uint32_t clk_source_dsib_lp; /* _CLK_SOURCE_DSIB_LP_0, 0x624 */ + uint32_t clk_source_entropy; /* _CLK_SOURCE_ENTROPY_0, 0x628 */ + uint32_t clk_source_dvfs_ref; /* _CLK_SOURCE_DVFS_REF_0, 0x62c */ + uint32_t clk_source_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC_0, 0x630 */ + uint32_t _0x634[3]; + uint32_t clk_source_emc_latency; /* _CLK_SOURCE_EMC_LATENCY_0, 0x640 */ + uint32_t clk_source_soc_therm; /* _CLK_SOURCE_SOC_THERM_0, 0x644 */ + uint32_t _0x648; + uint32_t clk_source_dmic1; /* _CLK_SOURCE_DMIC1_0, 0x64c */ + uint32_t clk_source_dmic2; /* _CLK_SOURCE_DMIC2_0, 0x650 */ + uint32_t _0x654; + uint32_t clk_source_vi_sensor2; /* _CLK_SOURCE_VI_SENSOR2_0, 0x658 */ + uint32_t clk_source_i2c6; /* _CLK_SOURCE_I2C6_0, 0x65c */ + uint32_t clk_source_mipibif; /* _CLK_SOURCE_MIPIBIF_0, 0x660 */ + uint32_t clk_source_emc_dll; /* _CLK_SOURCE_EMC_DLL_0, 0x664 */ + uint32_t _0x668; + uint32_t clk_source_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIPI_CAL_0, 0x66c */ + uint32_t _0x670[2]; + uint32_t clk_source_vic; /* _CLK_SOURCE_VIC_0, 0x678 */ + + uint32_t pllp_outc; /* _PLLP_OUTC_0, 0x67c */ + uint32_t pllp_misc1; /* _PLLP_MISC1_0, 0x680 */ + uint32_t _0x684[2]; + uint32_t emc_div_clk_shaper_ctrl; /* _EMC_DIV_CLK_SHAPER_CTRL_0, 0x68c */ + uint32_t emc_pllc_shaper_ctrl; /* _EMC_PLLC_SHAPER_CTRL_0, 0x690 */ + + uint32_t clk_source_sdmmc_legacy_tm; /* _CLK_SOURCE_SDMMC_LEGACY_TM_0, 0x694 */ + uint32_t clk_source_nvdec; /* _CLK_SOURCE_NVDEC_0, 0x698 */ + uint32_t clk_source_nvjpg; /* _CLK_SOURCE_NVJPG_0, 0x69c */ + uint32_t clk_source_nvenc; /* _CLK_SOURCE_NVENC_0, 0x6a0 */ + + uint32_t plla1_base; /* _PLLA1_BASE_0, 0x6a4 */ + uint32_t plla1_misc0; /* _PLLA1_MISC_0_0, 0x6a8 */ + uint32_t plla1_misc1; /* _PLLA1_MISC_1_0, 0x6ac */ + uint32_t plla1_misc2; /* _PLLA1_MISC_2_0, 0x6b0 */ + uint32_t plla1_misc3; /* _PLLA1_MISC_3_0, 0x6b4 */ + uint32_t audio_sync_clk_dmic3; /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */ + + uint32_t clk_source_dmic3; /* _CLK_SOURCE_DMIC3_0, 0x6bc */ + uint32_t clk_source_ape; /* _CLK_SOURCE_APE_0, 0x6c0 */ + uint32_t clk_source_qspi; /* _CLK_SOURCE_QSPI_0, 0x6c4 */ + uint32_t clk_source_vi_i2c; /* _CLK_SOURCE_VI_I2C_0, 0x6c8 */ + uint32_t clk_source_usb2_hsic_trk; /* _CLK_SOURCE_USB2_HSIC_TRK_0, 0x6cc */ + uint32_t clk_source_pex_sata_usb_rx_byp; /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0, 0x6d0 */ + uint32_t clk_source_maud; /* _CLK_SOURCE_MAUD_0, 0x6d4 */ + uint32_t clk_source_tsecb; /* _CLK_SOURCE_TSECB_0, 0x6d8 */ + + uint32_t clk_cpug_misc1; /* _CLK_CPUG_MISC1_0, 0x6dc */ + uint32_t aclk_burst_policy; /* _ACLK_BURST_POLICY_0, 0x6e0 */ + uint32_t super_aclk_divider; /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */ + + uint32_t nvenc_super_clk_divider; /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */ + uint32_t vi_super_clk_divider; /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */ + uint32_t vic_super_clk_divider; /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */ + uint32_t nvdec_super_clk_divider; /* _NVDEC_SUPER_CLK_DIVIDER_0, 0x6f4 */ + uint32_t isp_super_clk_divider; /* _ISP_SUPER_CLK_DIVIDER_0, 0x6f8 */ + uint32_t ispb_super_clk_divider; /* _ISPB_SUPER_CLK_DIVIDER_0, 0x6fc */ + uint32_t nvjpg_super_clk_divider; /* _NVJPG_SUPER_CLK_DIVIDER_0, 0x700 */ + uint32_t se_super_clk_divider; /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */ + uint32_t tsec_super_clk_divider; /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */ + uint32_t tsecb_super_clk_divider; /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */ + + uint32_t clk_source_uartape; /* _CLK_SOURCE_UARTAPE_0, 0x710 */ + uint32_t clk_source_dbgapb; /* _CLK_SOURCE_DBGAPB_0, 0x718 */ + uint32_t clk_ccplex_cc4_ret_clk_enb; /* _CLK_CCPLEX_CC4_RET_CLK_ENB_0, 0x71c */ + uint32_t actmon_cpu_clk; /* _ACTMON_CPU_CLK_0, 0x720 */ + uint32_t clk_source_emc_safe; /* _CLK_SOURCE_EMC_SAFE_0, 0x724 */ + uint32_t sdmmc2_pllc4_out0_shaper_ctrl; /* _SDMMC2_PLLC4_OUT0_SHAPER_CTRL_0, 0x728 */ + uint32_t sdmmc2_pllc4_out1_shaper_ctrl; /* _SDMMC2_PLLC4_OUT1_SHAPER_CTRL_0, 0x72c */ + uint32_t sdmmc2_pllc4_out2_shaper_ctrl; /* _SDMMC2_PLLC4_OUT2_SHAPER_CTRL_0, 0x730 */ + uint32_t sdmmc2_div_clk_shaper_ctrl; /* _SDMMC2_DIV_CLK_SHAPER_CTRL_0, 0x734 */ + uint32_t sdmmc4_pllc4_out0_shaper_ctrl; /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */ + uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */ + uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */ + uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */ } tegra_car_t; -static inline volatile tegra_car_t *car_get_regs(void) -{ - return (volatile tegra_car_t *)0x60006000; +static inline volatile tegra_car_t *car_get_regs(void) { + return (volatile tegra_car_t *)CAR_BASE; } +void clk_enable(CarDevice dev); +void clk_disable(CarDevice dev); +void rst_enable(CarDevice dev); +void rst_disable(CarDevice dev); + +void clkrst_enable(CarDevice dev); +void clkrst_disable(CarDevice dev); +void clkrst_reboot(CarDevice dev); + +void clkrst_enable_fuse_regs(bool enable); + #endif diff --git a/fusee/fusee-secondary/src/cluster.c b/fusee/fusee-secondary/src/cluster.c new file mode 100644 index 000000000..bceaf7d73 --- /dev/null +++ b/fusee/fusee-secondary/src/cluster.c @@ -0,0 +1,135 @@ +#include + +#include "cluster.h" +#include "flow.h" +#include "sysreg.h" +#include "i2c.h" +#include "car.h" +#include "timers.h" +#include "pmc.h" +#include "max77620.h" + +void _cluster_enable_power() +{ + uint8_t val = 0; + i2c_query(4, 0x3C, MAX77620_REG_AME_GPIO, &val, 1); + + val &= 0xDF; + i2c_send(4, 0x3C, MAX77620_REG_AME_GPIO, &val, 1); + val = 0x09; + i2c_send(4, 0x3C, MAX77620_REG_GPIO5, &val, 1); + + /* Enable power. */ + val = 0x20; + i2c_send(4, 0x1B, MAX77620_REG_CNFGGLBL3, &val, 1); + val = 0x8D; + i2c_send(4, 0x1B, MAX77620_REG_CNFG1_32K, &val, 1); + val = 0xB7; + i2c_send(4, 0x1B, MAX77620_REG_CNFGGLBL1, &val, 1); + val = 0xB7; + i2c_send(4, 0x1B, MAX77620_REG_CNFGGLBL2, &val, 1); +} + +int _cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) +{ + volatile tegra_pmc_t *pmc = pmc_get_regs(); + + /* Check if the partition has already been turned on. */ + if (pmc->pwrgate_status & part) + return 1; + + uint32_t i = 5001; + while (pmc->pwrgate_toggle & 0x100) + { + udelay(1); + i--; + if (i < 1) + return 0; + } + + pmc->pwrgate_toggle = (toggle | 0x100); + + i = 5001; + while (i > 0) + { + if (pmc->pwrgate_status & part) + break; + + udelay(1); + i--; + } + + return 1; +} + +void cluster_boot_cpu0(uint32_t entry) +{ + volatile tegra_car_t *car = car_get_regs(); + + /* Set ACTIVE_CLUSER to FAST. */ + FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE; + + _cluster_enable_power(); + + if (!(car->pllx_base & 0x40000000)) + { + car->pllx_misc3 &= 0xFFFFFFF7; + udelay(2); + car->pllx_base = 0x80404E02; + car->pllx_base = 0x404E02; + car->pllx_misc = ((car->pllx_base & 0xFFFBFFFF) | 0x40000); + car->pllx_base = 0x40404E02; + } + + while (!(car->pllx_base & 0x8000000)) { + /* Spinlock. */ + } + + /* Configure MSELECT source and enable clock. */ + car->clk_source_mselect = ((car->clk_source_mselect & 0x1FFFFF00) | 6); + car->clk_out_enb_v = ((car->clk_out_enb_v & 0xFFFFFFF7) | 8); + + /* Configure initial CPU clock frequency and enable clock. */ + car->cclk_brst_pol = 0x20008888; + car->super_cclk_div = 0x80000000; + car->clk_enb_v_set = 1; + + clkrst_reboot(CARDEVICE_CORESIGHT); + + /* CAR2PMC_CPU_ACK_WIDTH should be set to 0. */ + car->cpu_softrst_ctrl2 &= 0xFFFFF000; + + /* Enable CPU rail. */ + _cluster_pmc_enable_partition(1, 0); + + /* Enable cluster 0 non-CPU. */ + _cluster_pmc_enable_partition(0x8000, 15); + + /* Enable CE0. */ + _cluster_pmc_enable_partition(0x4000, 14); + + /* Request and wait for RAM repair. */ + FLOW_CTLR_RAM_REPAIR_0 = 1; + while (!(FLOW_CTLR_RAM_REPAIR_0 & 2)){ + /* Spinlock. */ + } + + MAKE_EXCP_VEC_REG(0x100) = 0; + + /* Set reset vector. */ + SB_AA64_RESET_LOW_0 = entry | 1; + SB_AA64_RESET_HIGH_0 = 0; + + /* Non-secure reset vector write disable. */ + SB_CSR_0 = 2; + (void)SB_CSR_0; + + /* Clear MSELECT reset. */ + car->rst_dev_v &= 0xFFFFFFF7; + + /* Clear NONCPU reset. */ + car->rst_cpug_cmplx_clr = 0x20000000; + + /* Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.*/ + car->rst_cpug_cmplx_clr = 0x411F000F; +} diff --git a/fusee/fusee-secondary/src/cluster.h b/fusee/fusee-secondary/src/cluster.h new file mode 100644 index 000000000..e8e60c3ee --- /dev/null +++ b/fusee/fusee-secondary/src/cluster.h @@ -0,0 +1,6 @@ +#ifndef FUSEE_CLUSTER_H_ +#define FUSEE_CLUSTER_H_ + +void cluster_boot_cpu0(uint32_t entry); + +#endif diff --git a/fusee/fusee-secondary/src/console.c b/fusee/fusee-secondary/src/console.c index 4d26d9601..68532636d 100644 --- a/fusee/fusee-secondary/src/console.c +++ b/fusee/fusee-secondary/src/console.c @@ -5,7 +5,7 @@ #include #include #include "console.h" -#include "hwinit.h" +#include "di.h" #include "display/video_fb.h" static void *g_framebuffer = NULL; @@ -98,7 +98,7 @@ static void console_init_display(void) { /* Turn on the backlight after initializing the lfb */ /* to avoid flickering. */ if (!g_display_initialized) { - display_enable_backlight(true); + display_backlight(true); } g_display_initialized = true; @@ -144,7 +144,6 @@ static int console_create(void) { return 0; } - int console_init(bool display_initialized) { g_display_initialized = display_initialized; @@ -193,7 +192,7 @@ int console_resume(void) { int console_end(void) { /* Deinitialize the framebuffer and display */ if (g_display_initialized) { - display_enable_backlight(false); + display_backlight(false); display_end(); } free(g_framebuffer); diff --git a/fusee/fusee-secondary/src/di.c b/fusee/fusee-secondary/src/di.c new file mode 100644 index 000000000..e22257465 --- /dev/null +++ b/fusee/fusee-secondary/src/di.c @@ -0,0 +1,255 @@ +#include + +#include "di.h" +#include "timers.h" +#include "i2c.h" +#include "pmc.h" +#include "max77620.h" +#include "gpio.h" +#include "pinmux.h" +#include "car.h" + +#include "di.inl" + +static uint32_t _display_ver = 0; + +static void exec_cfg(uint32_t *base, const cfg_op_t *ops, uint32_t num_ops) +{ + for (uint32_t i = 0; i < num_ops; i++) + base[ops[i].off] = ops[i].val; +} + +static void _display_dsi_wait(uint32_t timeout, uint32_t off, uint32_t mask) +{ + uint32_t end = get_time_us() + timeout; + while ((get_time_us() < end) && (MAKE_DSI_REG(off) & mask)) { + /* Wait. */ + } + udelay(5); +} + +void display_init() +{ + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pmc_t *pmc = pmc_get_regs(); + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + /* Power on. */ + uint8_t val = 0xD0; + i2c_send(4, 0x3C, MAX77620_REG_LDO0_CFG, &val, 1); + val = 0x09; + i2c_send(4, 0x3C, MAX77620_REG_GPIO7, &val, 1); + + /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */ + car->rst_dev_h_clr = 0x1010000; + car->clk_enb_h_set = 0x1010000; + car->rst_dev_l_clr = 0x18000000; + car->clk_enb_l_set = 0x18000000; + car->clk_enb_x_set = 0x20000; + car->clk_source_uart_fst_mipi_cal = 0xA; + car->clk_enb_w_set = 0x80000; + car->clk_source_dsia_lp = 0xA; + + /* DPD idle. */ + pmc->io_dpd_req = 0x40000000; + pmc->io_dpd2_req = 0x40000000; + + /* Configure pins. */ + pinmux->nfc_en &= ~PINMUX_TRISTATE; + pinmux->nfc_int &= ~PINMUX_TRISTATE; + pinmux->lcd_bl_pwm &= ~PINMUX_TRISTATE; + pinmux->lcd_bl_en &= ~PINMUX_TRISTATE; + pinmux->lcd_rst &= ~PINMUX_TRISTATE; + + /* Configure Backlight +-5V GPIOs. */ + gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT); + + /* Enable Backlight +5V. */ + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); + + udelay(10000u); + + /* Enable Backlight -5V. */ + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); + + udelay(10000); + + /* Configure Backlight PWM, EN and RST GPIOs. */ + gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO); + gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO); + gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT); + gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT); + + /* Enable Backlight EN. */ + gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH); + + /* Configure display interface and display. */ + MAKE_MIPI_CAL_REG(0x60) = 0; + + exec_cfg((uint32_t *)CAR_BASE, _display_config_1, 4); + exec_cfg((uint32_t *)DI_BASE, _display_config_2, 94); + exec_cfg((uint32_t *)DSI_BASE, _display_config_3, 60); + + udelay(10000); + + /* Enable Backlight RST. */ + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH); + + udelay(60000); + + MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204; + MAKE_DSI_REG(DSI_WR_DATA) = 0x337; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + _display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO)); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x406; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + _display_dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO)); + + MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC); + _display_dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA); + + udelay(5000); + + _display_ver = MAKE_DSI_REG(DSI_RD_DATA); + + if (_display_ver == 0x10) + exec_cfg((uint32_t *)DSI_BASE, _display_config_4, 43); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x1105; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + + udelay(180000); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x2905; + MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; + + udelay(20000); + + exec_cfg((uint32_t *)DSI_BASE, _display_config_5, 21); + exec_cfg((uint32_t *)CAR_BASE, _display_config_6, 3); + + MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4; + exec_cfg((uint32_t *)DSI_BASE, _display_config_7, 10); + + udelay(10000); + + exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_8, 6); + exec_cfg((uint32_t *)DSI_BASE, _display_config_9, 4); + exec_cfg((uint32_t *)MIPI_CAL_BASE, _display_config_10, 16); + + udelay(10000); + + exec_cfg((uint32_t *)DI_BASE, _display_config_11, 113); +} + +void display_backlight(bool enable) +{ + /* Enable Backlight PWM. */ + gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); +} + +void display_end() +{ + volatile tegra_car_t *car = car_get_regs(); + volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); + + /* Disable Backlight. */ + display_backlight(false); + + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; + MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; + + uint32_t host1x_delay = MAKE_HOST1X_REG(0x30A4) + 5; + while (MAKE_HOST1X_REG(0x30A4) < host1x_delay) { + /* Wait. */ + } + + MAKE_DI_REG(DC_CMD_STATE_ACCESS) = 5; + MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; + + exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17); + exec_cfg((uint32_t *)DSI_BASE, _display_config_13, 16); + + udelay(10000); + + if (_display_ver == 0x10) + exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22); + + MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; + MAKE_DSI_REG(DSI_TRIGGER) = 2; + + udelay(50000); + + /* Disable Backlight RST. */ + gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable Backlight -5V. */ + gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable Backlight +5V. */ + gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW); + + udelay(10000); + + /* Disable clocks. */ + car->rst_dev_h_set = 0x1010000; + car->clk_enb_h_clr = 0x1010000; + car->rst_dev_l_set = 0x18000000; + car->clk_enb_l_clr = 0x18000000; + + MAKE_DSI_REG(DSI_PAD_CONTROL_0) = 0x10F010F; + MAKE_DSI_REG(DSI_POWER_CONTROL) = 0; + + /* Backlight PWM. */ + gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO); + + pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE); + pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1); +} + +void display_color_screen(uint32_t color) +{ + exec_cfg((uint32_t *)DI_BASE, cfg_display_one_color, 8); + + /* Configure display to show single color. */ + MAKE_DI_REG(DC_WIN_AD_WIN_OPTIONS) = 0; + MAKE_DI_REG(DC_WIN_BD_WIN_OPTIONS) = 0; + MAKE_DI_REG(DC_WIN_CD_WIN_OPTIONS) = 0; + MAKE_DI_REG(DC_DISP_BLEND_BACKGROUND_COLOR) = color; + MAKE_DI_REG(DC_CMD_STATE_CONTROL) = ((MAKE_DI_REG(DC_CMD_STATE_CONTROL) & 0xFFFFFFFE) | GENERAL_ACT_REQ); + + udelay(35000); + + display_backlight(true); +} + +uint32_t *display_init_framebuffer(void *address) +{ + static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0}; + if(conf[0].val == 0) { + for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) { + conf[i] = cfg_display_framebuffer[i]; + } + } + + uint32_t *lfb_addr = (uint32_t *)address; + + conf[19].val = (uint32_t)address; + + //This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). + exec_cfg((uint32_t *)DI_BASE, conf, 32); + + udelay(35000); + + return lfb_addr; +} diff --git a/fusee/fusee-secondary/src/di.h b/fusee/fusee-secondary/src/di.h new file mode 100644 index 000000000..bca4b569a --- /dev/null +++ b/fusee/fusee-secondary/src/di.h @@ -0,0 +1,350 @@ +#ifndef FUSEE_DI_H_ +#define FUSEE_DI_H_ + +#include +#include + +#define HOST1X_BASE 0x50000000 +#define DI_BASE 0x54200000 +#define DSI_BASE 0x54300000 +#define VIC_BASE 0x54340000 +#define MIPI_CAL_BASE 0x700E3000 +#define MAKE_HOST1X_REG(n) MAKE_REG32(HOST1X_BASE + n) +#define MAKE_DI_REG(n) MAKE_REG32(DI_BASE + n * 4) +#define MAKE_DSI_REG(n) MAKE_REG32(DSI_BASE + n * 4) +#define MAKE_MIPI_CAL_REG(n) MAKE_REG32(MIPI_CAL_BASE + n) +#define MAKE_VIC_REG(n) MAKE_REG32(VIC_BASE + n) + +/* Display registers. */ +#define DC_CMD_GENERAL_INCR_SYNCPT 0x00 + +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01 +#define SYNCPT_CNTRL_NO_STALL (1 << 8) +#define SYNCPT_CNTRL_SOFT_RESET (1 << 0) + +#define DC_CMD_CONT_SYNCPT_VSYNC 0x28 +#define SYNCPT_VSYNC_ENABLE (1 << 8) + +#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 + +#define DC_CMD_DISPLAY_COMMAND 0x32 +#define DISP_CTRL_MODE_STOP (0 << 5) +#define DISP_CTRL_MODE_C_DISPLAY (1 << 5) +#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) +#define DISP_CTRL_MODE_MASK (3 << 5) + +#define DC_CMD_DISPLAY_POWER_CONTROL 0x36 +#define PW0_ENABLE (1 << 0) +#define PW1_ENABLE (1 << 2) +#define PW2_ENABLE (1 << 4) +#define PW3_ENABLE (1 << 6) +#define PW4_ENABLE (1 << 8) +#define PM0_ENABLE (1 << 16) +#define PM1_ENABLE (1 << 18) + +#define DC_CMD_INT_MASK 0x38 +#define DC_CMD_INT_ENABLE 0x39 + +#define DC_CMD_STATE_ACCESS 0x40 +#define READ_MUX (1 << 0) +#define WRITE_MUX (1 << 2) + +#define DC_CMD_STATE_CONTROL 0x41 +#define GENERAL_ACT_REQ (1 << 0) +#define WIN_A_ACT_REQ (1 << 1) +#define WIN_B_ACT_REQ (1 << 2) +#define WIN_C_ACT_REQ (1 << 3) +#define CURSOR_ACT_REQ (1 << 7) +#define GENERAL_UPDATE (1 << 8) +#define WIN_A_UPDATE (1 << 9) +#define WIN_B_UPDATE (1 << 10) +#define WIN_C_UPDATE (1 << 11) +#define CURSOR_UPDATE (1 << 15) +#define NC_HOST_TRIG (1 << 24) + +#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42 +#define WINDOW_A_SELECT (1 << 4) +#define WINDOW_B_SELECT (1 << 5) +#define WINDOW_C_SELECT (1 << 6) + +#define DC_CMD_REG_ACT_CONTROL 0x043 + +#define DC_COM_CRC_CONTROL 0x300 +#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) +#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) + +#define DC_COM_DSC_TOP_CTL 0x33E + +#define DC_DISP_DISP_WIN_OPTIONS 0x402 +#define HDMI_ENABLE (1 << 30) +#define DSI_ENABLE (1 << 29) +#define SOR1_TIMING_CYA (1 << 27) +#define SOR1_ENABLE (1 << 26) +#define SOR_ENABLE (1 << 25) +#define CURSOR_ENABLE (1 << 16) + +#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 +#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 +#define DC_DISP_DISP_TIMING_OPTIONS 0x405 +#define DC_DISP_REF_TO_SYNC 0x406 +#define DC_DISP_SYNC_WIDTH 0x407 +#define DC_DISP_BACK_PORCH 0x408 +#define DC_DISP_ACTIVE 0x409 +#define DC_DISP_FRONT_PORCH 0x40A + +#define DC_DISP_DISP_CLOCK_CONTROL 0x42E +#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) +#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) +#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) +#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) +#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) +#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) +#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) +#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) +#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) +#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) +#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) +#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) +#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) +#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) + +#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F +#define DISP_DATA_FORMAT_DF1P1C (0 << 0) +#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) +#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) +#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) +#define DISP_DATA_FORMAT_DF2S (4 << 0) +#define DISP_DATA_FORMAT_DF3S (5 << 0) +#define DISP_DATA_FORMAT_DFSPI (6 << 0) +#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) +#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) +#define DISP_ALIGNMENT_MSB (0 << 8) +#define DISP_ALIGNMENT_LSB (1 << 8) +#define DISP_ORDER_RED_BLUE (0 << 9) +#define DISP_ORDER_BLUE_RED (1 << 9) + +#define DC_DISP_DISP_COLOR_CONTROL 0x430 +#define DITHER_CONTROL_MASK (3 << 8) +#define DITHER_CONTROL_DISABLE (0 << 8) +#define DITHER_CONTROL_ORDERED (2 << 8) +#define DITHER_CONTROL_ERRDIFF (3 << 8) +#define BASE_COLOR_SIZE_MASK (0xf << 0) +#define BASE_COLOR_SIZE_666 (0 << 0) +#define BASE_COLOR_SIZE_111 (1 << 0) +#define BASE_COLOR_SIZE_222 (2 << 0) +#define BASE_COLOR_SIZE_333 (3 << 0) +#define BASE_COLOR_SIZE_444 (4 << 0) +#define BASE_COLOR_SIZE_555 (5 << 0) +#define BASE_COLOR_SIZE_565 (6 << 0) +#define BASE_COLOR_SIZE_332 (7 << 0) +#define BASE_COLOR_SIZE_888 (8 << 0) + +#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 +#define SC1_H_QUALIFIER_NONE (1 << 16) +#define SC0_H_QUALIFIER_NONE (1 << 0) + +#define DC_DISP_DATA_ENABLE_OPTIONS 0x432 +#define DE_SELECT_ACTIVE_BLANK (0 << 0) +#define DE_SELECT_ACTIVE (1 << 0) +#define DE_SELECT_ACTIVE_IS (2 << 0) +#define DE_CONTROL_ONECLK (0 << 2) +#define DE_CONTROL_NORMAL (1 << 2) +#define DE_CONTROL_EARLY_EXT (2 << 2) +#define DE_CONTROL_EARLY (3 << 2) +#define DE_CONTROL_ACTIVE_BLANK (4 << 2) + +#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 +#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4 + +#define DC_WIN_CSC_YOF 0x611 +#define DC_WIN_CSC_KYRGB 0x612 +#define DC_WIN_CSC_KUR 0x613 +#define DC_WIN_CSC_KVR 0x614 +#define DC_WIN_CSC_KUG 0x615 +#define DC_WIN_CSC_KVG 0x616 +#define DC_WIN_CSC_KUB 0x617 +#define DC_WIN_CSC_KVB 0x618 +#define DC_WIN_AD_WIN_OPTIONS 0xB80 +#define DC_WIN_BD_WIN_OPTIONS 0xD80 +#define DC_WIN_CD_WIN_OPTIONS 0xF80 + +/* The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER). */ +#define DC_WIN_WIN_OPTIONS 0x700 +#define H_DIRECTION (1 << 0) +#define V_DIRECTION (1 << 2) +#define COLOR_EXPAND (1 << 6) +#define CSC_ENABLE (1 << 18) +#define WIN_ENABLE (1 << 30) + +#define DC_WIN_COLOR_DEPTH 0x703 +#define WIN_COLOR_DEPTH_P1 0x0 +#define WIN_COLOR_DEPTH_P2 0x1 +#define WIN_COLOR_DEPTH_P4 0x2 +#define WIN_COLOR_DEPTH_P8 0x3 +#define WIN_COLOR_DEPTH_B4G4R4A4 0x4 +#define WIN_COLOR_DEPTH_B5G5R5A 0x5 +#define WIN_COLOR_DEPTH_B5G6R5 0x6 +#define WIN_COLOR_DEPTH_AB5G5R5 0x7 +#define WIN_COLOR_DEPTH_B8G8R8A8 0xC +#define WIN_COLOR_DEPTH_R8G8B8A8 0xD +#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE +#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF +#define WIN_COLOR_DEPTH_YCbCr422 0x10 +#define WIN_COLOR_DEPTH_YUV422 0x11 +#define WIN_COLOR_DEPTH_YCbCr420P 0x12 +#define WIN_COLOR_DEPTH_YUV420P 0x13 +#define WIN_COLOR_DEPTH_YCbCr422P 0x14 +#define WIN_COLOR_DEPTH_YUV422P 0x15 +#define WIN_COLOR_DEPTH_YCbCr422R 0x16 +#define WIN_COLOR_DEPTH_YUV422R 0x17 +#define WIN_COLOR_DEPTH_YCbCr422RA 0x18 +#define WIN_COLOR_DEPTH_YUV422RA 0x19 + +#define DC_WIN_BUFFER_CONTROL 0x702 +#define DC_WIN_POSITION 0x704 + +#define DC_WIN_SIZE 0x705 +#define H_SIZE(x) (((x) & 0x1fff) << 0) +#define V_SIZE(x) (((x) & 0x1fff) << 16) + +#define DC_WIN_PRESCALED_SIZE 0x706 +#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) +#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) + +#define DC_WIN_H_INITIAL_DDA 0x707 +#define DC_WIN_V_INITIAL_DDA 0x708 + +#define DC_WIN_DDA_INC 0x709 +#define H_DDA_INC(x) (((x) & 0xffff) << 0) +#define V_DDA_INC(x) (((x) & 0xffff) << 16) + +#define DC_WIN_LINE_STRIDE 0x70A +#define DC_WIN_DV_CONTROL 0x70E + +/* The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */ +#define DC_WINBUF_START_ADDR 0x800 +#define DC_WINBUF_ADDR_H_OFFSET 0x806 +#define DC_WINBUF_ADDR_V_OFFSET 0x808 +#define DC_WINBUF_SURFACE_KIND 0x80B + +/* Display serial interface registers. */ +#define DSI_RD_DATA 0x9 +#define DSI_WR_DATA 0xA + +#define DSI_POWER_CONTROL 0xB +#define DSI_POWER_CONTROL_ENABLE 1 + +#define DSI_INT_ENABLE 0xC +#define DSI_INT_STATUS 0xD +#define DSI_INT_MASK 0xE + +#define DSI_HOST_CONTROL 0xF +#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21) +#define DSI_HOST_CONTROL_CRC_RESET (1 << 20) +#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12) +#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12) +#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12) +#define DSI_HOST_CONTROL_RAW (1 << 6) +#define DSI_HOST_CONTROL_HS (1 << 5) +#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4) +#define DSI_HOST_CONTROL_IMM_BTA (1 << 3) +#define DSI_HOST_CONTROL_PKT_BTA (1 << 2) +#define DSI_HOST_CONTROL_CS (1 << 1) +#define DSI_HOST_CONTROL_ECC (1 << 0) + +#define DSI_CONTROL 0x10 +#define DSI_CONTROL_HS_CLK_CTRL (1 << 20) +#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16) +#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12) +#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8) +#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4) +#define DSI_CONTROL_DCS_ENABLE (1 << 3) +#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2) +#define DSI_CONTROL_VIDEO_ENABLE (1 << 1) +#define DSI_CONTROL_HOST_ENABLE (1 << 0) + +#define DSI_SOL_DELAY 0x11 +#define DSI_MAX_THRESHOLD 0x12 + +#define DSI_TRIGGER 0x13 +#define DSI_TRIGGER_HOST (1 << 1) +#define DSI_TRIGGER_VIDEO (1 << 0) + +#define DSI_TX_CRC 0x14 +#define DSI_STATUS 0x15 +#define DSI_INIT_SEQ_CONTROL 0x1A +#define DSI_INIT_SEQ_DATA_0 0x1B +#define DSI_INIT_SEQ_DATA_1 0x1C +#define DSI_INIT_SEQ_DATA_2 0x1D +#define DSI_INIT_SEQ_DATA_3 0x1E +#define DSI_PKT_SEQ_0_LO 0x23 +#define DSI_PKT_SEQ_0_HI 0x24 +#define DSI_PKT_SEQ_1_LO 0x25 +#define DSI_PKT_SEQ_1_HI 0x26 +#define DSI_PKT_SEQ_2_LO 0x27 +#define DSI_PKT_SEQ_2_HI 0x28 +#define DSI_PKT_SEQ_3_LO 0x29 +#define DSI_PKT_SEQ_3_HI 0x2A +#define DSI_PKT_SEQ_4_LO 0x2B +#define DSI_PKT_SEQ_4_HI 0x2C +#define DSI_PKT_SEQ_5_LO 0x2D +#define DSI_PKT_SEQ_5_HI 0x2E +#define DSI_DCS_CMDS 0x33 +#define DSI_PKT_LEN_0_1 0x34 +#define DSI_PKT_LEN_2_3 0x35 +#define DSI_PKT_LEN_4_5 0x36 +#define DSI_PKT_LEN_6_7 0x37 +#define DSI_PHY_TIMING_0 0x3C +#define DSI_PHY_TIMING_1 0x3D +#define DSI_PHY_TIMING_2 0x3E +#define DSI_BTA_TIMING 0x3F + +#define DSI_TIMEOUT_0 0x44 +#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) +#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) + +#define DSI_TIMEOUT_1 0x45 +#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) +#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) + +#define DSI_TO_TALLY 0x46 + +#define DSI_PAD_CONTROL_0 0x4B +#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24) +#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) +#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) +#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) + +#define DSI_PAD_CONTROL_CD 0x4c +#define DSI_VIDEO_MODE_CONTROL 0x4E + +#define DSI_PAD_CONTROL_1 0x4F +#define DSI_PAD_CONTROL_2 0x50 + +#define DSI_PAD_CONTROL_3 0x51 +#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12) +#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8) +#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4) +#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) + +#define DSI_PAD_CONTROL_4 0x52 + +typedef struct _cfg_op_t +{ + uint32_t off; + uint32_t val; +} cfg_op_t; + +void display_init(); +void display_end(); + +/* Show one single color on the display. */ +void display_color_screen(uint32_t color); + +/* Switches screen backlight ON/OFF. */ +void display_backlight(bool enable); + +/* Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */ +uint32_t *display_init_framebuffer(void *address); + +#endif diff --git a/fusee/fusee-secondary/src/di.inl b/fusee/fusee-secondary/src/di.inl new file mode 100644 index 000000000..c34fb4cf2 --- /dev/null +++ b/fusee/fusee-secondary/src/di.inl @@ -0,0 +1,546 @@ +//Clock config. +static const cfg_op_t _display_config_1[4] = { + {0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 + {0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE + {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 + {0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC +}; + +//Display A config. +static const cfg_op_t _display_config_2[94] = { + {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_REG_ACT_CONTROL, 0x54}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_DISP_DC_MCCIF_FIFOCTRL, 0}, + {DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, + {DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, + {DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, + {DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, + {DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {0x4E4, 0}, + {DC_COM_CRC_CONTROL, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_COMMAND, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ} +}; + +//DSI Init config. +static const cfg_op_t _display_config_3[60] = { + {DSI_WR_DATA, 0}, + {DSI_INT_ENABLE, 0}, + {DSI_INT_STATUS, 0}, + {DSI_INT_MASK, 0}, + {DSI_INIT_SEQ_DATA_0, 0}, + {DSI_INIT_SEQ_DATA_1, 0}, + {DSI_INIT_SEQ_DATA_2, 0}, + {DSI_INIT_SEQ_DATA_3, 0}, + {DSI_DCS_CMDS, 0}, + {DSI_PKT_SEQ_0_LO, 0}, + {DSI_PKT_SEQ_1_LO, 0}, + {DSI_PKT_SEQ_2_LO, 0}, + {DSI_PKT_SEQ_3_LO, 0}, + {DSI_PKT_SEQ_4_LO, 0}, + {DSI_PKT_SEQ_5_LO, 0}, + {DSI_PKT_SEQ_0_HI, 0}, + {DSI_PKT_SEQ_1_HI, 0}, + {DSI_PKT_SEQ_2_HI, 0}, + {DSI_PKT_SEQ_3_HI, 0}, + {DSI_PKT_SEQ_4_HI, 0}, + {DSI_PKT_SEQ_5_HI, 0}, + {DSI_CONTROL, 0}, + {DSI_PAD_CONTROL_CD, 0}, + {DSI_SOL_DELAY, 0x18}, + {DSI_MAX_THRESHOLD, 0x1E0}, + {DSI_TRIGGER, 0}, + {DSI_INIT_SEQ_CONTROL, 0}, + {DSI_PKT_LEN_0_1, 0}, + {DSI_PKT_LEN_2_3, 0}, + {DSI_PKT_LEN_4_5, 0}, + {DSI_PKT_LEN_6_7, 0}, + {DSI_PAD_CONTROL_1, 0}, + {DSI_PHY_TIMING_0, 0x6070601}, + {DSI_PHY_TIMING_1, 0x40A0E05}, + {DSI_PHY_TIMING_2, 0x30109}, + {DSI_BTA_TIMING, 0x190A14}, + {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TO_TALLY, 0}, + {DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_POWER_CONTROL, 0}, + {DSI_POWER_CONTROL, 0}, + {DSI_PAD_CONTROL_1, 0}, + {DSI_PHY_TIMING_0, 0x6070601}, + {DSI_PHY_TIMING_1, 0x40A0E05}, + {DSI_PHY_TIMING_2, 0x30118}, + {DSI_BTA_TIMING, 0x190A14}, + {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TO_TALLY, 0}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_MAX_THRESHOLD, 0x40}, + {DSI_TRIGGER, 0}, + {DSI_TX_CRC, 0}, + {DSI_INIT_SEQ_CONTROL, 0} +}; + +//DSI config (if ver == 0x10). +static const cfg_op_t _display_config_4[43] = { + {DSI_WR_DATA, 0x439}, + {DSI_WR_DATA, 0x9483FFB9}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0xBD15}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x1939}, + {DSI_WR_DATA, 0xAAAAAAD8}, + {DSI_WR_DATA, 0xAAAAAAEB}, + {DSI_WR_DATA, 0xAAEBAAAA}, + {DSI_WR_DATA, 0xAAAAAAAA}, + {DSI_WR_DATA, 0xAAAAAAEB}, + {DSI_WR_DATA, 0xAAEBAAAA}, + {DSI_WR_DATA, 0xAA}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x1BD15}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x2739}, + {DSI_WR_DATA, 0xFFFFFFD8}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFF}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x2BD15}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0xF39}, + {DSI_WR_DATA, 0xFFFFFFD8}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFFFF}, + {DSI_WR_DATA, 0xFFFFFF}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0xBD15}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x6D915}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x439}, + {DSI_WR_DATA, 0xB9}, + {DSI_TRIGGER, DSI_TRIGGER_HOST} +}; + +//DSI config. +static const cfg_op_t _display_config_5[21] = { + {DSI_PAD_CONTROL_1, 0}, + {DSI_PHY_TIMING_0, 0x6070601}, + {DSI_PHY_TIMING_1, 0x40A0E05}, + {DSI_PHY_TIMING_2, 0x30172}, + {DSI_BTA_TIMING, 0x190A14}, + {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TO_TALLY, 0}, + {DSI_PKT_SEQ_0_LO, 0x40000208}, + {DSI_PKT_SEQ_2_LO, 0x40000308}, + {DSI_PKT_SEQ_4_LO, 0x40000308}, + {DSI_PKT_SEQ_1_LO, 0x40000308}, + {DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, + {DSI_PKT_SEQ_3_HI, 0x2CC}, + {DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, + {DSI_PKT_SEQ_5_HI, 0x2CC}, + {DSI_PKT_LEN_0_1, 0xCE0000}, + {DSI_PKT_LEN_2_3, 0x87001A2}, + {DSI_PKT_LEN_4_5, 0x190}, + {DSI_PKT_LEN_6_7, 0x190}, + {DSI_HOST_CONTROL, 0}, +}; + +//Clock config. +static const cfg_op_t _display_config_6[3] = { + {0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE + {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 + {0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC +}; + +//DSI config. +static const cfg_op_t _display_config_7[10] = { + {DSI_TRIGGER, 0}, + {DSI_CONTROL, 0}, + {DSI_SOL_DELAY, 6}, + {DSI_MAX_THRESHOLD, 0x1E0}, + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} +}; + +//MIPI CAL config. +static const cfg_op_t _display_config_8[6] = { + {0x18, 0}, + {2, 0xF3F10000}, + {0x16, 1}, + {0x18, 0}, + {0x18, 0x10010}, + {0x17, 0x300} +}; + +//DSI config. +static const cfg_op_t _display_config_9[4] = { + {DSI_PAD_CONTROL_1, 0}, + {DSI_PAD_CONTROL_2, 0}, + {DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, + {DSI_PAD_CONTROL_4, 0} +}; + +//MIPI CAL config. +static const cfg_op_t _display_config_10[16] = { + {0xE, 0x200200}, + {0xF, 0x200200}, + {0x19, 0x200002}, + {0x1A, 0x200002}, + {5, 0}, + {6, 0}, + {7, 0}, + {8, 0}, + {9, 0}, + {0xA, 0}, + {0x10, 0}, + {0x11, 0}, + {0x1A, 0}, + {0x1C, 0}, + {0x1D, 0}, + {0, 0x2A000001} +}; + +//Display A config. +static const cfg_op_t _display_config_11[113] = { + {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_DV_CONTROL, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + /* Setup default YUV colorspace conversion coefficients */ + {DC_WIN_CSC_YOF, 0xF0}, + {DC_WIN_CSC_KYRGB, 0x12A}, + {DC_WIN_CSC_KUR, 0}, + {DC_WIN_CSC_KVR, 0x198}, + {DC_WIN_CSC_KUG, 0x39B}, + {DC_WIN_CSC_KVG, 0x32F}, + {DC_WIN_CSC_KUB, 0x204}, + {DC_WIN_CSC_KVB, 0}, + /* End of color coefficients */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, + {0x4E4, 0}, + {DC_COM_CRC_CONTROL, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {0x716, 0x10000FF}, + {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_COMMAND, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, + {DC_CMD_STATE_ACCESS, 0}, + /* Set Display timings */ + {DC_DISP_DISP_TIMING_OPTIONS, 0}, + {DC_DISP_REF_TO_SYNC, (1 << 16)}, // h_ref_to_sync = 0, v_ref_to_sync = 1. + {DC_DISP_SYNC_WIDTH, 0x10048}, + {DC_DISP_BACK_PORCH, 0x90048}, + {DC_DISP_ACTIVE, 0x50002D0}, + {DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should be above the DC_DISP_ACTIVE cmd. + /* End of Display timings */ + {DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, + {DC_COM_PIN_OUTPUT_ENABLE(1), 0}, + {DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, + {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, + {DC_DISP_DISP_CLOCK_CONTROL, 0}, + {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, + {DC_DISP_FRONT_PORCH, 0xA0088}, + {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_STATE_ACCESS, 0}, + {DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, + {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, + {DC_CMD_DISPLAY_COMMAND_OPTION0, 0} +}; + +////Display A config. +static const cfg_op_t _display_config_12[17] = { + {DC_DISP_FRONT_PORCH, 0xA0088}, + {DC_CMD_INT_MASK, 0}, + {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_INT_ENABLE, 0}, + {DC_CMD_CONT_SYNCPT_VSYNC, 0}, + {DC_CMD_DISPLAY_COMMAND, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + {DC_CMD_DISPLAY_POWER_CONTROL, 0}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, +}; + +//DSI config. +static const cfg_op_t _display_config_13[16] = { + {DSI_POWER_CONTROL, 0}, + {DSI_PAD_CONTROL_1, 0}, + {DSI_PHY_TIMING_0, 0x6070601}, + {DSI_PHY_TIMING_1, 0x40A0E05}, + {DSI_PHY_TIMING_2, 0x30109}, + {DSI_BTA_TIMING, 0x190A14}, + {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TO_TALLY, 0}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, + {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, + {DSI_MAX_THRESHOLD, 0x40}, + {DSI_TRIGGER, 0}, + {DSI_TX_CRC, 0}, + {DSI_INIT_SEQ_CONTROL, 0} +}; + +//DSI config (if ver == 0x10). +static const cfg_op_t _display_config_14[22] = { + {DSI_WR_DATA, 0x439}, + {DSI_WR_DATA, 0x9483FFB9}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x2139}, + {DSI_WR_DATA, 0x191919D5}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19191919}, + {DSI_WR_DATA, 0x19}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0xB39}, + {DSI_WR_DATA, 0x4F0F41B1}, + {DSI_WR_DATA, 0xF179A433}, + {DSI_WR_DATA, 0x2D81}, + {DSI_TRIGGER, DSI_TRIGGER_HOST}, + {DSI_WR_DATA, 0x439}, + {DSI_WR_DATA, 0xB9}, + {DSI_TRIGGER, DSI_TRIGGER_HOST} +}; + +//Display A config. +static const cfg_op_t cfg_display_one_color[8] = { + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} //DISPLAY_CTRL_MODE: continuous display. +}; + +//Display A config. +static const cfg_op_t cfg_display_framebuffer[32] = { + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, //Enable window C. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, //Enable window B. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, //Enable window A. + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, //T_A8R8G8B8 //NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8 + {DC_WIN_WIN_OPTIONS, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_WIN_POSITION, 0}, //(0,0) + {DC_WIN_H_INITIAL_DDA, 0}, + {DC_WIN_V_INITIAL_DDA, 0}, + {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, //Pre-scaled size: 1280x2880 bytes. + {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, + {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, //Window size: 1280 vertical lines x 720 horizontal pixels. + {DC_WIN_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_BUFFER_CONTROL, 0}, + {DC_WINBUF_SURFACE_KIND, 0}, //Regular surface. + {DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address. + {DC_WINBUF_ADDR_H_OFFSET, 0}, + {DC_WINBUF_ADDR_V_OFFSET, 0}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, //DSI_ENABLE + {DC_WIN_WIN_OPTIONS, WIN_ENABLE}, //Enable window AD. + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, //DISPLAY_CTRL_MODE: continuous display. + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, //General update; window A update. + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} //General activation request; window A activation request. +}; diff --git a/fusee/fusee-secondary/src/flow.h b/fusee/fusee-secondary/src/flow.h index 65b9a2359..b3128d55e 100644 --- a/fusee/fusee-secondary/src/flow.h +++ b/fusee/fusee-secondary/src/flow.h @@ -1,44 +1,15 @@ #ifndef FUSEE_FLOW_CTLR_H #define FUSEE_FLOW_CTLR_H -#include "utils.h" +#include -#define FLOW_BASE 0x60007000 - -#define MAKE_FLOW_REG(ofs) MAKE_REG32(FLOW_BASE + ofs) +#define FLOW_CTLR_BASE 0x60007000 +#define MAKE_FLOW_REG(ofs) MAKE_REG32(FLOW_CTLR_BASE + ofs) #define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004) +#define FLOW_CTLR_RAM_REPAIR_0 MAKE_FLOW_REG(0x040) #define FLOW_CTLR_FLOW_DBG_QUAL_0 MAKE_FLOW_REG(0x050) #define FLOW_CTLR_L2FLUSH_CONTROL_0 MAKE_FLOW_REG(0x094) #define FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 MAKE_FLOW_REG(0x098) - -static const struct { - unsigned int CPUN_CSR_OFS; - unsigned int HALT_CPUN_EVENTS_OFS; - unsigned int CC4_COREN_CTRL_OFS; -} g_flow_core_offsets[NUM_CPU_CORES] = { - {0x008, 0x000, 0x06C}, - {0x018, 0x014, 0x070}, - {0x020, 0x01C, 0x074}, - {0x028, 0x024, 0x078}, -}; - -static inline void flow_set_cc4_ctrl(uint32_t core, uint32_t cc4_ctrl) { - MAKE_FLOW_REG(g_flow_core_offsets[core].CC4_COREN_CTRL_OFS) = cc4_ctrl; -} - -static inline void flow_set_halt_events(uint32_t core, bool halt_events) { - MAKE_FLOW_REG(g_flow_core_offsets[core].HALT_CPUN_EVENTS_OFS) = (halt_events ? 0x40000F00 : 0x40000000); -} - -static inline void flow_set_csr(uint32_t core, uint32_t csr) { - MAKE_FLOW_REG(g_flow_core_offsets[core].CPUN_CSR_OFS) = (0x100 << core) | (csr << 12) | 0xC001; -} - -static inline void flow_clear_csr0_and_events(uint32_t core) { - MAKE_FLOW_REG(g_flow_core_offsets[core].CPUN_CSR_OFS) = 0; - MAKE_FLOW_REG(g_flow_core_offsets[core].HALT_CPUN_EVENTS_OFS) = 0; -} - #endif diff --git a/fusee/fusee-secondary/src/fuse.c b/fusee/fusee-secondary/src/fuse.c index 2bdfa3740..04780c9ce 100644 --- a/fusee/fusee-secondary/src/fuse.c +++ b/fusee/fusee-secondary/src/fuse.c @@ -2,7 +2,7 @@ #include #include -#include "hwinit.h" +#include "car.h" #include "fuse.h" #include "timers.h" @@ -13,154 +13,155 @@ void fuse_enable_power(void); void fuse_disable_power(void); void fuse_wait_idle(void); -/* Initialize the FUSE driver */ -void fuse_init(void) -{ - /* - Already done by hwinit, except maybe fuse_secondary_private_key_disable (?) - fuse_make_regs_visible(); - fuse_secondary_private_key_disable(); - fuse_disable_programming(); - */ +/* Initialize the fuse driver */ +void fuse_init(void) { + fuse_make_regs_visible(); + fuse_secondary_private_key_disable(); + fuse_disable_programming(); /* TODO: Overrides (iROM patches) and various reads happen here */ } /* Make all fuse registers visible */ -void fuse_make_regs_visible(void) -{ - clock_enable_fuse(1); +void fuse_make_regs_visible(void) { + clkrst_enable_fuse_regs(true); } /* Enable power to the fuse hardware array */ -void fuse_enable_power(void) -{ - FUSE_REGS->FUSE_PWR_GOOD_SW = 1; - wait(1); +void fuse_enable_power(void) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); + fuse->FUSE_PWR_GOOD_SW = 1; + udelay(1); } /* Disable power to the fuse hardware array */ -void fuse_disable_power(void) -{ - FUSE_REGS->FUSE_PWR_GOOD_SW = 0; - wait(1); +void fuse_disable_power(void) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); + fuse->FUSE_PWR_GOOD_SW = 0; + udelay(1); } /* Wait for the fuse driver to go idle */ -void fuse_wait_idle(void) -{ +void fuse_wait_idle(void) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); uint32_t ctrl_val = 0; /* Wait for STATE_IDLE */ while ((ctrl_val & (0xF0000)) != 0x40000) { - wait(1); - ctrl_val = FUSE_REGS->FUSE_CTRL; + udelay(1); + ctrl_val = fuse->FUSE_CTRL; } } /* Read a fuse from the hardware array */ -uint32_t fuse_hw_read(uint32_t addr) -{ +uint32_t fuse_hw_read(uint32_t addr) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); fuse_wait_idle(); /* Program the target address */ - FUSE_REGS->FUSE_REG_ADDR = addr; + fuse->FUSE_REG_ADDR = addr; /* Enable read operation in control register */ - uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL; + uint32_t ctrl_val = fuse->FUSE_CTRL; ctrl_val &= ~0x3; ctrl_val |= 0x1; /* Set FUSE_READ command */ - FUSE_REGS->FUSE_CTRL = ctrl_val; + fuse->FUSE_CTRL = ctrl_val; fuse_wait_idle(); - return FUSE_REGS->FUSE_REG_READ; + return fuse->FUSE_REG_READ; } /* Write a fuse in the hardware array */ -void fuse_hw_write(uint32_t value, uint32_t addr) -{ +void fuse_hw_write(uint32_t value, uint32_t addr) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); fuse_wait_idle(); /* Program the target address and value */ - FUSE_REGS->FUSE_REG_ADDR = addr; - FUSE_REGS->FUSE_REG_WRITE = value; + fuse->FUSE_REG_ADDR = addr; + fuse->FUSE_REG_WRITE = value; /* Enable write operation in control register */ - uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL; + uint32_t ctrl_val = fuse->FUSE_CTRL; ctrl_val &= ~0x3; ctrl_val |= 0x2; /* Set FUSE_WRITE command */ - FUSE_REGS->FUSE_CTRL = ctrl_val; + fuse->FUSE_CTRL = ctrl_val; fuse_wait_idle(); } /* Sense the fuse hardware array into the shadow cache */ -void fuse_hw_sense(void) -{ +void fuse_hw_sense(void) { + volatile tegra_fuse_t *fuse = fuse_get_regs(); fuse_wait_idle(); /* Enable sense operation in control register */ - uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL; + uint32_t ctrl_val = fuse->FUSE_CTRL; ctrl_val &= ~0x3; ctrl_val |= 0x3; /* Set FUSE_SENSE command */ - FUSE_REGS->FUSE_CTRL = ctrl_val; + fuse->FUSE_CTRL = ctrl_val; fuse_wait_idle(); } /* Disables all fuse programming. */ void fuse_disable_programming(void) { - FUSE_REGS->FUSE_DIS_PGM = 1; + volatile tegra_fuse_t *fuse = fuse_get_regs(); + fuse->FUSE_DIS_PGM = 1; } /* Unknown exactly what this does, but it alters the contents read from the fuse cache. */ void fuse_secondary_private_key_disable(void) { - FUSE_REGS->FUSE_PRIVATEKEYDISABLE = 0x10; + volatile tegra_fuse_t *fuse = fuse_get_regs(); + fuse->FUSE_PRIVATEKEYDISABLE = 0x10; } /* Read the SKU info register from the shadow cache */ -uint32_t fuse_get_sku_info(void) -{ - return FUSE_CHIP_REGS->FUSE_SKU_INFO; +uint32_t fuse_get_sku_info(void) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + return fuse_chip->FUSE_SKU_INFO; } /* Read the bootrom patch version from a register in the shadow cache */ -uint32_t fuse_get_bootrom_patch_version(void) -{ - return FUSE_CHIP_REGS->FUSE_SOC_SPEEDO_1; +uint32_t fuse_get_bootrom_patch_version(void) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + return fuse_chip->FUSE_SOC_SPEEDO_1; } /* Read a spare bit register from the shadow cache */ -uint32_t fuse_get_spare_bit(uint32_t idx) -{ +uint32_t fuse_get_spare_bit(uint32_t idx) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + if (idx >= 32) { return 0; } - return FUSE_CHIP_REGS->FUSE_SPARE_BIT[idx]; + return fuse_chip->FUSE_SPARE_BIT[idx]; } /* Read a reserved ODM register from the shadow cache */ -uint32_t fuse_get_reserved_odm(uint32_t idx) -{ +uint32_t fuse_get_reserved_odm(uint32_t idx) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + if (idx >= 8) { return 0; } - return FUSE_CHIP_REGS->FUSE_RESERVED_ODM[idx]; + return fuse_chip->FUSE_RESERVED_ODM[idx]; } /* Derive the Device ID using values in the shadow cache */ uint64_t fuse_get_device_id(void) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + uint64_t device_id = 0; - uint64_t y_coord = FUSE_CHIP_REGS->FUSE_Y_COORDINATE & 0x1FF; - uint64_t x_coord = FUSE_CHIP_REGS->FUSE_X_COORDINATE & 0x1FF; - uint64_t wafer_id = FUSE_CHIP_REGS->FUSE_WAFER_ID & 0x3F; - uint32_t lot_code = FUSE_CHIP_REGS->FUSE_LOT_CODE_0; - uint64_t fab_code = FUSE_CHIP_REGS->FUSE_FAB_CODE & 0x3F; + uint64_t y_coord = fuse_chip->FUSE_Y_COORDINATE & 0x1FF; + uint64_t x_coord = fuse_chip->FUSE_X_COORDINATE & 0x1FF; + uint64_t wafer_id = fuse_chip->FUSE_WAFER_ID & 0x3F; + uint32_t lot_code = fuse_chip->FUSE_LOT_CODE_0; + uint64_t fab_code = fuse_chip->FUSE_FAB_CODE & 0x3F; uint64_t derived_lot_code = 0; for (unsigned int i = 0; i < 5; i++) { derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F); @@ -177,24 +178,27 @@ uint64_t fuse_get_device_id(void) { /* Get the DRAM ID using values in the shadow cache */ uint32_t fuse_get_dram_id(void) { - return (FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 3) & 0x7; + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + return (fuse_chip->FUSE_RESERVED_ODM[4] >> 3) & 0x7; } /* Derive the Hardware Type using values in the shadow cache */ uint32_t fuse_get_hardware_type(void) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + /* This function is very different between 4.x and < 4.x */ - uint32_t hardware_type = ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 7) & 2) | ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 2) & 1); + uint32_t hardware_type = ((fuse_chip->FUSE_RESERVED_ODM[4] >> 7) & 2) | ((fuse_chip->FUSE_RESERVED_ODM[4] >> 2) & 1); /* TODO: choose; if (mkey_get_revision() >= MASTERKEY_REVISION_400_CURRENT) { static const uint32_t types[] = {0,1,4,3}; - hardware_type |= (FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 14) & 0x3C; + hardware_type |= (fuse_chip->FUSE_RESERVED_ODM[4] >> 14) & 0x3C; hardware_type--; return hardware_type > 3 ? 4 : types[hardware_type]; } else {*/ if (hardware_type >= 1) { return hardware_type > 2 ? 3 : hardware_type - 1; - } else if ((FUSE_CHIP_REGS->FUSE_SPARE_BIT[9] & 1) == 0) { + } else if ((fuse_chip->FUSE_SPARE_BIT[9] & 1) == 0) { return 0; } else { return 3; @@ -204,8 +208,10 @@ uint32_t fuse_get_hardware_type(void) { /* Derive the Retail Type using values in the shadow cache */ uint32_t fuse_get_retail_type(void) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); + /* Retail type = IS_RETAIL | UNIT_TYPE */ - uint32_t retail_type = ((FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] >> 7) & 4) | (FUSE_CHIP_REGS->FUSE_RESERVED_ODM[4] & 3); + uint32_t retail_type = ((fuse_chip->FUSE_RESERVED_ODM[4] >> 7) & 4) | (fuse_chip->FUSE_RESERVED_ODM[4] & 3); if (retail_type == 4) { /* Standard retail unit, IS_RETAIL | 0. */ return 1; } else if (retail_type == 3) { /* Standard dev unit, 0 | DEV_UNIT. */ @@ -216,16 +222,17 @@ uint32_t fuse_get_retail_type(void) { /* Derive the 16-byte Hardware Info using values in the shadow cache, and copy to output buffer. */ void fuse_get_hardware_info(void *dst) { + volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs(); uint32_t hw_info[0x4]; - uint32_t unk_hw_fuse = FUSE_CHIP_REGS->_0x120 & 0x3F; - uint32_t y_coord = FUSE_CHIP_REGS->FUSE_Y_COORDINATE & 0x1FF; - uint32_t x_coord = FUSE_CHIP_REGS->FUSE_X_COORDINATE & 0x1FF; - uint32_t wafer_id = FUSE_CHIP_REGS->FUSE_WAFER_ID & 0x3F; - uint32_t lot_code_0 = FUSE_CHIP_REGS->FUSE_LOT_CODE_0; - uint32_t lot_code_1 = FUSE_CHIP_REGS->FUSE_LOT_CODE_1 & 0x0FFFFFFF; - uint32_t fab_code = FUSE_CHIP_REGS->FUSE_FAB_CODE & 0x3F; - uint32_t vendor_code = FUSE_CHIP_REGS->FUSE_VENDOR_CODE & 0xF; + uint32_t unk_hw_fuse = fuse_chip->_0x120 & 0x3F; + uint32_t y_coord = fuse_chip->FUSE_Y_COORDINATE & 0x1FF; + uint32_t x_coord = fuse_chip->FUSE_X_COORDINATE & 0x1FF; + uint32_t wafer_id = fuse_chip->FUSE_WAFER_ID & 0x3F; + uint32_t lot_code_0 = fuse_chip->FUSE_LOT_CODE_0; + uint32_t lot_code_1 = fuse_chip->FUSE_LOT_CODE_1 & 0x0FFFFFFF; + uint32_t fab_code = fuse_chip->FUSE_FAB_CODE & 0x3F; + uint32_t vendor_code = fuse_chip->FUSE_VENDOR_CODE & 0xF; /* Hardware Info = unk_hw_fuse || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */ hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (unk_hw_fuse)); diff --git a/fusee/fusee-secondary/src/fuse.h b/fusee/fusee-secondary/src/fuse.h index 989f564bf..63285b64f 100644 --- a/fusee/fusee-secondary/src/fuse.h +++ b/fusee/fusee-secondary/src/fuse.h @@ -1,6 +1,11 @@ #ifndef FUSEE_FUSE_H #define FUSEE_FUSE_H +#define FUSE_BASE 0x7000F800 +#define FUSE_CHIP_BASE (FUSE_BASE + 0x100) +#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n) +#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n) + typedef struct { uint32_t FUSE_CTRL; uint32_t FUSE_REG_ADDR; @@ -17,7 +22,7 @@ typedef struct { uint32_t FUSE_WRITE_ACCESS; uint32_t FUSE_PWR_GOOD_SW; uint32_t _0x38[0x32]; -} fuse_registers_t; +} tegra_fuse_t; typedef struct { uint32_t FUSE_PRODUCTION_MODE; @@ -160,17 +165,15 @@ typedef struct { uint32_t _0x278; uint32_t _0x27C; uint32_t FUSE_SPARE_BIT[0x20]; -} fuse_chip_registers_t; +} tegra_fuse_chip_t; -static inline volatile fuse_registers_t *get_fuse_regs(void) { - return (volatile fuse_registers_t *)(0x7000F000 + 0x800); +static inline volatile tegra_fuse_t *fuse_get_regs(void) { + return (volatile tegra_fuse_t *)FUSE_BASE; } -static inline volatile fuse_chip_registers_t *get_fuse_chip_regs(void) { - return (volatile fuse_chip_registers_t *)(0x7000F000 + 0x900); +static inline volatile tegra_fuse_chip_t *fuse_chip_get_regs(void) { + return (volatile tegra_fuse_chip_t *)FUSE_CHIP_BASE; } -#define FUSE_REGS (get_fuse_regs()) -#define FUSE_CHIP_REGS (get_fuse_chip_regs()) void fuse_init(void); diff --git a/fusee/fusee-secondary/src/gpio.h b/fusee/fusee-secondary/src/gpio.h index b3da7dc56..a916c989c 100644 --- a/fusee/fusee-secondary/src/gpio.h +++ b/fusee/fusee-secondary/src/gpio.h @@ -1,6 +1,11 @@ #ifndef FUSEE_GPIO_H #define FUSEE_GPIO_H +#include + +#define GPIO_BASE 0x6000D000 +#define MAKE_GPIO_REG(n) MAKE_REG32(GPIO_BASE + n) + #define TEGRA_GPIO_PORTS 4 #define TEGRA_GPIO_BANKS 8 #define GPIO_BANK_SHIFT 5 @@ -68,7 +73,7 @@ typedef struct { static inline volatile tegra_gpio_t *gpio_get_regs(void) { - return (volatile tegra_gpio_t *)0x6000D000; + return (volatile tegra_gpio_t *)GPIO_BASE; } #define TEGRA_GPIO(port, offset) \ @@ -87,9 +92,16 @@ static inline volatile tegra_gpio_t *gpio_get_regs(void) #define GPIO_LEVEL_HIGH 1 /* Named GPIOs */ +#define GPIO_BUTTON_VOL_DOWN TEGRA_GPIO(X, 7) +#define GPIO_BUTTON_VOL_UP TEGRA_GPIO(X, 6) #define GPIO_MICROSD_CARD_DETECT TEGRA_GPIO(Z, 1) #define GPIO_MICROSD_WRITE_PROTECT TEGRA_GPIO(Z, 4) #define GPIO_MICROSD_SUPPLY_ENABLE TEGRA_GPIO(E, 4) +#define GPIO_LCD_BL_P5V TEGRA_GPIO(I, 0) +#define GPIO_LCD_BL_N5V TEGRA_GPIO(I, 1) +#define GPIO_LCD_BL_PWM TEGRA_GPIO(V, 0) +#define GPIO_LCD_BL_EN TEGRA_GPIO(V, 1) +#define GPIO_LCD_BL_RST TEGRA_GPIO(V, 2) void gpio_configure_mode(uint32_t pin, uint32_t mode); void gpio_configure_direction(uint32_t pin, uint32_t dir); diff --git a/fusee/fusee-secondary/src/hwinit.h b/fusee/fusee-secondary/src/hwinit.h deleted file mode 100644 index 1d4a47299..000000000 --- a/fusee/fusee-secondary/src/hwinit.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef FUSEE_HWINIT_H -#define FUSEE_HWINIT_H - -/* Symbols from hwinit that we're using, but w/o importing macro definitions that may clash with ours */ - -#include "hwinit/types.h" -#include "hwinit/hwinit.h" -#include "hwinit/i2c.h" - -#include - -#define UART_A 0 -#define UART_B 1 -#define UART_C 2 -#define BAUD_115200 115200 - -void uart_init(u32 idx, u32 baud); -void uart_wait_idle(u32 idx, u32 which); -void uart_send(u32 idx, u8 *buf, u32 len); -void uart_recv(u32 idx, u8 *buf, u32 len); - -void display_init(); -void display_end(); - -void clock_enable_fuse(u32 enable); - -/*! Show one single color on the display. */ -void display_color_screen(u32 color); - -/*! Init display in full 1280x720 resolution (32bpp, line stride 768, framebuffer size = 1280*768*4 bytes). */ -u32 *display_init_framebuffer(void *address); - -/*! Enable or disable the backlight. Should only be called when the screen is completely set up, to avoid flickering. */ -void display_enable_backlight(bool on); - -void cluster_enable_cpu0(u64 entry, u32 ns_disable); - -void mc_enable_ahb_redirect(); - -int tsec_query(u32 carveout, u8 *dst, u32 rev); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/btn.c b/fusee/fusee-secondary/src/hwinit/btn.c deleted file mode 100644 index 50bf1b37d..000000000 --- a/fusee/fusee-secondary/src/hwinit/btn.c +++ /dev/null @@ -1,25 +0,0 @@ -#include "btn.h" -#include "i2c.h" -#include "t210.h" - -u32 btn_read() -{ - u32 res = 0; - if(!(GPIO_6(0x3C) & 0x80)) - res |= BTN_VOL_DOWN; - if(!(GPIO_6(0x3C) & 0x40)) - res |= BTN_VOL_UP; - if(i2c_recv_byte(4, 0x3C, 0x15) & 0x4) - res |= BTN_POWER; - return res; -} - -u32 btn_wait() -{ - u32 res = 0, btn = btn_read(); - do - { - res = btn_read(); - } while (btn == res); - return res; -} diff --git a/fusee/fusee-secondary/src/hwinit/btn.h b/fusee/fusee-secondary/src/hwinit/btn.h deleted file mode 100644 index 7ae7af9e7..000000000 --- a/fusee/fusee-secondary/src/hwinit/btn.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _BTN_H_ -#define _BTN_H_ - -#include "types.h" - -#define BTN_POWER 0x1 -#define BTN_VOL_DOWN 0x2 -#define BTN_VOL_UP 0x4 - -u32 btn_read(); -u32 btn_wait(); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/clock.c b/fusee/fusee-secondary/src/hwinit/clock.c deleted file mode 100644 index b0b4ab93b..000000000 --- a/fusee/fusee-secondary/src/hwinit/clock.c +++ /dev/null @@ -1,145 +0,0 @@ -#include "clock.h" -#include "t210.h" -#include "util.h" - -static const clock_t _clock_uart[] = { - /* UART A */ { 4, 0x10, 0x178, 6, 0, 0 }, - /* UART B */ { 4, 0x10, 0x17C, 7, 0, 0 }, - /* UART C */ { 8, 0x14, 0x1A0, 0x17, 0, 0 }, - /* UART D */ { 0 }, - /* UART E */ { 0 } -}; - -static const clock_t _clock_i2c[] = { - /* I2C1 */ { 4, 0x10, 0x124, 0xC, 6, 0 }, - /* I2C2 */ { 0 }, - /* I2C3 */ { 0 }, - /* I2C4 */ { 0 }, - /* I2C5 */ { 8, 0x14, 0x128, 0xF, 6, 0 }, - /* I2C6 */ { 0 } -}; - -static clock_t _clock_se = { 0x358, 0x360, 0x42C, 0x1F, 0, 0 }; - -static clock_t _clock_host1x = { 4, 0x10, 0x180, 0x1C, 4, 3 }; -static clock_t _clock_tsec = { 0xC, 0x18, 0x1F4, 0x13, 0, 2 }; -static clock_t _clock_sor_safe = { 0x2A4, 0x298, 0, 0x1E, 0, 0 }; -static clock_t _clock_sor0 = { 0x28C, 0x280, 0, 0x16, 0, 0 }; -static clock_t _clock_sor1 = { 0x28C, 0x280, 0x410, 0x17, 0, 2 }; -static clock_t _clock_kfuse = { 8, 0x14, 0, 8, 0, 0 }; - -static clock_t _clock_coresight = { 0xC, 0x18, 0x1D4, 9, 0, 4}; - -void clock_enable(const clock_t *clk) -{ - //Put clock into reset. - CLOCK(clk->reset) = CLOCK(clk->reset) & ~(1 << clk->index) | (1 << clk->index); - //Disable. - CLOCK(clk->enable) &= ~(1 << clk->index); - //Configure clock source if required. - if (clk->source) - CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29); - //Enable. - CLOCK(clk->enable) = CLOCK(clk->enable) & ~(1 << clk->index) | (1 << clk->index); - //Take clock off reset. - CLOCK(clk->reset) &= ~(1 << clk->index); -} - -void clock_disable(const clock_t *clk) -{ - //Put clock into reset. - CLOCK(clk->reset) = CLOCK(clk->reset) & ~(1 << clk->index) | (1 << clk->index); - //Disable. - CLOCK(clk->enable) &= ~(1 << clk->index); -} - -void clock_enable_fuse(u32 enable) -{ - CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF | ((enable & 1) << 28) & 0x10000000; -} - -void clock_enable_uart(u32 idx) -{ - clock_enable(&_clock_uart[idx]); -} - -void clock_enable_i2c(u32 idx) -{ - clock_enable(&_clock_i2c[idx]); -} - -void clock_enable_se() -{ - clock_enable(&_clock_se); -} - -void clock_enable_host1x() -{ - clock_enable(&_clock_host1x); -} - -void clock_enable_tsec() -{ - clock_enable(&_clock_tsec); -} - -void clock_enable_sor_safe() -{ - clock_enable(&_clock_sor_safe); -} - -void clock_enable_sor0() -{ - clock_enable(&_clock_sor0); -} - -void clock_enable_sor1() -{ - clock_enable(&_clock_sor1); -} - -void clock_enable_kfuse() -{ - //clock_enable(&_clock_kfuse); - CLOCK(0x8) = CLOCK(0x8) & 0xFFFFFEFF | 0x100; - CLOCK(0x14) &= 0xFFFFFEFF; - CLOCK(0x14) = CLOCK(0x14) & 0xFFFFFEFF | 0x100; - sleep(10); - CLOCK(0x8) &= 0xFFFFFEFF; - sleep(20); -} - -void clock_disable_host1x() -{ - clock_disable(&_clock_host1x); -} - -void clock_disable_tsec() -{ - clock_disable(&_clock_tsec); -} - -void clock_disable_sor_safe() -{ - clock_disable(&_clock_sor_safe); -} - -void clock_disable_sor0() -{ - clock_disable(&_clock_sor0); -} - -void clock_disable_sor1() -{ - clock_disable(&_clock_sor1); -} - -void clock_disable_kfuse() -{ - clock_disable(&_clock_kfuse); -} - -void clock_enable_coresight() -{ - clock_enable(&_clock_coresight); -} diff --git a/fusee/fusee-secondary/src/hwinit/clock.h b/fusee/fusee-secondary/src/hwinit/clock.h deleted file mode 100644 index 027fd4b26..000000000 --- a/fusee/fusee-secondary/src/hwinit/clock.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _CLOCK_H_ -#define _CLOCK_H_ - -#include "types.h" - -/*! Clock registers. */ -#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY 0x28 -#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2C -#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 -#define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48 -#define CLK_RST_CONTROLLER_OSC_CTRL 0x50 -#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C -#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284 -#define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308 -#define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328 -#define CLK_RST_CONTROLLER_RST_DEVICES_V 0x358 -#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454 -#define CLK_RST_CONTROLLER_SPARE_REG0 0x55C -#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8 - -typedef struct _clock_t -{ - u32 reset; - u32 enable; - u32 source; - u8 index; - u8 clk_src; - u8 clk_div; -} clock_t; - -void clock_enable(const clock_t *clk); -void clock_disable(const clock_t *clk); -void clock_enable_fuse(u32 enable); -void clock_enable_uart(u32 idx); -void clock_enable_i2c(u32 idx); -void clock_enable_se(); -void clock_enable_host1x(); -void clock_enable_tsec(); -void clock_enable_sor_safe(); -void clock_enable_sor0(); -void clock_enable_sor1(); -void clock_enable_kfuse(); -void clock_disable_host1x(); -void clock_disable_tsec(); -void clock_disable_sor_safe(); -void clock_disable_sor0(); -void clock_disable_sor1(); -void clock_disable_kfuse(); -void clock_enable_coresight(); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/cluster.c b/fusee/fusee-secondary/src/hwinit/cluster.c deleted file mode 100644 index 26f6e8d3e..000000000 --- a/fusee/fusee-secondary/src/hwinit/cluster.c +++ /dev/null @@ -1,117 +0,0 @@ -#include "cluster.h" -#include "i2c.h" -#include "clock.h" -#include "util.h" -#include "pmc.h" -#include "t210.h" - -void _cluster_enable_power() -{ - u8 tmp; - - if (i2c_recv_buf_small(&tmp, 1, I2C_5, 0x3C, 0x40)) - { - tmp &= 0xDFu; - i2c_send_byte(I2C_5, 0x3C, 0x40, tmp); - } - i2c_send_byte(I2C_5, 0x3C, 0x3B, 0x09); - - //Enable cores power. - i2c_send_byte(I2C_5, 0x1B, 0x02, 0x20); - i2c_send_byte(I2C_5, 0x1B, 0x03, 0x8D); - i2c_send_byte(I2C_5, 0x1B, 0x00, 0xB7); - i2c_send_byte(I2C_5, 0x1B, 0x01, 0xB7); -} - -int _cluster_pmc_enable_partition(u32 part, u32 toggle) -{ - //Check if the partition has already been turned on. - if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part) - return 0; - - u32 i = 5001; - while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100) - { - sleep(1); - i--; - if (i < 1) - return 0; - } - - PMC(APBDEV_PMC_PWRGATE_TOGGLE) = toggle | 0x100; - - i = 5001; - while (i > 0) - { - if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part) - break; - sleep(1); - i--; - } - - return 1; -} - -void cluster_enable_cpu0(u64 entry, u32 ns_disable) -{ - //Set ACTIVE_CLUSER to FAST. - FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= 0xFFFFFFFE; - - _cluster_enable_power(); - - if (!(CLOCK(0xE0) & 0x40000000)) - { - CLOCK(0x518) &= 0xFFFFFFF7; - sleep(2); - CLOCK(0xE0) = 0x80404E02; - CLOCK(0xE0) = 0x404E02; - CLOCK(0xE4) = CLOCK(0xE4) & 0xFFFBFFFF | 0x40000; - CLOCK(0xE0) = 0x40404E02; - } - while (!(CLOCK(0xE0) & 0x8000000)) - ; - - CLOCK(0x3B4) = CLOCK(0x3B4) & 0x1FFFFF00 | 6; - CLOCK(0x360) = CLOCK(0x360) & 0xFFFFFFF7 | 8; - CLOCK(0x20) = 0x20008888; - CLOCK(0x24) = 0x80000000; - CLOCK(0x440) = 1; - - clock_enable_coresight(); - - CLOCK(0x388) = CLOCK(0x388) & 0xFFFFF000; - - //Enable CPU rail. - _cluster_pmc_enable_partition(1, 0); - //Enable cluster 0 non-CPU. - _cluster_pmc_enable_partition(0x8000, 15); - //Enable CE0. - _cluster_pmc_enable_partition(0x4000, 14); - - //Request and wait for RAM repair. - FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1; - while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2)) - ; - - EXCP_VEC(0x100) = 0; - - if(ns_disable) - { - //Set reset vectors. - SB(SB_AA64_RESET_LOW) = (u32)entry | 1; - SB(SB_AA64_RESET_HIGH) = (u32)(entry >> 32); - //Non-secure reset vector write disable. - SB(SB_CSR_0) = 2; - } - else - { - //Set reset vectors. - SB(SB_AA64_RESET_LOW) = (u32)entry; - SB(SB_AA64_RESET_HIGH) = (u32)(entry >> 32); - } - - //Until here the CPU was in reset, this kicks execution. - CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7; - CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000; - CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x411F000F; -} diff --git a/fusee/fusee-secondary/src/hwinit/cluster.h b/fusee/fusee-secondary/src/hwinit/cluster.h deleted file mode 100644 index 41ae68f52..000000000 --- a/fusee/fusee-secondary/src/hwinit/cluster.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _CLUSTER_H_ -#define _CLUSTER_H_ - -#include "types.h" - -/*! Flow controller registers. */ -#define FLOW_CTLR_RAM_REPAIR 0x40 -#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98 - -void cluster_enable_cpu0(u64 entry, u32 ns_disable); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/di.c b/fusee/fusee-secondary/src/hwinit/di.c deleted file mode 100644 index a168f8dc4..000000000 --- a/fusee/fusee-secondary/src/hwinit/di.c +++ /dev/null @@ -1,209 +0,0 @@ -#include "di.h" -#include "t210.h" -#include "util.h" -#include "i2c.h" -#include "pmc.h" - -#include "di.inl" - -static u32 _display_ver = 0; - -static void _display_dsi_wait(u32 timeout, u32 off, u32 mask) -{ - u32 end = TMR(0x10) + timeout; - while (TMR(0x10) < end && DSI(off) & mask) - ; - sleep(5); -} - -void display_init() -{ - //Power on. - i2c_send_byte(I2C_5, 0x3C, 0x23, 0xD0); - i2c_send_byte(I2C_5, 0x3C, 0x3D, 0x09); - - //Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. - CLOCK(0x30C) = 0x1010000; - CLOCK(0x328) = 0x1010000; - CLOCK(0x304) = 0x18000000; - CLOCK(0x320) = 0x18000000; - CLOCK(0x284) = 0x20000; - CLOCK(0x66C) = 0xA; - CLOCK(0x448) = 0x80000; - CLOCK(0x620) = 0xA; - - //DPD idle. - PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000; - PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000; - - //Config pins. - PINMUX_AUX(0x1D0) &= 0xFFFFFFEF; - PINMUX_AUX(0x1D4) &= 0xFFFFFFEF; - PINMUX_AUX(0x1FC) &= 0xFFFFFFEF; - PINMUX_AUX(0x200) &= 0xFFFFFFEF; - PINMUX_AUX(0x204) &= 0xFFFFFFEF; - - GPIO_3(0x00) = GPIO_3(0x00) & 0xFFFFFFFC | 0x3; - GPIO_3(0x10) = GPIO_3(0x10) & 0xFFFFFFFC | 0x3; - GPIO_3(0x20) = GPIO_3(0x20) & 0xFFFFFFFE | 0x1; - - sleep(10000u); - - GPIO_3(0x20) = GPIO_3(0x20) & 0xFFFFFFFD | 0x2; - - sleep(10000); - - GPIO_6(0x04) = GPIO_6(0x04) & 0xFFFFFFF8 | 0x7; - GPIO_6(0x14) = GPIO_6(0x14) & 0xFFFFFFF8 | 0x7; - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFD | 0x2; - - //Config display interface and display. - MIPI_CAL(0x60) = 0; - - exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4); - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94); - exec_cfg((u32 *)DSI_BASE, _display_config_3, 60); - - sleep(10000); - - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFB | 0x4; - - sleep(60000); - - DSI(_DSIREG(DSI_DSI_BTA_TIMING)) = 0x50204; - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x337; - DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; - _display_dsi_wait(250000, _DSIREG(DSI_DSI_TRIGGER), 3); - - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x406; - DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; - _display_dsi_wait(250000, _DSIREG(DSI_DSI_TRIGGER), 3); - - DSI(_DSIREG(DSI_HOST_DSI_CONTROL)) = 0x200B; - _display_dsi_wait(150000, _DSIREG(DSI_HOST_DSI_CONTROL), 8); - - sleep(5000); - - _display_ver = DSI(_DSIREG(DSI_DSI_RD_DATA)); - if (_display_ver == 0x10) - exec_cfg((u32 *)DSI_BASE, _display_config_4, 43); - - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x1105; - DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; - - sleep(180000); - - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x2905; - DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2; - - sleep(20000); - - exec_cfg((u32 *)DSI_BASE, _display_config_5, 21); - exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3); - DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4; - exec_cfg((u32 *)DSI_BASE, _display_config_7, 10); - - sleep(10000); - - exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6); - exec_cfg((u32 *)DSI_BASE, _display_config_9, 4); - exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16); - - sleep(10000); - - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113); -} - -void display_end() -{ - GPIO_6(0x24) &= 0xFFFFFFFE; - DSI(_DSIREG(DSI_DSI_VID_MODE_CONTROL)) = 1; - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x2805; - - u32 end = HOST1X(0x30A4) + 5; - while (HOST1X(0x30A4) < end) - ; - - DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = 5; - DSI(_DSIREG(DSI_DSI_VID_MODE_CONTROL)) = 0; - - exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17); - exec_cfg((u32 *)DSI_BASE, _display_config_13, 16); - - sleep(10000); - - if (_display_ver == 0x10) - exec_cfg((u32 *)DSI_BASE, _display_config_14, 22); - - DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x1005; - DSI(_DSIREG(DSI_DSI_TRIGGER)) = 2; - - sleep(50000); - - GPIO_6(0x24) &= 0xFFFFFFFB; - - sleep(10000); - - GPIO_3(0x20) &= 0xFFFFFFFD; - - sleep(10000); - - GPIO_3(0x20) = (GPIO_3(0x20) >> 1) << 1; - - sleep(10000); - - //Disable clocks. - CLOCK(0x308) = 0x1010000; - CLOCK(0x32C) = 0x1010000; - CLOCK(0x300) = 0x18000000; - CLOCK(0x324) = 0x18000000; - - DSI(_DSIREG(DSI_PAD_CONTROL)) = 0x10F010F; - DSI(_DSIREG(DSI_DSI_POWER_CONTROL)) = 0; - - GPIO_6(0x04) &= 0xFFFFFFFE; - - PINMUX_AUX(0x1FC) = PINMUX_AUX(0x1FC) & 0xFFFFFFEF | 0x10; - PINMUX_AUX(0x1FC) = (PINMUX_AUX(0x1FC) >> 2) << 2 | 1; -} - -void display_color_screen(u32 color) -{ - exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_one_color, 8); - - //Configure display to show single color. - DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0; - DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0; - DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0; - DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE | 1; - - sleep(35000); - - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFE | 1; -} - -void display_enable_backlight(bool on) { - GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFE | !!on; -} - - -u32 *display_init_framebuffer(void *address) -{ - static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0}; - if(conf[0].val == 0) { - for (u32 i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) { - conf[i] = cfg_display_framebuffer[i]; - } - } - - u32 *lfb_addr = (u32 *)address; - - conf[19].val = (u32)address; - //This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). - exec_cfg((u32 *)DISPLAY_A_BASE, conf, 32); - - sleep(35000); - - return lfb_addr; -} diff --git a/fusee/fusee-secondary/src/hwinit/di.h b/fusee/fusee-secondary/src/hwinit/di.h deleted file mode 100644 index 9d482e072..000000000 --- a/fusee/fusee-secondary/src/hwinit/di.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef _DI_H_ -#define _DI_H_ - -#include "types.h" -#include - -/*! Display registers. */ -#define _DIREG(reg) ((reg) * 4) -#define DC_CMD_DISPLAY_COMMAND 0x32 -#define DC_CMD_STATE_ACCESS 0x40 -#define DC_CMD_STATE_CONTROL 0x41 -#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42 -#define DC_DISP_DISP_WIN_OPTIONS 0x402 -#define DC_DISP_DISP_CLOCK_CONTROL 0x42E -#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4 -#define DC_WIN_AD_WIN_OPTIONS 0xB80 -#define DC_WIN_BD_WIN_OPTIONS 0xD80 -#define DC_WIN_CD_WIN_OPTIONS 0xF80 - -//The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER). -#define DC_X_WIN_XD_WIN_OPTIONS 0x700 -#define DC_X_WIN_XD_COLOR_DEPTH 0x703 -#define DC_X_WIN_XD_POSITION 0x704 -#define DC_X_WIN_XD_SIZE 0x705 -#define DC_X_WIN_XD_PRESCALED_SIZE 0x706 -#define DC_X_WIN_XD_H_INITIAL_DDA 0x707 -#define DC_X_WIN_XD_V_INITIAL_DDA 0x708 -#define DC_X_WIN_XD_DDA_INCREMENT 0x709 -#define DC_X_WIN_XD_LINE_STRIDE 0x70A - -//The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). -#define DC_X_WINBUF_XD_START_ADDR 0x800 -#define DC_X_WINBUF_XD_ADDR_H_OFFSET 0x806 -#define DC_X_WINBUF_XD_ADDR_V_OFFSET 0x808 -#define DC_X_WINBUF_XD_SURFACE_KIND 0x80B - -/*! Display serial interface registers. */ -#define _DSIREG(reg) ((reg) * 4) -#define DSI_DSI_RD_DATA 0x9 -#define DSI_DSI_WR_DATA 0xA -#define DSI_DSI_POWER_CONTROL 0xB -#define DSI_HOST_DSI_CONTROL 0xF -#define DSI_DSI_TRIGGER 0x13 -#define DSI_DSI_BTA_TIMING 0x3F -#define DSI_PAD_CONTROL 0x4B -#define DSI_DSI_VID_MODE_CONTROL 0x4E - -void display_init(); -void display_end(); - -/*! Show one single color on the display. */ -void display_color_screen(u32 color); - -/*! Init display in full 1280x720 resolution (32bpp, line stride 768, framebuffer size = 1280*768*4 bytes). */ -u32 *display_init_framebuffer(void *address); - -/*! Enable or disable the backlight. Should only be called when the screen is completely set up, to avoid flickering. */ -void display_enable_backlight(bool on); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/di.inl b/fusee/fusee-secondary/src/hwinit/di.inl deleted file mode 100644 index b2e6d1533..000000000 --- a/fusee/fusee-secondary/src/hwinit/di.inl +++ /dev/null @@ -1,532 +0,0 @@ -//Clock config. -static const cfg_op_t _display_config_1[4] = { - {0x4E, 0x40000000}, //CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 - {0x34, 0x4830A001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2D0AAA} //CLK_RST_CONTROLLER_PLLD_MISC -}; - -//Display A config. -static const cfg_op_t _display_config_2[94] = { - {0x40, 0}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0x43, 0x54}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0x42, 0x10}, - {0x42, 0x20}, - {0x42, 0x40}, - {0x480, 0}, - {0x403, 0}, - {0x404, 0}, - {0x36, 0x50155}, - {1, 0x100}, - {0x28, 0x109}, - {DC_CMD_STATE_CONTROL, 0xF00}, - {DC_CMD_STATE_CONTROL, 0xF}, - {0x40, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x10}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x10}, - {0x42, 0x10}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x20}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x20}, - {0x42, 0x20}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x42, 0x40}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x40}, - {0x42, 0x40}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x430, 8}, - {0x42F, 0}, - {0x307, 0x1000000}, - {0x309, 0}, - {0x4E4, 0}, - {0x300, 0}, - {DC_CMD_STATE_CONTROL, 0xF00}, - {DC_CMD_STATE_CONTROL, 0xF}, - {0x42, 0x10}, - {0x716, 0x10000FF}, - {0x42, 0x20}, - {0x716, 0x10000FF}, - {0x42, 0x40}, - {0x716, 0x10000FF}, - {0x31, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x402, 0}, - {0x32, 0}, - {DC_CMD_STATE_CONTROL, 0xF00}, - {DC_CMD_STATE_CONTROL, 0xF} -}; - -//DSI config. -static const cfg_op_t _display_config_3[60] = { - {0xA, 0}, - {0xC, 0}, - {0xD, 0}, - {0xE, 0}, - {0x1B, 0}, - {0x1C, 0}, - {0x1D, 0}, - {0x1E, 0}, - {0x33, 0}, - {0x23, 0}, - {0x25, 0}, - {0x27, 0}, - {0x29, 0}, - {0x2B, 0}, - {0x2D, 0}, - {0x24, 0}, - {0x26, 0}, - {0x28, 0}, - {0x2A, 0}, - {0x2C, 0}, - {0x2E, 0}, - {0x10, 0}, - {0x4C, 0}, - {0x11, 0x18}, - {0x12, 0x1E0}, - {0x13, 0}, - {0x1A, 0}, - {0x34, 0}, - {0x35, 0}, - {0x36, 0}, - {0x37, 0}, - {0x4F, 0}, - {0x3C, 0x6070601}, - {0x3D, 0x40A0E05}, - {0x3E, 0x30109}, - {0x3F, 0x190A14}, - {0x44, 0x2000FFFF}, - {0x45, 0x7652000}, - {0x46, 0}, - {0x4B, 0}, - {DSI_DSI_POWER_CONTROL, 1}, - {DSI_DSI_POWER_CONTROL, 1}, - {DSI_DSI_POWER_CONTROL, 0}, - {DSI_DSI_POWER_CONTROL, 0}, - {0x4F, 0}, - {0x3C, 0x6070601}, - {0x3D, 0x40A0E05}, - {0x3E, 0x30118}, - {0x3F, 0x190A14}, - {0x44, 0x2000FFFF}, - {0x45, 0x13432000}, - {0x46, 0}, - {0xF, 0x102003}, - {0x10, 0x31}, - {DSI_DSI_POWER_CONTROL, 1}, - {DSI_DSI_POWER_CONTROL, 1}, - {0x12, 0x40}, - {0x13, 0}, - {0x14, 0}, - {0x1A, 0} -}; - -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_4[43] = { - {DSI_DSI_WR_DATA, 0x439}, - {DSI_DSI_WR_DATA, 0x9483FFB9}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0xBD15}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x1939}, - {DSI_DSI_WR_DATA, 0xAAAAAAD8}, - {DSI_DSI_WR_DATA, 0xAAAAAAEB}, - {DSI_DSI_WR_DATA, 0xAAEBAAAA}, - {DSI_DSI_WR_DATA, 0xAAAAAAAA}, - {DSI_DSI_WR_DATA, 0xAAAAAAEB}, - {DSI_DSI_WR_DATA, 0xAAEBAAAA}, - {DSI_DSI_WR_DATA, 0xAA}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x1BD15}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x2739}, - {DSI_DSI_WR_DATA, 0xFFFFFFD8}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFF}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x2BD15}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0xF39}, - {DSI_DSI_WR_DATA, 0xFFFFFFD8}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFFFF}, - {DSI_DSI_WR_DATA, 0xFFFFFF}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0xBD15}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x6D915}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x439}, - {DSI_DSI_WR_DATA, 0xB9}, - {DSI_DSI_TRIGGER, 2} -}; - -//DSI config. -static const cfg_op_t _display_config_5[21] = { - {0x4F, 0}, - {0x3C, 0x6070601}, - {0x3D, 0x40A0E05}, - {0x3E, 0x30172}, - {0x3F, 0x190A14}, - {0x44, 0x20000A40}, - {0x45, 0x5A2F2000}, - {0x46, 0}, - {0x23, 0x40000208}, - {0x27, 0x40000308}, - {0x2B, 0x40000308}, - {0x25, 0x40000308}, - {0x29, 0x3F3B2B08}, - {0x2A, 0x2CC}, - {0x2D, 0x3F3B2B08}, - {0x2E, 0x2CC}, - {0x34, 0xCE0000}, - {0x35, 0x87001A2}, - {0x36, 0x190}, - {0x37, 0x190}, - {0xF, 0}, -}; - -//Clock config. -static const cfg_op_t _display_config_6[3] = { - {0x34, 0x4810C001}, //CLK_RST_CONTROLLER_PLLD_BASE - {0x36, 0x20}, //CLK_RST_CONTROLLER_PLLD_MISC1 - {0x37, 0x2DFC00} //CLK_RST_CONTROLLER_PLLD_MISC -}; - -//DSI config. -static const cfg_op_t _display_config_7[10] = { - {0x13, 0}, - {0x10, 0}, - {0x11, 6}, - {0x12, 0x1E0}, - {DSI_DSI_POWER_CONTROL, 1}, - {0x10, 0x103032}, - {0xF, 0x33}, - {0x10, 0x103032}, - {0xF, 3}, - {0xF, 0x23} -}; - -//MIPI CAL config. -static const cfg_op_t _display_config_8[6] = { - {0x18, 0}, - {2, 0xF3F10000}, - {0x16, 1}, - {0x18, 0}, - {0x18, 0x10010}, - {0x17, 0x300} -}; - -//DSI config. -static const cfg_op_t _display_config_9[4] = { - {0x4F, 0}, - {0x50, 0}, - {0x51, 0x3333}, - {0x52, 0} -}; - -//MIPI CAL config. -static const cfg_op_t _display_config_10[16] = { - {0xE, 0x200200}, - {0xF, 0x200200}, - {0x19, 0x200002}, - {0x1A, 0x200002}, - {5, 0}, - {6, 0}, - {7, 0}, - {8, 0}, - {9, 0}, - {0xA, 0}, - {0x10, 0}, - {0x11, 0}, - {0x1A, 0}, - {0x1C, 0}, - {0x1D, 0}, - {0, 0x2A000001} -}; - -//Display A config. -static const cfg_op_t _display_config_11[113] = { - {0x40, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x10}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x10}, - {0x42, 0x10}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x20}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x20}, - {0x42, 0x20}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x42, 0x40}, - {0x70E, 0}, - {0x700, 0}, - {0x42, 0x40}, - {0x42, 0x40}, - {0x611, 0xF0}, - {0x612, 0x12A}, - {0x613, 0}, - {0x614, 0x198}, - {0x615, 0x39B}, - {0x616, 0x32F}, - {0x617, 0x204}, - {0x618, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x430, 8}, - {0x42F, 0}, - {0x307, 0x1000000}, - {0x309, 0}, - {0x4E4, 0}, - {0x300, 0}, - {DC_CMD_STATE_CONTROL, 0xF00}, - {DC_CMD_STATE_CONTROL, 0xF}, - {0x42, 0x10}, - {0x716, 0x10000FF}, - {0x42, 0x20}, - {0x716, 0x10000FF}, - {0x42, 0x40}, - {0x716, 0x10000FF}, - {0x31, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x402, 0}, - {0x32, 0}, - {DC_CMD_STATE_CONTROL, 0xF00}, - {DC_CMD_STATE_CONTROL, 0xF}, - {0x40, 0}, - {0x405, 0}, - {0x406, 0x10000}, - {0x407, 0x10048}, - {0x408, 0x90048}, - {0x409, 0x50002D0}, - {0x40A, 0xA0088}, - {0x431, 0x10001}, - {0x303, 0}, - {0x432, 5}, - {0x42F, 0}, - {0x42E, 0}, - {0x31, 0}, - {0x42, 0x10}, - {0x700, 0}, - {0x42, 0x20}, - {0x700, 0}, - {0x42, 0x40}, - {0x700, 0}, - {0x402, 0}, - {0x32, 0x20}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0x40, 5}, - {0x40A, 0xA0088}, - {0x40, 0}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0, 0x301}, - {0, 0x301}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0x40, 0}, - {0x42E, 4}, - {0x430, 8}, - {0x31, 0} -}; - -////Display A config. -static const cfg_op_t _display_config_12[17] = { - {0x40A, 0xA0088}, - {0x38, 0}, - {0x40, 0}, - {0x39, 0}, - {0x28, 0}, - {0x32, 0}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0, 0x301}, - {0, 0x301}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1}, - {0x36, 0}, - {DC_CMD_STATE_CONTROL, 0x100}, - {DC_CMD_STATE_CONTROL, 1} -}; - -//DSI config. -static const cfg_op_t _display_config_13[16] = { - {DSI_DSI_POWER_CONTROL, 0}, - {0x4F, 0}, - {0x3C, 0x6070601}, - {0x3D, 0x40A0E05}, - {0x3E, 0x30109}, - {0x3F, 0x190A14}, - {0x44, 0x2000FFFF}, - {0x45, 0x7652000}, - {0x46, 0}, - {0xF, 0x102003}, - {0x10, 0x31}, - {DSI_DSI_POWER_CONTROL, 1}, - {0x12, 0x40}, - {0x13, 0}, - {0x14, 0}, - {0x1A, 0} -}; - -//DSI config (if ver == 0x10). -static const cfg_op_t _display_config_14[22] = { - {DSI_DSI_WR_DATA, 0x439}, - {DSI_DSI_WR_DATA, 0x9483FFB9}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x2139}, - {DSI_DSI_WR_DATA, 0x191919D5}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19191919}, - {DSI_DSI_WR_DATA, 0x19}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0xB39}, - {DSI_DSI_WR_DATA, 0x4F0F41B1}, - {DSI_DSI_WR_DATA, 0xF179A433}, - {DSI_DSI_WR_DATA, 0x2D81}, - {DSI_DSI_TRIGGER, 2}, - {DSI_DSI_WR_DATA, 0x439}, - {DSI_DSI_WR_DATA, 0xB9}, - {DSI_DSI_TRIGGER, 2} -}; - -//Display A config. -static const cfg_op_t cfg_display_one_color[8] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x10}, //Enable window A. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x20}, //Enable window B. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x40}, //Enable window C. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE - {DC_CMD_DISPLAY_COMMAND, 0x20} //DISPLAY_CTRL_MODE: continuous display. -}; - -//Display A config. -static const cfg_op_t cfg_display_framebuffer[32] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x40}, //Enable window C. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x20}, //Enable window B. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, 0x10}, //Enable window A. - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE - {DC_X_WIN_XD_COLOR_DEPTH, 0xD}, //T_A8B8G8R8 - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_X_WIN_XD_POSITION, 0}, //(0,0) - {DC_X_WIN_XD_H_INITIAL_DDA, 0}, - {DC_X_WIN_XD_V_INITIAL_DDA, 0}, - {DC_X_WIN_XD_PRESCALED_SIZE, 0x5000B40}, //Pre-scaled size: 1280x2880 bytes (= 0x500 vertical lines x 0xB40 bytes). - {DC_X_WIN_XD_DDA_INCREMENT, 0x10001000}, - {DC_X_WIN_XD_SIZE, 0x50002D0}, //Window size: 1280x720 (= 0x500 vertical lines x 0x2D0 horizontal pixels). - {DC_X_WIN_XD_LINE_STRIDE, 0x6000C00}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. - {0x702, 0}, - {DC_X_WINBUF_XD_SURFACE_KIND, 0}, //Regular surface. - {DC_X_WINBUF_XD_START_ADDR, 0xC0000000}, //Framebuffer address. - {DC_X_WINBUF_XD_ADDR_H_OFFSET, 0}, - {DC_X_WINBUF_XD_ADDR_V_OFFSET, 0}, - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE - {DC_X_WIN_XD_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0x20000000}, //DSI_ENABLE - {DC_X_WIN_XD_WIN_OPTIONS, 0x40000000}, //Enable window AD. - {DC_CMD_DISPLAY_COMMAND, 0x20}, //DISPLAY_CTRL_MODE: continuous display. - {DC_CMD_STATE_CONTROL, 0x300}, //General update; window A update. - {DC_CMD_STATE_CONTROL, 3} //General activation request; window A activation request. -}; diff --git a/fusee/fusee-secondary/src/hwinit/emc.h b/fusee/fusee-secondary/src/hwinit/emc.h deleted file mode 100644 index ce134c2fe..000000000 --- a/fusee/fusee-secondary/src/hwinit/emc.h +++ /dev/null @@ -1,665 +0,0 @@ -/* -* arch/arm/mach-tegra/tegra21_emc.h -* -* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -* -*/ - -#ifndef _EMC_H_ -#define _EMC_H_ - -#define EMC_CONFIG_SAMPLE_DELAY 0x5f0 -#define EMC_CFG_UPDATE 0x5f4 -#define EMC_ADR_CFG 0x10 -#define EMC_REFCTRL 0x20 -#define EMC_PIN 0x24 -#define EMC_TIMING_CONTROL 0x28 -#define EMC_RC 0x2c -#define EMC_RFC 0x30 -#define EMC_RFCPB 0x590 -#define EMC_RAS 0x34 -#define EMC_RP 0x38 -#define EMC_R2W 0x3c -#define EMC_W2R 0x40 -#define EMC_R2P 0x44 -#define EMC_W2P 0x48 -#define EMC_CCDMW 0x5c0 -#define EMC_RD_RCD 0x4c -#define EMC_WR_RCD 0x50 -#define EMC_RRD 0x54 -#define EMC_REXT 0x58 -#define EMC_WDV 0x5c -#define EMC_QUSE 0x60 -#define EMC_QRST 0x64 -#define EMC_ISSUE_QRST 0x428 -#define EMC_QSAFE 0x68 -#define EMC_RDV 0x6c -#define EMC_REFRESH 0x70 -#define EMC_BURST_REFRESH_NUM 0x74 -#define EMC_PDEX2WR 0x78 -#define EMC_PDEX2RD 0x7c -#define EMC_PDEX2CKE 0x118 -#define EMC_PCHG2PDEN 0x80 -#define EMC_ACT2PDEN 0x84 -#define EMC_AR2PDEN 0x88 -#define EMC_RW2PDEN 0x8c -#define EMC_CKE2PDEN 0x11c -#define EMC_TXSR 0x90 -#define EMC_TCKE 0x94 -#define EMC_TFAW 0x98 -#define EMC_TRPAB 0x9c -#define EMC_TCLKSTABLE 0xa0 -#define EMC_TCLKSTOP 0xa4 -#define EMC_TREFBW 0xa8 -#define EMC_TPPD 0xac -#define EMC_PDEX2MRR 0xb4 -#define EMC_ODT_WRITE 0xb0 -#define EMC_WEXT 0xb8 -#define EMC_RFC_SLR 0xc0 -#define EMC_MRS_WAIT_CNT2 0xc4 -#define EMC_MRS_WAIT_CNT 0xc8 -#define EMC_MRS 0xcc -#define EMC_EMRS 0xd0 -#define EMC_REF 0xd4 -#define EMC_PRE 0xd8 -#define EMC_NOP 0xdc -#define EMC_SELF_REF 0xe0 -#define EMC_DPD 0xe4 -#define EMC_MRW 0xe8 -#define EMC_MRR 0xec -#define EMC_CMDQ 0xf0 -#define EMC_MC2EMCQ 0xf4 -#define EMC_FBIO_SPARE 0x100 -#define EMC_FBIO_CFG5 0x104 -#define EMC_CFG_RSV 0x120 -#define EMC_ACPD_CONTROL 0x124 -#define EMC_MPC 0x128 -#define EMC_EMRS2 0x12c -#define EMC_EMRS3 0x130 -#define EMC_MRW2 0x134 -#define EMC_MRW3 0x138 -#define EMC_MRW4 0x13c -#define EMC_MRW5 0x4a0 -#define EMC_MRW6 0x4a4 -#define EMC_MRW7 0x4a8 -#define EMC_MRW8 0x4ac -#define EMC_MRW9 0x4b0 -#define EMC_MRW10 0x4b4 -#define EMC_MRW11 0x4b8 -#define EMC_MRW12 0x4bc -#define EMC_MRW13 0x4c0 -#define EMC_MRW14 0x4c4 -#define EMC_MRW15 0x4d0 -#define EMC_CFG_SYNC 0x4d4 -#define EMC_CLKEN_OVERRIDE 0x140 -#define EMC_R2R 0x144 -#define EMC_W2W 0x148 -#define EMC_EINPUT 0x14c -#define EMC_EINPUT_DURATION 0x150 -#define EMC_PUTERM_EXTRA 0x154 -#define EMC_TCKESR 0x158 -#define EMC_TPD 0x15c -#define EMC_STAT_CONTROL 0x160 -#define EMC_STAT_STATUS 0x164 -#define EMC_STAT_DRAM_CLOCK_LIMIT_LO 0x19c -#define EMC_STAT_DRAM_CLOCK_LIMIT_HI 0x1a0 -#define EMC_STAT_DRAM_CLOCKS_LO 0x1a4 -#define EMC_STAT_DRAM_CLOCKS_HI 0x1a8 -#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO 0x1ac -#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI 0x1b0 -#define EMC_STAT_DRAM_DEV0_READ_CNT_LO 0x1b4 -#define EMC_STAT_DRAM_DEV0_READ_CNT_HI 0x1b8 -#define EMC_STAT_DRAM_DEV0_READ8_CNT_LO 0x1bc -#define EMC_STAT_DRAM_DEV0_READ8_CNT_HI 0x1c0 -#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO 0x1c4 -#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI 0x1c8 -#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_LO 0x1cc -#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_HI 0x1d0 -#define EMC_STAT_DRAM_DEV0_REF_CNT_LO 0x1d4 -#define EMC_STAT_DRAM_DEV0_REF_CNT_HI 0x1d8 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1dc -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e0 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1e4 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e8 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1ec -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f0 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1f4 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f8 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x1fc -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x200 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x204 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x208 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x20c -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x210 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x214 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x218 -#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_LO 0x21c -#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_HI 0x220 -#define EMC_STAT_DRAM_DEV0_DSR 0x224 -#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO 0x228 -#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI 0x22c -#define EMC_STAT_DRAM_DEV1_READ_CNT_LO 0x230 -#define EMC_STAT_DRAM_DEV1_READ_CNT_HI 0x234 -#define EMC_STAT_DRAM_DEV1_READ8_CNT_LO 0x238 -#define EMC_STAT_DRAM_DEV1_READ8_CNT_HI 0x23c -#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO 0x240 -#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI 0x244 -#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_LO 0x248 -#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_HI 0x24c -#define EMC_STAT_DRAM_DEV1_REF_CNT_LO 0x250 -#define EMC_STAT_DRAM_DEV1_REF_CNT_HI 0x254 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x258 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x25c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x260 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x264 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x268 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x26c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x270 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x274 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x278 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x27c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x280 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x284 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x288 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x28c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x290 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x294 -#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_LO 0x298 -#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_HI 0x29c -#define EMC_STAT_DRAM_DEV1_DSR 0x2a0 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc8c -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc90 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc94 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc98 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xc9c -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca0 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xca4 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca8 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcac -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb0 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcb4 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb8 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcbc -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc0 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcc4 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc8 -#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_LO 0xccc -#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI 0xcd0 -#define EMC_STAT_DRAM_IO_DSR 0xcd4 -#define EMC_AUTO_CAL_CONFIG 0x2a4 -#define EMC_AUTO_CAL_CONFIG2 0x458 -#define EMC_AUTO_CAL_CONFIG3 0x45c -#define EMC_AUTO_CAL_CONFIG4 0x5b0 -#define EMC_AUTO_CAL_CONFIG5 0x5b4 -#define EMC_AUTO_CAL_CONFIG6 0x5cc -#define EMC_AUTO_CAL_CONFIG7 0x574 -#define EMC_AUTO_CAL_CONFIG8 0x2dc -#define EMC_AUTO_CAL_VREF_SEL_0 0x2f8 -#define EMC_AUTO_CAL_VREF_SEL_1 0x300 -#define EMC_AUTO_CAL_INTERVAL 0x2a8 -#define EMC_AUTO_CAL_STATUS 0x2ac -#define EMC_AUTO_CAL_STATUS2 0x3d4 -#define EMC_AUTO_CAL_CHANNEL 0x464 -#define EMC_PMACRO_RX_TERM 0xc48 -#define EMC_PMACRO_DQ_TX_DRV 0xc70 -#define EMC_PMACRO_CA_TX_DRV 0xc74 -#define EMC_PMACRO_CMD_TX_DRV 0xc4c -#define EMC_PMACRO_AUTOCAL_CFG_0 0x700 -#define EMC_PMACRO_AUTOCAL_CFG_1 0x704 -#define EMC_PMACRO_AUTOCAL_CFG_2 0x708 -#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78 -#define EMC_PMACRO_ZCTRL 0xc44 -#define EMC_XM2COMPPADCTRL 0x30c -#define EMC_XM2COMPPADCTRL2 0x578 -#define EMC_XM2COMPPADCTRL3 0x2f4 -#define EMC_COMP_PAD_SW_CTRL 0x57c -#define EMC_REQ_CTRL 0x2b0 -#define EMC_EMC_STATUS 0x2b4 -#define EMC_CFG_2 0x2b8 -#define EMC_CFG_DIG_DLL 0x2bc -#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 -#define EMC_DIG_DLL_STATUS 0x2c4 -#define EMC_CFG_DIG_DLL_1 0x2c8 -#define EMC_RDV_MASK 0x2cc -#define EMC_WDV_MASK 0x2d0 -#define EMC_RDV_EARLY_MASK 0x2d4 -#define EMC_RDV_EARLY 0x2d8 -#define EMC_WDV_CHK 0x4e0 -#define EMC_ZCAL_INTERVAL 0x2e0 -#define EMC_ZCAL_WAIT_CNT 0x2e4 -#define EMC_ZCAL_MRW_CMD 0x2e8 -#define EMC_ZQ_CAL 0x2ec -#define EMC_SCRATCH0 0x324 -#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8 -#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc -#define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0 -#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8 -#define EMC_SEL_DPD_CTRL 0x3d8 -#define EMC_FDPD_CTRL_DQ 0x310 -#define EMC_FDPD_CTRL_CMD 0x314 -#define EMC_PRE_REFRESH_REQ_CNT 0x3dc -#define EMC_REFCTRL2 0x580 -#define EMC_FBIO_CFG7 0x584 -#define EMC_DATA_BRLSHFT_0 0x588 -#define EMC_DATA_BRLSHFT_1 0x58c -#define EMC_DQS_BRLSHFT_0 0x594 -#define EMC_DQS_BRLSHFT_1 0x598 -#define EMC_CMD_BRLSHFT_0 0x59c -#define EMC_CMD_BRLSHFT_1 0x5a0 -#define EMC_CMD_BRLSHFT_2 0x5a4 -#define EMC_CMD_BRLSHFT_3 0x5a8 -#define EMC_QUSE_BRLSHFT_0 0x5ac -#define EMC_QUSE_BRLSHFT_1 0x5b8 -#define EMC_QUSE_BRLSHFT_2 0x5bc -#define EMC_QUSE_BRLSHFT_3 0x5c4 -#define EMC_FBIO_CFG8 0x5c8 -#define EMC_CMD_MAPPING_CMD0_0 0x380 -#define EMC_CMD_MAPPING_CMD0_1 0x384 -#define EMC_CMD_MAPPING_CMD0_2 0x388 -#define EMC_CMD_MAPPING_CMD1_0 0x38c -#define EMC_CMD_MAPPING_CMD1_1 0x390 -#define EMC_CMD_MAPPING_CMD1_2 0x394 -#define EMC_CMD_MAPPING_CMD2_0 0x398 -#define EMC_CMD_MAPPING_CMD2_1 0x39c -#define EMC_CMD_MAPPING_CMD2_2 0x3a0 -#define EMC_CMD_MAPPING_CMD3_0 0x3a4 -#define EMC_CMD_MAPPING_CMD3_1 0x3a8 -#define EMC_CMD_MAPPING_CMD3_2 0x3ac -#define EMC_CMD_MAPPING_BYTE 0x3b0 -#define EMC_DYN_SELF_REF_CONTROL 0x3e0 -#define EMC_TXSRDLL 0x3e4 -#define EMC_CCFIFO_ADDR 0x3e8 -#define EMC_CCFIFO_DATA 0x3ec -#define EMC_CCFIFO_STATUS 0x3f0 -#define EMC_SWIZZLE_RANK0_BYTE0 0x404 -#define EMC_SWIZZLE_RANK0_BYTE1 0x408 -#define EMC_SWIZZLE_RANK0_BYTE2 0x40c -#define EMC_SWIZZLE_RANK0_BYTE3 0x410 -#define EMC_SWIZZLE_RANK1_BYTE0 0x418 -#define EMC_SWIZZLE_RANK1_BYTE1 0x41c -#define EMC_SWIZZLE_RANK1_BYTE2 0x420 -#define EMC_SWIZZLE_RANK1_BYTE3 0x424 -#define EMC_TR_TIMING_0 0x3b4 -#define EMC_TR_CTRL_0 0x3b8 -#define EMC_TR_CTRL_1 0x3bc -#define EMC_TR_DVFS 0x460 -#define EMC_SWITCH_BACK_CTRL 0x3c0 -#define EMC_TR_RDV 0x3c4 -#define EMC_TR_QPOP 0x3f4 -#define EMC_TR_RDV_MASK 0x3f8 -#define EMC_TR_QSAFE 0x3fc -#define EMC_TR_QRST 0x400 -#define EMC_IBDLY 0x468 -#define EMC_OBDLY 0x46c -#define EMC_TXDSRVTTGEN 0x480 -#define EMC_WE_DURATION 0x48c -#define EMC_WS_DURATION 0x490 -#define EMC_WEV 0x494 -#define EMC_WSV 0x498 -#define EMC_CFG_3 0x49c -#define EMC_CFG_PIPE_2 0x554 -#define EMC_CFG_PIPE_CLK 0x558 -#define EMC_CFG_PIPE_1 0x55c -#define EMC_CFG_PIPE 0x560 -#define EMC_QPOP 0x564 -#define EMC_QUSE_WIDTH 0x568 -#define EMC_PUTERM_WIDTH 0x56c -#define EMC_PROTOBIST_CONFIG_ADR_1 0x5d0 -#define EMC_PROTOBIST_CONFIG_ADR_2 0x5d4 -#define EMC_PROTOBIST_MISC 0x5d8 -#define EMC_PROTOBIST_WDATA_LOWER 0x5dc -#define EMC_PROTOBIST_WDATA_UPPER 0x5e0 -#define EMC_PROTOBIST_RDATA 0x5ec -#define EMC_DLL_CFG_0 0x5e4 -#define EMC_DLL_CFG_1 0x5e8 -#define EMC_TRAINING_CMD 0xe00 -#define EMC_TRAINING_CTRL 0xe04 -#define EMC_TRAINING_STATUS 0xe08 -#define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c -#define EMC_TRAINING_QUSE_FINE_CTRL 0xe10 -#define EMC_TRAINING_QUSE_CTRL_MISC 0xe14 -#define EMC_TRAINING_WRITE_FINE_CTRL 0xe18 -#define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c -#define EMC_TRAINING_WRITE_VREF_CTRL 0xe20 -#define EMC_TRAINING_READ_FINE_CTRL 0xe24 -#define EMC_TRAINING_READ_CTRL_MISC 0xe28 -#define EMC_TRAINING_READ_VREF_CTRL 0xe2c -#define EMC_TRAINING_CA_FINE_CTRL 0xe30 -#define EMC_TRAINING_CA_CTRL_MISC 0xe34 -#define EMC_TRAINING_CA_CTRL_MISC1 0xe38 -#define EMC_TRAINING_CA_VREF_CTRL 0xe3c -#define EMC_TRAINING_CA_TADR_CTRL 0xe40 -#define EMC_TRAINING_SETTLE 0xe44 -#define EMC_TRAINING_DEBUG_CTRL 0xe48 -#define EMC_TRAINING_DEBUG_DQ0 0xe4c -#define EMC_TRAINING_DEBUG_DQ1 0xe50 -#define EMC_TRAINING_DEBUG_DQ2 0xe54 -#define EMC_TRAINING_DEBUG_DQ3 0xe58 -#define EMC_TRAINING_MPC 0xe5c -#define EMC_TRAINING_PATRAM_CTRL 0xe60 -#define EMC_TRAINING_PATRAM_DQ 0xe64 -#define EMC_TRAINING_PATRAM_DMI 0xe68 -#define EMC_TRAINING_VREF_SETTLE 0xe6c -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE0 0xe70 -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE1 0xe74 -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE2 0xe78 -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE3 0xe7c -#define EMC_TRAINING_RW_EYE_CENTER_IB_MISC 0xe80 -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE0 0xe84 -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE1 0xe88 -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE2 0xe8c -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE3 0xe90 -#define EMC_TRAINING_RW_EYE_CENTER_OB_MISC 0xe94 -#define EMC_TRAINING_RW_OFFSET_IB_BYTE0 0xe98 -#define EMC_TRAINING_RW_OFFSET_IB_BYTE1 0xe9c -#define EMC_TRAINING_RW_OFFSET_IB_BYTE2 0xea0 -#define EMC_TRAINING_RW_OFFSET_IB_BYTE3 0xea4 -#define EMC_TRAINING_RW_OFFSET_IB_MISC 0xea8 -#define EMC_TRAINING_RW_OFFSET_OB_BYTE0 0xeac -#define EMC_TRAINING_RW_OFFSET_OB_BYTE1 0xeb0 -#define EMC_TRAINING_RW_OFFSET_OB_BYTE2 0xeb4 -#define EMC_TRAINING_RW_OFFSET_OB_BYTE3 0xeb8 -#define EMC_TRAINING_RW_OFFSET_OB_MISC 0xebc -#define EMC_TRAINING_OPT_CA_VREF 0xec0 -#define EMC_TRAINING_OPT_DQ_OB_VREF 0xec4 -#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK0 0xec8 -#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK1 0xecc -#define EMC_TRAINING_QUSE_VREF_CTRL 0xed0 -#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4 -#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8 -#define EMC_TRAINING_DRAMC_TIMING 0xedc -#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600 -#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604 -#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608 -#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c -#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610 -#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614 -#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620 -#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624 -#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628 -#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c -#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630 -#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4 0x6d0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5 0x6d4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4 0x6f0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5 0x6f4 -#define EMC_PMACRO_TX_PWRD_0 0x720 -#define EMC_PMACRO_TX_PWRD_1 0x724 -#define EMC_PMACRO_TX_PWRD_2 0x728 -#define EMC_PMACRO_TX_PWRD_3 0x72c -#define EMC_PMACRO_TX_PWRD_4 0x730 -#define EMC_PMACRO_TX_PWRD_5 0x734 -#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740 -#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744 -#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c -#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748 -#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750 -#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754 -#define EMC_PMACRO_DDLL_BYPASS 0x760 -#define EMC_PMACRO_DDLL_PWRD_0 0x770 -#define EMC_PMACRO_DDLL_PWRD_1 0x774 -#define EMC_PMACRO_DDLL_PWRD_2 0x778 -#define EMC_PMACRO_CMD_CTRL_0 0x780 -#define EMC_PMACRO_CMD_CTRL_1 0x784 -#define EMC_PMACRO_CMD_CTRL_2 0x788 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0 0xa80 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1 0xa84 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2 0xa88 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0 0xa90 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1 0xa94 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2 0xa98 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0 0xaa0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1 0xaa4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2 0xaa8 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0 0xab0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1 0xab4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2 0xab8 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0 0xb80 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1 0xb84 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2 0xb88 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0 0xb90 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1 0xb94 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2 0xb98 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0 0xba0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1 0xba4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2 0xba8 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0 0xbb0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1 0xbb4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2 0xbb8 -#define EMC_PMACRO_IB_VREF_DQ_0 0xbe0 -#define EMC_PMACRO_IB_VREF_DQ_1 0xbe4 -#define EMC_PMACRO_IB_VREF_DQ_2 0xbe8 -#define EMC_PMACRO_IB_VREF_DQS_0 0xbf0 -#define EMC_PMACRO_IB_VREF_DQS_1 0xbf4 -#define EMC_PMACRO_IB_VREF_DQS_2 0xbf8 -#define EMC_PMACRO_IB_RXRT 0xcf4 -#define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00 -#define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04 -#define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08 -#define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c -#define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10 -#define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14 -#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20 -#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24 -#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28 -#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30 -#define EMC_PMACRO_VTTGEN_CTRL_0 0xc34 -#define EMC_PMACRO_VTTGEN_CTRL_1 0xc38 -#define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0 -#define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c -#define EMC_PMACRO_PAD_CFG_CTRL 0xc40 -#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50 -#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54 -#define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58 -#define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c -#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60 -#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64 -#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68 -#define EMC_PMACRO_BRICK_MAPPING_0 0xc80 -#define EMC_PMACRO_BRICK_MAPPING_1 0xc84 -#define EMC_PMACRO_BRICK_MAPPING_2 0xc88 -#define EMC_PMACRO_DDLLCAL_CAL 0xce0 -#define EMC_PMACRO_DDLL_OFFSET 0xce4 -#define EMC_PMACRO_DDLL_PERIODIC_OFFSET 0xce8 -#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330 -#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334 -#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318 -#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c -#define EMC_PMACRO_TRAINING_CTRL_0 0xcf8 -#define EMC_PMACRO_TRAINING_CTRL_1 0xcfc -#define EMC_PMC_SCRATCH1 0x440 -#define EMC_PMC_SCRATCH2 0x444 -#define EMC_PMC_SCRATCH3 0x448 - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/fuse.h b/fusee/fusee-secondary/src/hwinit/fuse.h deleted file mode 100644 index 1f19f466f..000000000 --- a/fusee/fusee-secondary/src/hwinit/fuse.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _FUSE_H_ -#define _FUSE_H_ - -#include "types.h" - -/*! Fuse registers. */ -#define FUSE_CTRL 0x0 -#define FUSE_ADDR 0x4 -#define FUSE_RDATA 0x8 -#define FUSE_WDATA 0xC -#define FUSE_TIME_RD1 0x10 -#define FUSE_TIME_RD2 0x14 -#define FUSE_TIME_PGM1 0x18 -#define FUSE_TIME_PGM2 0x1C -#define FUSE_PRIV2INTFC 0x20 -#define FUSE_FUSEBYPASS 0x24 -#define FUSE_PRIVATEKEYDISABLE 0x28 -#define FUSE_DISABLEREGPROGRAM 0x2C -#define FUSE_WRITE_ACCESS_SW 0x30 -#define FUSE_PWR_GOOD_SW 0x34 - -/*! Fuse cache registers. */ -#define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x)) - -void fuse_disable_program(); -u32 fuse_read_odm(u32 idx); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/hwinit.c b/fusee/fusee-secondary/src/hwinit/hwinit.c deleted file mode 100644 index 467efdee5..000000000 --- a/fusee/fusee-secondary/src/hwinit/hwinit.c +++ /dev/null @@ -1,280 +0,0 @@ -#include "clock.h" -#include "uart.h" -#include "i2c.h" -#include "sdram.h" -#include "di.h" -#include "mc.h" -#include "t210.h" -#include "pmc.h" -#include "pinmux.h" -#include "fuse.h" -#include "util.h" - -void config_oscillators() -{ - CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3 | 4; - SYSCTR0(SYSCTR0_CNTFID0) = 19200000; - TMR(0x14) = 0x45F; - CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; - PMC(APBDEV_PMC_OSC_EDPD_OVER) = PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81 | 0xE; - PMC(APBDEV_PMC_OSC_EDPD_OVER) = PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF | 0x400000; - PMC(APBDEV_PMC_CNTRL2) = PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF | 0x1000; - PMC(APBDEV_PMC_SCRATCH188) = PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF | 0x2000000; - CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; - PMC(APBDEV_PMC_TSC_MULT) = PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000 | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz) - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; - CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; -} - -void config_gpios() -{ - PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0; - PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0; - - PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = 0x40; - PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = 0x40; - - GPIO_2(0x8) = GPIO_2(0x8) & 0xFFFFFFFE | 1; - GPIO_1(0xC) = GPIO_1(0xC) & 0xFFFFFFFD | 2; - GPIO_2(0x0) = GPIO_2(0x0) & 0xFFFFFFBF | 0x40; - GPIO_2(0xC) = GPIO_2(0xC) & 0xFFFFFFBF | 0x40; - GPIO_2(0x18) &= 0xFFFFFFFE; - GPIO_1(0x1C) &= 0xFFFFFFFD; - GPIO_2(0x10) &= 0xFFFFFFBF; - GPIO_2(0x1C) &= 0xFFFFFFBF; - - pinmux_config_i2c(I2C_1); - pinmux_config_i2c(I2C_5); - pinmux_config_uart(UART_A); - - GPIO_6(0xC) = GPIO_6(0xC) & 0xFFFFFFBF | 0x40; - GPIO_6(0xC) = GPIO_6(0xC) & 0xFFFFFF7F | 0x80; - GPIO_6(0x1C) &= 0xFFFFFFBF; - GPIO_6(0x1C) &= 0xFFFFFF7F; -} - -void config_pmc_scratch() -{ - PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; - PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; - PMC(APBDEV_PMC_SECURE_SCRATCH21) |= 0x10; -} - -void mc_config_tsec_carveout(u32 bom, u32 size1mb, int lock) -{ - MC(0x670) = 0x90000000; - MC(0x674) = 1; - if (lock) - MC(0x678) = 1; -} - -void mc_config_carveout() -{ - *(vu32 *)0x8005FFFC = 0xC0EDBBCC; - MC(0x984) = 1; - MC(0x988) = 0; - MC(0x648) = 0; - MC(0x64C) = 0; - MC(0x650) = 1; - - //Official code disables and locks the carveout here. - //mc_config_tsec_carveout(0, 0, 1); - - MC(0x9A0) = 0; - MC(0x9A4) = 0; - MC(0x9A8) = 0; - MC(0x9AC) = 1; - MC(0xC0C) = 0; - MC(0xC10) = 0; - MC(0xC14) = 0; - MC(0xC18) = 0; - MC(0xC1C) = 0; - MC(0xC20) = 0; - MC(0xC24) = 0; - MC(0xC28) = 0; - MC(0xC2C) = 0; - MC(0xC30) = 0; - MC(0xC34) = 0; - MC(0xC38) = 0; - MC(0xC3C) = 0; - MC(0xC08) = 0x4000006; - MC(0xC5C) = 0x80020000; - MC(0xC60) = 0; - MC(0xC64) = 2; - MC(0xC68) = 0; - MC(0xC6C) = 0; - MC(0xC70) = 0x3000000; - MC(0xC74) = 0; - MC(0xC78) = 0x300; - MC(0xC7C) = 0; - MC(0xC80) = 0; - MC(0xC84) = 0; - MC(0xC88) = 0; - MC(0xC8C) = 0; - MC(0xC58) = 0x440167E; - MC(0xCAC) = 0; - MC(0xCB0) = 0; - MC(0xCB4) = 0; - MC(0xCB8) = 0; - MC(0xCBC) = 0; - MC(0xCC0) = 0x3000000; - MC(0xCC4) = 0; - MC(0xCC8) = 0x300; - MC(0xCCC) = 0; - MC(0xCD0) = 0; - MC(0xCD4) = 0; - MC(0xCD8) = 0; - MC(0xCDC) = 0; - MC(0xCA8) = 0x4401E7E; - MC(0xCFC) = 0; - MC(0xD00) = 0; - MC(0xD04) = 0; - MC(0xD08) = 0; - MC(0xD0C) = 0; - MC(0xD10) = 0; - MC(0xD14) = 0; - MC(0xD18) = 0; - MC(0xD1C) = 0; - MC(0xD20) = 0; - MC(0xD24) = 0; - MC(0xD28) = 0; - MC(0xD2C) = 0; - MC(0xCF8) = 0x8F; - MC(0xD4C) = 0; - MC(0xD50) = 0; - MC(0xD54) = 0; - MC(0xD58) = 0; - MC(0xD5C) = 0; - MC(0xD60) = 0; - MC(0xD64) = 0; - MC(0xD68) = 0; - MC(0xD6C) = 0; - MC(0xD70) = 0; - MC(0xD74) = 0; - MC(0xD78) = 0; - MC(0xD7C) = 0; - MC(0xD48) = 0x8F; -} - -void enable_clocks() -{ - CLOCK(0x410) = (CLOCK(0x410) | 0x8000) & 0xFFFFBFFF; - CLOCK(0xD0) |= 0x40800000u; - CLOCK(0x2AC) = 64; - CLOCK(0x294) = 0x40000; - CLOCK(0x304) = 0x18000000; - sleep(2); - - I2S(0x0A0) |= 0x400; - I2S(0x088) &= 0xFFFFFFFE; - I2S(0x1A0) |= 0x400; - I2S(0x188) &= 0xFFFFFFFE; - I2S(0x2A0) |= 0x400; - I2S(0x288) &= 0xFFFFFFFE; - I2S(0x3A0) |= 0x400; - I2S(0x388) &= 0xFFFFFFFE; - I2S(0x4A0) |= 0x400; - I2S(0x488) &= 0xFFFFFFFE; - DISPLAY_A(0xCF8) |= 4; - VIC(0x8C) = 0xFFFFFFFF; - sleep(2); - - CLOCK(0x2A8) = 0x40; - CLOCK(0x300) = 0x18000000; - CLOCK(0x290) = 0x40000; - CLOCK(0x14) = 0xC0; - CLOCK(0x10) = 0x80000130; - CLOCK(0x18) = 0x1F00200; - CLOCK(0x360) = 0x80400808; - CLOCK(0x364) = 0x402000FC; - CLOCK(0x280) = 0x23000780; - CLOCK(0x298) = 0x300; - CLOCK(0xF8) = 0; - CLOCK(0xFC) = 0; - CLOCK(0x3A0) = 0; - CLOCK(0x3A4) = 0; - CLOCK(0x554) = 0; - CLOCK(0xD0) &= 0x1F7FFFFFu; - CLOCK(0x410) &= 0xFFFF3FFF; - CLOCK(0x148) = CLOCK(0x148) & 0x1FFFFFFF | 0x80000000; - CLOCK(0x180) = CLOCK(0x180) & 0x1FFFFFFF | 0x80000000; - CLOCK(0x6A0) = CLOCK(0x6A0) & 0x1FFFFFFF | 0x80000000; -} - -void mc_enable_ahb_redirect() -{ - CLOCK(0x3A4) = CLOCK(0x3A4) & 0xFFF7FFFF | 0x80000; - //MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE; - MC(MC_IRAM_BOM) = 0x40000000; - MC(MC_IRAM_TOM) = 0x4003F000; -} - -void mc_disable_ahb_redirect() -{ - MC(MC_IRAM_BOM) = 0xFFFFF000; - MC(MC_IRAM_TOM) = 0; - //Disable IRAM_CFG_WRITE_ACCESS (sticky). - //MC(MC_IRAM_REG_CTRL) = MC(MC_IRAM_REG_CTRL) & 0xFFFFFFFE | 1; - CLOCK(0x3A4) &= 0xFFF7FFFF; -} - -void mc_enable() -{ - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF | 0x40000000; - //Enable MIPI CAL clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFDFFFFFF | 0x2000000; - //Enable MC clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) & 0xFFFFFFFE | 1; - //Enable EMC DLL clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF | 0x4000; - CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x2000001; //Clear EMC and MC reset. - sleep(5); -} - -clock_t clock_unk1 = { 0x358, 0x360, 0x42C, 0x1F, 0, 0 }; -clock_t clock_unk2 = { 0x358, 0x360, 0, 0x1E, 0, 0 }; - -void nx_hwinit() -{ - enable_clocks(); - clock_enable_se(); - clock_enable_fuse(1); - fuse_disable_program(); - - mc_enable(); - - config_oscillators(); - _REG(0x70000000, 0x40) = 0; - - config_gpios(); - - clock_enable_i2c(I2C_1); - clock_enable_i2c(I2C_5); - clock_enable(&clock_unk1); - clock_enable(&clock_unk2); - - i2c_init(I2C_1); - i2c_init(I2C_5); - - //Config PMIC (TODO: use max77620.h) - i2c_send_byte(I2C_5, 0x3C, 4, 0x40); - i2c_send_byte(I2C_5, 0x3C, 0x41, 0x78); - i2c_send_byte(I2C_5, 0x3C, 0x43, 0x38); - i2c_send_byte(I2C_5, 0x3C, 0x44, 0x3A); - i2c_send_byte(I2C_5, 0x3C, 0x45, 0x38); - i2c_send_byte(I2C_5, 0x3C, 0x4A, 0xF); - i2c_send_byte(I2C_5, 0x3C, 0x4E, 0xC7); - i2c_send_byte(I2C_5, 0x3C, 0x4F, 0x4F); - i2c_send_byte(I2C_5, 0x3C, 0x50, 0x29); - i2c_send_byte(I2C_5, 0x3C, 0x52, 0x1B); - i2c_send_byte(I2C_5, 0x3C, 0x16, 42); //42 = (1000 * 1125 - 600000) / 12500 - - config_pmc_scratch(); - - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888 | 0x3333; - - mc_config_carveout(); - - sdram_init(); -} diff --git a/fusee/fusee-secondary/src/hwinit/hwinit.h b/fusee/fusee-secondary/src/hwinit/hwinit.h deleted file mode 100644 index fda89d4f4..000000000 --- a/fusee/fusee-secondary/src/hwinit/hwinit.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _HWINIT_H_ -#define _HWINIT_H_ - -void mc_config_tsec_carveout(u32 bom, u32 size1mb, int lock); -void mc_enable_ahb_redirect(); -void mc_disable_ahb_redirect(); -void nx_hwinit(); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/hwinit_fuse.c b/fusee/fusee-secondary/src/hwinit/hwinit_fuse.c deleted file mode 100644 index 80fa85788..000000000 --- a/fusee/fusee-secondary/src/hwinit/hwinit_fuse.c +++ /dev/null @@ -1,12 +0,0 @@ -#include "fuse.h" -#include "t210.h" - -void fuse_disable_program() -{ - FUSE(FUSE_DISABLEREGPROGRAM) = 1; -} - -u32 fuse_read_odm(u32 idx) -{ - return FUSE(FUSE_RESERVED_ODMX(idx)); -} diff --git a/fusee/fusee-secondary/src/hwinit/i2c.c b/fusee/fusee-secondary/src/hwinit/i2c.c deleted file mode 100644 index b44b9ffa5..000000000 --- a/fusee/fusee-secondary/src/hwinit/i2c.c +++ /dev/null @@ -1,116 +0,0 @@ -#include - -#include "i2c.h" -#include "util.h" - -static u32 i2c_addrs[] = { 0x7000C000, 0x7000C400, 0x7000C500, 0x7000C700, 0x7000D000, 0x7000D100 }; - -static void _i2c_wait(vu32 *base) -{ - base[0x23] = 0x25; - for (u32 i = 0; i < 20; i++) - { - sleep(1); - if (!(base[0x23] & 1)) - break; - } -} - -static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size) -{ - if (size > 4) - return 0; - - u32 tmp = 0; - memcpy(&tmp, buf, size); - - vu32 *base = (vu32 *)i2c_addrs[idx]; - base[1] = x << 1; //Set x (send mode). - base[3] = tmp; //Set value. - base[0] = (2 * size - 2) | 0x2800; //Set size and send mode. - _i2c_wait(base); //Kick transaction. - - base[0] = base[0] & 0xFFFFFDFF | 0x200; - while (base[7] & 0x100) - ; - - if (base[7] << 28) - return 0; - - return 1; -} - -static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x) -{ - if (size > 4) - return 0; - - vu32 *base = (vu32 *)i2c_addrs[idx]; - base[1] = (x << 1) | 1; //Set x (recv mode). - base[0] = (2 * size - 2) | 0x2840; //Set size and recv mode. - _i2c_wait(base); //Kick transaction. - - base[0] = base[0] & 0xFFFFFDFF | 0x200; - while (base[7] & 0x100) - ; - - if (base[7] << 28) - return 0; - - u32 tmp = base[3]; //Get value. - memcpy(buf, &tmp, size); - - return 1; -} - -void i2c_init(u32 idx) -{ - vu32 *base = (vu32 *)i2c_addrs[idx]; - - base[0x1B] = 0x50001; - base[0x21] = 0x90003; - _i2c_wait(base); - - for (u32 i = 0; i < 10; i++) - { - sleep(20000); - if (base[0x1A] & 0x800) - break; - } - - vu32 dummy = base[0x22]; - base[0x1A] = base[0x1A]; -} - -int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size) -{ - u8 tmp[4]; - - if (size > 3) - return 0; - - tmp[0] = y; - memcpy(tmp + 1, buf, size); - - return _i2c_send_pkt(idx, x, tmp, size + 1); -} - -int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y) -{ - int res = _i2c_send_pkt(idx, x, (u8 *)&y, 1); - if (res) - res = _i2c_recv_pkt(idx, buf, size, x); - return res; -} - -void i2c_send_byte(u32 idx, u32 x, u32 y, u8 b) -{ - i2c_send_buf_small(idx, x, y, &b, 1); -} - -u8 i2c_recv_byte(u32 idx, u32 x, u32 y) -{ - u8 tmp; - i2c_recv_buf_small(&tmp, 1, idx, x, y); - return tmp; -} diff --git a/fusee/fusee-secondary/src/hwinit/i2c.h b/fusee/fusee-secondary/src/hwinit/i2c.h deleted file mode 100644 index 921533d6b..000000000 --- a/fusee/fusee-secondary/src/hwinit/i2c.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef _I2C_H_ -#define _I2C_H_ - -#include "types.h" - -#define I2C_1 0 -#define I2C_2 1 -#define I2C_3 2 -#define I2C_4 3 -#define I2C_5 4 -#define I2C_6 5 - -void i2c_init(u32 idx); -int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size); -int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y); -void i2c_send_byte(u32 idx, u32 x, u32 y, u8 b); -u8 i2c_recv_byte(u32 idx, u32 x, u32 y); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/max77620.h b/fusee/fusee-secondary/src/hwinit/max77620.h deleted file mode 100644 index 7223067dc..000000000 --- a/fusee/fusee-secondary/src/hwinit/max77620.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Defining registers address and its bit definitions of MAX77620 and MAX20024 - * - * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - */ - -#ifndef _MFD_MAX77620_H_ -#define _MFD_MAX77620_H_ - -/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */ -#define MAX77620_REG_CNFGGLBL1 0x00 -#define MAX77620_REG_CNFGGLBL2 0x01 -#define MAX77620_REG_CNFGGLBL3 0x02 -#define MAX77620_REG_CNFG1_32K 0x03 -#define MAX77620_REG_CNFGBBC 0x04 -#define MAX77620_REG_IRQTOP 0x05 -#define MAX77620_REG_INTLBT 0x06 -#define MAX77620_REG_IRQSD 0x07 -#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 -#define MAX77620_REG_IRQ_LVL2_L8 0x09 -#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A -#define MAX77620_REG_ONOFFIRQ 0x0B -#define MAX77620_REG_NVERC 0x0C -#define MAX77620_REG_IRQTOPM 0x0D -#define MAX77620_REG_INTENLBT 0x0E -#define MAX77620_REG_IRQMASKSD 0x0F -#define MAX77620_REG_IRQ_MSK_L0_7 0x10 -#define MAX77620_REG_IRQ_MSK_L8 0x11 -#define MAX77620_REG_ONOFFIRQM 0x12 -#define MAX77620_REG_STATLBT 0x13 -#define MAX77620_REG_STATSD 0x14 -#define MAX77620_REG_ONOFFSTAT 0x15 - -/* SD and LDO Registers */ -#define MAX77620_REG_SD0 0x16 -#define MAX77620_REG_SD1 0x17 -#define MAX77620_REG_SD2 0x18 -#define MAX77620_REG_SD3 0x19 -#define MAX77620_REG_SD4 0x1A -#define MAX77620_REG_DVSSD0 0x1B -#define MAX77620_REG_DVSSD1 0x1C -#define MAX77620_REG_SD0_CFG 0x1D -#define MAX77620_REG_SD1_CFG 0x1E -#define MAX77620_REG_SD2_CFG 0x1F -#define MAX77620_REG_SD3_CFG 0x20 -#define MAX77620_REG_SD4_CFG 0x21 -#define MAX77620_REG_SD_CFG2 0x22 -#define MAX77620_REG_LDO0_CFG 0x23 -#define MAX77620_REG_LDO0_CFG2 0x24 -#define MAX77620_REG_LDO1_CFG 0x25 -#define MAX77620_REG_LDO1_CFG2 0x26 -#define MAX77620_REG_LDO2_CFG 0x27 -#define MAX77620_REG_LDO2_CFG2 0x28 -#define MAX77620_REG_LDO3_CFG 0x29 -#define MAX77620_REG_LDO3_CFG2 0x2A -#define MAX77620_REG_LDO4_CFG 0x2B -#define MAX77620_REG_LDO4_CFG2 0x2C -#define MAX77620_REG_LDO5_CFG 0x2D -#define MAX77620_REG_LDO5_CFG2 0x2E -#define MAX77620_REG_LDO6_CFG 0x2F -#define MAX77620_REG_LDO6_CFG2 0x30 -#define MAX77620_REG_LDO7_CFG 0x31 -#define MAX77620_REG_LDO7_CFG2 0x32 -#define MAX77620_REG_LDO8_CFG 0x33 -#define MAX77620_REG_LDO8_CFG2 0x34 -#define MAX77620_REG_LDO_CFG3 0x35 - -#define MAX77620_LDO_SLEW_RATE_MASK 0x1 - -/* LDO Configuration 3 */ -#define MAX77620_TRACK4_MASK (1 << 5) -#define MAX77620_TRACK4_SHIFT 5 - -/* Voltage */ -#define MAX77620_SDX_VOLT_MASK 0xFF -#define MAX77620_SD0_VOLT_MASK 0x3F -#define MAX77620_SD1_VOLT_MASK 0x7F -#define MAX77620_LDO_VOLT_MASK 0x3F - -#define MAX77620_REG_GPIO0 0x36 -#define MAX77620_REG_GPIO1 0x37 -#define MAX77620_REG_GPIO2 0x38 -#define MAX77620_REG_GPIO3 0x39 -#define MAX77620_REG_GPIO4 0x3A -#define MAX77620_REG_GPIO5 0x3B -#define MAX77620_REG_GPIO6 0x3C -#define MAX77620_REG_GPIO7 0x3D -#define MAX77620_REG_PUE_GPIO 0x3E -#define MAX77620_REG_PDE_GPIO 0x3F -#define MAX77620_REG_AME_GPIO 0x40 -#define MAX77620_REG_ONOFFCNFG1 0x41 -#define MAX77620_REG_ONOFFCNFG2 0x42 - -/* FPS Registers */ -#define MAX77620_REG_FPS_CFG0 0x43 -#define MAX77620_REG_FPS_CFG1 0x44 -#define MAX77620_REG_FPS_CFG2 0x45 -#define MAX77620_REG_FPS_LDO0 0x46 -#define MAX77620_REG_FPS_LDO1 0x47 -#define MAX77620_REG_FPS_LDO2 0x48 -#define MAX77620_REG_FPS_LDO3 0x49 -#define MAX77620_REG_FPS_LDO4 0x4A -#define MAX77620_REG_FPS_LDO5 0x4B -#define MAX77620_REG_FPS_LDO6 0x4C -#define MAX77620_REG_FPS_LDO7 0x4D -#define MAX77620_REG_FPS_LDO8 0x4E -#define MAX77620_REG_FPS_SD0 0x4F -#define MAX77620_REG_FPS_SD1 0x50 -#define MAX77620_REG_FPS_SD2 0x51 -#define MAX77620_REG_FPS_SD3 0x52 -#define MAX77620_REG_FPS_SD4 0x53 -#define MAX77620_REG_FPS_NONE 0 - -#define MAX77620_FPS_SRC_MASK 0xC0 -#define MAX77620_FPS_SRC_SHIFT 6 -#define MAX77620_FPS_PU_PERIOD_MASK 0x38 -#define MAX77620_FPS_PU_PERIOD_SHIFT 3 -#define MAX77620_FPS_PD_PERIOD_MASK 0x07 -#define MAX77620_FPS_PD_PERIOD_SHIFT 0 -#define MAX77620_FPS_TIME_PERIOD_MASK 0x38 -#define MAX77620_FPS_TIME_PERIOD_SHIFT 3 -#define MAX77620_FPS_EN_SRC_MASK 0x06 -#define MAX77620_FPS_EN_SRC_SHIFT 1 -#define MAX77620_FPS_ENFPS_SW_MASK 0x01 -#define MAX77620_FPS_ENFPS_SW 0x01 - -/* Minimum and maximum FPS period time (in microseconds) are - * different for MAX77620 and Max20024. - */ -#define MAX77620_FPS_PERIOD_MIN_US 40 -#define MAX20024_FPS_PERIOD_MIN_US 20 - -#define MAX77620_FPS_PERIOD_MAX_US 2560 -#define MAX20024_FPS_PERIOD_MAX_US 5120 - -#define MAX77620_REG_FPS_GPIO1 0x54 -#define MAX77620_REG_FPS_GPIO2 0x55 -#define MAX77620_REG_FPS_GPIO3 0x56 -#define MAX77620_REG_FPS_RSO 0x57 -#define MAX77620_REG_CID0 0x58 -#define MAX77620_REG_CID1 0x59 -#define MAX77620_REG_CID2 0x5A -#define MAX77620_REG_CID3 0x5B -#define MAX77620_REG_CID4 0x5C -#define MAX77620_REG_CID5 0x5D - -#define MAX77620_REG_DVSSD4 0x5E -#define MAX20024_REG_MAX_ADD 0x70 - -#define MAX77620_CID_DIDM_MASK 0xF0 -#define MAX77620_CID_DIDM_SHIFT 4 - -/* CNCG2SD */ -#define MAX77620_SD_CNF2_ROVS_EN_SD1 (1 << 1) -#define MAX77620_SD_CNF2_ROVS_EN_SD0 (1 << 2) - -/* Device Identification Metal */ -#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF) -/* Device Indentification OTP */ -#define MAX77620_CID5_DIDO(n) ((n) & 0xF) - -/* SD CNFG1 */ -#define MAX77620_SD_SR_MASK 0xC0 -#define MAX77620_SD_SR_SHIFT 6 -#define MAX77620_SD_POWER_MODE_MASK 0x30 -#define MAX77620_SD_POWER_MODE_SHIFT 4 -#define MAX77620_SD_CFG1_ADE_MASK (1 << 3) -#define MAX77620_SD_CFG1_ADE_DISABLE 0 -#define MAX77620_SD_CFG1_ADE_ENABLE (1 << 3) -#define MAX77620_SD_FPWM_MASK 0x04 -#define MAX77620_SD_FPWM_SHIFT 2 -#define MAX77620_SD_FSRADE_MASK 0x01 -#define MAX77620_SD_FSRADE_SHIFT 0 -#define MAX77620_SD_CFG1_FPWM_SD_MASK (1 << 2) -#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0 -#define MAX77620_SD_CFG1_FPWM_SD_FPWM (1 << 2) -#define MAX20024_SD_CFG1_MPOK_MASK (1 << 1) -#define MAX77620_SD_CFG1_FSRADE_SD_MASK (1 << 0) -#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0 -#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0) - -/* LDO_CNFG2 */ -#define MAX77620_LDO_POWER_MODE_MASK 0xC0 -#define MAX77620_LDO_POWER_MODE_SHIFT 6 -#define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2) -#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1) -#define MAX77620_LDO_CFG2_ADE_DISABLE 0 -#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1) -#define MAX77620_LDO_CFG2_SS_MASK (1 << 0) -#define MAX77620_LDO_CFG2_SS_FAST (1 << 0) -#define MAX77620_LDO_CFG2_SS_SLOW 0 - -#define MAX77620_IRQ_TOP_GLBL_MASK (1 << 7) -#define MAX77620_IRQ_TOP_SD_MASK (1 << 6) -#define MAX77620_IRQ_TOP_LDO_MASK (1 << 5) -#define MAX77620_IRQ_TOP_GPIO_MASK (1 << 4) -#define MAX77620_IRQ_TOP_RTC_MASK (1 << 3) -#define MAX77620_IRQ_TOP_32K_MASK (1 << 2) -#define MAX77620_IRQ_TOP_ONOFF_MASK (1 << 1) - -#define MAX77620_IRQ_LBM_MASK (1 << 3) -#define MAX77620_IRQ_TJALRM1_MASK (1 << 2) -#define MAX77620_IRQ_TJALRM2_MASK (1 << 1) - -#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0 -#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1) -#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1) -#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0 -#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0 -#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4) -#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4) -#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5) -#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6) -#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6) -#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6) -#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6) -#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6) - -#define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0) -#define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1) -#define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2) -#define MAX77620_IRQ_LVL2_GPIO_EDGE3 (1 << 3) -#define MAX77620_IRQ_LVL2_GPIO_EDGE4 (1 << 4) -#define MAX77620_IRQ_LVL2_GPIO_EDGE5 (1 << 5) -#define MAX77620_IRQ_LVL2_GPIO_EDGE6 (1 << 6) -#define MAX77620_IRQ_LVL2_GPIO_EDGE7 (1 << 7) - -#define MAX77620_CNFG1_32K_OUT0_EN (1 << 2) - -#define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7) -#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38 -#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3 -#define MAX77620_ONOFFCNFG1_SLPEN (1 << 2) -#define MAX77620_ONOFFCNFG1_PWR_OFF (1 << 1) -#define MAX20024_ONOFFCNFG1_CLRSE 0x18 - -#define MAX77620_ONOFFCNFG2_SFT_RST_WK (1 << 7) -#define MAX77620_ONOFFCNFG2_WD_RST_WK (1 << 6) -#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK (1 << 5) -#define MAX77620_ONOFFCNFG2_WK_ALARM1 (1 << 2) -#define MAX77620_ONOFFCNFG2_WK_EN0 (1 << 0) - -#define MAX77620_GLBLM_MASK (1 << 0) - -#define MAX77620_WDTC_MASK 0x3 -#define MAX77620_WDTOFFC (1 << 4) -#define MAX77620_WDTSLPC (1 << 3) -#define MAX77620_WDTEN (1 << 2) - -#define MAX77620_TWD_MASK 0x3 -#define MAX77620_TWD_2s 0x0 -#define MAX77620_TWD_16s 0x1 -#define MAX77620_TWD_64s 0x2 -#define MAX77620_TWD_128s 0x3 - -#define MAX77620_CNFGGLBL1_LBDAC_EN (1 << 7) -#define MAX77620_CNFGGLBL1_MPPLD (1 << 6) -#define MAX77620_CNFGGLBL1_LBHYST ((1 << 5) | (1 << 4)) -#define MAX77620_CNFGGLBL1_LBDAC 0x0E -#define MAX77620_CNFGGLBL1_LBRSTEN (1 << 0) - -/* CNFG BBC registers */ -#define MAX77620_CNFGBBC_ENABLE (1 << 0) -#define MAX77620_CNFGBBC_CURRENT_MASK 0x06 -#define MAX77620_CNFGBBC_CURRENT_SHIFT 1 -#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18 -#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3 -#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5) -#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0 -#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6 - -#define MAX77620_FPS_COUNT 3 - -/* Interrupts */ -enum { - MAX77620_IRQ_TOP_GLBL, /* Low-Battery */ - MAX77620_IRQ_TOP_SD, /* SD power fail */ - MAX77620_IRQ_TOP_LDO, /* LDO power fail */ - MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */ - MAX77620_IRQ_TOP_RTC, /* RTC */ - MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */ - MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */ - MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */ - MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */ - MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */ -}; - -/* GPIOs */ -enum { - MAX77620_GPIO0, - MAX77620_GPIO1, - MAX77620_GPIO2, - MAX77620_GPIO3, - MAX77620_GPIO4, - MAX77620_GPIO5, - MAX77620_GPIO6, - MAX77620_GPIO7, - MAX77620_GPIO_NR, -}; - -/* FPS Source */ -enum max77620_fps_src { - MAX77620_FPS_SRC_0, - MAX77620_FPS_SRC_1, - MAX77620_FPS_SRC_2, - MAX77620_FPS_SRC_NONE, - MAX77620_FPS_SRC_DEF, -}; - -enum max77620_chip_id { - MAX77620, - MAX20024, -}; - -#endif /* _MFD_MAX77620_H_ */ diff --git a/fusee/fusee-secondary/src/hwinit/max7762x.c b/fusee/fusee-secondary/src/hwinit/max7762x.c deleted file mode 100644 index 67caaf230..000000000 --- a/fusee/fusee-secondary/src/hwinit/max7762x.c +++ /dev/null @@ -1,136 +0,0 @@ -/* -* Copyright (c) 2018 naehrwert -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . -*/ - -#include "max7762x.h" -#include "max77620.h" -#include "i2c.h" -#include "util.h" - -#define REGULATOR_SD 0 -#define REGULATOR_LDO 1 - -typedef struct _max77620_regulator_t -{ - u8 type; - const char *name; - u8 reg_sd; - u32 mv_step; - u32 mv_min; - u32 mv_default; - u32 mv_max; - u8 volt_addr; - u8 cfg_addr; - u8 volt_mask; - u8 enable_mask; - u8 enable_shift; - u8 status_mask; - - u8 fps_addr; - u8 fps_src; - u8 pd_period; - u8 pu_period; -} max77620_regulator_t; - -static const max77620_regulator_t _pmic_regulators[] = { - { REGULATOR_SD, "sd0", 0x16, 12500, 600000, 625000, 1400000, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, 0x3F, 0x30, 4, 0x80, 0x4F, 1, 7, 1 }, - { REGULATOR_SD, "sd1", 0x17, 12500, 600000, 1125000, 1125000, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, 0x3F, 0x30, 4, 0x40, 0x50, 0, 1, 5 }, - { REGULATOR_SD, "sd2", 0x18, 12500, 600000, 1325000, 1350000, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, 0xFF, 0x30, 4, 0x20, 0x51, 1, 5, 2 }, - { REGULATOR_SD, "sd3", 0x19, 12500, 600000, 1800000, 1800000, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, 0xFF, 0x30, 4, 0x10, 0x52, 0, 3, 3 }, - { REGULATOR_LDO, "ldo0", 0x00, 25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, 0x3F, 0xC0, 6, 0x00, 0x46, 3, 7, 0 }, - { REGULATOR_LDO, "ldo1", 0x00, 25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, 0x3F, 0xC0, 6, 0x00, 0x47, 3, 7, 0 }, - { REGULATOR_LDO, "ldo2", 0x00, 50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, 0x3F, 0xC0, 6, 0x00, 0x48, 3, 7, 0 }, - { REGULATOR_LDO, "ldo3", 0x00, 50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, 0x3F, 0xC0, 6, 0x00, 0x49, 3, 7, 0 }, - { REGULATOR_LDO, "ldo4", 0x00, 12500, 800000, 850000, 850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4A, 0, 7, 1 }, - { REGULATOR_LDO, "ldo5", 0x00, 50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4B, 3, 7, 0 }, - { REGULATOR_LDO, "ldo6", 0x00, 50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4C, 3, 7, 0 }, - { REGULATOR_LDO, "ldo7", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4D, 1, 4, 3 }, - { REGULATOR_LDO, "ldo8", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4E, 3, 7, 0 } -}; - -int max77620_regulator_get_status(u32 id) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - - if (reg->type == REGULATOR_SD) - return i2c_recv_byte(I2C_5, 0x3C, MAX77620_REG_STATSD) & reg->status_mask ? 0 : 1; - return i2c_recv_byte(I2C_5, 0x3C, reg->cfg_addr) & 8 ? 1 : 0; -} - -int max77620_regulator_config_fps(u32 id) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - - i2c_send_byte(I2C_5, 0x3C, reg->fps_addr, (reg->fps_src << 6) | (reg->pu_period << 3) | (reg->pd_period)); - - return 1; -} - -int max77620_regulator_set_voltage(u32 id, u32 mv) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - - if (mv < reg->mv_default || mv > reg->mv_max) - return 0; - - u32 mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step; - u8 val = i2c_recv_byte(I2C_5, 0x3C, reg->volt_addr); - val = (val & ~reg->volt_mask) | (mult & reg->volt_mask); - i2c_send_byte(I2C_5, 0x3C, reg->volt_addr, val); - sleep(1000); - - return 1; -} - -int max77620_regulator_enable(u32 id, int enable) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - - u32 addr = reg->type == REGULATOR_SD ? reg->cfg_addr : reg->volt_addr; - u8 val = i2c_recv_byte(I2C_5, 0x3C, addr); - if (enable) - val = (val & ~reg->enable_mask) | ((3 << reg->enable_shift) & reg->enable_mask); - else - val &= ~reg->enable_mask; - i2c_send_byte(I2C_5, 0x3C, addr, val); - sleep(1000); - - return 1; -} - -void max77620_config_default() -{ - for (u32 i = 1; i <= REGULATOR_MAX; i++) - { - i2c_recv_byte(I2C_5, 0x3C, MAX77620_REG_CID4); - max77620_regulator_config_fps(i); - max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default); - if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE) - max77620_regulator_enable(i, 1); - } - i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_SD_CFG2, 4); -} diff --git a/fusee/fusee-secondary/src/hwinit/pinmux.c b/fusee/fusee-secondary/src/hwinit/pinmux.c deleted file mode 100644 index 269c91a57..000000000 --- a/fusee/fusee-secondary/src/hwinit/pinmux.c +++ /dev/null @@ -1,16 +0,0 @@ -#include "pinmux.h" -#include "t210.h" - -void pinmux_config_uart(u32 idx) -{ - PINMUX_AUX(PINMUX_AUX_UARTX_RX(idx)) = 0; - PINMUX_AUX(PINMUX_AUX_UARTX_TX(idx)) = 0x48; - PINMUX_AUX(PINMUX_AUX_UARTX_RTS(idx)) = 0; - PINMUX_AUX(PINMUX_AUX_UARTX_CTS(idx)) = 0x44; -} - -void pinmux_config_i2c(u32 idx) -{ - PINMUX_AUX(PINMUX_AUX_X_I2C_SCL(idx)) = 0x40; - PINMUX_AUX(PINMUX_AUX_X_I2C_SDA(idx)) = 0x40; -} diff --git a/fusee/fusee-secondary/src/hwinit/pinmux.h b/fusee/fusee-secondary/src/hwinit/pinmux.h deleted file mode 100644 index 59bf506d8..000000000 --- a/fusee/fusee-secondary/src/hwinit/pinmux.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _PINMUX_H_ -#define _PINMUX_H_ - -#include "types.h" - -/*! Pinmux registers. */ -#define PINMUX_AUX_UART2_TX 0xF4 -#define PINMUX_AUX_UART3_TX 0x104 -#define PINMUX_AUX_GPIO_PE6 0x248 -#define PINMUX_AUX_GPIO_PH6 0x250 -/*! 0:UART-A, 1:UART-B, 3:UART-C, 3:UART-D */ -#define PINMUX_AUX_UARTX_TX(x) (0xE4 + 0x10 * (x)) -#define PINMUX_AUX_UARTX_RX(x) (0xE8 + 0x10 * (x)) -#define PINMUX_AUX_UARTX_RTS(x) (0xEC + 0x10 * (x)) -#define PINMUX_AUX_UARTX_CTS(x) (0xF0 + 0x10 * (x)) -/*! 0:GEN1, 1:GEN2, 2:GEN3, 3:CAM, 4:PWR */ -#define PINMUX_AUX_X_I2C_SCL(x) (0xBC + 8 * (x)) -#define PINMUX_AUX_X_I2C_SDA(x) (0xC0 + 8 * (x)) - -void pinmux_config_uart(u32 idx); -void pinmux_config_i2c(u32 idx); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/pmc.h b/fusee/fusee-secondary/src/hwinit/pmc.h deleted file mode 100644 index 4c8677239..000000000 --- a/fusee/fusee-secondary/src/hwinit/pmc.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _PMC_H_ -#define _PMC_H_ - -/*! PMC registers. */ -#define APBDEV_PMC_PWRGATE_TOGGLE 0x30 -#define APBDEV_PMC_PWRGATE_STATUS 0x38 -#define APBDEV_PMC_NO_IOPOWER 0x44 -#define APBDEV_PMC_SCRATCH20 0xA0 -#define APBDEV_PMC_DDR_PWR 0xE8 -#define APBDEV_PMC_CRYPTO_OP 0xF4 -#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4 -#define APBDEV_PMC_IO_DPD_REQ 0x1B8 -#define APBDEV_PMC_IO_DPD2_REQ 0x1C0 -#define APBDEV_PMC_VDDP_SEL 0x1CC -#define APBDEV_PMC_TSC_MULT 0x2B4 -#define APBDEV_PMC_REG_SHORT 0x2CC -#define APBDEV_PMC_WEAK_BIAS 0x2C8 -#define APBDEV_PMC_SECURE_SCRATCH21 0x334 -#define APBDEV_PMC_CNTRL2 0x440 -#define APBDEV_PMC_IO_DPD4_REQ 0x464 -#define APBDEV_PMC_DDR_CNTRL 0x4E4 -#define APBDEV_PMC_SCRATCH188 0x810 -#define APBDEV_PMC_SCRATCH190 0x818 -#define APBDEV_PMC_SCRATCH200 0x840 - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/sdram.c b/fusee/fusee-secondary/src/hwinit/sdram.c deleted file mode 100644 index a64d7b886..000000000 --- a/fusee/fusee-secondary/src/hwinit/sdram.c +++ /dev/null @@ -1,488 +0,0 @@ -#include "i2c.h" -#include "t210.h" -#include "mc.h" -//#include "emc.h" -#include "pmc.h" -#include "util.h" -#include "fuse.h" - -#include "sdram.inl" - -static u32 _get_sdram_id() -{ - return (fuse_read_odm(4) & 0x38) >> 3; -} - -static void _sdram_config(const u32 *_cfg) -{ - const u32 *_cfg_120 = _cfg + 0x120; - const u32 *_cfg_100 = _cfg + 0x100; - - PMC(0x45C) = (((4 * _cfg[0x12F] >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF; - sleep(_cfg[0x111]); - - u32 req = (4 * _cfg_120[0x10] >> 2) + 0x80000000; - PMC(APBDEV_PMC_IO_DPD4_REQ) = (req ^ 0x3FFF0000) >> 16 << 16; - sleep(_cfg_100[0x12]); - PMC(APBDEV_PMC_IO_DPD4_REQ) = (req ^ 0xFFFF) & 0xC000FFFF; - sleep(_cfg_100[0x12]); - PMC(APBDEV_PMC_WEAK_BIAS) = 0; - sleep(1); - - CLOCK(0x98) = _cfg[4]; - CLOCK(0x9C) = 0; - CLOCK(0x90) = (_cfg[2] << 8) | (*((u16 *)_cfg + 0xA) << 20) | _cfg[1] | 0x40000000; - - u32 wait_end = TMR(0x10) + 300; - while (!((CLOCK(0x90) >> 27) & 1)) - { - if (TMR(0x10) >= wait_end) - goto break_nosleep; - } - sleep(10); -break_nosleep: - - CLOCK(0x19C) = _cfg[0x16] & 0xFFFEFFFF | (_cfg[0x175] >> 11) & 0x10000; - if (_cfg[0x17]) - CLOCK(0x664) = _cfg[0x17]; - if (_cfg[0x1A]) - CLOCK(0x44C) = 0x40000000; - CLOCK(0x328) = 0x2000001; - CLOCK(0x284) = 0x4000; - CLOCK(0x30C) = 0x2000001; - EMC(0xC34) = _cfg_120[0x13]; - EMC(0xC38) = _cfg_120[0x14]; - EMC(0xCF0) = _cfg_120[0x15]; - EMC(0x28) = 1; - sleep(1); - EMC(0x8) = _cfg[0xA9] | 2 * _cfg[0xAA]; - if (_cfg[0xA]) - *(vu32 *)_cfg[0xA] = _cfg[0xB]; - EMC(0x584) = _cfg[0x7B]; - EMC(0x380) = _cfg[0x7D]; - EMC(0x384) = _cfg[0x7E]; - EMC(0x388) = _cfg[0x7F]; - EMC(0x38C) = _cfg[0x80]; - EMC(0x390) = _cfg[0x81]; - EMC(0x394) = _cfg[0x82]; - EMC(0x398) = _cfg[0x83]; - EMC(0x39C) = _cfg[0x84]; - EMC(0x3A0) = _cfg[0x85]; - EMC(0x3A4) = _cfg[0x86]; - EMC(0x3A8) = _cfg[0x87]; - EMC(0x3AC) = _cfg[0x88]; - EMC(0x3B0) = _cfg[0x89]; - EMC(0xC80) = _cfg[0x14A]; - EMC(0xC84) = _cfg[0x14B]; - EMC(0xC88) = _cfg[0x14C]; - EMC(0x330) = (_cfg_120[0x16] | 0xFEEDFEED) & 0x1FFF1FFF; - EMC(0x5F0) = _cfg[0x149]; - EMC(0x5C8) = _cfg[0x7C]; - EMC(0x404) = _cfg_100[0x18]; - EMC(0x408) = _cfg_100[0x19]; - EMC(0x40C) = _cfg_100[0x1A]; - EMC(0x410) = _cfg_100[0x1B]; - EMC(0x418) = _cfg_100[0x1C]; - EMC(0x41C) = _cfg_100[0x1D]; - EMC(0x420) = _cfg_100[0x1E]; - EMC(0x424) = _cfg_100[0x1F]; - if (_cfg[0xE]) - *(vu32 *)_cfg[0xE] = _cfg[0xF]; - EMC(0x30C) = _cfg[0x31]; - EMC(0x578) = _cfg[0x32]; - EMC(0x2F4) = _cfg[0x33]; - EMC(0x458) = _cfg[0x1D]; - EMC(0x45C) = _cfg[0x1E]; - EMC(0x5B0) = _cfg[0x1F]; - EMC(0x5B4) = _cfg[0x20]; - EMC(0x5CC) = _cfg[0x21]; - EMC(0x574) = _cfg[0x22]; - EMC(0x2DC) = _cfg[0x23]; - EMC(0xC48) = _cfg[0x2A]; - EMC(0xC70) = _cfg[0x2B]; - EMC(0xC74) = _cfg[0x2C]; - EMC(0xC4C) = _cfg[0x2D]; - EMC(0xC78) = _cfg[0x2E]; - EMC(0x464) = _cfg[0x26]; - EMC(0xC44) = _cfg[0x2F]; - EMC(0x5E4) = _cfg_120[0xD]; - EMC(0x5E8) = _cfg_120[0xE]; - EMC(0x2C8) = _cfg[0xB0]; - EMC(0x588) = _cfg_120[1]; - EMC(0x58C) = _cfg_120[2]; - EMC(0x594) = _cfg_120[3]; - EMC(0x598) = _cfg_120[4]; - EMC(0x59C) = _cfg_120[5]; - EMC(0x5A0) = _cfg_120[6]; - EMC(0x5A4) = _cfg_120[7]; - EMC(0x5A8) = _cfg_120[8]; - EMC(0x5AC) = _cfg_120[9]; - EMC(0x5B8) = _cfg_120[0xA]; - EMC(0x5BC) = _cfg_120[0xB]; - EMC(0x5C4) = _cfg_120[0xC]; - EMC(0x330) = (_cfg_120[0x16] | 0xFE40FE40) & 0x1FFF1FFF; - EMC(0xC40) = _cfg_120[0x12]; - EMC(0x318) = _cfg_120[0x17]; - EMC(0x334) = _cfg_120[0x18] & 0xFF7FFF7F; - EMC(0x31C) = _cfg_120[0x19]; - EMC(0xC3C) = _cfg_120[0x1A]; - EMC(0xC54) = _cfg_120[0x1B]; - EMC(0xC50) = _cfg_120[0x1C]; - EMC(0xC64) = _cfg_120[0x1F]; - EMC(0xC5C) = _cfg_120[0x1D]; - EMC(0xC58) = _cfg_120[0x1E]; - EMC(0xC60) = _cfg[0x141]; - EMC(0x49C) = _cfg[0x142]; - EMC(0x720) = _cfg[0x143]; - EMC(0x724) = _cfg[0x144]; - EMC(0x728) = _cfg[0x145]; - EMC(0x72C) = _cfg[0x146]; - EMC(0x730) = _cfg[0x147]; - EMC(0x734) = _cfg[0x148]; - EMC(0x740) = _cfg[0x14D]; - EMC(0x744) = _cfg[0x14E]; - EMC(0x748) = _cfg[0x14F]; - EMC(0x74C) = _cfg[0x150]; - EMC(0x750) = _cfg[0x151]; - EMC(0x754) = _cfg[0x152]; - EMC(0x760) = _cfg[0x153]; - EMC(0x770) = _cfg[0x154]; - EMC(0x774) = _cfg[0x155]; - EMC(0x778) = _cfg[0x156]; - EMC(0x780) = _cfg[0x157]; - EMC(0x784) = _cfg[0x158]; - EMC(0x788) = _cfg[0x159]; - EMC(0xBE0) = _cfg[0xB6]; - EMC(0xBE4) = _cfg[0xB7]; - EMC(0xBF0) = _cfg[0xB8]; - EMC(0xBF4) = _cfg[0xB9]; - EMC(0xCF4) = _cfg[0xBA]; - EMC(0x600) = _cfg[0xBD]; - EMC(0x604) = _cfg[0xBE]; - EMC(0x608) = _cfg[0xBF]; - EMC(0x60C) = _cfg[0xC0]; - EMC(0x610) = _cfg[0xC1]; - EMC(0x614) = _cfg[0xC2]; - EMC(0x620) = _cfg[0xC3]; - EMC(0x624) = _cfg[0xC4]; - EMC(0x628) = _cfg[0xC5]; - EMC(0x62C) = _cfg[0xC6]; - EMC(0x630) = _cfg[0xC7]; - EMC(0x634) = _cfg[0xC8]; - EMC(0x330) = _cfg_120[0x16]; - EMC(0x640) = _cfg[0xC9]; - EMC(0x644) = _cfg[0xCA]; - EMC(0x648) = _cfg[0xCB]; - EMC(0x64C) = _cfg[0xCC]; - EMC(0x650) = _cfg[0xCD]; - EMC(0x654) = _cfg[0xCE]; - EMC(0x660) = _cfg[0xCF]; - EMC(0x664) = _cfg[0xD0]; - EMC(0x668) = _cfg[0xD1]; - EMC(0x66C) = _cfg[0xD2]; - EMC(0x670) = _cfg[0xD3]; - EMC(0x674) = _cfg[0xD4]; - EMC(0x680) = _cfg[0xD5]; - EMC(0x684) = _cfg[0xD6]; - EMC(0x688) = _cfg[0xD7]; - EMC(0x68C) = _cfg[0xD8]; - EMC(0x690) = _cfg[0xD9]; - EMC(0x694) = _cfg[0xDA]; - EMC(0x6A0) = _cfg[0xDB]; - EMC(0x6A4) = _cfg[0xDC]; - EMC(0x6A8) = _cfg[0xDD]; - EMC(0x6AC) = _cfg[0xDE]; - EMC(0x6B0) = _cfg[0xDF]; - EMC(0x6B4) = _cfg[0xE0]; - EMC(0x6C0) = _cfg[0xE1]; - EMC(0x6C4) = _cfg[0xE2]; - EMC(0x6C8) = _cfg[0xE3]; - EMC(0x6CC) = _cfg[0xE4]; - EMC(0x6E0) = _cfg[0xE5]; - EMC(0x6E4) = _cfg[0xE6]; - EMC(0x6E8) = _cfg[0xE7]; - EMC(0x6EC) = _cfg[0xE8]; - EMC(0xC00) = _cfg[0xE9]; - EMC(0xC04) = _cfg[0xEA]; - EMC(0xC08) = _cfg[0xEB]; - EMC(0xC0C) = _cfg[0xEC]; - EMC(0xC10) = _cfg[0xED]; - EMC(0xC20) = _cfg[0xEE]; - EMC(0xC24) = _cfg[0xEF]; - EMC(0xC28) = _cfg[0xF0]; - EMC(0xC68) = (*((u8 *)_cfg + 0x500) | 0xFFFFFFFE) & 0xF; - if (_cfg[0xC]) - *(vu32 *)_cfg[0xC] = _cfg[0xD]; - EMC(0x28) = 1; - MC(0x648) = _cfg[0x180]; - MC(0x978) = _cfg[0x181]; - MC(0x64C) = _cfg[0x182]; - MC(0x418) = _cfg[0x183]; - MC(0x590) = _cfg[0x184]; - MC(0x984) = _cfg[0x185]; - MC(0x988) = _cfg[0x186]; - MC(0x54) = _cfg[0x15A]; - MC(0x58) = _cfg[0x15B]; - MC(0x5C) = _cfg[0x15C]; - MC(0x60) = _cfg[0x15D]; - MC(0x64) = _cfg[0x15E]; - MC(0x68) = _cfg[0x15F]; - MC(0x6C) = _cfg[0x160]; - MC(0x50) = _cfg[0x161]; - MC(0x670) = _cfg[0x187]; - MC(0x9D4) = _cfg[0x188]; - MC(0x674) = _cfg[0x189]; - MC(0x9A0) = _cfg[0x1D6]; - MC(0x9A8) = _cfg[0x1D7]; - MC(0x9A4) = _cfg[0x1D8]; - MC(0x90) = _cfg[0x162]; - MC(0x94) = _cfg[0x163]; - MC(0x6F0) = _cfg[0x164]; - MC(0x6F4) = _cfg[0x165]; - MC(0x98) = _cfg[0x166]; - MC(0x9C) = _cfg[0x167]; - MC(0xA0) = _cfg[0x168]; - MC(0xA4) = _cfg[0x169]; - MC(0xA8) = _cfg[0x16A]; - MC(0xAC) = _cfg[0x16B]; - MC(0xB0) = _cfg[0x16C]; - MC(0xB4) = _cfg[0x16D]; - MC(0xB8) = _cfg[0x16E]; - MC(0xBC) = _cfg[0x16F]; - MC(0x6C4) = _cfg[0x17D]; - MC(0xC0) = _cfg[0x170]; - MC(0xC4) = _cfg[0x171]; - MC(0x6C0) = _cfg[0x172]; - MC(0xD0) = _cfg[0x173]; - MC(0xD4) = _cfg[0x174]; - MC(0xD8) = _cfg[0x175]; - MC(0xDC) = _cfg[0x176]; - MC(0xC8) = _cfg[0x177]; - MC(0xE0) = _cfg[0x178]; - MC(0xE8) = _cfg[0x179]; - MC(0x968) = _cfg[0x17A]; - MC(0xEC) = _cfg[0x17B]; - MC(0x9DC) = _cfg[0x17C]; - MC(0xFC) = 1; - MC(0xF4) = _cfg[0x17E]; - MC(0x100) = _cfg[0x17F]; - EMC(0x10) = _cfg[0x34]; - EMC(0x140) = _cfg_100[7]; - EMC(0x700) = _cfg[0x27]; - EMC(0x704) = _cfg[0x28]; - EMC(0x708) = _cfg[0x29]; - EMC(0x2F8) = _cfg[0x24]; - EMC(0x300) = _cfg[0x25]; - EMC(0x2A8) = _cfg[0x1B]; - EMC(0x2A4) = _cfg[0x1C]; - sleep(_cfg[0x30]); - if (_cfg[0x10]) - *(vu32 *)_cfg[0x10] = _cfg[0x11]; - EMC(0x2B8) = _cfg[0xA4]; - EMC(0x560) = _cfg[0xA5]; - EMC(0x55C) = _cfg[0xBB]; - EMC(0x554) = _cfg[0xBC]; - EMC(0xF0) = _cfg[0xAB]; - EMC(0xF4) = _cfg[0xAC]; - EMC(0xC8) = _cfg[0xA1]; - EMC(0xC4) = _cfg[0xA2]; - EMC(0x104) = _cfg[0x7A]; - EMC(0x2C) = _cfg[0x3A]; - EMC(0x30) = _cfg[0x3B]; - EMC(0x590) = _cfg[0x3C]; - EMC(0x580) = _cfg[0x3D]; - EMC(0xC0) = _cfg[0x3E]; - EMC(0x34) = _cfg[0x3F]; - EMC(0x38) = _cfg[0x40]; - EMC(0xAC) = _cfg[0x47]; - EMC(0x144) = _cfg[0x41]; - EMC(0x148) = _cfg[0x42]; - EMC(0x3C) = _cfg[0x43]; - EMC(0x40) = _cfg[0x44]; - EMC(0x44) = _cfg[0x45]; - EMC(0x48) = _cfg[0x46]; - EMC(0x5C0) = _cfg[0x48]; - EMC(0x4C) = _cfg[0x49]; - EMC(0x50) = _cfg[0x4A]; - EMC(0x54) = _cfg[0x4B]; - EMC(0x58) = _cfg[0x4C]; - EMC(0xB8) = _cfg[0x4D]; - EMC(0x5C) = _cfg[0x4E]; - EMC(0x4E0) = _cfg[0x4F]; - EMC(0x498) = _cfg[0x50]; - EMC(0x494) = _cfg[0x51]; - EMC(0x2D0) = _cfg[0x52]; - EMC(0x490) = _cfg[0x53]; - EMC(0x48C) = _cfg[0x54]; - EMC(0x60) = _cfg[0x55]; - EMC(0x568) = _cfg[0x56]; - EMC(0x468) = _cfg[0x57]; - EMC(0x46C) = _cfg[0x58]; - EMC(0x14C) = _cfg[0x59]; - EMC(0x150) = _cfg[0x5A]; - EMC(0x154) = _cfg[0x5B]; - EMC(0x56C) = _cfg[0x5C]; - EMC(0xC68) = _cfg[0x140]; - EMC(0x8) = _cfg[0xA9]; - EMC(0x64) = _cfg[0x5D]; - EMC(0x428) = 0; - EMC(0x68) = _cfg[0x5E]; - EMC(0x6C) = _cfg[0x5F]; - EMC(0x2CC) = _cfg[0x60]; - EMC(0x2D8) = _cfg[0x61]; - EMC(0x2D4) = _cfg[0x62]; - EMC(0x564) = _cfg[0x63]; - EMC(0x70) = _cfg[0x64]; - EMC(0x74) = _cfg[0x65]; - EMC(0x3DC) = _cfg[0x66]; - EMC(0x78) = _cfg[0x67]; - EMC(0x7C) = _cfg[0x68]; - EMC(0x80) = _cfg[0x69]; - EMC(0x84) = _cfg[0x6A]; - EMC(0x88) = _cfg[0x6B]; - EMC(0x8C) = _cfg[0x6C]; - EMC(0x11C) = _cfg[0x6D]; - EMC(0x118) = _cfg[0x6E]; - EMC(0xB4) = _cfg[0x6F]; - EMC(0x90) = _cfg[0x70]; - EMC(0x3E4) = _cfg[0x71]; - EMC(0x94) = _cfg[0x72]; - EMC(0x158) = _cfg[0x73]; - EMC(0x15C) = _cfg[0x74]; - EMC(0x98) = _cfg[0x75]; - EMC(0x9C) = _cfg[0x76]; - EMC(0xA0) = _cfg[0x77]; - EMC(0xA4) = _cfg[0x78]; - EMC(0xA8) = _cfg[0x79]; - EMC(0xB0) = _cfg[0xF2]; - EMC(0x2BC) = _cfg[0xAF]; - EMC(0x2C0) = _cfg[0xB1]; - EMC(0x100) = _cfg[0x8A] & 0xFFFFFFFD; - EMC(0x120) = _cfg[0x8B]; - EMC(0x440) = _cfg_120[0xF]; - EMC(0x444) = _cfg_120[0x10]; - EMC(0x448) = _cfg_120[0x11]; - EMC(0x124) = _cfg_100[0x17]; - EMC(0x480) = *_cfg_120; - EMC(0xC) = ((_cfg[0xA3] & 4 | 0x3C00000) & 0xFFFFFFF7 | _cfg[0xA3] & 8) & 0xFFFFFFFD | _cfg[0xA3] & 2; - if ((_cfg[0x1D4] & 0x80000000) != 0) - { - *(vu32 *)(4 * _cfg[0x1D4] + 0x70000000) = _cfg[0x1D5]; - MC(0xFC) = 1; - } - PMC(0x45C) = ((4 * _cfg_120[0xF] >> 2) + 0x40000000) & 0xCFFF0000; - sleep(_cfg_100[0x11]); - if (!_cfg[0x1B]) - EMC(0x2A4) = _cfg[0x1C] | 0x200; - EMC(0x334) = _cfg_120[0x18]; - if (_cfg[0xFA] << 31) - { - if (*_cfg == 2) - EMC(0x2E4) = 8 * _cfg[0xF4]; - if (*_cfg == 3) - { - EMC(0x2E4) = _cfg[0xF4]; - EMC(0x2E8) = _cfg[0xF5]; - } - } - EMC(0x28) = 1; - sleep(_cfg[0x39]); - PMC(0x4E4) &= 0xFFF8007F; - sleep(_cfg_100[0x15]); - if (*_cfg == 2) - { - EMC(0x24) = (_cfg[0x37] << 16) | (_cfg[0x38] << 12); - sleep(_cfg[0x36] + 200); - EMC(0x24) = ((_cfg[0x37] << 16) | (_cfg[0x38] << 12)) + 0x100; - sleep(_cfg[0x36] + 500); - } - if (*_cfg == 3) - { - EMC(0x24) = (_cfg[0x37] << 16) | (_cfg[0x38] << 12); - sleep(_cfg[0x36] + 200); - EMC(0x24) = ((_cfg[0x37] << 16) | (_cfg[0x38] << 12)) + 0x100; - sleep(_cfg[0x36] + 2000); - } - EMC(0x24) = ((_cfg[0x37] << 16) | (_cfg[0x38] << 12)) + 0x101; - sleep(_cfg[0x35]); - if (*_cfg != 3) - EMC(0xDC) = (_cfg[0xB2] << 30) + 1; - if (*_cfg == 1) - sleep(_cfg[0x36] + 200); - if (*_cfg == 3) - { - if (_cfg[0x12]) - *(vu32 *)_cfg[0x12] = _cfg[0x13]; - EMC(0x134) = _cfg[0x91]; - EMC(0xE8) = _cfg[0x90]; - EMC(0x138) = _cfg[0x92]; - EMC(0x13C) = _cfg[0x93]; - EMC(0x4A4) = _cfg[0x94]; - EMC(0x4C4) = _cfg[0x9A]; - EMC(0x4AC) = _cfg[0x95]; - EMC(0x4BC) = _cfg[0x98]; - EMC(0x4B0) = _cfg[0x96]; - EMC(0x4C0) = _cfg[0x99]; - if (_cfg[0xFA] << 31) - { - EMC(0x2EC) = _cfg[0xF7]; - sleep(_cfg[0xF9]); - EMC(0x2EC) = _cfg[0xF7] ^ 3; - if (!(_cfg[0xB2] & 2)) - { - EMC(0x2EC) = _cfg[0xF8]; - sleep(_cfg[0xF9]); - EMC(0x2EC) = _cfg[0xF8] ^ 3; - } - } - } - PMC(0x1D0) = _cfg_100[0xF]; - if (_cfg[0] == 1 || _cfg[0] == 2 || _cfg[0] == 3) - { - EMC(0x2E0) = _cfg[0xF3]; - EMC(0x2E4) = _cfg[0xF4]; - EMC(0x2E8) = _cfg[0xF5]; - } - if (_cfg[0x14]) - *(vu32 *)_cfg[0x14] = _cfg[0x15]; - EMC(0x28) = 1; - if (_cfg_100[8]) - EMC(0xD4) = ((1 << _cfg_100[8] << 8) - 0xFD) | (_cfg[0x38] << 30); - EMC(0x20) = _cfg[0xB2] | 0x80000000; - EMC(0x3E0) = _cfg[0xAD]; - EMC(0x5F4) = _cfg[0xA8]; - EMC(0xC) = _cfg[0xA3]; - EMC(0x310) = _cfg[0xB4]; - EMC(0x314) = _cfg[0xB5]; - EMC(0x3D8) = _cfg[0xB3]; - EMC(0x100) = _cfg[0x8A] | 2; - EMC(0x28) = 1; - EMC(0x558) = _cfg[0xA6]; - EMC(0x4D8) = _cfg[0xA7]; - SYSREG(AHB_ARBITRATION_XBAR_CTRL) = SYSREG(AHB_ARBITRATION_XBAR_CTRL) & 0xFFFEFFFF | (*((u16 *)_cfg + 0x15C) << 16); - MC(0x650) = _cfg[0x18A]; - MC(0x678) = _cfg[0x18B]; - MC(0x9AC) = _cfg[0x1D9]; - MC(MC_EMEM_CFG_ACCESS_CTRL) = 1; //Disable write access to a bunch of MC registers. -} - -void sdram_init() -{ - u32 sdram_id = _get_sdram_id(); - const u32 *cfg = _dram_cfgs[sdram_id]; //TODO: sdram_id should be in [0,4]. - - i2c_send_byte(I2C_5, 0x3C, 0x22, 0x05); - i2c_send_byte(I2C_5, 0x3C, 0x17, 40); //40 = (1000 * 1100 - 600000) / 12500 - - PMC(APBDEV_PMC_VDDP_SEL) = cfg[0x10C]; - sleep(cfg[0x10D]); - PMC(APBDEV_PMC_DDR_PWR) = PMC(0xE8); - PMC(APBDEV_PMC_NO_IOPOWER) = cfg[0x114]; - PMC(APBDEV_PMC_REG_SHORT) = cfg[0x113]; - PMC(APBDEV_PMC_DDR_CNTRL) = cfg[0x116]; - - if (cfg[8]) - *(vu32 *)cfg[8] = cfg[9]; - - _sdram_config(cfg); -} diff --git a/fusee/fusee-secondary/src/hwinit/sdram.h b/fusee/fusee-secondary/src/hwinit/sdram.h deleted file mode 100644 index 19db6da9b..000000000 --- a/fusee/fusee-secondary/src/hwinit/sdram.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _SDRAM_H_ -#define _SDRAM_H_ - -void sdram_init(); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/sdram.inl b/fusee/fusee-secondary/src/hwinit/sdram.inl deleted file mode 100644 index 788dcc8aa..000000000 --- a/fusee/fusee-secondary/src/hwinit/sdram.inl +++ /dev/null @@ -1,812 +0,0 @@ -static const u8 _dram_cfg_0[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, - 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, - 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, - 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, - 0xA6, 0xA6, 0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - 0x1F, 0x1F, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, - 0xA1, 0x01, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, - 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x16, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, - 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, - 0xBF, 0x3B, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, - 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, - 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, - 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, - 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, - 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, 0x00, 0x0D, 0x08, - 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00, 0x00, 0x0B, 0x08, - 0x72, 0x72, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x0D, 0x0C, - 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x04, 0x00, 0x01, 0x08, - 0x00, 0x00, 0x11, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0xCC, 0x00, - 0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, - 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x00, 0x80, - 0x01, 0x00, 0x00, 0x00, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x00, 0x00, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, - 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28, 0x28, 0x28, - 0x28, 0x28, 0x28, 0x28, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, - 0xBE, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75, 0x64, 0x32, - 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45, 0x32, 0x67, - 0x00, 0x00, 0x00, 0x00, 0x49, 0x92, 0x24, 0x00, 0x49, 0x92, 0x24, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x2F, 0x41, 0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, - 0xFF, 0xFF, 0xAF, 0x4F, 0xFF, 0xFF, 0xFF, 0x7F, 0x0B, 0xD7, 0x06, 0x40, - 0x00, 0x00, 0x02, 0x00, 0x08, 0x08, 0x03, 0x00, 0x00, 0x5C, 0x01, 0x00, - 0x10, 0x10, 0x10, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, - 0x37, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, - 0x00, 0x30, 0x00, 0x00, 0x11, 0x01, 0x00, 0x02, 0x08, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0A, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static const u8 _dram_cfg_3[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, - 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x76, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x7E, 0x16, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static const u32 *_dram_cfgs[5] = { - (const u32 *)_dram_cfg_0, - (const u32 *)_dram_cfg_1, - (const u32 *)_dram_cfg_2, - (const u32 *)_dram_cfg_3, - (const u32 *)_dram_cfg_4 -}; diff --git a/fusee/fusee-secondary/src/hwinit/t210.h b/fusee/fusee-secondary/src/hwinit/t210.h deleted file mode 100644 index 578d6282b..000000000 --- a/fusee/fusee-secondary/src/hwinit/t210.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef _T210_H_ -#define _T210_H_ - -#include "types.h" - -#define HOST1X_BASE 0x50000000 -#define DISPLAY_A_BASE 0x54200000 -#define DSI_BASE 0x54300000 -#define VIC_BASE 0x54340000 -#define TSEC_BASE 0x54500000 -#define SOR1_BASE 0x54580000 -#define TMR_BASE 0x60005000 -#define CLOCK_BASE 0x60006000 -#define FLOW_CTLR_BASE 0x60007000 -#define SYSREG_BASE 0x6000C000 -#define SB_BASE (SYSREG_BASE + 0x200) -#define GPIO_BASE 0x6000D000 -#define GPIO_1_BASE (GPIO_BASE) -#define GPIO_2_BASE (GPIO_BASE + 0x100) -#define GPIO_3_BASE (GPIO_BASE + 0x200) -#define GPIO_6_BASE (GPIO_BASE + 0x500) -#define EXCP_VEC_BASE 0x6000F000 -#define PINMUX_AUX_BASE 0x70003000 -#define UART_BASE 0x70006000 -#define PMC_BASE 0x7000E400 -#define SYSCTR0_BASE 0x7000F000 -#define FUSE_BASE 0x7000F800 -#define MC_BASE 0x70019000 -#define EMC_BASE 0x7001B000 -#define MIPI_CAL_BASE 0x700E3000 -#define I2S_BASE 0x702D1000 - -#define _REG(base, off) *(vu32 *)((base) + (off)) - -#define HOST1X(off) _REG(HOST1X_BASE, off) -#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off) -#define DSI(off) _REG(DSI_BASE, off) -#define VIC(off) _REG(VIC_BASE, off) -#define TSEC(off) _REG(TSEC_BASE, off) -#define SOR1(off) _REG(SOR1_BASE, off) -#define TMR(off) _REG(TMR_BASE, off) -#define CLOCK(off) _REG(CLOCK_BASE, off) -#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off) -#define SYSREG(off) _REG(SYSREG_BASE, off) -#define SB(off) _REG(SB_BASE, off) -#define GPIO_1(off) _REG(GPIO_1_BASE, off) -#define GPIO_2(off) _REG(GPIO_2_BASE, off) -#define GPIO_3(off) _REG(GPIO_3_BASE, off) -#define GPIO_6(off) _REG(GPIO_6_BASE, off) -#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off) -#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off) -#define PMC(off) _REG(PMC_BASE, off) -#define SYSCTR0(off) _REG(SYSCTR0_BASE, off) -#define FUSE(off) _REG(FUSE_BASE, off) -#define MC(off) _REG(MC_BASE, off) -#define EMC(off) _REG(EMC_BASE, off) -#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off) -#define I2S(off) _REG(I2S_BASE, off) - -/*! System registers. */ -#define AHB_ARBITRATION_XBAR_CTRL 0xE0 - -/*! Secure boot registers. */ -#define SB_CSR_0 0x0 -#define SB_AA64_RESET_LOW 0x30 -#define SB_AA64_RESET_HIGH 0x34 - -/*! SYSCTR0 registers. */ -#define SYSCTR0_CNTFID0 0x20 - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/tsec.c b/fusee/fusee-secondary/src/hwinit/tsec.c deleted file mode 100644 index 3b229fc52..000000000 --- a/fusee/fusee-secondary/src/hwinit/tsec.c +++ /dev/null @@ -1,113 +0,0 @@ -#include -#include "tsec.h" -#include "clock.h" -#include "t210.h" - -static int _tsec_dma_wait_idle() -{ - u32 timeout = TMR(0x10) + 10000000; - - while (!(TSEC(0x1118) & 2)) - if (TMR(0x10) > timeout) - return 0; - - return 1; -} - -static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offset) -{ - u32 cmd; - - if (not_imem) - cmd = 0x600; // DMA 0x100 bytes - else - cmd = 0x10; // dma imem - - TSEC(0x1114) = i_offset; // tsec_dmatrfmoffs_r - TSEC(0x111C) = pa_offset; // tsec_dmatrffboffs_r - TSEC(0x1118) = cmd; // tsec_dmatrfcmd_r - - return _tsec_dma_wait_idle(); -} - -int tsec_query(u32 carveout, u8 *dst, u32 rev) -{ - int res = 0; - - //Enable clocks. - clock_enable_host1x(); - clock_enable_tsec(); - clock_enable_sor_safe(); - clock_enable_sor0(); - clock_enable_sor1(); - clock_enable_kfuse(); - - //Configure Falcon. - TSEC(0x110C) = 0; // tsec_dmactl_r - TSEC(0x1010) = 0xFFF2; // tsec_irqmset_r - TSEC(0x101C) = 0xFFF0; // tsec_irqdest_r - TSEC(0x1048) = 3; // tsec_itfen_r - if (!_tsec_dma_wait_idle()) - { - res = -1; - goto out; - } - - //Load firmware. - TSEC(0x1110) = carveout >> 8;// tsec_dmatrfbase_r - for (u32 addr = 0; addr < 0xF00; addr += 0x100) - if (!_tsec_dma_pa_to_internal_100(0, addr, addr)) - { - res = -2; - goto out; - } - - //Execute firmware. - HOST1X(0x3300) = 0x34C2E1DA; - TSEC(0x1044) = 0; - TSEC(0x1040) = rev; - TSEC(0x1104) = 0; // tsec_bootvec_r - TSEC(0x1100) = 2; // tsec_cpuctl_r - if (!_tsec_dma_wait_idle()) - { - res = -3; - goto out; - } - u32 timeout = TMR(0x10) + 2000000; - while (!TSEC(0x1044)) - if (TMR(0x10) > timeout) - { - res = -4; - goto out; - } - if (TSEC(0x1044) != 0xB0B0B0B0) - { - res = -5; - goto out; - } - - //Fetch result. - HOST1X(0x3300) = 0; - u32 buf[4]; - buf[0] = SOR1(0x1E8); - buf[1] = SOR1(0x21C); - buf[2] = SOR1(0x208); - buf[3] = SOR1(0x20C); - SOR1(0x1E8) = 0; - SOR1(0x21C) = 0; - SOR1(0x208) = 0; - SOR1(0x20C) = 0; - memcpy(dst, &buf, 0x10); - -out:; - - //Disable clocks. - clock_disable_kfuse(); - clock_disable_sor1(); - clock_disable_sor0(); - clock_disable_sor_safe(); - clock_disable_tsec(); - clock_disable_host1x(); - - return res; -} diff --git a/fusee/fusee-secondary/src/hwinit/tsec.h b/fusee/fusee-secondary/src/hwinit/tsec.h deleted file mode 100644 index 03fb503d2..000000000 --- a/fusee/fusee-secondary/src/hwinit/tsec.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _TSEC_H_ -#define _TSEC_H_ - -#include "types.h" - -int tsec_query(u32 carveout, u8 *dst, u32 rev); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/types.h b/fusee/fusee-secondary/src/hwinit/types.h deleted file mode 100644 index dff2978da..000000000 --- a/fusee/fusee-secondary/src/hwinit/types.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _TYPES_H_ -#define _TYPES_H_ - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned int u32; -typedef volatile unsigned int vu32; -typedef unsigned long long int u64; -typedef volatile unsigned long long int vu64; - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/uart.c b/fusee/fusee-secondary/src/hwinit/uart.c deleted file mode 100644 index b9b35aa8c..000000000 --- a/fusee/fusee-secondary/src/hwinit/uart.c +++ /dev/null @@ -1,62 +0,0 @@ -#include "uart.h" -#include "t210.h" -#include "util.h" - -/* UART A, B, C, D and E. */ -static const u32 uart_baseoff[5] = { 0, 0x40, 0x200, 0x300, 0x400 }; - -void uart_init(u32 idx, u32 baud) -{ - volatile uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); - - //Set baud rate. - u32 rate = (8 * baud + 408000000) / (16 * baud); - uart->UART_LCR = 0x80; //Enable DLAB. - uart->UART_THR_DLAB = (u8)rate; //Divisor latch LSB. - uart->UART_IER_DLAB = (u8)(rate >> 8); //Divisor latch MSB. - uart->UART_LCR = 0; //Diable DLAB. - - //Setup UART in fifo mode. - uart->UART_IER_DLAB = 0; - uart->UART_IIR_FCR = 7; //Enable and clear TX and RX FIFOs. - volatile u32 tmp = uart->UART_LSR; - sleep(3 * ((baud + 999999) / baud)); - uart->UART_LCR = 3; //Set word length 8. - uart->UART_MCR = 0; - uart->UART_MSR = 0; - uart->UART_IRDA_CSR = 0; - uart->UART_RX_FIFO_CFG = 1; - uart->UART_MIE = 0; - uart->UART_ASR = 0; -} - -void uart_wait_idle(u32 idx, u32 which) -{ - volatile uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); - while (!(uart->UART_VENDOR_STATUS & which)) - ; -} - -void uart_send(u32 idx, u8 *buf, u32 len) -{ - volatile uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); - - for (u32 i = 0; i != len; i++) - { - while (uart->UART_LSR & UART_TX_FIFO_FULL) - ; - uart->UART_THR_DLAB = buf[i]; - }; -} - -void uart_recv(u32 idx, u8 *buf, u32 len) -{ - volatile uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); - - for (u32 i = 0; i != len; i++) - { - while (uart->UART_LSR & UART_RX_FIFO_EMPTY) - ; - buf[i] = uart->UART_THR_DLAB; - }; -} diff --git a/fusee/fusee-secondary/src/hwinit/uart.h b/fusee/fusee-secondary/src/hwinit/uart.h deleted file mode 100644 index ac8222215..000000000 --- a/fusee/fusee-secondary/src/hwinit/uart.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef _UART_H_ -#define _UART_H_ - -#include "types.h" - -#define UART_A 0 -#define UART_B 1 -#define UART_C 2 -//TODO: define clock inits for those. -/*#define UART_D 3 -#define UART_E 4*/ - -#define BAUD_115200 115200 - -#define UART_TX_IDLE 0x00000001 -#define UART_RX_IDLE 0x00000002 -#define UART_TX_FIFO_FULL 0x100 -#define UART_RX_FIFO_EMPTY 0x200 - -typedef struct _uart_t -{ - /* 0x00 */ u32 UART_THR_DLAB; - /* 0x04 */ u32 UART_IER_DLAB; - /* 0x08 */ u32 UART_IIR_FCR; - /* 0x0C */ u32 UART_LCR; - /* 0x10 */ u32 UART_MCR; - /* 0x14 */ u32 UART_LSR; - /* 0x18 */ u32 UART_MSR; - /* 0x1C */ u32 UART_SPR; - /* 0x20 */ u32 UART_IRDA_CSR; - /* 0x24 */ u32 UART_RX_FIFO_CFG; - /* 0x28 */ u32 UART_MIE; - /* 0x2C */ u32 UART_VENDOR_STATUS; - /* 0x30 */ u8 _pad_30[0x0C]; - /* 0x3C */ u32 UART_ASR; -} uart_t; - -void uart_init(u32 idx, u32 baud); -void uart_wait_idle(u32 idx, u32 which); -void uart_send(u32 idx, u8 *buf, u32 len); -void uart_recv(u32 idx, u8 *buf, u32 len); - -#endif diff --git a/fusee/fusee-secondary/src/hwinit/util.c b/fusee/fusee-secondary/src/hwinit/util.c deleted file mode 100644 index 780b31177..000000000 --- a/fusee/fusee-secondary/src/hwinit/util.c +++ /dev/null @@ -1,16 +0,0 @@ -#include "util.h" -#include "t210.h" - -void sleep(u32 ticks) -{ - u32 start = TMR(0x10); - while (TMR(0x10) - start <= ticks) - ; -} - -void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops) -{ - for(u32 i = 0; i < num_ops; i++) - base[ops[i].off] = ops[i].val; -} - diff --git a/fusee/fusee-secondary/src/hwinit/util.h b/fusee/fusee-secondary/src/hwinit/util.h deleted file mode 100644 index 13bc8024f..000000000 --- a/fusee/fusee-secondary/src/hwinit/util.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _UTIL_H_ -#define _UTIL_H_ - -#include "types.h" -#pragma GCC diagnostic ignored "-Wparentheses" -#pragma GCC diagnostic ignored "-Wunused-variable" - -typedef struct _cfg_op_t -{ - u32 off; - u32 val; -} cfg_op_t; - -void sleep(u32 ticks); -void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops); - -#endif diff --git a/fusee/fusee-secondary/src/i2c.c b/fusee/fusee-secondary/src/i2c.c new file mode 100644 index 000000000..a98d7fa6e --- /dev/null +++ b/fusee/fusee-secondary/src/i2c.c @@ -0,0 +1,205 @@ +#include "i2c.h" +#include "utils.h" +#include "timers.h" + +/* Prototypes for internal commands. */ +volatile tegra_i2c_t *i2c_get_registers_from_id(unsigned int id); +void i2c_load_config(volatile tegra_i2c_t *regs); + +bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size); +bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size); + +bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size); +bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size); + +/* Initialize I2C based on registers. */ +void i2c_init(unsigned int id) { + volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id); + + /* Setup divisor, and clear the bus. */ + regs->I2C_I2C_CLK_DIVISOR_REGISTER_0 = 0x50001; + regs->I2C_I2C_BUS_CLEAR_CONFIG_0 = 0x90003; + + /* Load hardware configuration. */ + i2c_load_config(regs); + + /* Wait a while until BUS_CLEAR_DONE is set. */ + for (unsigned int i = 0; i < 10; i++) { + udelay(20000); + if (regs->I2C_INTERRUPT_STATUS_REGISTER_0 & 0x800) { + break; + } + } + + /* Read the BUS_CLEAR_STATUS. Result doesn't matter. */ + regs->I2C_I2C_BUS_CLEAR_STATUS_0; + + /* Read and set the Interrupt Status. */ + uint32_t int_status = regs->I2C_INTERRUPT_STATUS_REGISTER_0; + regs->I2C_INTERRUPT_STATUS_REGISTER_0 = int_status; +} + +/* Sets a bit in a PMIC register over I2C during CPU shutdown. */ +void i2c_send_pmic_cpu_shutdown_cmd(void) { + uint32_t val = 0; + /* PMIC == Device 4:3C. */ + i2c_query(4, 0x3C, 0x41, &val, 1); + val |= 4; + i2c_send(4, 0x3C, 0x41, &val, 1); +} + +/* Queries the value of TI charger bit over I2C. */ +bool i2c_query_ti_charger_bit_7(void) { + uint32_t val = 0; + /* TI Charger = Device 0:6B. */ + i2c_query(0, 0x6B, 0, &val, 1); + return (val & 0x80) != 0; +} + +/* Clears TI charger bit over I2C. */ +void i2c_clear_ti_charger_bit_7(void) { + uint32_t val = 0; + /* TI Charger = Device 0:6B. */ + i2c_query(0, 0x6B, 0, &val, 1); + val &= 0x7F; + i2c_send(0, 0x6B, 0, &val, 1); +} + +/* Sets TI charger bit over I2C. */ +void i2c_set_ti_charger_bit_7(void) { + uint32_t val = 0; + /* TI Charger = Device 0:6B. */ + i2c_query(0, 0x6B, 0, &val, 1); + val |= 0x80; + i2c_send(0, 0x6B, 0, &val, 1); +} + +/* Get registers pointer based on I2C ID. */ +volatile tegra_i2c_t *i2c_get_registers_from_id(unsigned int id) { + switch (id) { + case 0: + return I2C1_REGS; + case 1: + return I2C2_REGS; + case 2: + return I2C3_REGS; + case 3: + return I2C4_REGS; + case 4: + return I2C5_REGS; + case 5: + return I2C6_REGS; + default: + generic_panic(); + } + return NULL; +} + +/* Load hardware config for I2C4. */ +void i2c_load_config(volatile tegra_i2c_t *regs) { + /* Set MSTR_CONFIG_LOAD, TIMEOUT_CONFIG_LOAD, undocumented bit. */ + regs->I2C_I2C_CONFIG_LOAD_0 = 0x25; + + /* Wait a bit for master config to be loaded. */ + for (unsigned int i = 0; i < 20; i++) { + udelay(1); + if (!(regs->I2C_I2C_CONFIG_LOAD_0 & 1)) { + break; + } + } +} + +/* Reads a register from a device over I2C, writes result to output. */ +bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size) { + volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id); + uint32_t val = r; + + /* Write single byte register ID to device. */ + if (!i2c_write(regs, device, &val, 1)) { + return false; + } + /* Limit output size to 32-bits. */ + if (dst_size > 4) { + return false; + } + + return i2c_read(regs, device, dst, dst_size); +} + +/* Writes a value to a register over I2C. */ +bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size) { + uint32_t val = r; + if (src_size == 0) { + return true; + } else if (src_size <= 3) { + memcpy(((uint8_t *)&val) + 1, src, src_size); + return i2c_write(i2c_get_registers_from_id(id), device, &val, src_size + 1); + } else { + return false; + } +} + +/* Writes bytes to device over I2C. */ +bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size) { + if (src_size > 4) { + return false; + } else if (src_size == 0) { + return true; + } + + /* Set device for 7-bit write mode. */ + regs->I2C_I2C_CMD_ADDR0_0 = device << 1; + + /* Load in data to write. */ + regs->I2C_I2C_CMD_DATA1_0 = read32le(src, 0); + + /* Set config with LENGTH = src_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */ + regs->I2C_I2C_CNFG_0 = ((src_size << 1) - 2) | 0x2800; + + i2c_load_config(regs); + + /* Config |= SEND; */ + regs->I2C_I2C_CNFG_0 |= 0x200; + + + while (regs->I2C_I2C_STATUS_0 & 0x100) { + /* Wait until not busy. */ + } + + /* Return CMD1_STAT == SL1_XFER_SUCCESSFUL. */ + return (regs->I2C_I2C_STATUS_0 & 0xF) == 0; +} + +/* Reads bytes from device over I2C. */ +bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size) { + if (dst_size > 4) { + return false; + } else if (dst_size == 0) { + return true; + } + + /* Set device for 7-bit read mode. */ + regs->I2C_I2C_CMD_ADDR0_0 = (device << 1) | 1; + + /* Set config with LENGTH = dst_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */ + regs->I2C_I2C_CNFG_0 = ((dst_size << 1) - 2) | 0x2840; + + i2c_load_config(regs); + + /* Config |= SEND; */ + regs->I2C_I2C_CNFG_0 |= 0x200; + + + while (regs->I2C_I2C_STATUS_0 & 0x100) { + /* Wait until not busy. */ + } + + /* Ensure success. */ + if ((regs->I2C_I2C_STATUS_0 & 0xF) != 0) { + return false; + } + + uint32_t val = regs->I2C_I2C_CMD_DATA1_0; + memcpy(dst, &val, dst_size); + return true; +} diff --git a/fusee/fusee-secondary/src/i2c.h b/fusee/fusee-secondary/src/i2c.h new file mode 100644 index 000000000..e07ed3349 --- /dev/null +++ b/fusee/fusee-secondary/src/i2c.h @@ -0,0 +1,71 @@ +#ifndef FUSEE_I2C_H +#define FUSEE_I2C_H + +#include +#include +#include + +#define I2C234_BASE 0x7000C000 +#define I2C56_BASE 0x7000D000 + +typedef struct { + uint32_t I2C_I2C_CNFG_0; + uint32_t I2C_I2C_CMD_ADDR0_0; + uint32_t I2C_I2C_CMD_ADDR1_0; + uint32_t I2C_I2C_CMD_DATA1_0; + uint32_t I2C_I2C_CMD_DATA2_0; + uint32_t _0x14; + uint32_t _0x18; + uint32_t I2C_I2C_STATUS_0; + uint32_t I2C_I2C_SL_CNFG_0; + uint32_t I2C_I2C_SL_RCVD_0; + uint32_t I2C_I2C_SL_STATUS_0; + uint32_t I2C_I2C_SL_ADDR1_0; + uint32_t I2C_I2C_SL_ADDR2_0; + uint32_t I2C_I2C_TLOW_SEXT_0; + uint32_t _0x38; + uint32_t I2C_I2C_SL_DELAY_COUNT_0; + uint32_t I2C_I2C_SL_INT_MASK_0; + uint32_t I2C_I2C_SL_INT_SOURCE_0; + uint32_t I2C_I2C_SL_INT_SET_0; + uint32_t _0x4C; + uint32_t I2C_I2C_TX_PACKET_FIFO_0; + uint32_t I2C_I2C_RX_FIFO_0; + uint32_t I2C_PACKET_TRANSFER_STATUS_0; + uint32_t I2C_FIFO_CONTROL_0; + uint32_t I2C_FIFO_STATUS_0; + uint32_t I2C_INTERRUPT_MASK_REGISTER_0; + uint32_t I2C_INTERRUPT_STATUS_REGISTER_0; + uint32_t I2C_I2C_CLK_DIVISOR_REGISTER_0; + uint32_t I2C_I2C_INTERRUPT_SOURCE_REGISTER_0; + uint32_t I2C_I2C_INTERRUPT_SET_REGISTER_0; + uint32_t I2C_I2C_SLV_TX_PACKET_FIFO_0; + uint32_t I2C_I2C_SLV_RX_FIFO_0; + uint32_t I2C_I2C_SLV_PACKET_STATUS_0; + uint32_t I2C_I2C_BUS_CLEAR_CONFIG_0; + uint32_t I2C_I2C_BUS_CLEAR_STATUS_0; + uint32_t I2C_I2C_CONFIG_LOAD_0; + uint32_t _0x90; + uint32_t I2C_I2C_INTERFACE_TIMING_0_0; + uint32_t I2C_I2C_INTERFACE_TIMING_1_0; + uint32_t I2C_I2C_HS_INTERFACE_TIMING_0_0; + uint32_t I2C_I2C_HS_INTERFACE_TIMING_1_0; +} tegra_i2c_t; + +#define I2C1_REGS ((volatile tegra_i2c_t *)(I2C234_BASE + 0x000)) +#define I2C2_REGS ((volatile tegra_i2c_t *)(I2C234_BASE + 0x400)) +#define I2C3_REGS ((volatile tegra_i2c_t *)(I2C234_BASE + 0x500)) +#define I2C4_REGS ((volatile tegra_i2c_t *)(I2C234_BASE + 0x700)) +#define I2C5_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x000)) +#define I2C6_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x100)) + +void i2c_init(unsigned int id); +bool i2c_query(unsigned int id, uint8_t device, uint8_t r, void *dst, size_t dst_size); +bool i2c_send(unsigned int id, uint8_t device, uint8_t r, void *src, size_t src_size); + +void i2c_send_pmic_cpu_shutdown_cmd(void); +bool i2c_query_ti_charger_bit_7(void); +void i2c_clear_ti_charger_bit_7(void); +void i2c_set_ti_charger_bit_7(void); + +#endif diff --git a/fusee/fusee-secondary/src/key_derivation.c b/fusee/fusee-secondary/src/key_derivation.c index c048cc05d..900b7f9df 100644 --- a/fusee/fusee-secondary/src/key_derivation.c +++ b/fusee/fusee-secondary/src/key_derivation.c @@ -3,7 +3,7 @@ #include "se.h" #include "exocfg.h" #include "fuse.h" -#include "hwinit.h" +#include "tsec.h" #include "utils.h" #define AL16 ALIGN(16) @@ -39,7 +39,7 @@ static const uint8_t AL16 masterkey_4x_seed[0x10] = { static nx_dec_keyblob_t AL16 g_dec_keyblobs[32]; static int get_tsec_key(void *dst, const void *tsec_fw, size_t tsec_fw_size, uint32_t tsec_key_id) { - return tsec_query((u32)tsec_fw, dst, tsec_key_id); + return tsec_get_key(dst, tsec_key_id, tsec_fw); } static int get_keyblob(nx_keyblob_t *dst, uint32_t revision, const nx_keyblob_t *keyblobs, uint32_t available_revision) { diff --git a/fusee/fusee-secondary/src/lib/driver_utils.h b/fusee/fusee-secondary/src/lib/driver_utils.h index 2a24f67d9..eefc51215 100644 --- a/fusee/fusee-secondary/src/lib/driver_utils.h +++ b/fusee/fusee-secondary/src/lib/driver_utils.h @@ -7,4 +7,4 @@ #define vprintk vprintf #define printk printf -#endif +#endif \ No newline at end of file diff --git a/fusee/fusee-secondary/src/max77620.h b/fusee/fusee-secondary/src/max77620.h new file mode 100644 index 000000000..ad22a06b5 --- /dev/null +++ b/fusee/fusee-secondary/src/max77620.h @@ -0,0 +1,326 @@ +/* + * Defining registers address and its bit definitions of MAX77620 and MAX20024 + * + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#ifndef _MFD_MAX77620_H_ +#define _MFD_MAX77620_H_ + +/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */ +#define MAX77620_REG_CNFGGLBL1 0x00 +#define MAX77620_REG_CNFGGLBL2 0x01 +#define MAX77620_REG_CNFGGLBL3 0x02 +#define MAX77620_REG_CNFG1_32K 0x03 +#define MAX77620_REG_CNFGBBC 0x04 +#define MAX77620_REG_IRQTOP 0x05 +#define MAX77620_REG_INTLBT 0x06 +#define MAX77620_REG_IRQSD 0x07 +#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 +#define MAX77620_REG_IRQ_LVL2_L8 0x09 +#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A +#define MAX77620_REG_ONOFFIRQ 0x0B +#define MAX77620_REG_NVERC 0x0C +#define MAX77620_REG_IRQTOPM 0x0D +#define MAX77620_REG_INTENLBT 0x0E +#define MAX77620_REG_IRQMASKSD 0x0F +#define MAX77620_REG_IRQ_MSK_L0_7 0x10 +#define MAX77620_REG_IRQ_MSK_L8 0x11 +#define MAX77620_REG_ONOFFIRQM 0x12 +#define MAX77620_REG_STATLBT 0x13 +#define MAX77620_REG_STATSD 0x14 +#define MAX77620_REG_ONOFFSTAT 0x15 + +/* SD and LDO Registers */ +#define MAX77620_REG_SD0 0x16 +#define MAX77620_REG_SD1 0x17 +#define MAX77620_REG_SD2 0x18 +#define MAX77620_REG_SD3 0x19 +#define MAX77620_REG_SD4 0x1A +#define MAX77620_REG_DVSSD0 0x1B +#define MAX77620_REG_DVSSD1 0x1C +#define MAX77620_REG_SD0_CFG 0x1D +#define MAX77620_REG_SD1_CFG 0x1E +#define MAX77620_REG_SD2_CFG 0x1F +#define MAX77620_REG_SD3_CFG 0x20 +#define MAX77620_REG_SD4_CFG 0x21 +#define MAX77620_REG_SD_CFG2 0x22 +#define MAX77620_REG_LDO0_CFG 0x23 +#define MAX77620_REG_LDO0_CFG2 0x24 +#define MAX77620_REG_LDO1_CFG 0x25 +#define MAX77620_REG_LDO1_CFG2 0x26 +#define MAX77620_REG_LDO2_CFG 0x27 +#define MAX77620_REG_LDO2_CFG2 0x28 +#define MAX77620_REG_LDO3_CFG 0x29 +#define MAX77620_REG_LDO3_CFG2 0x2A +#define MAX77620_REG_LDO4_CFG 0x2B +#define MAX77620_REG_LDO4_CFG2 0x2C +#define MAX77620_REG_LDO5_CFG 0x2D +#define MAX77620_REG_LDO5_CFG2 0x2E +#define MAX77620_REG_LDO6_CFG 0x2F +#define MAX77620_REG_LDO6_CFG2 0x30 +#define MAX77620_REG_LDO7_CFG 0x31 +#define MAX77620_REG_LDO7_CFG2 0x32 +#define MAX77620_REG_LDO8_CFG 0x33 +#define MAX77620_REG_LDO8_CFG2 0x34 +#define MAX77620_REG_LDO_CFG3 0x35 + +#define MAX77620_LDO_SLEW_RATE_MASK 0x1 + +/* LDO Configuration 3 */ +#define MAX77620_TRACK4_MASK (1 << 5) +#define MAX77620_TRACK4_SHIFT 5 + +/* Voltage */ +#define MAX77620_SDX_VOLT_MASK 0xFF +#define MAX77620_SD0_VOLT_MASK 0x3F +#define MAX77620_SD1_VOLT_MASK 0x7F +#define MAX77620_LDO_VOLT_MASK 0x3F + +#define MAX77620_REG_GPIO0 0x36 +#define MAX77620_REG_GPIO1 0x37 +#define MAX77620_REG_GPIO2 0x38 +#define MAX77620_REG_GPIO3 0x39 +#define MAX77620_REG_GPIO4 0x3A +#define MAX77620_REG_GPIO5 0x3B +#define MAX77620_REG_GPIO6 0x3C +#define MAX77620_REG_GPIO7 0x3D +#define MAX77620_REG_PUE_GPIO 0x3E +#define MAX77620_REG_PDE_GPIO 0x3F +#define MAX77620_REG_AME_GPIO 0x40 +#define MAX77620_REG_ONOFFCNFG1 0x41 +#define MAX77620_REG_ONOFFCNFG2 0x42 + +/* FPS Registers */ +#define MAX77620_REG_FPS_CFG0 0x43 +#define MAX77620_REG_FPS_CFG1 0x44 +#define MAX77620_REG_FPS_CFG2 0x45 +#define MAX77620_REG_FPS_LDO0 0x46 +#define MAX77620_REG_FPS_LDO1 0x47 +#define MAX77620_REG_FPS_LDO2 0x48 +#define MAX77620_REG_FPS_LDO3 0x49 +#define MAX77620_REG_FPS_LDO4 0x4A +#define MAX77620_REG_FPS_LDO5 0x4B +#define MAX77620_REG_FPS_LDO6 0x4C +#define MAX77620_REG_FPS_LDO7 0x4D +#define MAX77620_REG_FPS_LDO8 0x4E +#define MAX77620_REG_FPS_SD0 0x4F +#define MAX77620_REG_FPS_SD1 0x50 +#define MAX77620_REG_FPS_SD2 0x51 +#define MAX77620_REG_FPS_SD3 0x52 +#define MAX77620_REG_FPS_SD4 0x53 +#define MAX77620_REG_FPS_NONE 0 + +#define MAX77620_FPS_SRC_MASK 0xC0 +#define MAX77620_FPS_SRC_SHIFT 6 +#define MAX77620_FPS_PU_PERIOD_MASK 0x38 +#define MAX77620_FPS_PU_PERIOD_SHIFT 3 +#define MAX77620_FPS_PD_PERIOD_MASK 0x07 +#define MAX77620_FPS_PD_PERIOD_SHIFT 0 +#define MAX77620_FPS_TIME_PERIOD_MASK 0x38 +#define MAX77620_FPS_TIME_PERIOD_SHIFT 3 +#define MAX77620_FPS_EN_SRC_MASK 0x06 +#define MAX77620_FPS_EN_SRC_SHIFT 1 +#define MAX77620_FPS_ENFPS_SW_MASK 0x01 +#define MAX77620_FPS_ENFPS_SW 0x01 + +/* Minimum and maximum FPS period time (in microseconds) are + * different for MAX77620 and Max20024. + */ +#define MAX77620_FPS_PERIOD_MIN_US 40 +#define MAX20024_FPS_PERIOD_MIN_US 20 + +#define MAX77620_FPS_PERIOD_MAX_US 2560 +#define MAX20024_FPS_PERIOD_MAX_US 5120 + +#define MAX77620_REG_FPS_GPIO1 0x54 +#define MAX77620_REG_FPS_GPIO2 0x55 +#define MAX77620_REG_FPS_GPIO3 0x56 +#define MAX77620_REG_FPS_RSO 0x57 +#define MAX77620_REG_CID0 0x58 +#define MAX77620_REG_CID1 0x59 +#define MAX77620_REG_CID2 0x5A +#define MAX77620_REG_CID3 0x5B +#define MAX77620_REG_CID4 0x5C +#define MAX77620_REG_CID5 0x5D + +#define MAX77620_REG_DVSSD4 0x5E +#define MAX20024_REG_MAX_ADD 0x70 + +#define MAX77620_CID_DIDM_MASK 0xF0 +#define MAX77620_CID_DIDM_SHIFT 4 + +/* CNCG2SD */ +#define MAX77620_SD_CNF2_ROVS_EN_SD1 (1 << 1) +#define MAX77620_SD_CNF2_ROVS_EN_SD0 (1 << 2) + +/* Device Identification Metal */ +#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF) +/* Device Indentification OTP */ +#define MAX77620_CID5_DIDO(n) ((n) & 0xF) + +/* SD CNFG1 */ +#define MAX77620_SD_SR_MASK 0xC0 +#define MAX77620_SD_SR_SHIFT 6 +#define MAX77620_SD_POWER_MODE_MASK 0x30 +#define MAX77620_SD_POWER_MODE_SHIFT 4 +#define MAX77620_SD_CFG1_ADE_MASK (1 << 3) +#define MAX77620_SD_CFG1_ADE_DISABLE 0 +#define MAX77620_SD_CFG1_ADE_ENABLE (1 << 3) +#define MAX77620_SD_FPWM_MASK 0x04 +#define MAX77620_SD_FPWM_SHIFT 2 +#define MAX77620_SD_FSRADE_MASK 0x01 +#define MAX77620_SD_FSRADE_SHIFT 0 +#define MAX77620_SD_CFG1_FPWM_SD_MASK (1 << 2) +#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0 +#define MAX77620_SD_CFG1_FPWM_SD_FPWM (1 << 2) +#define MAX20024_SD_CFG1_MPOK_MASK (1 << 1) +#define MAX77620_SD_CFG1_FSRADE_SD_MASK (1 << 0) +#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0 +#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0) + +/* LDO_CNFG2 */ +#define MAX77620_LDO_POWER_MODE_MASK 0xC0 +#define MAX77620_LDO_POWER_MODE_SHIFT 6 +#define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2) +#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1) +#define MAX77620_LDO_CFG2_ADE_DISABLE 0 +#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1) +#define MAX77620_LDO_CFG2_SS_MASK (1 << 0) +#define MAX77620_LDO_CFG2_SS_FAST (1 << 0) +#define MAX77620_LDO_CFG2_SS_SLOW 0 + +#define MAX77620_IRQ_TOP_GLBL_MASK (1 << 7) +#define MAX77620_IRQ_TOP_SD_MASK (1 << 6) +#define MAX77620_IRQ_TOP_LDO_MASK (1 << 5) +#define MAX77620_IRQ_TOP_GPIO_MASK (1 << 4) +#define MAX77620_IRQ_TOP_RTC_MASK (1 << 3) +#define MAX77620_IRQ_TOP_32K_MASK (1 << 2) +#define MAX77620_IRQ_TOP_ONOFF_MASK (1 << 1) + +#define MAX77620_IRQ_LBM_MASK (1 << 3) +#define MAX77620_IRQ_TJALRM1_MASK (1 << 2) +#define MAX77620_IRQ_TJALRM2_MASK (1 << 1) + +#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0) +#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0) +#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0 +#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1) +#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1) +#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0 +#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3) +#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0 +#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4) +#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4) +#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5) +#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6) +#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6) +#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6) +#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6) +#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6) + +#define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0) +#define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1) +#define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2) +#define MAX77620_IRQ_LVL2_GPIO_EDGE3 (1 << 3) +#define MAX77620_IRQ_LVL2_GPIO_EDGE4 (1 << 4) +#define MAX77620_IRQ_LVL2_GPIO_EDGE5 (1 << 5) +#define MAX77620_IRQ_LVL2_GPIO_EDGE6 (1 << 6) +#define MAX77620_IRQ_LVL2_GPIO_EDGE7 (1 << 7) + +#define MAX77620_CNFG1_32K_OUT0_EN (1 << 2) + +#define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7) +#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38 +#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3 +#define MAX77620_ONOFFCNFG1_SLPEN (1 << 2) +#define MAX77620_ONOFFCNFG1_PWR_OFF (1 << 1) +#define MAX20024_ONOFFCNFG1_CLRSE 0x18 + +#define MAX77620_ONOFFCNFG2_SFT_RST_WK (1 << 7) +#define MAX77620_ONOFFCNFG2_WD_RST_WK (1 << 6) +#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK (1 << 5) +#define MAX77620_ONOFFCNFG2_WK_ALARM1 (1 << 2) +#define MAX77620_ONOFFCNFG2_WK_EN0 (1 << 0) + +#define MAX77620_GLBLM_MASK (1 << 0) + +#define MAX77620_WDTC_MASK 0x3 +#define MAX77620_WDTOFFC (1 << 4) +#define MAX77620_WDTSLPC (1 << 3) +#define MAX77620_WDTEN (1 << 2) + +#define MAX77620_TWD_MASK 0x3 +#define MAX77620_TWD_2s 0x0 +#define MAX77620_TWD_16s 0x1 +#define MAX77620_TWD_64s 0x2 +#define MAX77620_TWD_128s 0x3 + +#define MAX77620_CNFGGLBL1_LBDAC_EN (1 << 7) +#define MAX77620_CNFGGLBL1_MPPLD (1 << 6) +#define MAX77620_CNFGGLBL1_LBHYST ((1 << 5) | (1 << 4)) +#define MAX77620_CNFGGLBL1_LBHYST_N (1 << 4) +#define MAX77620_CNFGGLBL1_LBDAC 0x0E +#define MAX77620_CNFGGLBL1_LBDAC_N (1 << 1) +#define MAX77620_CNFGGLBL1_LBRSTEN (1 << 0) + +/* CNFG BBC registers */ +#define MAX77620_CNFGBBC_ENABLE (1 << 0) +#define MAX77620_CNFGBBC_CURRENT_MASK 0x06 +#define MAX77620_CNFGBBC_CURRENT_SHIFT 1 +#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18 +#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3 +#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5) +#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0 +#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6 + +#define MAX77620_FPS_COUNT 3 + +/* Interrupts */ +enum { + MAX77620_IRQ_TOP_GLBL, /* Low-Battery */ + MAX77620_IRQ_TOP_SD, /* SD power fail */ + MAX77620_IRQ_TOP_LDO, /* LDO power fail */ + MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */ + MAX77620_IRQ_TOP_RTC, /* RTC */ + MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */ + MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */ + MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */ + MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */ + MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */ +}; + +/* GPIOs */ +enum { + MAX77620_GPIO0, + MAX77620_GPIO1, + MAX77620_GPIO2, + MAX77620_GPIO3, + MAX77620_GPIO4, + MAX77620_GPIO5, + MAX77620_GPIO6, + MAX77620_GPIO7, + MAX77620_GPIO_NR, +}; + +/* FPS Source */ +enum max77620_fps_src { + MAX77620_FPS_SRC_0, + MAX77620_FPS_SRC_1, + MAX77620_FPS_SRC_2, + MAX77620_FPS_SRC_NONE, + MAX77620_FPS_SRC_DEF, +}; + +enum max77620_chip_id { + MAX77620, + MAX20024, +}; + +#endif /* _MFD_MAX77620_H_ */ diff --git a/fusee/fusee-secondary/src/max7762x.c b/fusee/fusee-secondary/src/max7762x.c new file mode 100644 index 000000000..419a13bce --- /dev/null +++ b/fusee/fusee-secondary/src/max7762x.c @@ -0,0 +1,161 @@ +#include + +#include "max7762x.h" +#include "max77620.h" +#include "i2c.h" +#include "timers.h" + +#define REGULATOR_SD 0 +#define REGULATOR_LDO 1 + +typedef struct _max77620_regulator_t +{ + uint8_t type; + const char *name; + uint8_t reg_sd; + uint32_t mv_step; + uint32_t mv_min; + uint32_t mv_default; + uint32_t mv_max; + uint8_t volt_addr; + uint8_t cfg_addr; + uint8_t volt_mask; + uint8_t enable_mask; + uint8_t enable_shift; + uint8_t status_mask; + + uint8_t fps_addr; + uint8_t fps_src; + uint8_t pd_period; + uint8_t pu_period; +} max77620_regulator_t; + +static const max77620_regulator_t _pmic_regulators[] = { + { REGULATOR_SD, "sd0", 0x16, 12500, 600000, 625000, 1400000, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, 0x3F, 0x30, 4, 0x80, 0x4F, 1, 7, 1 }, + { REGULATOR_SD, "sd1", 0x17, 12500, 600000, 1125000, 1125000, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, 0x3F, 0x30, 4, 0x40, 0x50, 0, 1, 5 }, + { REGULATOR_SD, "sd2", 0x18, 12500, 600000, 1325000, 1350000, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, 0xFF, 0x30, 4, 0x20, 0x51, 1, 5, 2 }, + { REGULATOR_SD, "sd3", 0x19, 12500, 600000, 1800000, 1800000, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, 0xFF, 0x30, 4, 0x10, 0x52, 0, 3, 3 }, + { REGULATOR_LDO, "ldo0", 0x00, 25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, 0x3F, 0xC0, 6, 0x00, 0x46, 3, 7, 0 }, + { REGULATOR_LDO, "ldo1", 0x00, 25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, 0x3F, 0xC0, 6, 0x00, 0x47, 3, 7, 0 }, + { REGULATOR_LDO, "ldo2", 0x00, 50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, 0x3F, 0xC0, 6, 0x00, 0x48, 3, 7, 0 }, + { REGULATOR_LDO, "ldo3", 0x00, 50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, 0x3F, 0xC0, 6, 0x00, 0x49, 3, 7, 0 }, + { REGULATOR_LDO, "ldo4", 0x00, 12500, 800000, 850000, 850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4A, 0, 7, 1 }, + { REGULATOR_LDO, "ldo5", 0x00, 50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4B, 3, 7, 0 }, + { REGULATOR_LDO, "ldo6", 0x00, 50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4C, 3, 7, 0 }, + { REGULATOR_LDO, "ldo7", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4D, 1, 4, 3 }, + { REGULATOR_LDO, "ldo8", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4E, 3, 7, 0 } +}; + +int max77620_regulator_get_status(uint32_t id) +{ + if (id > REGULATOR_MAX) + return 0; + + const max77620_regulator_t *reg = &_pmic_regulators[id]; + uint8_t val = 0; + + if (reg->type == REGULATOR_SD) { + if (i2c_query(4, 0x3C, MAX77620_REG_STATSD, &val, 1)) + return (val & reg->status_mask) ? 0 : 1; + } + + if (i2c_query(4, 0x3C, reg->cfg_addr, &val, 1)) + return (val & 8) ? 0 : 1; + + return 0; +} + +int max77620_regulator_config_fps(uint32_t id) +{ + if (id > REGULATOR_MAX) + return 0; + + const max77620_regulator_t *reg = &_pmic_regulators[id]; + uint8_t val = ((reg->fps_src << 6) | (reg->pu_period << 3) | (reg->pd_period)); + + if (i2c_send(4, 0x3C, reg->fps_addr, &val, 1)) { + return 1; + } + + return 0; +} + +int max77620_regulator_set_voltage(uint32_t id, uint32_t mv) +{ + if (id > REGULATOR_MAX) + return 0; + + const max77620_regulator_t *reg = &_pmic_regulators[id]; + + if ((mv < reg->mv_default) || (mv > reg->mv_max)) + return 0; + + uint32_t mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step; + uint8_t val = 0; + + if (i2c_query(4, 0x3C, reg->volt_addr, &val, 1)) + { + val = ((val & ~reg->volt_mask) | (mult & reg->volt_mask)); + + if (i2c_send(4, 0x3C, reg->volt_addr, &val, 1)) + { + udelay(1000); + return 1; + } + } + + return 0; +} + +int max77620_regulator_enable(uint32_t id, int enable) +{ + if (id > REGULATOR_MAX) + return 0; + + const max77620_regulator_t *reg = &_pmic_regulators[id]; + + uint32_t addr = (reg->type == REGULATOR_SD) ? reg->cfg_addr : reg->volt_addr; + uint8_t val = 0; + + if (i2c_query(4, 0x3C, addr, &val, 1)) + { + if (enable) + val = ((val & ~reg->enable_mask) | ((3 << reg->enable_shift) & reg->enable_mask)); + else + val &= ~reg->enable_mask; + + if (i2c_send(4, 0x3C, addr, &val, 1)) + { + udelay(1000); + return 1; + } + } + + return 0; +} + +void max77620_config_default() +{ + for (uint32_t i = 1; i <= REGULATOR_MAX; i++) + { + uint8_t val = 0; + if (i2c_query(4, 0x3C, MAX77620_REG_CID4, &val, 1)) + { + max77620_regulator_config_fps(i); + max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default); + + if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE) { + max77620_regulator_enable(i, 1); + } + } + } + + uint8_t val = 4; + i2c_send(4, 0x3C, MAX77620_REG_SD_CFG2, &val, 1); +} + +void max77620_low_battery_monitor_config() +{ + uint8_t val = (MAX77620_CNFGGLBL1_LBDAC_EN | MAX77620_CNFGGLBL1_LBHYST_N | MAX77620_CNFGGLBL1_LBDAC_N); + i2c_send(4, 0x3C, MAX77620_REG_CNFGGLBL1, &val, 1); +} diff --git a/fusee/fusee-secondary/src/hwinit/max7762x.h b/fusee/fusee-secondary/src/max7762x.h similarity index 62% rename from fusee/fusee-secondary/src/hwinit/max7762x.h rename to fusee/fusee-secondary/src/max7762x.h index 05434956e..c106a27d4 100644 --- a/fusee/fusee-secondary/src/hwinit/max7762x.h +++ b/fusee/fusee-secondary/src/max7762x.h @@ -1,34 +1,16 @@ -/* -* Copyright (c) 2018 naehrwert -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . -*/ - -#ifndef _MAX7762X_H_ -#define _MAX7762X_H_ - -#include "types.h" +#ifndef FUSEE_MAX7762X_H_ +#define FUSEE_MAX7762X_H_ /* * Switch Power domains (max77620): * Name | Usage | uV step | uV min | uV default | uV max | Init *-------+---------------+---------+--------+------------+---------+------------------ * sd0 | core | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1) -* sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1) +* sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1) * sd2 | ldo{0-1, 7-8} | 12500 | 600000 | 1325000 | 1350000 | 1.325V (pcv) * sd3 | 1.8V general | 12500 | 600000 | 1800000 | 1800000 | -* ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1) -* ldo1 | XUSB | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv) +* ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1) +* ldo1 | XUSB, PCIE | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv) * ldo2 | SDMMC1 | 50000 | 800000 | 1800000 | 3300000 | * ldo3 | | 50000 | 800000 | 3100000 | 3100000 | * ldo4 | RTC | 12500 | 800000 | 850000 | 850000 | @@ -59,10 +41,11 @@ #define REGULATOR_LDO8 12 #define REGULATOR_MAX 12 -int max77620_regulator_get_status(u32 id); -int max77620_regulator_config_fps(u32 id); -int max77620_regulator_set_voltage(u32 id, u32 mv); -int max77620_regulator_enable(u32 id, int enable); +int max77620_regulator_get_status(uint32_t id); +int max77620_regulator_config_fps(uint32_t id); +int max77620_regulator_set_voltage(uint32_t id, uint32_t mv); +int max77620_regulator_enable(uint32_t id, int enable); void max77620_config_default(); +void max77620_low_battery_monitor_config(); #endif diff --git a/fusee/fusee-secondary/src/mc.c b/fusee/fusee-secondary/src/mc.c new file mode 100644 index 000000000..a98b6fbf7 --- /dev/null +++ b/fusee/fusee-secondary/src/mc.c @@ -0,0 +1,146 @@ +#include "mc.h" +#include "car.h" +#include "timers.h" + +void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock) +{ + MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = bom; + MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = size1mb; + + if (lock) + MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = 1; +} + +void mc_config_carveout() +{ + *(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1; + MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0; + MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0; + MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0; + MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1; + + mc_config_tsec_carveout(0, 0, 1); + + MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0; + MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0; + MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0; + MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006; + + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM_HI) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0x3000000; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0x300; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F; +} + +void mc_config_carveout_finalize() +{ + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM_HI) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = 0x3000000; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = 0x300; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; + MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E; +} + +void mc_enable_ahb_redirect() +{ + volatile tegra_car_t *car = car_get_regs(); + car->lvl2_clk_gate_ovrd = ((car->lvl2_clk_gate_ovrd & 0xFFF7FFFF) | 0x80000); + + MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000; + MAKE_MC_REG(MC_IRAM_TOM) = 0x4003F000; +} + +void mc_disable_ahb_redirect() +{ + volatile tegra_car_t *car = car_get_regs(); + + MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000; + MAKE_MC_REG(MC_IRAM_TOM) = 0; + + car->lvl2_clk_gate_ovrd &= 0xFFF7FFFF; +} + +void mc_enable() +{ + volatile tegra_car_t *car = car_get_regs(); + + /* Set EMC clock source. */ + car->clk_source_emc = ((car->clk_source_emc & 0x1FFFFFFF) | 0x40000000); + + /* Enable MIPI CAL clock. */ + car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFDFFFFFF) | 0x2000000); + + /* Enable MC clock. */ + car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFFFFFFFE) | 1); + + /* Enable EMC DLL clock. */ + car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000); + + /* Clear EMC and MC reset. */ + car->rst_dev_h_set = 0x2000001; + udelay(5); + + mc_disable_ahb_redirect(); +} \ No newline at end of file diff --git a/fusee/fusee-secondary/src/hwinit/mc.h b/fusee/fusee-secondary/src/mc.h similarity index 98% rename from fusee/fusee-secondary/src/hwinit/mc.h rename to fusee/fusee-secondary/src/mc.h index 7eebdf4e0..e93bfc7bf 100644 --- a/fusee/fusee-secondary/src/hwinit/mc.h +++ b/fusee/fusee-secondary/src/mc.h @@ -1,18 +1,11 @@ -/* -* Copyright (c) 2014, NVIDIA Corporation. All rights reserved. -* -* This software is licensed under the terms of the GNU General Public -* License version 2, as published by the Free Software Foundation, and -* may be copied, distributed, and modified under those terms. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -*/ +#ifndef FUSEE_MC_H_ +#define FUSEE_MC_H_ -#ifndef _MC_H_ -#define _MC_ +#include +#include + +#define MC_BASE 0x70019000 +#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n) #define MC_INTSTATUS 0x0 #define MC_INTMASK 0x4 @@ -463,4 +456,11 @@ #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 #define MC_DA_CONFIG0 0x9dc -#endif +void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock); +void mc_config_carveout(); +void mc_config_carveout_finalize(); +void mc_enable_ahb_redirect(); +void mc_disable_ahb_redirect(); +void mc_enable(); + +#endif \ No newline at end of file diff --git a/fusee/fusee-secondary/src/nxboot.c b/fusee/fusee-secondary/src/nxboot.c index 70c1f90f3..9d30d1454 100644 --- a/fusee/fusee-secondary/src/nxboot.c +++ b/fusee/fusee-secondary/src/nxboot.c @@ -6,6 +6,13 @@ #include "utils.h" #include "fs_utils.h" #include "nxboot.h" +#include "nxfs.h" +#include "di.h" +#include "mc.h" +#include "se.h" +#include "cluster.h" +#include "flow.h" +#include "timers.h" #include "key_derivation.h" #include "package1.h" #include "package2.h" @@ -14,7 +21,6 @@ #include "exocfg.h" #include "display/video_fb.h" #include "lib/ini.h" -#include "hwinit/t210.h" #define u8 uint8_t #define u32 uint32_t @@ -22,8 +28,6 @@ #undef u8 #undef u32 -#include "hwinit/cluster.h" - static int exosphere_ini_handler(void *user, const char *section, const char *name, const char *value) { exosphere_config_t *exo_cfg = (exosphere_config_t *)user; if (strcmp(section, "exosphere") == 0) { @@ -58,6 +62,7 @@ static void nxboot_configure_exosphere(void) { /* This is the main function responsible for booting Horizon. */ static nx_keyblob_t __attribute__((aligned(16))) g_keyblobs[32]; void nxboot_main(void) { + volatile tegra_se_t *se = se_get_regs(); loader_ctx_t *loader_ctx = get_loader_ctx(); /* void *bootconfig; */ package2_header_t *package2; @@ -74,7 +79,6 @@ void nxboot_main(void) { FILE *boot0, *pk2file; void *exosphere_memaddr; - /* TODO: How should we deal with bootconfig? */ package2 = memalign(4096, PACKAGE2_SIZE_MAX); if (package2 == NULL) { fatal_error("nxboot: out of memory!\n"); @@ -185,10 +189,12 @@ void nxboot_main(void) { } printf("Rebuilding package2...\n"); + /* Patch package2, adding Thermosphère + custom KIPs. */ package2_rebuild_and_copy(package2, MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware); printf(u8"Reading Exosphère...\n"); + /* Copy Exosphère to a good location (or read it directly to it.) */ if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware <= EXOSPHERE_TARGET_FIRMWARE_400) { exosphere_memaddr = (void *)0x40020000; @@ -211,26 +217,7 @@ void nxboot_main(void) { } else { memcpy(exosphere_memaddr, exosphere_bin, exosphere_bin_size); } - - /* Boot up Exosphère. */ - MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE = 0; - if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { - MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_LOADED_PACKAGE2; - } else { - MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_LOADED_PACKAGE2_4X; - } - printf("Powering on the CCPLEX...\n"); - cluster_enable_cpu0((uint64_t)(uintptr_t)exosphere_memaddr, 1); - while (MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE == 0) { - /* Wait for Exosphere to wake up. */ - } - printf(u8"Exopshère is responding!\n"); - if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { - MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_FINISHED; - } else { - MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_FINISHED_4X; - } - + /* Clean up. */ free(package1loader); if (loader_ctx->tsecfw_path[0] != '\0') { @@ -240,12 +227,79 @@ void nxboot_main(void) { free(warmboot_fw); } free(package2); + + /* Unmount everything. */ + nxfs_unmount_all(); + + /* Clear used keyslots. */ + clear_aes_keyslot(KEYSLOT_SWITCH_PACKAGE2KEY); + clear_aes_keyslot(KEYSLOT_SWITCH_RNGKEY); + + /* Lock keyslots. */ + set_aes_keyslot_flags(KEYSLOT_SWITCH_MASTERKEY, 0xFF); + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { + set_aes_keyslot_flags(KEYSLOT_SWITCH_DEVICEKEY, 0xFF); + } else { + set_aes_keyslot_flags(KEYSLOT_SWITCH_4XOLDDEVICEKEY, 0xFF); + } + /* TODO: Handle bootconfig. */ + memset((void *)0x4003D000, 0, 0x3000); + + /* Finalize the GPU UCODE carveout. */ + mc_config_carveout_finalize(); + + /* Lock AES keyslots. */ + for (uint32_t i = 0; i < 16; i++) + set_aes_keyslot_flags(i, 0x15); + + /* Lock RSA keyslots. */ + for (uint32_t i = 0; i < 2; i++) + set_rsa_keyslot_flags(i, 1); + + /* Lock the Security Engine. */ + se->_0x4 = 0; + se->AES_KEY_READ_DISABLE_REG = 0; + se->RSA_KEY_READ_DISABLE_REG = 0; + se->_0x0 &= 0xFFFFFFFB; + + /* Boot up Exosphère. */ + MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE = 0; + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { + MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_LOADED_PACKAGE2; + } else { + MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_LOADED_PACKAGE2_4X; + } + + printf("Powering on the CCPLEX...\n"); + /* Display splash screen. */ display_splash_screen_bmp(loader_ctx->custom_splash_path); + + /* Turn off the backlight. */ + display_backlight(false); + + /* Terminate the display if necessary. */ + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) + display_end(); + + /* Boot CPU0. */ + cluster_boot_cpu0((uint64_t)(uintptr_t)exosphere_memaddr); + + /* Wait for Exosphère to wake up. */ + while (MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE == 0) { + udelay(1); + } + + /* Signal Exosphère. */ + if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { + MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_FINISHED; + } else { + MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_FINISHED_4X; + } - //Halt ourselves in waitevent state. + /* Halt ourselves in waitevent state. */ while (1) { - FLOW_CTLR(0x4) = 0x50000000; + FLOW_CTLR_HALT_COP_EVENTS_0 = 0x50000000; } } diff --git a/fusee/fusee-secondary/src/nxfs.c b/fusee/fusee-secondary/src/nxfs.c index 521117f3d..fcb05d0f9 100644 --- a/fusee/fusee-secondary/src/nxfs.c +++ b/fusee/fusee-secondary/src/nxfs.c @@ -4,9 +4,9 @@ #include #include #include "nxfs.h" +#include "mc.h" #include "gpt.h" #include "se.h" -#include "hwinit.h" #include "utils.h" #include "sdmmc/sdmmc.h" diff --git a/fusee/fusee-secondary/src/package2.c b/fusee/fusee-secondary/src/package2.c index b968818f2..8449b72ac 100644 --- a/fusee/fusee-secondary/src/package2.c +++ b/fusee/fusee-secondary/src/package2.c @@ -85,7 +85,6 @@ void package2_rebuild_and_copy(package2_header_t *package2, uint32_t target_firm free(rebuilt_package2); } - static void package2_crypt_ctr(unsigned int master_key_rev, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size) { /* Derive package2 key. */ const uint8_t __attribute__((aligned(16))) package2_key_source[0x10] = { @@ -262,9 +261,6 @@ static size_t package2_get_thermosphere(void **thermosphere) { return 0; } - - - static ini1_header_t *package2_rebuild_ini1(ini1_header_t *ini1, uint32_t target_firmware) { /* TODO: Do we want to support loading another INI from sd:/whatever/INI1.bin? */ ini1_header_t *inis_to_merge[STRATOSPHERE_INI1_MAX] = {0}; diff --git a/fusee/fusee-secondary/src/panic.c b/fusee/fusee-secondary/src/panic.c index b5c4591b6..ce0b54747 100644 --- a/fusee/fusee-secondary/src/panic.c +++ b/fusee/fusee-secondary/src/panic.c @@ -1,8 +1,8 @@ #include "panic.h" +#include "di.h" #include "pmc.h" #include "fuse.h" #include "utils.h" -#include "hwinit.h" static uint32_t g_panic_code = 0; diff --git a/fusee/fusee-secondary/src/pinmux.h b/fusee/fusee-secondary/src/pinmux.h index d7131d1d5..80fc3a37c 100644 --- a/fusee/fusee-secondary/src/pinmux.h +++ b/fusee/fusee-secondary/src/pinmux.h @@ -1,6 +1,9 @@ #ifndef FUSEE_PINMUX_H #define FUSEE_PINMUX_H +#define PINMUX_BASE 0x70003000 +#define MAKE_PINMUX_REG(n) MAKE_REG32(PINMUX_BASE + n) + #define PINMUX_TRISTATE (1 << 4) #define PINMUX_PARKED (1 << 5) #define PINMUX_INPUT (1 << 6) @@ -186,7 +189,7 @@ typedef struct { static inline volatile tegra_pinmux_t *pinmux_get_regs(void) { - return (volatile tegra_pinmux_t *)0x70003000; + return (volatile tegra_pinmux_t *)PINMUX_BASE; } #endif diff --git a/fusee/fusee-secondary/src/pmc.h b/fusee/fusee-secondary/src/pmc.h index 4c10d1a0e..0c851eb47 100644 --- a/fusee/fusee-secondary/src/pmc.h +++ b/fusee/fusee-secondary/src/pmc.h @@ -1,25 +1,49 @@ #ifndef FUSEE_PMC_H #define FUSEE_PMC_H -/* TODO: get rid of these defines; use the struct instead */ +#include + #define PMC_BASE 0x7000E400 +#define MAKE_PMC_REG(n) MAKE_REG32(PMC_BASE + n) #define PMC_CONTROL_SDMMC1 (1 << 12) #define PMC_CONTROL_SDMMC3 (1 << 13) #define PMC_CONTROL_SDMMC4 (1 << 14) -#define APBDEV_PMC_CONTROL MAKE_REG32(PMC_BASE + 0x00) -#define APBDEV_PMC_DPD_ENABLE_0 MAKE_REG32(PMC_BASE + 0x24) -#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_REG32(PMC_BASE + 0x30) -#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_REG32(PMC_BASE + 0x38) -#define APBDEV_PMC_SCRATCH0_0 MAKE_REG32(PMC_BASE + 0x50) -#define APBDEV_PMC_CRYPTO_OP_0 MAKE_REG32(PMC_BASE + 0xF4) -#define APBDEV_PM_0 MAKE_REG32(PMC_BASE + 0x14) -#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_REG32(PMC_BASE + 0x168) -#define APBDEV_PMC_RST_STATUS_0 MAKE_REG32(PMC_BASE + 0x1B4) -#define APBDEV_PMC_CNTRL2_0 MAKE_REG32(PMC_BASE + 0x440) -#define APBDEV_PMC_SCRATCH43_0 MAKE_REG32(PMC_BASE + 0x22C) -#define APBDEV_PMC_SCRATCH200_0 MAKE_REG32(PMC_BASE + 0x840) +#define APBDEV_PMC_CONTROL MAKE_PMC_REG(0x00) +#define APBDEV_PM_0 MAKE_PMC_REG(0x14) +#define APBDEV_PMC_DPD_ENABLE_0 MAKE_PMC_REG(0x24) +#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x30) +#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x38) +#define APBDEV_PMC_NO_IOPOWER_0 MAKE_PMC_REG(0x44) +#define APBDEV_PMC_SCRATCH0_0 MAKE_PMC_REG(0x50) +#define APBDEV_PMC_SCRATCH1_0 MAKE_PMC_REG(0x54) +#define APBDEV_PMC_SCRATCH20_0 MAKE_PMC_REG(0xA0) +#define APBDEV_PMC_PWR_DET_VAL_0 MAKE_PMC_REG(0xE4) +#define APBDEV_PMC_DDR_PWR_0 MAKE_PMC_REG(0xE8) +#define APBDEV_PMC_CRYPTO_OP_0 MAKE_PMC_REG(0xF4) +#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_PMC_REG(0x168) +#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4) +#define APBDEV_PMC_RST_STATUS_0 MAKE_PMC_REG(0x1B4) +#define APBDEV_PMC_IO_DPD_REQ_0 MAKE_PMC_REG(0x1B8) +#define APBDEV_PMC_IO_DPD2_REQ_0 MAKE_PMC_REG(0x1C0) +#define APBDEV_PMC_VDDP_SEL_0 MAKE_PMC_REG(0x1CC) +#define APBDEV_PMC_SCRATCH49_0 MAKE_PMC_REG(0x244) +#define APBDEV_PMC_TSC_MULT_0 MAKE_PMC_REG(0x2B4) +#define APBDEV_PMC_REG_SHORT_0 MAKE_PMC_REG(0x2CC) +#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8) +#define APBDEV_PMC_SECURE_SCRATCH21_0 MAKE_PMC_REG(0x334) +#define APBDEV_PMC_SECURE_SCRATCH32_0 MAKE_PMC_REG(0x360) +#define APBDEV_PMC_SECURE_SCRATCH49_0 MAKE_PMC_REG(0x3A4) +#define APBDEV_PMC_CNTRL2_0 MAKE_PMC_REG(0x440) +#define APBDEV_PMC_IO_DPD4_REQ_0 MAKE_PMC_REG(0x464) +#define APBDEV_PMC_UTMIP_PAD_CFG1_0 MAKE_PMC_REG(0x4C4) +#define APBDEV_PMC_UTMIP_PAD_CFG3_0 MAKE_PMC_REG(0x4CC) +#define APBDEV_PMC_DDR_CNTRL_0 MAKE_PMC_REG(0x4E4) +#define APBDEV_PMC_SCRATCH43_0 MAKE_PMC_REG(0x22C) +#define APBDEV_PMC_SCRATCH188_0 MAKE_PMC_REG(0x810) +#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818) +#define APBDEV_PMC_SCRATCH200_0 MAKE_PMC_REG(0x840) typedef struct { uint32_t cntrl; @@ -42,7 +66,6 @@ typedef struct { uint32_t no_iopower; uint32_t pwr_det; uint32_t pwr_det_latch; - uint32_t scratch0; uint32_t scratch1; uint32_t scratch2; @@ -67,14 +90,12 @@ typedef struct { uint32_t scratch21; uint32_t scratch22; uint32_t scratch23; - uint32_t secure_scratch0; uint32_t secure_scratch1; uint32_t secure_scratch2; uint32_t secure_scratch3; uint32_t secure_scratch4; uint32_t secure_scratch5; - uint32_t cpupwrgood_timer; uint32_t cpupwroff_timer; uint32_t pg_mask; @@ -88,7 +109,6 @@ typedef struct { uint32_t usb_ao; uint32_t crypto_op; uint32_t pllp_wb0_override; - uint32_t scratch24; uint32_t scratch25; uint32_t scratch26; @@ -108,7 +128,6 @@ typedef struct { uint32_t scratch40; uint32_t scratch41; uint32_t scratch42; - uint32_t bo_mirror0; uint32_t bo_mirror1; uint32_t bo_mirror2; @@ -143,10 +162,9 @@ typedef struct { uint32_t io_dpd2_stat; uint32_t sel_dpd_tim; uint32_t vddp_sel; - uint32_t ddr_cfg; uint32_t e_no_vttgen; - uint32_t reserved0; + uint32_t _reserved0; uint32_t pllm_wb0_ovrride_frq; uint32_t test_pwrgate; uint32_t pwrgate_timer_mult; @@ -156,8 +174,12 @@ typedef struct { uint32_t utmip_pad_cfg; uint32_t utmip_term_pad_cfg; uint32_t utmip_uhsic_sleep_cfg; - - uint32_t todo_0[9]; + uint32_t utmip_uhsic_sleepwalk_cfg; + uint32_t utmip_sleepwalk_p[3]; + uint32_t uhsic_sleepwalk_p0; + uint32_t utmip_uhsic_status; + uint32_t utmip_uhsic_fake; + uint32_t bo_mirror3[2]; uint32_t secure_scratch6; uint32_t secure_scratch7; uint32_t scratch43; @@ -176,7 +198,22 @@ typedef struct { uint32_t scratch0_eco; uint32_t por_dpd_ctrl; uint32_t scratch2_eco; - uint32_t todo_1[17]; + uint32_t utmip_uhsic_line_wakeup; + uint32_t utmip_bias_master_cntrl; + uint32_t utmip_master_config; + uint32_t td_pwrgate_inter_part_timer; + uint32_t utmip_uhsic2_triggers; + uint32_t utmip_uhsic2_saved_state; + uint32_t utmip_uhsic2_sleep_cfg; + uint32_t utmip_uhsic2_sleepwalk_cfg; + uint32_t uhsic2_sleepwalk_p1; + uint32_t utmip_uhsic2_status; + uint32_t utmip_uhsic2_fake; + uint32_t utmip_uhsic2_line_wakeup; + uint32_t utmip_master2_config; + uint32_t utmip_uhsic_rpd_cfg; + uint32_t pg_mask_ce0; + uint32_t pg_mask3[2]; uint32_t pllm_wb0_override2; uint32_t tsc_mult; uint32_t cpu_vsense_override; @@ -184,7 +221,9 @@ typedef struct { uint32_t sticky_bits; uint32_t sec_disable2; uint32_t weak_bias; - uint32_t todo_3[13]; + uint32_t reg_short; + uint32_t pg_mask_andor; + uint32_t _reserved1[11]; uint32_t secure_scratch8; uint32_t secure_scratch9; uint32_t secure_scratch10; @@ -213,15 +252,64 @@ typedef struct { uint32_t secure_scratch33; uint32_t secure_scratch34; uint32_t secure_scratch35; - - uint32_t reserved1[52]; + uint32_t secure_scratch36; + uint32_t secure_scratch37; + uint32_t secure_scratch38; + uint32_t secure_scratch39; + uint32_t secure_scratch40; + uint32_t secure_scratch41; + uint32_t secure_scratch42; + uint32_t secure_scratch43; + uint32_t secure_scratch44; + uint32_t secure_scratch45; + uint32_t secure_scratch46; + uint32_t secure_scratch47; + uint32_t secure_scratch48; + uint32_t secure_scratch49; + uint32_t secure_scratch50; + uint32_t secure_scratch51; + uint32_t secure_scratch52; + uint32_t secure_scratch53; + uint32_t secure_scratch54; + uint32_t secure_scratch55; + uint32_t secure_scratch56; + uint32_t secure_scratch57; + uint32_t secure_scratch58; + uint32_t secure_scratch59; + uint32_t secure_scratch60; + uint32_t secure_scratch61; + uint32_t secure_scratch62; + uint32_t secure_scratch63; + uint32_t secure_scratch64; + uint32_t secure_scratch65; + uint32_t secure_scratch66; + uint32_t secure_scratch67; + uint32_t secure_scratch68; + uint32_t secure_scratch69; + uint32_t secure_scratch70; + uint32_t secure_scratch71; + uint32_t secure_scratch72; + uint32_t secure_scratch73; + uint32_t secure_scratch74; + uint32_t secure_scratch75; + uint32_t secure_scratch76; + uint32_t secure_scratch77; + uint32_t secure_scratch78; + uint32_t secure_scratch79; + uint32_t _reserved2[8]; uint32_t cntrl2; - uint32_t reserved2[6]; + uint32_t _reserved3[2]; + uint32_t event_counter; + uint32_t fuse_control; + uint32_t scratch1_eco; + uint32_t _reserved4; uint32_t io_dpd3_req; - uint32_t io_dpd3_stat; - uint32_t strap_opt_a; - uint32_t reserved3[102]; - + uint32_t io_dpd3_status; + uint32_t io_dpd4_req; + uint32_t io_dpd4_status; + uint32_t _reserved5[30]; + uint32_t ddr_cntrl; + uint32_t _reserved6[70]; uint32_t scratch56; uint32_t scratch57; uint32_t scratch58; @@ -286,12 +374,232 @@ typedef struct { uint32_t scratch117; uint32_t scratch118; uint32_t scratch119; - uint32_t scratch1_eco; + uint32_t scratch120; + uint32_t scratch121; + uint32_t scratch122; + uint32_t scratch123; + uint32_t scratch124; + uint32_t scratch125; + uint32_t scratch126; + uint32_t scratch127; + uint32_t scratch128; + uint32_t scratch129; + uint32_t scratch130; + uint32_t scratch131; + uint32_t scratch132; + uint32_t scratch133; + uint32_t scratch134; + uint32_t scratch135; + uint32_t scratch136; + uint32_t scratch137; + uint32_t scratch138; + uint32_t scratch139; + uint32_t scratch140; + uint32_t scratch141; + uint32_t scratch142; + uint32_t scratch143; + uint32_t scratch144; + uint32_t scratch145; + uint32_t scratch146; + uint32_t scratch147; + uint32_t scratch148; + uint32_t scratch149; + uint32_t scratch150; + uint32_t scratch151; + uint32_t scratch152; + uint32_t scratch153; + uint32_t scratch154; + uint32_t scratch155; + uint32_t scratch156; + uint32_t scratch157; + uint32_t scratch158; + uint32_t scratch159; + uint32_t scratch160; + uint32_t scratch161; + uint32_t scratch162; + uint32_t scratch163; + uint32_t scratch164; + uint32_t scratch165; + uint32_t scratch166; + uint32_t scratch167; + uint32_t scratch168; + uint32_t scratch169; + uint32_t scratch170; + uint32_t scratch171; + uint32_t scratch172; + uint32_t scratch173; + uint32_t scratch174; + uint32_t scratch175; + uint32_t scratch176; + uint32_t scratch177; + uint32_t scratch178; + uint32_t scratch179; + uint32_t scratch180; + uint32_t scratch181; + uint32_t scratch182; + uint32_t scratch183; + uint32_t scratch184; + uint32_t scratch185; + uint32_t scratch186; + uint32_t scratch187; + uint32_t scratch188; + uint32_t scratch189; + uint32_t scratch190; + uint32_t scratch191; + uint32_t scratch192; + uint32_t scratch193; + uint32_t scratch194; + uint32_t scratch195; + uint32_t scratch196; + uint32_t scratch197; + uint32_t scratch198; + uint32_t scratch199; + uint32_t scratch200; + uint32_t scratch201; + uint32_t scratch202; + uint32_t scratch203; + uint32_t scratch204; + uint32_t scratch205; + uint32_t scratch206; + uint32_t scratch207; + uint32_t scratch208; + uint32_t scratch209; + uint32_t scratch210; + uint32_t scratch211; + uint32_t scratch212; + uint32_t scratch213; + uint32_t scratch214; + uint32_t scratch215; + uint32_t scratch216; + uint32_t scratch217; + uint32_t scratch218; + uint32_t scratch219; + uint32_t scratch220; + uint32_t scratch221; + uint32_t scratch222; + uint32_t scratch223; + uint32_t scratch224; + uint32_t scratch225; + uint32_t scratch226; + uint32_t scratch227; + uint32_t scratch228; + uint32_t scratch229; + uint32_t scratch230; + uint32_t scratch231; + uint32_t scratch232; + uint32_t scratch233; + uint32_t scratch234; + uint32_t scratch235; + uint32_t scratch236; + uint32_t scratch237; + uint32_t scratch238; + uint32_t scratch239; + uint32_t scratch240; + uint32_t scratch241; + uint32_t scratch242; + uint32_t scratch243; + uint32_t scratch244; + uint32_t scratch245; + uint32_t scratch246; + uint32_t scratch247; + uint32_t scratch248; + uint32_t scratch249; + uint32_t scratch250; + uint32_t scratch251; + uint32_t scratch252; + uint32_t scratch253; + uint32_t scratch254; + uint32_t scratch255; + uint32_t scratch256; + uint32_t scratch257; + uint32_t scratch258; + uint32_t scratch259; + uint32_t scratch260; + uint32_t scratch261; + uint32_t scratch262; + uint32_t scratch263; + uint32_t scratch264; + uint32_t scratch265; + uint32_t scratch266; + uint32_t scratch267; + uint32_t scratch268; + uint32_t scratch269; + uint32_t scratch270; + uint32_t scratch271; + uint32_t scratch272; + uint32_t scratch273; + uint32_t scratch274; + uint32_t scratch275; + uint32_t scratch276; + uint32_t scratch277; + uint32_t scratch278; + uint32_t scratch279; + uint32_t scratch280; + uint32_t scratch281; + uint32_t scratch282; + uint32_t scratch283; + uint32_t scratch284; + uint32_t scratch285; + uint32_t scratch286; + uint32_t scratch287; + uint32_t scratch288; + uint32_t scratch289; + uint32_t scratch290; + uint32_t scratch291; + uint32_t scratch292; + uint32_t scratch293; + uint32_t scratch294; + uint32_t scratch295; + uint32_t scratch296; + uint32_t scratch297; + uint32_t scratch298; + uint32_t scratch299; + uint32_t _reserved7[50]; + uint32_t secure_scratch80; + uint32_t secure_scratch81; + uint32_t secure_scratch82; + uint32_t secure_scratch83; + uint32_t secure_scratch84; + uint32_t secure_scratch85; + uint32_t secure_scratch86; + uint32_t secure_scratch87; + uint32_t secure_scratch88; + uint32_t secure_scratch89; + uint32_t secure_scratch90; + uint32_t secure_scratch91; + uint32_t secure_scratch92; + uint32_t secure_scratch93; + uint32_t secure_scratch94; + uint32_t secure_scratch95; + uint32_t secure_scratch96; + uint32_t secure_scratch97; + uint32_t secure_scratch98; + uint32_t secure_scratch99; + uint32_t secure_scratch100; + uint32_t secure_scratch101; + uint32_t secure_scratch102; + uint32_t secure_scratch103; + uint32_t secure_scratch104; + uint32_t secure_scratch105; + uint32_t secure_scratch106; + uint32_t secure_scratch107; + uint32_t secure_scratch108; + uint32_t secure_scratch109; + uint32_t secure_scratch110; + uint32_t secure_scratch111; + uint32_t secure_scratch112; + uint32_t secure_scratch113; + uint32_t secure_scratch114; + uint32_t secure_scratch115; + uint32_t secure_scratch116; + uint32_t secure_scratch117; + uint32_t secure_scratch118; + uint32_t secure_scratch119; } tegra_pmc_t; static inline volatile tegra_pmc_t *pmc_get_regs(void) { - return (volatile tegra_pmc_t *)0x7000E400; + return (volatile tegra_pmc_t *)PMC_BASE; } #endif diff --git a/fusee/fusee-secondary/src/sdmmc/sdmmc_core.c b/fusee/fusee-secondary/src/sdmmc/sdmmc_core.c index 85cab87ba..c30a1f837 100644 --- a/fusee/fusee-secondary/src/sdmmc/sdmmc_core.c +++ b/fusee/fusee-secondary/src/sdmmc/sdmmc_core.c @@ -11,8 +11,8 @@ #include "../apb_misc.h" #include "../gpio.h" #include "../pmc.h" +#include "../max7762x.h" #include "../lib/driver_utils.h" -#include "../hwinit/max7762x.h" static SdmmcLogLevel g_sdmmc_log_level = SDMMC_LOG_NONE; @@ -399,16 +399,16 @@ static int sdmmc_clk_set_source(SdmmcControllerNum controller, uint32_t clk_freq switch (controller) { case SDMMC_1: - car->clk_src[CLK_SOURCE_SDMMC1] = (CLK_SOURCE_FIRST | car_div); + car->clk_source_sdmmc1 = (CLK_SOURCE_FIRST | car_div); break; case SDMMC_2: - car->clk_src[CLK_SOURCE_SDMMC2] = (CLK_SOURCE_FIRST | car_div); + car->clk_source_sdmmc2 = (CLK_SOURCE_FIRST | car_div); break; case SDMMC_3: - car->clk_src[CLK_SOURCE_SDMMC3] = (CLK_SOURCE_FIRST | car_div); + car->clk_source_sdmmc3 = (CLK_SOURCE_FIRST | car_div); break; case SDMMC_4: - car->clk_src[CLK_SOURCE_SDMMC4] = (CLK_SOURCE_FIRST | car_div); + car->clk_source_sdmmc4 = (CLK_SOURCE_FIRST | car_div); break; } diff --git a/fusee/fusee-secondary/src/se.c b/fusee/fusee-secondary/src/se.c index 18e16bd99..af86980b3 100644 --- a/fusee/fusee-secondary/src/se.c +++ b/fusee/fusee-secondary/src/se.c @@ -1,7 +1,6 @@ #include #include "utils.h" -/*#include "interrupt.h"*/ #include "se.h" void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size); @@ -24,42 +23,49 @@ void NOINLINE ll_init(volatile se_ll_t *ll, void *buffer, size_t size) { } void se_check_error_status_reg(void) { - if (SECURITY_ENGINE->ERR_STATUS_REG) { + volatile tegra_se_t *se = se_get_regs(); + if (se->ERR_STATUS_REG) { generic_panic(); } } void se_check_for_error(void) { - if (SECURITY_ENGINE->INT_STATUS_REG & 0x10000 || SECURITY_ENGINE->FLAGS_REG & 3 || SECURITY_ENGINE->ERR_STATUS_REG) { + volatile tegra_se_t *se = se_get_regs(); + if (se->INT_STATUS_REG & 0x10000 || se->FLAGS_REG & 3 || se->ERR_STATUS_REG) { generic_panic(); } } void se_verify_flags_cleared(void) { - if (SECURITY_ENGINE->FLAGS_REG & 3) { + volatile tegra_se_t *se = se_get_regs(); + if (se->FLAGS_REG & 3) { generic_panic(); } } /* Set the flags for an AES keyslot. */ void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } /* Misc flags. */ if (flags & ~0x80) { - SECURITY_ENGINE->AES_KEYSLOT_FLAGS[keyslot] = ~flags; + se->AES_KEYSLOT_FLAGS[keyslot] = ~flags; } /* Disable keyslot reads. */ if (flags & 0x80) { - SECURITY_ENGINE->AES_KEY_READ_DISABLE_REG &= ~(1 << keyslot); + se->AES_KEY_READ_DISABLE_REG &= ~(1 << keyslot); } } /* Set the flags for an RSA keyslot. */ void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_RSA_MAX) { generic_panic(); } @@ -67,28 +73,32 @@ void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags) { /* Misc flags. */ if (flags & ~0x80) { /* TODO: Why are flags assigned this way? */ - SECURITY_ENGINE->RSA_KEYSLOT_FLAGS[keyslot] = (((flags >> 4) & 4) | (flags & 3)) ^ 7; + se->RSA_KEYSLOT_FLAGS[keyslot] = (((flags >> 4) & 4) | (flags & 3)) ^ 7; } /* Disable keyslot reads. */ if (flags & 0x80) { - SECURITY_ENGINE->RSA_KEY_READ_DISABLE_REG &= ~(1 << keyslot); + se->RSA_KEY_READ_DISABLE_REG &= ~(1 << keyslot); } } void clear_aes_keyslot(unsigned int keyslot) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } /* Zero out the whole keyslot and IV. */ for (unsigned int i = 0; i < 0x10; i++) { - SECURITY_ENGINE->AES_KEYTABLE_ADDR = (keyslot << 4) | i; - SECURITY_ENGINE->AES_KEYTABLE_DATA = 0; + se->AES_KEYTABLE_ADDR = (keyslot << 4) | i; + se->AES_KEYTABLE_DATA = 0; } } void clear_rsa_keyslot(unsigned int keyslot) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_RSA_MAX) { generic_panic(); } @@ -96,40 +106,44 @@ void clear_rsa_keyslot(unsigned int keyslot) { /* Zero out the whole keyslot. */ for (unsigned int i = 0; i < 0x40; i++) { /* Select Keyslot Modulus[i] */ - SECURITY_ENGINE->RSA_KEYTABLE_ADDR = (keyslot << 7) | i | 0x40; - SECURITY_ENGINE->RSA_KEYTABLE_DATA = 0; + se->RSA_KEYTABLE_ADDR = (keyslot << 7) | i | 0x40; + se->RSA_KEYTABLE_DATA = 0; } for (unsigned int i = 0; i < 0x40; i++) { /* Select Keyslot Expontent[i] */ - SECURITY_ENGINE->RSA_KEYTABLE_ADDR = (keyslot << 7) | i; - SECURITY_ENGINE->RSA_KEYTABLE_DATA = 0; + se->RSA_KEYTABLE_ADDR = (keyslot << 7) | i; + se->RSA_KEYTABLE_DATA = 0; } } void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || key_size > KEYSIZE_AES_MAX) { generic_panic(); } for (size_t i = 0; i < (key_size >> 2); i++) { - SECURITY_ENGINE->AES_KEYTABLE_ADDR = (keyslot << 4) | i; - SECURITY_ENGINE->AES_KEYTABLE_DATA = read32le(key, 4 * i); + se->AES_KEYTABLE_ADDR = (keyslot << 4) | i; + se->AES_KEYTABLE_DATA = read32le(key, 4 * i); } } void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_RSA_MAX || modulus_size > KEYSIZE_RSA_MAX || exp_size > KEYSIZE_RSA_MAX) { generic_panic(); } for (size_t i = 0; i < (modulus_size >> 2); i++) { - SECURITY_ENGINE->RSA_KEYTABLE_ADDR = (keyslot << 7) | 0x40 | i; - SECURITY_ENGINE->RSA_KEYTABLE_DATA = read32be(modulus, (4 * (modulus_size >> 2)) - (4 * i) - 4); + se->RSA_KEYTABLE_ADDR = (keyslot << 7) | 0x40 | i; + se->RSA_KEYTABLE_DATA = read32be(modulus, (4 * (modulus_size >> 2)) - (4 * i) - 4); } for (size_t i = 0; i < (exp_size >> 2); i++) { - SECURITY_ENGINE->RSA_KEYTABLE_ADDR = (keyslot << 7) | i; - SECURITY_ENGINE->RSA_KEYTABLE_DATA = read32be(exponent, (4 * (exp_size >> 2)) - (4 * i) - 4); + se->RSA_KEYTABLE_ADDR = (keyslot << 7) | i; + se->RSA_KEYTABLE_DATA = read32be(exponent, (4 * (exp_size >> 2)) - (4 * i) - 4); } g_se_modulus_sizes[keyslot] = modulus_size; @@ -137,47 +151,55 @@ void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_ } void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || iv_size > 0x10) { generic_panic(); } for (size_t i = 0; i < (iv_size >> 2); i++) { - SECURITY_ENGINE->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; - SECURITY_ENGINE->AES_KEYTABLE_DATA = read32le(iv, 4 * i); + se->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; + se->AES_KEYTABLE_DATA = read32le(iv, 4 * i); } } void clear_aes_keyslot_iv(unsigned int keyslot) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } for (size_t i = 0; i < (0x10 >> 2); i++) { - SECURITY_ENGINE->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; - SECURITY_ENGINE->AES_KEYTABLE_DATA = 0; + se->AES_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; + se->AES_KEYTABLE_DATA = 0; } } void set_se_ctr(const void *ctr) { + volatile tegra_se_t *se = se_get_regs(); for (unsigned int i = 0; i < 4; i++) { - SECURITY_ENGINE->CRYPTO_CTR_REG[i] = read32le(ctr, i * 4); + se->CRYPTO_CTR_REG[i] = read32le(ctr, i * 4); } } void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot_dst >= KEYSLOT_AES_MAX || keyslot_src >= KEYSLOT_AES_MAX || wrapped_key_size > KEYSIZE_AES_MAX) { generic_panic(); } - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_DEC | DST_KEYTAB); - SECURITY_ENGINE->CRYPTO_REG = keyslot_src << 24; - SECURITY_ENGINE->BLOCK_COUNT_REG = 0; - SECURITY_ENGINE->CRYPTO_KEYTABLE_DST_REG = keyslot_dst << 8; + se->CONFIG_REG = (ALG_AES_DEC | DST_KEYTAB); + se->CRYPTO_REG = keyslot_src << 24; + se->BLOCK_COUNT_REG = 0; + se->CRYPTO_KEYTABLE_DST_REG = keyslot_dst << 8; trigger_se_blocking_op(OP_START, NULL, 0, wrapped_key, wrapped_key_size); } void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { + volatile tegra_se_t *se = se_get_regs(); uint8_t ALIGN(16) stack_buf[KEYSIZE_RSA_MAX]; if (keyslot >= KEYSLOT_RSA_MAX || src_size > KEYSIZE_RSA_MAX || dst_size > KEYSIZE_RSA_MAX) { @@ -189,18 +211,19 @@ void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, co stack_buf[i] = *((uint8_t *)src + src_size - i - 1); } - SECURITY_ENGINE->CONFIG_REG = (ALG_RSA | DST_RSAREG); - SECURITY_ENGINE->RSA_CONFIG = keyslot << 24; - SECURITY_ENGINE->RSA_KEY_SIZE_REG = (g_se_modulus_sizes[keyslot] >> 6) - 1; - SECURITY_ENGINE->RSA_EXP_SIZE_REG = g_se_exp_sizes[keyslot] >> 2; - + se->CONFIG_REG = (ALG_RSA | DST_RSAREG); + se->RSA_CONFIG = keyslot << 24; + se->RSA_KEY_SIZE_REG = (g_se_modulus_sizes[keyslot] >> 6) - 1; + se->RSA_EXP_SIZE_REG = g_se_exp_sizes[keyslot] >> 2; trigger_se_blocking_op(OP_START, NULL, 0, stack_buf, src_size); se_get_exp_mod_output(dst, dst_size); } void se_get_exp_mod_output(void *buf, size_t size) { + volatile tegra_se_t *se = se_get_regs(); size_t num_dwords = (size >> 2); + if (num_dwords < 1) { return; } @@ -210,7 +233,7 @@ void se_get_exp_mod_output(void *buf, size_t size) { /* Copy endian swapped output. */ while (num_dwords) { - *p_out = read32be(SECURITY_ENGINE->RSA_OUTPUT, offset); + *p_out = read32be(se->RSA_OUTPUT, offset); offset += 4; p_out--; num_dwords--; @@ -271,6 +294,7 @@ bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const v } void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size) { + volatile tegra_se_t *se = se_get_regs(); se_ll_t in_ll; se_ll_t out_ll; @@ -278,21 +302,22 @@ void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const v ll_init(&out_ll, dst, dst_size); /* Set the LLs. */ - SECURITY_ENGINE->IN_LL_ADDR_REG = (uint32_t) get_physical_address(&in_ll); - SECURITY_ENGINE->OUT_LL_ADDR_REG = (uint32_t) get_physical_address(&out_ll); + se->IN_LL_ADDR_REG = (uint32_t) get_physical_address(&in_ll); + se->OUT_LL_ADDR_REG = (uint32_t) get_physical_address(&out_ll); /* Set registers for operation. */ - SECURITY_ENGINE->ERR_STATUS_REG = SECURITY_ENGINE->ERR_STATUS_REG; - SECURITY_ENGINE->INT_STATUS_REG = SECURITY_ENGINE->INT_STATUS_REG; - SECURITY_ENGINE->OPERATION_REG = op; + se->ERR_STATUS_REG = se->ERR_STATUS_REG; + se->INT_STATUS_REG = se->INT_STATUS_REG; + se->OPERATION_REG = op; - while (!(SECURITY_ENGINE->INT_STATUS_REG & 0x10)) { /* Wait a while */ } + while (!(se->INT_STATUS_REG & 0x10)) { /* Wait a while */ } se_check_for_error(); } /* Secure AES Functionality. */ void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, size_t src_size) { + volatile tegra_se_t *se = se_get_regs(); uint8_t block[0x10] = {0}; if (src_size > sizeof(block) || dst_size > sizeof(block)) { @@ -305,7 +330,7 @@ void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, } /* Trigger AES operation. */ - SECURITY_ENGINE->BLOCK_COUNT_REG = 0; + se->BLOCK_COUNT_REG = 0; trigger_se_blocking_op(OP_START, block, sizeof(block), block, sizeof(block)); /* Copy output data into dst. */ @@ -315,21 +340,23 @@ void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, } void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || ctr_size != 0x10) { generic_panic(); } unsigned int num_blocks = src_size >> 4; /* Unknown what this write does, but official code writes it for CTR mode. */ - SECURITY_ENGINE->_0x80C = 1; - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | 0x91E; + se->SPARE_0 = 1; + se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY); + se->CRYPTO_REG = (keyslot << 24) | 0x91E; set_se_ctr(ctr); /* Handle any aligned blocks. */ size_t aligned_size = (size_t)num_blocks << 4; if (aligned_size) { - SECURITY_ENGINE->BLOCK_COUNT_REG = num_blocks - 1; + se->BLOCK_COUNT_REG = num_blocks - 1; trigger_se_blocking_op(OP_START, dst, dst_size, src, aligned_size); } @@ -344,15 +371,16 @@ void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const vo } void se_aes_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, unsigned int config_high) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) { generic_panic(); } /* Set configuration high (256-bit vs 128-bit) based on parameter. */ - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (config_high << 16); - SECURITY_ENGINE->CRYPTO_REG = keyslot << 24 | 0x100; + se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (config_high << 16); + se->CRYPTO_REG = keyslot << 24 | 0x100; se_perform_aes_block_operation(dst, 0x10, src, 0x10); - } void se_aes_128_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { @@ -365,12 +393,14 @@ void se_aes_256_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_si void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) { generic_panic(); } - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = keyslot << 24; + se->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY); + se->CRYPTO_REG = keyslot << 24; se_perform_aes_block_operation(dst, 0x10, src, 0x10); } @@ -422,6 +452,8 @@ void aes_128_xts_nintendo_xor_with_tweak(unsigned int keyslot, size_t sector, ui } void aes_128_xts_nintendo_crypt_sector(unsigned int keyslot_1, unsigned int keyslot_2, size_t sector, bool encrypt, void *dst, const void *src, size_t size) { + volatile tegra_se_t *se = se_get_regs(); + if ((size & 0xF) || size == 0) { generic_panic(); } @@ -431,13 +463,13 @@ void aes_128_xts_nintendo_crypt_sector(unsigned int keyslot_1, unsigned int keys /* Encrypt/Decrypt. */ if (encrypt) { - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = keyslot_1 << 24 | 0x100; + se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY); + se->CRYPTO_REG = keyslot_1 << 24 | 0x100; } else { - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = keyslot_1 << 24; + se->CONFIG_REG = (ALG_AES_DEC | DST_MEMORY); + se->CRYPTO_REG = keyslot_1 << 24; } - SECURITY_ENGINE->BLOCK_COUNT_REG = (size >> 4) - 1; + se->BLOCK_COUNT_REG = (size >> 4) - 1; trigger_se_blocking_op(OP_START, dst, size, src, size); /* XOR. */ @@ -469,6 +501,8 @@ void se_aes_128_xts_nintendo_decrypt(unsigned int keyslot_1, unsigned int keyslo } void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size, unsigned int config_high) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } @@ -481,17 +515,17 @@ void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, con shift_left_xor_rb(derived_key); } - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_HASHREG) | (config_high << 16); - SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | (0x145); + se->CONFIG_REG = (ALG_AES_ENC | DST_HASHREG) | (config_high << 16); + se->CRYPTO_REG = (keyslot << 24) | (0x145); clear_aes_keyslot_iv(keyslot); unsigned int num_blocks = (data_size + 0xF) >> 4; /* Handle aligned blocks. */ if (num_blocks > 1) { - SECURITY_ENGINE->BLOCK_COUNT_REG = num_blocks - 2; + se->BLOCK_COUNT_REG = num_blocks - 2; trigger_se_blocking_op(OP_START, NULL, 0, data, data_size); - SECURITY_ENGINE->CRYPTO_REG |= 0x80; + se->CRYPTO_REG |= 0x80; } /* Create final block. */ @@ -508,12 +542,12 @@ void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, con } /* Perform last operation. */ - SECURITY_ENGINE->BLOCK_COUNT_REG = 0; + se->BLOCK_COUNT_REG = 0; trigger_se_blocking_op(OP_START, NULL, 0, last_block, sizeof(last_block)); /* Copy output CMAC. */ for (unsigned int i = 0; i < (cmac_size >> 2); i++) { - ((uint32_t *)cmac)[i] = read32le(SECURITY_ENGINE->HASH_RESULT_REG, i << 2); + ((uint32_t *)cmac)[i] = read32le(se->HASH_RESULT_REG, i << 2); } } @@ -525,42 +559,48 @@ void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, } void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX || src_size < 0x10) { generic_panic(); } - SECURITY_ENGINE->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (0x202 << 16); - SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | 0x144; + se->CONFIG_REG = (ALG_AES_ENC | DST_MEMORY) | (0x202 << 16); + se->CRYPTO_REG = (keyslot << 24) | 0x144; set_aes_keyslot_iv(keyslot, iv, 0x10); - SECURITY_ENGINE->BLOCK_COUNT_REG = (src_size >> 4) - 1; + se->BLOCK_COUNT_REG = (src_size >> 4) - 1; trigger_se_blocking_op(OP_START, dst, dst_size, src, src_size); } /* SHA256 Implementation. */ void se_calculate_sha256(void *dst, const void *src, size_t src_size) { + volatile tegra_se_t *se = se_get_regs(); + /* Setup config for SHA256, size = BITS(src_size) */ - SECURITY_ENGINE->CONFIG_REG = (ENCMODE_SHA256 | ALG_SHA | DST_HASHREG); - SECURITY_ENGINE->SHA_CONFIG_REG = 1; - SECURITY_ENGINE->SHA_MSG_LENGTH_REG = (uint32_t)(src_size << 3); - SECURITY_ENGINE->_0x208 = 0; - SECURITY_ENGINE->_0x20C = 0; - SECURITY_ENGINE->_0x210 = 0; - SECURITY_ENGINE->SHA_MSG_LEFT_REG = (uint32_t)(src_size << 3); - SECURITY_ENGINE->_0x218 = 0; - SECURITY_ENGINE->_0x21C = 0; - SECURITY_ENGINE->_0x220 = 0; + se->CONFIG_REG = (ENCMODE_SHA256 | ALG_SHA | DST_HASHREG); + se->SHA_CONFIG_REG = 1; + se->SHA_MSG_LENGTH_REG = (uint32_t)(src_size << 3); + se->_0x208 = 0; + se->_0x20C = 0; + se->_0x210 = 0; + se->SHA_MSG_LEFT_REG = (uint32_t)(src_size << 3); + se->_0x218 = 0; + se->_0x21C = 0; + se->_0x220 = 0; /* Trigger the operation. */ trigger_se_blocking_op(OP_START, NULL, 0, src, src_size); /* Copy output hash. */ for (unsigned int i = 0; i < (0x20 >> 2); i++) { - ((uint32_t *)dst)[i] = read32be(SECURITY_ENGINE->HASH_RESULT_REG, i << 2); + ((uint32_t *)dst)[i] = read32be(se->HASH_RESULT_REG, i << 2); } } /* RNG API */ void se_initialize_rng(unsigned int keyslot) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } @@ -569,32 +609,33 @@ void se_initialize_rng(unsigned int keyslot) { /* This will be discarded, when done. */ uint8_t ALIGN(16) output_buf[0x10]; - SECURITY_ENGINE->RNG_SRC_CONFIG_REG = 3; /* Entropy enable + Entropy lock enable */ - SECURITY_ENGINE->RNG_RESEED_INTERVAL_REG = 70001; - SECURITY_ENGINE->CONFIG_REG = (ALG_RNG | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | 0x108; - SECURITY_ENGINE->RNG_CONFIG_REG = 5; - SECURITY_ENGINE->BLOCK_COUNT_REG = 0; + se->RNG_SRC_CONFIG_REG = 3; /* Entropy enable + Entropy lock enable */ + se->RNG_RESEED_INTERVAL_REG = 70001; + se->CONFIG_REG = (ALG_RNG | DST_MEMORY); + se->CRYPTO_REG = (keyslot << 24) | 0x108; + se->RNG_CONFIG_REG = 5; + se->BLOCK_COUNT_REG = 0; trigger_se_blocking_op(OP_START, output_buf, 0x10, NULL, 0); } void se_generate_random(unsigned int keyslot, void *dst, size_t size) { + volatile tegra_se_t *se = se_get_regs(); + if (keyslot >= KEYSLOT_AES_MAX) { generic_panic(); } uint32_t num_blocks = size >> 4; size_t aligned_size = num_blocks << 4; - SECURITY_ENGINE->CONFIG_REG = (ALG_RNG | DST_MEMORY); - SECURITY_ENGINE->CRYPTO_REG = (keyslot << 24) | 0x108; - SECURITY_ENGINE->RNG_CONFIG_REG = 4; + se->CONFIG_REG = (ALG_RNG | DST_MEMORY); + se->CRYPTO_REG = (keyslot << 24) | 0x108; + se->RNG_CONFIG_REG = 4; if (num_blocks >= 1) { - SECURITY_ENGINE->BLOCK_COUNT_REG = num_blocks - 1; + se->BLOCK_COUNT_REG = num_blocks - 1; trigger_se_blocking_op(OP_START, dst, aligned_size, NULL, 0); } if (size > aligned_size) { se_perform_aes_block_operation(dst + aligned_size, size - aligned_size, NULL, 0); } - } diff --git a/fusee/fusee-secondary/src/se.h b/fusee/fusee-secondary/src/se.h index a1ef7fa84..311567261 100644 --- a/fusee/fusee-secondary/src/se.h +++ b/fusee/fusee-secondary/src/se.h @@ -1,7 +1,8 @@ #ifndef FUSEE_SE_H #define FUSEE_SE_H -#include +#define SE_BASE 0x70012000 +#define MAKE_SE_REG(n) MAKE_REG32(SE_BASE + n) #define KEYSLOT_SWITCH_LP0TZRAMKEY 0x2 #define KEYSLOT_SWITCH_SRKGENKEY 0x8 @@ -98,10 +99,10 @@ typedef struct security_engine { uint32_t _0x21C; uint32_t _0x220; uint32_t _0x224; - uint8_t _0x228[0x5C]; + uint8_t _0x228[0x58]; uint32_t AES_KEY_READ_DISABLE_REG; uint32_t AES_KEYSLOT_FLAGS[0x10]; - uint8_t _0x2C8[0x38]; + uint8_t _0x2C4[0x3C]; uint32_t _0x300; uint32_t CRYPTO_REG; uint32_t CRYPTO_CTR_REG[4]; @@ -131,15 +132,13 @@ typedef struct security_engine { uint32_t FLAGS_REG; uint32_t ERR_STATUS_REG; uint32_t _0x808; - uint32_t _0x80C; + uint32_t SPARE_0; uint32_t _0x810; uint32_t _0x814; uint32_t _0x818; uint32_t _0x81C; uint8_t _0x820[0x17E0]; -} security_engine_t; - -static_assert(sizeof(security_engine_t) == 0x2000, "Mis-defined Security Engine Registers!"); +} tegra_se_t; typedef struct { uint32_t address; @@ -151,15 +150,10 @@ typedef struct { se_addr_info_t addr_info; /* This should really be an array...but for our use case it works. */ } se_ll_t; - -/* WIP, API subject to change. */ - -static inline volatile security_engine_t *get_security_engine(void) { - return (volatile security_engine_t *)0x70012000; +static inline volatile tegra_se_t *se_get_regs(void) { + return (volatile tegra_se_t *)SE_BASE; } -#define SECURITY_ENGINE (get_security_engine()) - /* This function MUST be registered to fire on the appropriate interrupt. */ void se_check_error_status_reg(void); diff --git a/fusee/fusee-secondary/src/stratosphere.c b/fusee/fusee-secondary/src/stratosphere.c index e849c88bc..a0d1b5db0 100644 --- a/fusee/fusee-secondary/src/stratosphere.c +++ b/fusee/fusee-secondary/src/stratosphere.c @@ -27,7 +27,7 @@ extern const uint32_t loader_kip_size, pm_kip_size, sm_kip_size; /* GCC doesn't consider the size as const... we have to write it ourselves. */ ini1_header_t *stratosphere_get_ini1(uint32_t target_firmware) { - const uint8_t *boot_kip = NULL; + /* const uint8_t *boot_kip = NULL; */ uint32_t boot_kip_size = 0; uint8_t *data; @@ -36,10 +36,10 @@ ini1_header_t *stratosphere_get_ini1(uint32_t target_firmware) { } if (target_firmware <= EXOSPHERE_TARGET_FIRMWARE_100) { - boot_kip = boot_100_kip; + /* boot_kip = boot_100_kip; */ boot_kip_size = boot_100_kip_size; } else { - boot_kip = boot_200_kip; + /* boot_kip = boot_200_kip; */ boot_kip_size = boot_200_kip_size; } @@ -52,7 +52,7 @@ ini1_header_t *stratosphere_get_ini1(uint32_t target_firmware) { g_stratosphere_ini1->magic = MAGIC_INI1; g_stratosphere_ini1->size = size; - g_stratosphere_ini1->num_processes = 4; + g_stratosphere_ini1->num_processes = 3; /*TODO: Change to 4 when boot is supported. */ g_stratosphere_ini1->_0xC = 0; data = g_stratosphere_ini1->kip_data; @@ -67,9 +67,12 @@ ini1_header_t *stratosphere_get_ini1(uint32_t target_firmware) { memcpy(data, sm_kip, sm_kip_size); data += sm_kip_size; + /* TODO: Uncomment when boot is supported. */ + /* memcpy(data, boot_kip, boot_kip_size); data += boot_kip_size; - + */ + return g_stratosphere_ini1; } diff --git a/fusee/fusee-secondary/src/sysreg.h b/fusee/fusee-secondary/src/sysreg.h new file mode 100644 index 000000000..d69cf8897 --- /dev/null +++ b/fusee/fusee-secondary/src/sysreg.h @@ -0,0 +1,32 @@ +#ifndef FUSEE_SYSREG_H +#define FUSEE_SYSREG_H + +#include + +#define SYSREG_BASE 0x6000C000 +#define SB_BASE (SYSREG_BASE + 0x200) +#define EXCP_VEC_BASE 0x6000F000 + +#define MAKE_SYSREG(n) MAKE_REG32(SYSREG_BASE + n) +#define MAKE_SB_REG(n) MAKE_REG32(SB_BASE + n) +#define MAKE_EXCP_VEC_REG(n) MAKE_REG32(EXCP_VEC_BASE + n) + +#define AHB_ARBITRATION_DISABLE_0 MAKE_SYSREG(0x004) +#define AHB_ARBITRATION_XBAR_CTRL_0 MAKE_SYSREG(0x0E0) +#define AHB_AHB_SPARE_REG_0 MAKE_SYSREG(0x110) + +#define SB_CSR_0 MAKE_SB_REG(0x00) +#define SB_PIROM_START_0 MAKE_SB_REG(0x04) +#define SB_PFCFG_0 MAKE_SB_REG(0x08) +#define SB_SECURE_SPAREREG_0_0 MAKE_SB_REG(0x0C) +#define SB_SECURE_SPAREREG_1_0 MAKE_SB_REG(0x10) +#define SB_SECURE_SPAREREG_2_0 MAKE_SB_REG(0x14) +#define SB_SECURE_SPAREREG_3_0 MAKE_SB_REG(0x18) +#define SB_SECURE_SPAREREG_4_0 MAKE_SB_REG(0x1C) +#define SB_SECURE_SPAREREG_5_0 MAKE_SB_REG(0x20) +#define SB_SECURE_SPAREREG_6_0 MAKE_SB_REG(0x24) +#define SB_SECURE_SPAREREG_7_0 MAKE_SB_REG(0x28) +#define SB_AA64_RESET_LOW_0 MAKE_SB_REG(0x30) +#define SB_AA64_RESET_HIGH_0 MAKE_SB_REG(0x34) + +#endif diff --git a/fusee/fusee-secondary/src/timers.h b/fusee/fusee-secondary/src/timers.h index 519c0292f..8c9569c19 100644 --- a/fusee/fusee-secondary/src/timers.h +++ b/fusee/fusee-secondary/src/timers.h @@ -8,6 +8,7 @@ #define TIMERUS_CNTR_1US_0 MAKE_REG32(TIMERS_BASE + 0x10) #define RTC_BASE 0x7000E000 +#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n) #define RTC_SECONDS MAKE_REG32(RTC_BASE + 0x08) #define RTC_SHADOW_SECONDS MAKE_REG32(RTC_BASE + 0x0C) #define RTC_MILLI_SECONDS MAKE_REG32(RTC_BASE + 0x10) diff --git a/fusee/fusee-secondary/src/tsec.c b/fusee/fusee-secondary/src/tsec.c new file mode 100644 index 000000000..12e8613ec --- /dev/null +++ b/fusee/fusee-secondary/src/tsec.c @@ -0,0 +1,156 @@ +#include "tsec.h" +#include "di.h" +#include "timers.h" +#include "car.h" + +static int tsec_dma_wait_idle() +{ + volatile tegra_tsec_t *tsec = tsec_get_regs(); + uint32_t timeout = (get_time_ms() + 10000); + + while (!(tsec->FALCON_DMATRFCMD & 2)) + if (get_time_ms() > timeout) + return 0; + + return 1; +} + +static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t phys_offset) +{ + volatile tegra_tsec_t *tsec = tsec_get_regs(); + uint32_t cmd = 0; + + if (!is_imem) + cmd = 0x600; + else + cmd = 0x10; + + tsec->FALCON_DMATRFMOFFS = flcn_offset; + tsec->FALCON_DMATRFFBOFFS = phys_offset; + tsec->FALCON_DMATRFCMD = cmd; + + return tsec_dma_wait_idle(); +} + +int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw) +{ + volatile tegra_tsec_t *tsec = tsec_get_regs(); + + /* Enable clocks. */ + clkrst_reboot(CARDEVICE_HOST1X); + clkrst_reboot(CARDEVICE_TSEC); + clkrst_reboot(CARDEVICE_SOR_SAFE); + clkrst_reboot(CARDEVICE_SOR0); + clkrst_reboot(CARDEVICE_SOR1); + clkrst_reboot(CARDEVICE_KFUSE); + + /* Configure Falcon. */ + tsec->FALCON_DMACTL = 0; + tsec->FALCON_IRQMSET = 0xFFF2; + tsec->FALCON_IRQDEST = 0xFFF0; + tsec->FALCON_ITFEN = 3; + + if (!tsec_dma_wait_idle()) + { + /* Disable clocks. */ + clkrst_disable(CARDEVICE_KFUSE); + clkrst_disable(CARDEVICE_SOR1); + clkrst_disable(CARDEVICE_SOR0); + clkrst_disable(CARDEVICE_SOR_SAFE); + clkrst_disable(CARDEVICE_TSEC); + clkrst_disable(CARDEVICE_HOST1X); + + return -1; + } + + /* Load firmware. */ + tsec->FALCON_DMATRFBASE = (uint32_t)tsec_fw >> 8; + for (uint32_t addr = 0; addr < 0xF00; addr += 0x100) + { + if (!tsec_dma_phys_to_flcn(true, addr, addr)) + { + /* Disable clocks. */ + clkrst_disable(CARDEVICE_KFUSE); + clkrst_disable(CARDEVICE_SOR1); + clkrst_disable(CARDEVICE_SOR0); + clkrst_disable(CARDEVICE_SOR_SAFE); + clkrst_disable(CARDEVICE_TSEC); + clkrst_disable(CARDEVICE_HOST1X); + + return -2; + } + } + + /* Unknown host1x write. */ + MAKE_HOST1X_REG(0x3300) = 0x34C2E1DA; + + /* Execute firmware. */ + tsec->FALCON_SCRATCH1 = 0; + tsec->FALCON_SCRATCH0 = rev; + tsec->FALCON_BOOTVEC = 0; + tsec->FALCON_CPUCTL = 2; + + if (!tsec_dma_wait_idle()) + { + /* Disable clocks. */ + clkrst_disable(CARDEVICE_KFUSE); + clkrst_disable(CARDEVICE_SOR1); + clkrst_disable(CARDEVICE_SOR0); + clkrst_disable(CARDEVICE_SOR_SAFE); + clkrst_disable(CARDEVICE_TSEC); + clkrst_disable(CARDEVICE_HOST1X); + + return -3; + } + + uint32_t timeout = (get_time_ms() + 2000); + while (!tsec->FALCON_SCRATCH1) + { + if (get_time_ms() > timeout) + { + /* Disable clocks. */ + clkrst_disable(CARDEVICE_KFUSE); + clkrst_disable(CARDEVICE_SOR1); + clkrst_disable(CARDEVICE_SOR0); + clkrst_disable(CARDEVICE_SOR_SAFE); + clkrst_disable(CARDEVICE_TSEC); + clkrst_disable(CARDEVICE_HOST1X); + + return -4; + } + } + + if (tsec->FALCON_SCRATCH1 != 0xB0B0B0B0) + { + /* Disable clocks. */ + clkrst_disable(CARDEVICE_KFUSE); + clkrst_disable(CARDEVICE_SOR1); + clkrst_disable(CARDEVICE_SOR0); + clkrst_disable(CARDEVICE_SOR_SAFE); + clkrst_disable(CARDEVICE_TSEC); + clkrst_disable(CARDEVICE_HOST1X); + + return -5; + } + + /* Unknown host1x write. */ + MAKE_HOST1X_REG(0x3300) = 0; + + /* Fetch result from SOR1. */ + uint32_t tmp[0x4] = {0}; + tmp[0] = SOR1_DP_HDCP_BKSV_LSB; + tmp[1] = SOR1_TMDS_HDCP_BKSV_LSB; + tmp[2] = SOR1_TMDS_HDCP_CN_MSB; + tmp[3] = SOR1_TMDS_HDCP_CN_LSB; + + /* Clear SOR1 registers. */ + SOR1_DP_HDCP_BKSV_LSB = 0; + SOR1_TMDS_HDCP_BKSV_LSB = 0; + SOR1_TMDS_HDCP_CN_MSB = 0; + SOR1_TMDS_HDCP_CN_LSB = 0; + + /* Copy back the key. */ + memcpy(key, &tmp, 0x10); + + return 0; +} \ No newline at end of file diff --git a/fusee/fusee-secondary/src/tsec.h b/fusee/fusee-secondary/src/tsec.h new file mode 100644 index 000000000..47be450bd --- /dev/null +++ b/fusee/fusee-secondary/src/tsec.h @@ -0,0 +1,97 @@ +#ifndef FUSEE_TSEC_H_ +#define FUSEE_TSEC_H_ + +#include +#include + +#define TSEC_BASE 0x54500000 +#define SOR1_BASE 0x54580000 + +#define SOR1_DP_HDCP_BKSV_LSB MAKE_REG32(SOR1_BASE + 0x1E8) +#define SOR1_TMDS_HDCP_BKSV_LSB MAKE_REG32(SOR1_BASE + 0x21C) +#define SOR1_TMDS_HDCP_CN_MSB MAKE_REG32(SOR1_BASE + 0x208) +#define SOR1_TMDS_HDCP_CN_LSB MAKE_REG32(SOR1_BASE + 0x20C) + +typedef struct { + uint8_t _0x0[0x1000]; /* Ignore non Falcon registers. */ + uint32_t FALCON_IRQSSET; + uint32_t FALCON_IRQSCLR; + uint32_t FALCON_IRQSTAT; + uint32_t FALCON_IRQMODE; + uint32_t FALCON_IRQMSET; + uint32_t FALCON_IRQMCLR; + uint32_t FALCON_IRQMASK; + uint32_t FALCON_IRQDEST; + uint8_t _0x1020[0x20]; + uint32_t FALCON_SCRATCH0; + uint32_t FALCON_SCRATCH1; + uint32_t FALCON_ITFEN; + uint32_t FALCON_IDLESTATE; + uint32_t FALCON_CURCTX; + uint32_t FALCON_NXTCTX; + uint8_t _0x1058[0x28]; + uint32_t FALCON_SCRATCH2; + uint32_t FALCON_SCRATCH3; + uint8_t _0x1088[0x18]; + uint32_t FALCON_CGCTL; + uint32_t FALCON_ENGCTL; + uint8_t _0x10A8[0x58]; + uint32_t FALCON_CPUCTL; + uint32_t FALCON_BOOTVEC; + uint32_t FALCON_HWCFG; + uint32_t FALCON_DMACTL; + uint32_t FALCON_DMATRFBASE; + uint32_t FALCON_DMATRFMOFFS; + uint32_t FALCON_DMATRFCMD; + uint32_t FALCON_DMATRFFBOFFS; + uint8_t _0x1120[0x10]; + uint32_t FALCON_CPUCTL_ALIAS; + uint8_t _0x1134[0x20]; + uint32_t FALCON_IMFILLRNG1; + uint32_t FALCON_IMFILLCTL; + uint32_t _0x115C; + uint32_t _0x1160; + uint32_t _0x1164; + uint32_t FALCON_EXTERRADDR; + uint32_t FALCON_EXTERRSTAT; + uint32_t _0x1170; + uint32_t _0x1174; + uint32_t _0x1178; + uint32_t FALCON_CG2; + uint32_t FALCON_CODE_INDEX; + uint32_t FALCON_CODE; + uint32_t FALCON_CODE_VIRT_ADDR; + uint8_t _0x118C[0x34]; + uint32_t FALCON_DATA_INDEX0; + uint32_t FALCON_DATA0; + uint32_t FALCON_DATA_INDEX1; + uint32_t FALCON_DATA1; + uint32_t FALCON_DATA_INDEX2; + uint32_t FALCON_DATA2; + uint32_t FALCON_DATA_INDEX3; + uint32_t FALCON_DATA3; + uint32_t FALCON_DATA_INDEX4; + uint32_t FALCON_DATA4; + uint32_t FALCON_DATA_INDEX5; + uint32_t FALCON_DATA5; + uint32_t FALCON_DATA_INDEX6; + uint32_t FALCON_DATA6; + uint32_t FALCON_DATA_INDEX7; + uint32_t FALCON_DATA7; + uint32_t FALCON_ICD_CMD; + uint32_t FALCON_ICD_ADDR; + uint32_t FALCON_ICD_WDATA; + uint32_t FALCON_ICD_RDATA; + uint8_t _0x1210[0x30]; + uint32_t FALCON_SCTL; + uint8_t _0x1244[0x5F8]; /* Ignore non Falcon registers. */ +} tegra_tsec_t; + +static inline volatile tegra_tsec_t *tsec_get_regs(void) +{ + return (volatile tegra_tsec_t *)TSEC_BASE; +} + +int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw); + +#endif \ No newline at end of file diff --git a/fusee/fusee-secondary/src/utils.c b/fusee/fusee-secondary/src/utils.c index 4aee48cf6..220c49d24 100644 --- a/fusee/fusee-secondary/src/utils.c +++ b/fusee/fusee-secondary/src/utils.c @@ -6,7 +6,7 @@ #include "pmc.h" #include "car.h" #include "timers.h" -#include "hwinit/btn.h" +#include "btn.h" #include "panic.h" #include