nold/Atmosphere
1
0
Fork 0
mirror of https://github.com/Atmosphere-NX/Atmosphere synced 2024-12-22 20:31:14 +00:00
Code Issues Projects Releases Packages Wiki Activity

fusee: Minor bugfixes.

Browse source
This commit is contained in:
hexkyz 2018-09-05 20:51:03 +01:00
parent ad4605abde
commit 2f8edfa8e2
14 changed files with 40 additions and 52 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
fusee/fusee-primary/src/di.c
View file

@ -70,7 +70,7 @@ void display_init()
/* Enable Backlight +5V. */ /* Enable Backlight +5V. */
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
udelay(10000u); udelay(10000);
/* Enable Backlight -5V. */ /* Enable Backlight -5V. */
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
@ -165,12 +165,7 @@ void display_end()
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; MAKE_DSI_REG(DSI_WR_DATA) = 0x2805;
uint32_t host1x_delay = MAKE_HOST1X_REG(0x30A4) + 5; MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
while (MAKE_HOST1X_REG(0x30A4) < host1x_delay) {
/* Wait. */
}
MAKE_DI_REG(DC_CMD_STATE_ACCESS) = 5;
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17); exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17);
@ -182,7 +177,7 @@ void display_end()
exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22); exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22);
MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; MAKE_DSI_REG(DSI_WR_DATA) = 0x1005;
MAKE_DSI_REG(DSI_TRIGGER) = 2; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
udelay(50000); udelay(50000);
@ -207,7 +202,7 @@ void display_end()
car->rst_dev_l_set = 0x18000000; car->rst_dev_l_set = 0x18000000;
car->clk_enb_l_clr = 0x18000000; car->clk_enb_l_clr = 0x18000000;
MAKE_DSI_REG(DSI_PAD_CONTROL_0) = 0x10F010F; MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF));
MAKE_DSI_REG(DSI_POWER_CONTROL) = 0; MAKE_DSI_REG(DSI_POWER_CONTROL) = 0;
/* Backlight PWM. */ /* Backlight PWM. */
@ -236,17 +231,16 @@ void display_color_screen(uint32_t color)
uint32_t *display_init_framebuffer(void *address) uint32_t *display_init_framebuffer(void *address)
{ {
static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0}; static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0};
if(conf[0].val == 0) { if (conf[0].val == 0) {
for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) { for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) {
conf[i] = cfg_display_framebuffer[i]; conf[i] = cfg_display_framebuffer[i];
} }
} }
uint32_t *lfb_addr = (uint32_t *)address; uint32_t *lfb_addr = (uint32_t *)address;
conf[19].val = (uint32_t)address; conf[19].val = (uint32_t)address;
//This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). /* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */
exec_cfg((uint32_t *)DI_BASE, conf, 32); exec_cfg((uint32_t *)DI_BASE, conf, 32);
udelay(35000); udelay(35000);

2
fusee/fusee-primary/src/flow.h
View file

@ -4,7 +4,7 @@
#include <stdint.h> #include <stdint.h>
#define FLOW_CTLR_BASE 0x60007000 #define FLOW_CTLR_BASE 0x60007000
#define MAKE_FLOW_REG(ofs) MAKE_REG32(FLOW_CTLR_BASE + ofs) #define MAKE_FLOW_REG(n) MAKE_REG32(FLOW_CTLR_BASE + n)
#define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004) #define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004)
#define FLOW_CTLR_RAM_REPAIR_0 MAKE_FLOW_REG(0x040) #define FLOW_CTLR_RAM_REPAIR_0 MAKE_FLOW_REG(0x040)

2
fusee/fusee-primary/src/hwinit.c
View file

@ -24,7 +24,7 @@ void config_oscillators()
car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4); car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4);
SYSCTR0_CNTFID0_0 = 19200000; SYSCTR0_CNTFID0_0 = 19200000;
MAKE_TIMERS_REG(0x14) = 0x45F; TIMERUS_USEC_CFG_0 = 0x45F;
car->osc_ctrl = 0x50000071; car->osc_ctrl = 0x50000071;
pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE); pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE);

2
fusee/fusee-primary/src/max7762x.c
View file

@ -60,7 +60,7 @@ int max77620_regulator_get_status(uint32_t id)
} }
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->cfg_addr, &val, 1)) if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->cfg_addr, &val, 1))
return (val & 8) ? 0 : 1; return (val & 8) ? 1 : 0;
return 0; return 0;
} }

2
fusee/fusee-primary/src/mc.c
View file

@ -20,7 +20,7 @@ void mc_config_carveout()
MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0; MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0;
MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1; MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1;
mc_config_tsec_carveout(0, 0, 1); mc_config_tsec_carveout(0, 0, true);
MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0; MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0;
MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0; MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;

11
fusee/fusee-primary/src/timers.h
View file

@ -5,13 +5,14 @@
#define TIMERS_BASE 0x60005000 #define TIMERS_BASE 0x60005000
#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n) #define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
#define TIMERUS_CNTR_1US_0 MAKE_REG32(TIMERS_BASE + 0x10) #define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
#define RTC_BASE 0x7000E000 #define RTC_BASE 0x7000E000
#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n) #define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
#define RTC_SECONDS MAKE_REG32(RTC_BASE + 0x08) #define RTC_SECONDS MAKE_RTC_REG(0x08)
#define RTC_SHADOW_SECONDS MAKE_REG32(RTC_BASE + 0x0C) #define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
#define RTC_MILLI_SECONDS MAKE_REG32(RTC_BASE + 0x10) #define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
typedef struct { typedef struct {
uint32_t CONFIG; uint32_t CONFIG;
@ -22,7 +23,7 @@ typedef struct {
#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n)) #define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
#define WDT_REBOOT_PATTERN 0xC45A #define WDT_REBOOT_PATTERN 0xC45A
#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8*n) #define GET_WDT_REBOOT_CFG_REG(n) MAKE_TIMERS_REG(0x60 + 0x8 * n)
void wait(uint32_t microseconds); void wait(uint32_t microseconds);

2
fusee/fusee-secondary/src/cluster.c
View file

@ -110,7 +110,7 @@ void cluster_boot_cpu0(uint32_t entry)
/* Request and wait for RAM repair. */ /* Request and wait for RAM repair. */
FLOW_CTLR_RAM_REPAIR_0 = 1; FLOW_CTLR_RAM_REPAIR_0 = 1;
while (!(FLOW_CTLR_RAM_REPAIR_0 & 2)){ while (!(FLOW_CTLR_RAM_REPAIR_0 & 2)) {
/* Wait. */ /* Wait. */
} }

18
fusee/fusee-secondary/src/di.c
View file

@ -70,7 +70,7 @@ void display_init()
/* Enable Backlight +5V. */ /* Enable Backlight +5V. */
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
udelay(10000u); udelay(10000);
/* Enable Backlight -5V. */ /* Enable Backlight -5V. */
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
@ -165,12 +165,7 @@ void display_end()
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; MAKE_DSI_REG(DSI_WR_DATA) = 0x2805;
uint32_t host1x_delay = MAKE_HOST1X_REG(0x30A4) + 5; MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
while (MAKE_HOST1X_REG(0x30A4) < host1x_delay) {
/* Wait. */
}
MAKE_DI_REG(DC_CMD_STATE_ACCESS) = 5;
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17); exec_cfg((uint32_t *)DI_BASE, _display_config_12, 17);
@ -182,7 +177,7 @@ void display_end()
exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22); exec_cfg((uint32_t *)DSI_BASE, _display_config_14, 22);
MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; MAKE_DSI_REG(DSI_WR_DATA) = 0x1005;
MAKE_DSI_REG(DSI_TRIGGER) = 2; MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
udelay(50000); udelay(50000);
@ -207,7 +202,7 @@ void display_end()
car->rst_dev_l_set = 0x18000000; car->rst_dev_l_set = 0x18000000;
car->clk_enb_l_clr = 0x18000000; car->clk_enb_l_clr = 0x18000000;
MAKE_DSI_REG(DSI_PAD_CONTROL_0) = 0x10F010F; MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF));
MAKE_DSI_REG(DSI_POWER_CONTROL) = 0; MAKE_DSI_REG(DSI_POWER_CONTROL) = 0;
/* Backlight PWM. */ /* Backlight PWM. */
@ -236,17 +231,16 @@ void display_color_screen(uint32_t color)
uint32_t *display_init_framebuffer(void *address) uint32_t *display_init_framebuffer(void *address)
{ {
static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0}; static cfg_op_t conf[sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t)] = {0};
if(conf[0].val == 0) { if (conf[0].val == 0) {
for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) { for (uint32_t i = 0; i < sizeof(cfg_display_framebuffer)/sizeof(cfg_op_t); i++) {
conf[i] = cfg_display_framebuffer[i]; conf[i] = cfg_display_framebuffer[i];
} }
} }
uint32_t *lfb_addr = (uint32_t *)address; uint32_t *lfb_addr = (uint32_t *)address;
conf[19].val = (uint32_t)address; conf[19].val = (uint32_t)address;
//This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). /* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */
exec_cfg((uint32_t *)DI_BASE, conf, 32); exec_cfg((uint32_t *)DI_BASE, conf, 32);
udelay(35000); udelay(35000);

2
fusee/fusee-secondary/src/flow.h
View file

@ -4,7 +4,7 @@
#include <stdint.h> #include <stdint.h>
#define FLOW_CTLR_BASE 0x60007000 #define FLOW_CTLR_BASE 0x60007000
#define MAKE_FLOW_REG(ofs) MAKE_REG32(FLOW_CTLR_BASE + ofs) #define MAKE_FLOW_REG(n) MAKE_REG32(FLOW_CTLR_BASE + n)
#define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004) #define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004)
#define FLOW_CTLR_RAM_REPAIR_0 MAKE_FLOW_REG(0x040) #define FLOW_CTLR_RAM_REPAIR_0 MAKE_FLOW_REG(0x040)

2
fusee/fusee-secondary/src/max7762x.c
View file

@ -60,7 +60,7 @@ int max77620_regulator_get_status(uint32_t id)
} }
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->cfg_addr, &val, 1)) if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->cfg_addr, &val, 1))
return (val & 8) ? 0 : 1; return (val & 8) ? 1 : 0;
return 0; return 0;
} }

2
fusee/fusee-secondary/src/mc.c
View file

@ -20,7 +20,7 @@ void mc_config_carveout()
MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0; MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0;
MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1; MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1;
mc_config_tsec_carveout(0, 0, 1); mc_config_tsec_carveout(0, 0, true);
MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0; MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0;
MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0; MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;

9
fusee/fusee-secondary/src/nxboot.c
View file

@ -133,7 +133,7 @@ static void nxboot_set_bootreason() {
boot_reason.boot_reason_state = 0x04; boot_reason.boot_reason_state = 0x04;
/* Set in memory. */ /* Set in memory. */
memcpy((void *)MAILBOX_NX_BOOTLOADER_BOOT_REASON, &boot_reason, sizeof(boot_reason)); memcpy((void *)MAILBOX_NX_BOOTLOADER_BOOT_REASON_BASE, &boot_reason, sizeof(boot_reason));
/* Clean up. */ /* Clean up. */
free(bct); free(bct);
@ -335,7 +335,7 @@ void nxboot_main(void) {
printf(u8"[NXBOOT]: Reading Exosphère...\n"); printf(u8"[NXBOOT]: Reading Exosphère...\n");
/* Select the right address for Exosphère. */ /* Select the right address for Exosphère. */
if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware <= EXOSPHERE_TARGET_FIRMWARE_400) { if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) {
exosphere_memaddr = (void *)0x4002D000; exosphere_memaddr = (void *)0x4002D000;
} else { } else {
exosphere_memaddr = (void *)0x4002B000; exosphere_memaddr = (void *)0x4002B000;
@ -415,7 +415,7 @@ void nxboot_main(void) {
if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) { if (MAILBOX_EXOSPHERE_CONFIGURATION->target_firmware < EXOSPHERE_TARGET_FIRMWARE_400) {
MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_LOADED_PACKAGE2; MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_LOADED_PACKAGE2;
} else { } else {
MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_LOADED_PACKAGE2_4X; MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_DRAM_INITIALIZED_4X;
} }
printf("[NXBOOT]: Powering on the CCPLEX...\n"); printf("[NXBOOT]: Powering on the CCPLEX...\n");
@ -426,9 +426,6 @@ void nxboot_main(void) {
/* Unmount everything. */ /* Unmount everything. */
nxfs_unmount_all(); nxfs_unmount_all();
/* Turn off the backlight. */
display_backlight(false);
/* Terminate the display. */ /* Terminate the display. */
display_end(); display_end();

9
fusee/fusee-secondary/src/nxboot.h
View file

@ -3,11 +3,12 @@
#include "utils.h" #include "utils.h"
#define MAILBOX_NX_BOOTLOADER_BASE ((void *)(0x40002000)) #define MAILBOX_NX_BOOTLOADER_BASE 0x40002000
#define MAILBOX_NX_BOOTLOADER_BOOT_REASON_BASE (MAILBOX_NX_BOOTLOADER_BASE + 0xE10)
#define MAKE_MAILBOX_NX_BOOTLOADER_REG(n) MAKE_REG32(MAILBOX_NX_BOOTLOADER_BASE + n)
#define MAILBOX_NX_BOOTLOADER_BOOT_REASON (MAILBOX_NX_BOOTLOADER_BASE + 0xE10) #define MAILBOX_NX_BOOTLOADER_SETUP_STATE MAKE_MAILBOX_NX_BOOTLOADER_REG(0xEF8)
#define MAILBOX_NX_BOOTLOADER_SETUP_STATE MAKE_REG32(MAILBOX_NX_BOOTLOADER_BASE + 0xEF8) #define MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE MAKE_MAILBOX_NX_BOOTLOADER_REG(0xEFC)
#define MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE MAKE_REG32(MAILBOX_NX_BOOTLOADER_BASE + 0xEFC)
#define NX_BOOTLOADER_STATE_INIT 0 #define NX_BOOTLOADER_STATE_INIT 0
#define NX_BOOTLOADER_STATE_MOVED_BOOTCONFIG 1 #define NX_BOOTLOADER_STATE_MOVED_BOOTCONFIG 1

11
fusee/fusee-secondary/src/timers.h
View file

@ -5,13 +5,14 @@
#define TIMERS_BASE 0x60005000 #define TIMERS_BASE 0x60005000
#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n) #define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
#define TIMERUS_CNTR_1US_0 MAKE_REG32(TIMERS_BASE + 0x10) #define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
#define RTC_BASE 0x7000E000 #define RTC_BASE 0x7000E000
#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n) #define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
#define RTC_SECONDS MAKE_REG32(RTC_BASE + 0x08) #define RTC_SECONDS MAKE_RTC_REG(0x08)
#define RTC_SHADOW_SECONDS MAKE_REG32(RTC_BASE + 0x0C) #define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
#define RTC_MILLI_SECONDS MAKE_REG32(RTC_BASE + 0x10) #define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
typedef struct { typedef struct {
uint32_t CONFIG; uint32_t CONFIG;
@ -22,7 +23,7 @@ typedef struct {
#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n)) #define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
#define WDT_REBOOT_PATTERN 0xC45A #define WDT_REBOOT_PATTERN 0xC45A
#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8*n) #define GET_WDT_REBOOT_CFG_REG(n) MAKE_TIMERS_REG(0x60 + 0x8 * n)
void wait(uint32_t microseconds); void wait(uint32_t microseconds);