mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-11-15 09:36:35 +00:00
thermosphere: add hypervisor timer code
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parent
3d3a9925b9
commit
1eb60a2a52
10 changed files with 169 additions and 17 deletions
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@ -144,8 +144,8 @@ ifeq ($(PLATFORM), qemu)
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export QEMU := qemu-system-aarch64
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QEMUFLAGS := -nographic -machine virt,virtualization=on,gic-version=2 -cpu cortex-a57 -smp 4 -m 1024\
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-kernel thermosphere.elf -d unimp,guest_errors -semihosting-config enable,target=native -serial mon:stdio
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QEMUFLAGS := -nographic -machine virt,virtualization=on,accel=tcg,gic-version=2 -cpu cortex-a57 -smp 4 -m 1024\
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-kernel thermosphere.elf -d unimp,guest_errors -semihosting-config enable,target=native -serial mon:stdio
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qemu: all
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@$(QEMU) $(QEMUFLAGS)
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@ -18,6 +18,7 @@
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#include "core_ctx.h"
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#include "debug_log.h"
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#include "vgic.h"
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#include "timer.h"
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IrqManager g_irqManager = {0};
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@ -183,6 +184,9 @@ void handleIrqException(ExceptionStackFrame *frame, bool isLowerEl, bool isA32)
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case GIC_IRQID_MAINTENANCE:
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isMaintenanceInterrupt = true;
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break;
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case TIMER_IRQID(CURRENT_TIMER):
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timerInterruptHandler();
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break;
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default:
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isGuestInterrupt = irqId >= 16;
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break;
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@ -77,5 +77,15 @@ static inline bool irqIsGuest(u16 id)
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return false;
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}
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return id != GIC_IRQID_MAINTENANCE && id != GIC_IRQID_HYP_TIMER;
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bool ret = id != GIC_IRQID_MAINTENANCE && id != GIC_IRQID_NS_PHYS_HYP_TIMER;
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#if GIC_IRQID_NS_VIRT_HYP_TIMER != GIC_IRQID_SPURIOUS
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ret = ret && id != GIC_IRQID_NS_VIRT_HYP_TIMER;
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#endif
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#if GIC_IRQID_SEC_PHYS_HYP_TIMER != GIC_IRQID_SPURIOUS
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ret = ret && id != GIC_IRQID_SEC_PHYS_HYP_TIMER;
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#endif
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#if GIC_IRQID_SEC_VIRT_HYP_TIMER != GIC_IRQID_SPURIOUS
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ret = ret && id != GIC_IRQID_SEC_VIRT_HYP_TIMER;
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#endif
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return ret;
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}
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@ -11,7 +11,7 @@
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#include "single_step.h"
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#include "breakpoints.h"
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#include "watchpoints.h"
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#include "timer.h"
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#include "irq.h"
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extern const u8 __start__[];
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@ -41,6 +41,7 @@ void thermosphereMain(ExceptionStackFrame *frame)
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{
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enableTraps();
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enableBreakpointsAndWatchpoints();
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timerInit();
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initIrq();
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if (currentCoreCtx->isBootCore) {
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@ -23,13 +23,18 @@
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#define GIC_IRQID_PMU 23
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#define GIC_IRQID_MAINTENANCE 25
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#define GIC_IRQID_HYP_TIMER 26
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#define GIC_IRQID_VIRT_TIMER 27
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#define GIC_IRQID_NS_PHYS_HYP_TIMER 26
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#define GIC_IRQID_NS_VIRT_TIMER 27
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//#define GIC_IRQID_LEGACY_NFIQ 28 not defined?
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#define GIC_IRQID_SEC_PHYS_TIMER 29
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#define GIC_IRQID_NS_PHYS_TIMER 30
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//#define GIC_IRQID_LEGACY_NIRQ 31 not defined?
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#define GIC_IRQID_NS_VIRT_HYP_TIMER GIC_IRQID_SPURIOUS // SBSA: 28. Unimplemented
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#define GIC_IRQID_SEC_PHYS_HYP_TIMER GIC_IRQID_SPURIOUS // SBSA: 20. Unimplemented
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#define GIC_IRQID_SEC_VIRT_HYP_TIMER GIC_IRQID_SPURIOUS // SBSA: 19. Unimplemented
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static inline void initGicV2Pointers(ArmGicV2 *gic)
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{
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gic->gicd = (volatile ArmGicV2Distributor *)0x08000000ull;
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@ -21,14 +21,17 @@
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// For both guest and host
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#define MAX_NUM_REGISTERED_INTERRUPTS 512
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#define GIC_IRQID_MAINTENANCE 25
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#define GIC_IRQID_HYP_TIMER 26
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#define GIC_IRQID_VIRT_TIMER 27
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#define GIC_IRQID_LEGACY_NFIQ 28
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#define GIC_IRQID_SEC_PHYS_TIMER 29
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#define GIC_IRQID_NS_PHYS_TIMER 30
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#define GIC_IRQID_LEGACY_NIRQ 31
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#define GIC_IRQID_MAINTENANCE 25
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#define GIC_IRQID_NS_PHYS_HYP_TIMER 26
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#define GIC_IRQID_NS_VIRT_TIMER 27
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#define GIC_IRQID_LEGACY_NFIQ 28
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#define GIC_IRQID_SEC_PHYS_TIMER 29
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#define GIC_IRQID_NS_PHYS_TIMER 30
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#define GIC_IRQID_LEGACY_NIRQ 31
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#define GIC_IRQID_NS_VIRT_HYP_TIMER GIC_IRQID_SPURIOUS // SBSA: 28. Unimplemented
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#define GIC_IRQID_SEC_PHYS_HYP_TIMER GIC_IRQID_SPURIOUS // SBSA: 20. Unimplemented
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#define GIC_IRQID_SEC_VIRT_HYP_TIMER GIC_IRQID_SPURIOUS // SBSA: 19. Unimplemented
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static inline void initGicV2Pointers(ArmGicV2 *gic)
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{
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@ -428,12 +428,12 @@
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#define GET_SYSREG(r) ({\
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u64 __val; \
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asm volatile("mrs %0, " STRINGIZE(r) : "=r" (__val)); \
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asm volatile("mrs %0, " STRINGIZE(r) : "=r" (__val)); \
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__val; \
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})
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#define SET_SYSREG(reg, val) do { u64 temp_reg = (val); __asm__ __volatile__ ("msr " #reg ", %0" :: "r"(temp_reg) : "memory"); } while(false)
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#define SET_SYSREG_IMM(reg, imm) do { __asm__ __volatile__ ("msr " #reg ", %0" :: "I"(imm) : "memory"); } while(false)
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#define SET_SYSREG(reg, val) do { u64 temp_reg = (val); __asm__ __volatile__ ("msr " STRINGIZE(reg) ", %0" :: "r"(temp_reg) : "memory"); } while(false)
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#define SET_SYSREG_IMM(reg, imm) do { __asm__ __volatile__ ("msr " STRINGIZE(reg) ", %0" :: "I"(imm) : "memory"); } while(false)
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#define SYSREG_OP1_AARCH32_AUTO 0
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#define SYSREG_OP1_AARCH64_EL1 0
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38
thermosphere/src/timer.c
Normal file
38
thermosphere/src/timer.c
Normal file
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "timer.h"
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#include "irq.h"
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u64 g_timerFreq = 0;
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void timerInit(void)
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{
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timerSetInterruptStatus(false, false);
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if (currentCoreCtx->isBootCore) {
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g_timerFreq = GET_SYSREG(cntfrq_el0);
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}
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}
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void timerInterruptHandler(void)
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{
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// Disable timer interrupts until reprogrammed
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timerSetInterruptStatus(false, false);
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// For fun
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DEBUG("EL2 [core %d]: Timer interrupt at %lums\n", (int)currentCoreCtx->coreId, timerGetSystemTimeMs());
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timerSetTimeoutMs(1000);
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}
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91
thermosphere/src/timer.h
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91
thermosphere/src/timer.h
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@ -0,0 +1,91 @@
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/*
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* Copyright (c) 2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "utils.h"
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#include "sysreg.h"
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#include "platform/interrupt_config.h"
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#define SECTONSECS 1000000000ull
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#define SECTOMSECS 1000ull
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// All generic timers possibly defined in the Arm architecture:
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// (suffix, time source suffix, level, irqid)
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#define NS_PHYS_TIMER (p, p, 0, GIC_IRQID_NS_PHYS_TIMER)
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#define NS_VIRT_TIMER (v, v, 0, GIC_IRQID_NS_VIRT_TIMER)
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#define NS_PHYS_HYP_TIMER (hp, p, 2, GIC_IRQID_NS_PHYS_HYP_TIMER)
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#define NS_VIRT_HYP_TIMER (hv, v, 2, GIC_IRQID_NS_VIRT_HYP_TIMER)
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#define SEC_PHYS_TIMER (ps, p, 1, GIC_IRQID_SEC_PHYS_TIMER)
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#define SEC_PHYS_HYP_TIMER (hps, p, 2, GIC_IRQID_SEC_PHYS_HYP_TIMER)
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#define SEC_VIRT_HYP_TIMER (hvs, v, 2, GIC_IRQID_SEC_VIRT_HYP_TIMER)
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#define TIMER_IRQID_FIELDS(ign, ign2, ign3, id) id
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#define TIMER_COUNTER_REG_FIELDS(ign, ts, ign2, ign3) cnt##ts##ct_el0
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#define TIMER_CTL_REG_FIELDS(t, ign, el, ign2) cnt##t##_ctl_el##el
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#define TIMER_CVAL_REG_FIELDS(t, ign, el, ign2) cnt##t##_cval_el##el
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#define TIMER_TVAL_REG_FIELDS(t, ign, el, ign2) cnt##t##_tval_el##el
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#define TIMER_IRQID(name) EVAL(TIMER_IRQID_FIELDS name)
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#define TIMER_COUNTER_REG(name) EVAL(TIMER_COUNTER_REG_FIELDS name)
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#define TIMER_CTL_REG(name) EVAL(TIMER_CTL_REG_FIELDS name)
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#define TIMER_CVAL_REG(name) EVAL(TIMER_CVAL_REG_FIELDS name)
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#define TIMER_TVAL_REG(name) EVAL(TIMER_TVAL_REG_FIELDS name)
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#define CURRENT_TIMER NS_PHYS_HYP_TIMER
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extern u64 g_timerFreq;
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void timerInit(void);
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void timerInterruptHandler(void);
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static inline u64 timerGetSystemTick(void)
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{
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return GET_SYSREG(TIMER_COUNTER_REG(CURRENT_TIMER));
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}
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static inline u64 timerGetSystemTimeNs(void)
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{
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return timerGetSystemTick() * SECTONSECS / g_timerFreq;
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}
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static inline u64 timerGetSystemTimeMs(void)
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{
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return timerGetSystemTick() * SECTOMSECS / g_timerFreq;
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}
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static inline void timerSetInterruptStatus(bool enabled, bool masked)
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{
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u32 ebit = enabled ? BIT(0) : 0;
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u32 mbit = masked ? BIT(1) : 0;
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SET_SYSREG(TIMER_CTL_REG(CURRENT_TIMER), mbit | ebit);
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}
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static inline void timerSetTimeoutTicks(u64 ticks)
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{
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SET_SYSREG(TIMER_CVAL_REG(CURRENT_TIMER), timerGetSystemTick() + ticks);
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timerSetInterruptStatus(true, false);
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}
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static inline void timerSetTimeoutNs(u64 ns)
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{
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timerSetTimeoutTicks(ns * g_timerFreq / SECTONSECS);
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}
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static inline void timerSetTimeoutMs(u64 ms)
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{
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timerSetTimeoutTicks(ms * g_timerFreq / SECTOMSECS);
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}
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@ -46,7 +46,7 @@
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static inline u##sz __##op##sz(u##sz n)\
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{\
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u##sz res;\
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__asm__ __volatile__ (#op " %" #regalloc "[res], %" #regalloc "[n]" : [res] "=r" (res) : [n] "r" (n));\
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__asm__ __volatile__ (STRINGIZE(op) " %" STRINGIZE(regalloc) "[res], %" STRINGIZE(regalloc) "[n]" : [res] "=r" (res) : [n] "r" (n));\
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return res;\
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}
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