From 17ca463c3fe522aab4699f88c3efd0544963b75d Mon Sep 17 00:00:00 2001 From: SciresM Date: Fri, 20 Aug 2021 13:13:29 -0700 Subject: [PATCH] ams: replace sept with tsec firmware (#1594) * ams: replace sept with tsec firmware This replaces sept with a custom tsec key derivation firmware. NOTE: This does not use any TSEC exploits whatsoever; it is a well-signed TSEC binary assembled with envyas and signed with the real cauth key. For more details, contact SciresM#0524. * fusee: only set SBK if it's readable --- Makefile | 17 +- .../loader_stub/source/secmon_loader_main.cpp | 6 +- exosphere/loader_stub/source/start.s | 6 +- fusee/common/fatfs/diskio.c | 2 - fusee/common/sdmmc/sdmmc.c | 16 +- fusee/common/sdmmc/sdmmc_core.c | 9 - .../fusee-primary-main/src/hwinit.c | 9 +- fusee/fusee-secondary/Makefile | 41 +- fusee/fusee-secondary/data/tsec_keygen.bin | Bin 0 -> 7936 bytes fusee/fusee-secondary/linker.ld | 8 +- fusee/fusee-secondary/src/car.h | 6 +- fusee/fusee-secondary/src/kernel_patches.c | 6 - fusee/fusee-secondary/src/key_derivation.c | 188 +- fusee/fusee-secondary/src/key_derivation.h | 23 +- fusee/fusee-secondary/src/masterkey.c | 4 +- fusee/fusee-secondary/src/nxboot.c | 130 +- fusee/fusee-secondary/src/nxboot_iram.c | 30 +- fusee/fusee-secondary/src/package1.c | 35 +- fusee/fusee-secondary/src/package1.h | 6 +- fusee/fusee-secondary/src/smmu.c | 284 -- fusee/fusee-secondary/src/smmu.h | 63 - fusee/fusee-secondary/src/start.s | 45 +- fusee/fusee-secondary/src/tsec.c | 142 +- fusee/fusee-secondary/src/tsec.h | 7 +- fusee/fusee-secondary/src/utils.c | 37 +- fusee/fusee-secondary/src/utils.h | 3 +- sept/Makefile | 10 - sept/sept-primary/Makefile | 168 - sept/sept-primary/linker.ld | 168 - sept/sept-primary/linker.specs | 7 - sept/sept-primary/src/apb_misc.h | 96 - sept/sept-primary/src/btn.c | 82 - sept/sept-primary/src/btn.h | 30 - sept/sept-primary/src/car.c | 142 - sept/sept-primary/src/car.h | 510 --- sept/sept-primary/src/di.h | 350 -- sept/sept-primary/src/fuse.c | 346 -- sept/sept-primary/src/fuse.h | 484 --- sept/sept-primary/src/gpio.c | 78 - sept/sept-primary/src/gpio.h | 127 - sept/sept-primary/src/i2c.c | 252 -- sept/sept-primary/src/i2c.h | 107 - sept/sept-primary/src/main.c | 257 -- sept/sept-primary/src/mc.c | 50 - sept/sept-primary/src/mc.h | 601 --- sept/sept-primary/src/panic.c | 93 - sept/sept-primary/src/panic.h | 34 - sept/sept-primary/src/pinmux.h | 211 - sept/sept-primary/src/pmc.h | 713 ---- sept/sept-primary/src/se.c | 649 --- sept/sept-primary/src/se.h | 210 - sept/sept-primary/src/start.s | 104 - sept/sept-primary/src/sysreg.h | 48 - sept/sept-primary/src/timers.h | 101 - sept/sept-primary/src/tsec.h | 307 -- sept/sept-primary/src/utils.c | 82 - sept/sept-primary/src/utils.h | 128 - sept/sept-secondary/KEYS_template.py | 38 - sept/sept-secondary/Makefile | 196 - sept/sept-secondary/key_derivation/Makefile | 158 - sept/sept-secondary/key_derivation/linker.ld | 17 - .../key_derivation/linker.specs | 7 - .../key_derivation/src/key_derivation.c | 155 - .../key_derivation/src/key_derivation.h | 26 - sept/sept-secondary/key_derivation/src/pmc.h | 713 ---- sept/sept-secondary/key_derivation/src/se.c | 757 ---- sept/sept-secondary/key_derivation/src/se.h | 216 - .../sept-secondary/key_derivation/src/start.s | 100 - .../sept-secondary/key_derivation/src/utils.c | 33 - .../sept-secondary/key_derivation/src/utils.h | 122 - sept/sept-secondary/linker.ld | 193 - sept/sept-secondary/linker.specs | 7 - sept/sept-secondary/sept_sign.py | 84 - sept/sept-secondary/src/apb_misc.h | 96 - sept/sept-secondary/src/btn.c | 82 - sept/sept-secondary/src/btn.h | 30 - sept/sept-secondary/src/car.c | 142 - sept/sept-secondary/src/car.h | 510 --- sept/sept-secondary/src/chainloader.c | 51 - sept/sept-secondary/src/chainloader.h | 42 - sept/sept-secondary/src/cluster.c | 178 - sept/sept-secondary/src/cluster.h | 23 - sept/sept-secondary/src/di.c | 465 --- sept/sept-secondary/src/di.h | 400 -- sept/sept-secondary/src/di.inl | 773 ---- sept/sept-secondary/src/emc.h | 1129 ------ sept/sept-secondary/src/exception_handlers.c | 118 - sept/sept-secondary/src/exception_handlers.h | 28 - .../src/exception_handlers_asm.s | 125 - sept/sept-secondary/src/flow.h | 31 - sept/sept-secondary/src/fs_utils.c | 138 - sept/sept-secondary/src/fs_utils.h | 35 - sept/sept-secondary/src/fuse.c | 346 -- sept/sept-secondary/src/fuse.h | 484 --- sept/sept-secondary/src/gpio.c | 78 - sept/sept-secondary/src/gpio.h | 127 - sept/sept-secondary/src/hwinit.c | 327 -- sept/sept-secondary/src/hwinit.h | 29 - sept/sept-secondary/src/i2c.c | 252 -- sept/sept-secondary/src/i2c.h | 107 - sept/sept-secondary/src/init.c | 91 - sept/sept-secondary/src/key_derivation.c | 82 - sept/sept-secondary/src/key_derivation.h | 27 - sept/sept-secondary/src/main.c | 187 - sept/sept-secondary/src/max77620.h | 357 -- sept/sept-secondary/src/max7762x.c | 178 - sept/sept-secondary/src/max7762x.h | 68 - sept/sept-secondary/src/max77812.h | 81 - sept/sept-secondary/src/mc.c | 169 - sept/sept-secondary/src/mc.h | 606 --- sept/sept-secondary/src/panic.c | 44 - sept/sept-secondary/src/panic.h | 33 - sept/sept-secondary/src/panic_color.h | 39 - sept/sept-secondary/src/pinmux.h | 211 - sept/sept-secondary/src/pmc.h | 713 ---- sept/sept-secondary/src/preprocessor.h | 207 - sept/sept-secondary/src/sdram.c | 1673 -------- sept/sept-secondary/src/sdram.h | 25 - sept/sept-secondary/src/sdram.inl | 3560 ----------------- sept/sept-secondary/src/sdram_lz.inl | 338 -- sept/sept-secondary/src/sdram_params.h | 1041 ----- sept/sept-secondary/src/se.c | 800 ---- sept/sept-secondary/src/se.h | 217 - sept/sept-secondary/src/splash.c | 61 - sept/sept-secondary/src/splash.h | 24 - sept/sept-secondary/src/stage2.c | 126 - sept/sept-secondary/src/stage2.h | 61 - sept/sept-secondary/src/start.s | 98 - sept/sept-secondary/src/sysctr0.h | 44 - sept/sept-secondary/src/sysreg.h | 48 - sept/sept-secondary/src/timers.h | 94 - sept/sept-secondary/src/uart.c | 135 - sept/sept-secondary/src/uart.h | 176 - sept/sept-secondary/src/utils.c | 129 - sept/sept-secondary/src/utils.h | 129 - .../source/amsmitm_initialization.cpp | 2 - troposphere/daybreak/nanovg/.gitignore | 3 +- 137 files changed, 149 insertions(+), 28364 deletions(-) create mode 100644 fusee/fusee-secondary/data/tsec_keygen.bin delete mode 100644 fusee/fusee-secondary/src/smmu.c delete mode 100644 fusee/fusee-secondary/src/smmu.h delete mode 100644 sept/Makefile delete mode 100644 sept/sept-primary/Makefile delete mode 100644 sept/sept-primary/linker.ld delete mode 100644 sept/sept-primary/linker.specs delete mode 100644 sept/sept-primary/src/apb_misc.h delete mode 100644 sept/sept-primary/src/btn.c delete mode 100644 sept/sept-primary/src/btn.h delete mode 100644 sept/sept-primary/src/car.c delete mode 100644 sept/sept-primary/src/car.h delete mode 100644 sept/sept-primary/src/di.h delete mode 100644 sept/sept-primary/src/fuse.c delete mode 100644 sept/sept-primary/src/fuse.h delete mode 100644 sept/sept-primary/src/gpio.c delete mode 100644 sept/sept-primary/src/gpio.h delete mode 100644 sept/sept-primary/src/i2c.c delete mode 100644 sept/sept-primary/src/i2c.h delete mode 100644 sept/sept-primary/src/main.c delete mode 100644 sept/sept-primary/src/mc.c delete mode 100644 sept/sept-primary/src/mc.h delete mode 100644 sept/sept-primary/src/panic.c delete mode 100644 sept/sept-primary/src/panic.h delete mode 100644 sept/sept-primary/src/pinmux.h delete mode 100644 sept/sept-primary/src/pmc.h delete mode 100644 sept/sept-primary/src/se.c delete mode 100644 sept/sept-primary/src/se.h delete mode 100644 sept/sept-primary/src/start.s delete mode 100644 sept/sept-primary/src/sysreg.h delete mode 100644 sept/sept-primary/src/timers.h delete mode 100644 sept/sept-primary/src/tsec.h delete mode 100644 sept/sept-primary/src/utils.c delete mode 100644 sept/sept-primary/src/utils.h delete mode 100644 sept/sept-secondary/KEYS_template.py delete mode 100644 sept/sept-secondary/Makefile delete mode 100644 sept/sept-secondary/key_derivation/Makefile delete mode 100644 sept/sept-secondary/key_derivation/linker.ld delete mode 100644 sept/sept-secondary/key_derivation/linker.specs delete mode 100644 sept/sept-secondary/key_derivation/src/key_derivation.c delete mode 100644 sept/sept-secondary/key_derivation/src/key_derivation.h delete mode 100644 sept/sept-secondary/key_derivation/src/pmc.h delete mode 100644 sept/sept-secondary/key_derivation/src/se.c delete mode 100644 sept/sept-secondary/key_derivation/src/se.h delete mode 100644 sept/sept-secondary/key_derivation/src/start.s delete mode 100644 sept/sept-secondary/key_derivation/src/utils.c delete mode 100644 sept/sept-secondary/key_derivation/src/utils.h delete mode 100644 sept/sept-secondary/linker.ld delete mode 100644 sept/sept-secondary/linker.specs delete mode 100644 sept/sept-secondary/sept_sign.py delete mode 100644 sept/sept-secondary/src/apb_misc.h delete mode 100644 sept/sept-secondary/src/btn.c delete mode 100644 sept/sept-secondary/src/btn.h delete mode 100644 sept/sept-secondary/src/car.c delete mode 100644 sept/sept-secondary/src/car.h delete mode 100644 sept/sept-secondary/src/chainloader.c delete mode 100644 sept/sept-secondary/src/chainloader.h delete mode 100644 sept/sept-secondary/src/cluster.c delete mode 100644 sept/sept-secondary/src/cluster.h delete mode 100644 sept/sept-secondary/src/di.c delete mode 100644 sept/sept-secondary/src/di.h delete mode 100644 sept/sept-secondary/src/di.inl delete mode 100644 sept/sept-secondary/src/emc.h delete mode 100644 sept/sept-secondary/src/exception_handlers.c delete mode 100644 sept/sept-secondary/src/exception_handlers.h delete mode 100644 sept/sept-secondary/src/exception_handlers_asm.s delete mode 100644 sept/sept-secondary/src/flow.h delete mode 100644 sept/sept-secondary/src/fs_utils.c delete mode 100644 sept/sept-secondary/src/fs_utils.h delete mode 100644 sept/sept-secondary/src/fuse.c delete mode 100644 sept/sept-secondary/src/fuse.h delete mode 100644 sept/sept-secondary/src/gpio.c delete mode 100644 sept/sept-secondary/src/gpio.h delete mode 100644 sept/sept-secondary/src/hwinit.c delete mode 100644 sept/sept-secondary/src/hwinit.h delete mode 100644 sept/sept-secondary/src/i2c.c delete mode 100644 sept/sept-secondary/src/i2c.h delete mode 100644 sept/sept-secondary/src/init.c delete mode 100644 sept/sept-secondary/src/key_derivation.c delete mode 100644 sept/sept-secondary/src/key_derivation.h delete mode 100644 sept/sept-secondary/src/main.c delete mode 100644 sept/sept-secondary/src/max77620.h delete mode 100644 sept/sept-secondary/src/max7762x.c delete mode 100644 sept/sept-secondary/src/max7762x.h delete mode 100644 sept/sept-secondary/src/max77812.h delete mode 100644 sept/sept-secondary/src/mc.c delete mode 100644 sept/sept-secondary/src/mc.h delete mode 100644 sept/sept-secondary/src/panic.c delete mode 100644 sept/sept-secondary/src/panic.h delete mode 100644 sept/sept-secondary/src/panic_color.h delete mode 100644 sept/sept-secondary/src/pinmux.h delete mode 100644 sept/sept-secondary/src/pmc.h delete mode 100644 sept/sept-secondary/src/preprocessor.h delete mode 100644 sept/sept-secondary/src/sdram.c delete mode 100644 sept/sept-secondary/src/sdram.h delete mode 100644 sept/sept-secondary/src/sdram.inl delete mode 100644 sept/sept-secondary/src/sdram_lz.inl delete mode 100644 sept/sept-secondary/src/sdram_params.h delete mode 100644 sept/sept-secondary/src/se.c delete mode 100644 sept/sept-secondary/src/se.h delete mode 100644 sept/sept-secondary/src/splash.c delete mode 100644 sept/sept-secondary/src/splash.h delete mode 100644 sept/sept-secondary/src/stage2.c delete mode 100644 sept/sept-secondary/src/stage2.h delete mode 100644 sept/sept-secondary/src/start.s delete mode 100644 sept/sept-secondary/src/sysctr0.h delete mode 100644 sept/sept-secondary/src/sysreg.h delete mode 100644 sept/sept-secondary/src/timers.h delete mode 100644 sept/sept-secondary/src/uart.c delete mode 100644 sept/sept-secondary/src/uart.h delete mode 100644 sept/sept-secondary/src/utils.c delete mode 100644 sept/sept-secondary/src/utils.h diff --git a/Makefile b/Makefile index 3921f75d7..7dec19499 100644 --- a/Makefile +++ b/Makefile @@ -32,10 +32,7 @@ mesosphere: exosphere libraries troposphere: stratosphere $(MAKE) -C troposphere all -sept: exosphere - $(MAKE) -C sept all - -fusee: exosphere mesosphere stratosphere sept +fusee: exosphere mesosphere stratosphere $(MAKE) -C $@ all libraries: @@ -61,7 +58,6 @@ dist-no-debug: all rm -rf out mkdir atmosphere-$(AMSVER) mkdir atmosphere-$(AMSVER)/atmosphere - mkdir atmosphere-$(AMSVER)/sept mkdir atmosphere-$(AMSVER)/switch mkdir -p atmosphere-$(AMSVER)/atmosphere/fatal_errors mkdir -p atmosphere-$(AMSVER)/atmosphere/config_templates @@ -71,13 +67,6 @@ dist-no-debug: all cp fusee/fusee-primary/fusee-primary.bin atmosphere-$(AMSVER)/atmosphere/reboot_payload.bin cp fusee/fusee-mtc/fusee-mtc.bin atmosphere-$(AMSVER)/atmosphere/fusee-mtc.bin cp fusee/fusee-secondary/fusee-secondary-experimental.bin atmosphere-$(AMSVER)/atmosphere/fusee-secondary.bin - cp fusee/fusee-secondary/fusee-secondary-experimental.bin atmosphere-$(AMSVER)/sept/payload.bin - cp sept/sept-primary/sept-primary.bin atmosphere-$(AMSVER)/sept/sept-primary.bin - cp sept/sept-secondary/sept-secondary.bin atmosphere-$(AMSVER)/sept/sept-secondary.bin - cp sept/sept-secondary/sept-secondary_00.enc atmosphere-$(AMSVER)/sept/sept-secondary_00.enc - cp sept/sept-secondary/sept-secondary_01.enc atmosphere-$(AMSVER)/sept/sept-secondary_01.enc - cp sept/sept-secondary/sept-secondary_dev_00.enc atmosphere-$(AMSVER)/sept/sept-secondary_dev_00.enc - cp sept/sept-secondary/sept-secondary_dev_01.enc atmosphere-$(AMSVER)/sept/sept-secondary_dev_01.enc cp config_templates/BCT.ini atmosphere-$(AMSVER)/atmosphere/config_templates/BCT.ini cp config_templates/override_config.ini atmosphere-$(AMSVER)/atmosphere/config_templates/override_config.ini cp config_templates/system_settings.ini atmosphere-$(AMSVER)/atmosphere/config_templates/system_settings.ini @@ -109,7 +98,6 @@ dist-no-debug: all cp troposphere/daybreak/daybreak.nro atmosphere-$(AMSVER)/switch/daybreak.nro cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER).zip ./*; cd ../; cp fusee/fusee-secondary/fusee-secondary.bin atmosphere-$(AMSVER)/atmosphere/fusee-secondary.bin - cp fusee/fusee-secondary/fusee-secondary.bin atmosphere-$(AMSVER)/sept/payload.bin cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip ./*; cd ../; rm -r atmosphere-$(AMSVER) mkdir out @@ -133,9 +121,6 @@ dist: dist-no-debug cp fusee/fusee-primary/fusee-primary.elf atmosphere-$(AMSVER)-debug/fusee-primary.elf cp fusee/fusee-mtc/fusee-mtc.elf atmosphere-$(AMSVER)-debug/fusee-mtc.elf cp fusee/fusee-secondary/fusee-secondary-experimental.elf atmosphere-$(AMSVER)-debug/fusee-secondary.elf - cp sept/sept-primary/sept-primary.elf atmosphere-$(AMSVER)-debug/sept-primary.elf - cp sept/sept-secondary/sept-secondary.elf atmosphere-$(AMSVER)-debug/sept-secondary.elf - cp sept/sept-secondary/key_derivation/key_derivation.elf atmosphere-$(AMSVER)-debug/sept-secondary-key-derivation.elf cp exosphere/loader_stub/loader_stub.elf atmosphere-$(AMSVER)-debug/exosphere-loader-stub.elf cp exosphere/program/program.elf atmosphere-$(AMSVER)-debug/exosphere-program.elf cp exosphere/warmboot/warmboot.elf atmosphere-$(AMSVER)-debug/exosphere-warmboot.elf diff --git a/exosphere/loader_stub/source/secmon_loader_main.cpp b/exosphere/loader_stub/source/secmon_loader_main.cpp index 70dc8555a..b05f7dd1c 100644 --- a/exosphere/loader_stub/source/secmon_loader_main.cpp +++ b/exosphere/loader_stub/source/secmon_loader_main.cpp @@ -20,13 +20,13 @@ namespace ams::secmon::loader { - NORETURN void UncompressAndExecute() { + NORETURN void UncompressAndExecute(const void *program, const void *boot_code) { /* Uncompress the program image. */ - Uncompress(secmon::MemoryRegionPhysicalTzramFullProgramImage.GetPointer(), secmon::MemoryRegionPhysicalTzramFullProgramImage.GetSize(), program_lz4, program_lz4_size); + Uncompress(secmon::MemoryRegionPhysicalTzramFullProgramImage.GetPointer(), secmon::MemoryRegionPhysicalTzramFullProgramImage.GetSize(), program, program_lz4_size); /* Copy the boot image to the end of IRAM */ u8 *relocated_boot_code = secmon::MemoryRegionPhysicalIramBootCodeImage.GetEndPointer() - boot_code_lz4_size; - std::memcpy(relocated_boot_code, boot_code_lz4, boot_code_lz4_size); + std::memcpy(relocated_boot_code, boot_code, boot_code_lz4_size); /* Uncompress the boot image. */ Uncompress(secmon::MemoryRegionPhysicalIramBootCodeImage.GetPointer(), secmon::MemoryRegionPhysicalIramBootCodeImage.GetSize(), relocated_boot_code, boot_code_lz4_size); diff --git a/exosphere/loader_stub/source/start.s b/exosphere/loader_stub/source/start.s index 7476605a7..415221f8f 100644 --- a/exosphere/loader_stub/source/start.s +++ b/exosphere/loader_stub/source/start.s @@ -98,8 +98,8 @@ _start: ldr x20, =0x7C020000 mov sp, x20 - /* Call our init array functions. */ - bl __libc_init_array + adr x0, program_lz4 + adr x1, boot_code_lz4 /* Uncompress the program and iram boot code images. */ - b _ZN3ams6secmon6loader20UncompressAndExecuteEv + b _ZN3ams6secmon6loader20UncompressAndExecuteEPKvS3_ diff --git a/fusee/common/fatfs/diskio.c b/fusee/common/fatfs/diskio.c index 4509e61f1..2bc445637 100644 --- a/fusee/common/fatfs/diskio.c +++ b/fusee/common/fatfs/diskio.c @@ -17,8 +17,6 @@ #include "../../../fusee/fusee-primary/fusee-primary-main/src/fs_utils.h" #elif defined(FUSEE_STAGE2_SRC) #include "../../../fusee/fusee-secondary/src/device_partition.h" -#elif defined(SEPT_STAGE2_SRC) -#include "../../../sept/sept-secondary/src/fs_utils.h" #endif #ifdef FUSEE_STAGE2_SRC diff --git a/fusee/common/sdmmc/sdmmc.c b/fusee/common/sdmmc/sdmmc.c index 2fb6bd320..65e5709af 100644 --- a/fusee/common/sdmmc/sdmmc.c +++ b/fusee/common/sdmmc/sdmmc.c @@ -30,8 +30,6 @@ #include "../../../fusee/fusee-primary/fusee-primary-main/src/timers.h" #elif defined(FUSEE_STAGE2_SRC) #include "../../../fusee/fusee-secondary/src/timers.h" -#elif defined(SEPT_STAGE2_SRC) -#include "../../../sept/sept-secondary/src/timers.h" #endif #define UNSTUFF_BITS(resp,start,size) \ @@ -102,7 +100,7 @@ static int sdmmc_device_send_r1_cmd(sdmmc_device_t *device, uint32_t opcode, uin if (resp_mask) { resp &= ~(resp_mask); } - + /* We got an error state. */ if (is_sdmmc_device_r1_error(resp)) { return 0; @@ -355,7 +353,7 @@ static int sdmmc_sd_decode_scr(sdmmc_device_t *device, uint8_t *scr) { if (device->scr.sda_spec3) { device->scr.cmds = UNSTUFF_BITS(resp, 32, 2); } - + /* Unknown SCR structure version. */ if (UNSTUFF_BITS(resp, 60, 4)) { return 0; @@ -465,7 +463,7 @@ static int sdmmc_sd_send_op_cond(sdmmc_device_t *device, bool is_sd_ver2, bool i if (is_uhs_en) { arg |= SD_OCR_S18R; } - + cmd.opcode = SD_APP_OP_COND; cmd.arg = arg; cmd.flags = SDMMC_RSP_R3; @@ -916,7 +914,7 @@ int sdmmc_device_sd_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth b if (!sdmmc_sd_decode_csd(device, csd)) { sdmmc_warn(sdmmc, "Got unknown CSD structure (0x%08x)!", device->csd.structure); } - + /* If we never switched to 1.8V, change the bus speed mode. */ if (!device->is_180v) { /* Reconfigure the internal clock. */ @@ -1155,7 +1153,7 @@ static int sdmmc_mmc_send_op_cond(sdmmc_device_t *device, SdmmcBusVoltage bus_vo if (resp & SD_OCR_CCS) { device->is_block_sdhc = true; } - + return 1; } @@ -1439,7 +1437,7 @@ int sdmmc_device_mmc_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth if (!sdmmc_mmc_decode_csd(device, csd)) { sdmmc_warn(sdmmc, "Got unknown CSD structure (0x%08x)!", device->csd.structure); } - + /* Reconfigure the internal clock. */ if (!sdmmc_select_speed(device->sdmmc, SDMMC_SPEED_MMC_LEGACY)) { sdmmc_error(sdmmc, "Failed to apply the correct bus speed!"); @@ -1498,7 +1496,7 @@ int sdmmc_device_mmc_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth } else { sdmmc_info(sdmmc, "BKOPS is disabled!"); } - + /* Switch to high speed mode. */ if (!sdmmc_mmc_select_timing(device, bus_speed)) { sdmmc_error(sdmmc, "Failed to switch to high speed mode!"); diff --git a/fusee/common/sdmmc/sdmmc_core.c b/fusee/common/sdmmc/sdmmc_core.c index d5dbf4337..5e002caaf 100644 --- a/fusee/common/sdmmc/sdmmc_core.c +++ b/fusee/common/sdmmc/sdmmc_core.c @@ -41,15 +41,6 @@ #include "../../../fusee/fusee-secondary/src/gpio.h" #include "../../../fusee/fusee-secondary/src/pmc.h" #include "../../../fusee/fusee-secondary/src/max7762x.h" -#elif defined(SEPT_STAGE2_SRC) -#include "../../../sept/sept-secondary/src/car.h" -#include "../../../sept/sept-secondary/src/fuse.h" -#include "../../../sept/sept-secondary/src/pinmux.h" -#include "../../../sept/sept-secondary/src/timers.h" -#include "../../../sept/sept-secondary/src/apb_misc.h" -#include "../../../sept/sept-secondary/src/gpio.h" -#include "../../../sept/sept-secondary/src/pmc.h" -#include "../../../sept/sept-secondary/src/max7762x.h" #endif #include "../log.h" diff --git a/fusee/fusee-primary/fusee-primary-main/src/hwinit.c b/fusee/fusee-primary/fusee-primary-main/src/hwinit.c index f51c23e67..40d94ae11 100644 --- a/fusee/fusee-primary/fusee-primary-main/src/hwinit.c +++ b/fusee/fusee-primary/fusee-primary-main/src/hwinit.c @@ -158,7 +158,12 @@ static void config_se_brom(void) { /* Bootrom part we skipped. */ uint32_t sbk[4] = {fuse_chip->FUSE_PRIVATE_KEY[0], fuse_chip->FUSE_PRIVATE_KEY[1], fuse_chip->FUSE_PRIVATE_KEY[2], fuse_chip->FUSE_PRIVATE_KEY[3]}; - set_aes_keyslot(0xE, sbk, 0x10); + for (int i = 0; i < 4; ++i) { + if (sbk[i] != 0xFFFFFFFF) { + set_aes_keyslot(0xE, sbk, 0x10); + break; + } + } /* Lock SBK from being read. */ se->SE_CRYPTO_KEYTABLE_ACCESS[0xE] = 0x7E; @@ -247,7 +252,7 @@ void nx_hwinit(bool enable_log) { } else { uint8_t val = 0x40; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1); - val = 0x60; + val = 0x58; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1); val = 0x38; i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG0, &val, 1); diff --git a/fusee/fusee-secondary/Makefile b/fusee/fusee-secondary/Makefile index 818644d4a..4d55a11a5 100644 --- a/fusee/fusee-secondary/Makefile +++ b/fusee/fusee-secondary/Makefile @@ -92,8 +92,8 @@ export KIPDIRS := $(AMS)/stratosphere/loader $(AMS)/stratosphere/ncm $(AMS)/stra export VPATH := $(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \ $(foreach dir,$(DATA),$(CURDIR)/$(dir)) \ $(AMS)/exosphere $(AMS)/exosphere/warmboot $(AMS)/exosphere/program/rebootstub \ - $(AMS)/thermosphere $(AMS)/fusee/fusee-primary $(AMS)/sept/sept-primary \ - $(AMS)/sept/sept-secondary $(AMS)/emummc $(AMS)/mesosphere $(AMS)/mesosphere/kernel_ldr $(KIPDIRS) + $(AMS)/thermosphere $(AMS)/fusee/fusee-primary $(AMS)/emummc $(AMS)/mesosphere \ + $(KIPDIRS) export DEPSDIR := $(CURDIR)/$(BUILD) @@ -103,9 +103,7 @@ SFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s))) KIPFILES := loader.kip ncm.kip pm.kip sm.kip ams_mitm.kip spl.kip boot.kip BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) fusee-primary.bin \ exosphere.bin warmboot.bin rebootstub.bin thermosphere.bin splash_screen.bin \ - sept-primary.bin sept-secondary_00.enc sept-secondary_01.enc emummc.kip \ - sept-secondary_dev_00.enc sept-secondary_dev_01.enc mesosphere.bin kernel_ldr.bin \ - mariko_fatal.bin $(KIPFILES) + emummc.kip mesosphere.bin mariko_fatal.bin $(KIPFILES) #--------------------------------------------------------------------------------- # use CXX for linking C++ projects, CC for standard C @@ -133,7 +131,7 @@ export INCLUDE := $(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \ export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib) .PHONY: $(BUILD) clean all -.PHONY: check_fusee_primary check_exosphere check_sept check_emummc check_thermosphere check_stratosphere check_libraries +.PHONY: check_fusee_primary check_exosphere check_emummc check_thermosphere check_stratosphere check_libraries #--------------------------------------------------------------------------------- all: $(BUILD) @@ -144,9 +142,6 @@ check_fusee_primary: check_exosphere: @$(MAKE) -C $(AMS)/exosphere all -check_sept: - @$(MAKE) -C $(AMS)/sept all - check_emummc: @$(MAKE) -C $(AMS)/emummc EMUMMCDIR=$(AMS)/emummc all @@ -163,7 +158,7 @@ check_libraries: @$(MAKE) -C $(AMS)/libraries all -$(BUILD): check_fusee_primary check_exosphere check_sept check_emummc check_thermosphere check_libraries check_stratosphere check_mesosphere +$(BUILD): check_fusee_primary check_exosphere check_emummc check_thermosphere check_libraries check_stratosphere check_mesosphere @[ -d $@ ] || mkdir -p $@ @$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile @@ -176,7 +171,6 @@ clean: @$(MAKE) -C $(AMS)/libraries clean @$(MAKE) -C $(AMS)/mesosphere clean @$(MAKE) -C $(AMS)/stratosphere clean - @$(MAKE) -C $(AMS)/sept clean @$(MAKE) -C $(AMS)/emummc clean @rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf @@ -216,31 +210,6 @@ fusee_primary.bin.o fusee_primary_bin.h: fusee-primary.bin @echo $(notdir $<) @$(_bin2o) -sept_primary.bin.o sept_primary_bin.h: sept-primary.bin -#--------------------------------------------------------------------------------- - @echo $(notdir $<) - @$(_bin2o) - -sept_secondary_00.enc.o sept_secondary_00_enc.h: sept-secondary_00.enc -#--------------------------------------------------------------------------------- - @echo $(notdir $<) - @$(_bin2o) - -sept_secondary_01.enc.o sept_secondary_01_enc.h: sept-secondary_01.enc -#--------------------------------------------------------------------------------- - @echo $(notdir $<) - @$(_bin2o) - -sept_secondary_dev_00.enc.o sept_secondary_dev_00_enc.h: sept-secondary_dev_00.enc -#--------------------------------------------------------------------------------- - @echo $(notdir $<) - @$(_bin2o) - -sept_secondary_dev_01.enc.o sept_secondary_dev_01_enc.h: sept-secondary_dev_01.enc -#--------------------------------------------------------------------------------- - @echo $(notdir $<) - @$(_bin2o) - %.bin.o %_bin.h: %.bin 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z^X)J1ct}AgU}alp$*1@aF4Gi;)$KO1bqzW$q#NDuUnWnIs;L7$)VKY@Kzw&P1jgYb7Q@+QPQg6=ibXD&xD)hngE zU5vz!giAsuR+n2YA-eKE#^C27tD>lcYt$#z@Nnrf5#pl@8hF`sbM$a31mh~DNquA+ z@3Y!fNZ88vuEa&D8ED}=j7kx3YsQet_TjXQaqk%cPF4roTxT^j-SH6zn^V~;U~6>t z2iZ$%&o#PKxP_c;ntBjc2##fF$}rFEPwN-Z3S1eq&0*Q@@vqgaAVOxhx^}BzWsZGi z7K#?u_SOZ@$|~e8hTg#AFvv_AG=@jU`CoA^t`L8*Hj#@r@F_0AqW|UF14Ju2Ryc-I ez*. */ - + #ifndef FUSEE_CAR_H #define FUSEE_CAR_H @@ -51,7 +51,7 @@ typedef enum { CARDEVICE_USB2 = ((1 << 5) | 0x1A), CARDEVICE_CORESIGHT = ((2 << 5) | 0x9), CARDEVICE_TSEC = ((2 << 5) | 0x13), - CARDEVICE_MSELECT = ((3 << 5) | 0x8), + CARDEVICE_MSELECT = ((3 << 5) | 0x3), CARDEVICE_ACTMON = ((3 << 5) | 0x17), CARDEVICE_TZRAM = ((3 << 5) | 0x1E), CARDEVICE_SE = ((3 << 5) | 0x1F), @@ -489,7 +489,7 @@ typedef struct { uint32_t sdmmc4_pllc4_out0_shaper_ctrl; /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */ uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */ uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */ - uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */ + uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */ } tegra_car_t; static inline volatile tegra_car_t *car_get_regs(void) { diff --git a/fusee/fusee-secondary/src/kernel_patches.c b/fusee/fusee-secondary/src/kernel_patches.c index 56fbe0882..dbaf9e090 100644 --- a/fusee/fusee-secondary/src/kernel_patches.c +++ b/fusee/fusee-secondary/src/kernel_patches.c @@ -21,12 +21,6 @@ #include "kernel_patches.h" #include "ips.h" -#define u8 uint8_t -#define u32 uint32_t -#include "kernel_ldr_bin.h" -#undef u8 -#undef u32 - #define MAKE_BRANCH(a, o) 0x14000000 | ((((o) - (a)) >> 2) & 0x3FFFFFF) #define MAKE_NOP 0xD503201F diff --git a/fusee/fusee-secondary/src/key_derivation.c b/fusee/fusee-secondary/src/key_derivation.c index e5700f14e..8f81fd1c0 100644 --- a/fusee/fusee-secondary/src/key_derivation.c +++ b/fusee/fusee-secondary/src/key_derivation.c @@ -26,19 +26,6 @@ #define AL16 ALIGN(16) -static const uint8_t AL16 keyblob_seeds[MASTERKEY_REVISION_MAX][0x10] = { - {0xDF, 0x20, 0x6F, 0x59, 0x44, 0x54, 0xEF, 0xDC, 0x70, 0x74, 0x48, 0x3B, 0x0D, 0xED, 0x9F, 0xD3}, /* Keyblob seed 00. */ - {0x0C, 0x25, 0x61, 0x5D, 0x68, 0x4C, 0xEB, 0x42, 0x1C, 0x23, 0x79, 0xEA, 0x82, 0x25, 0x12, 0xAC}, /* Keyblob seed 01. */ - {0x33, 0x76, 0x85, 0xEE, 0x88, 0x4A, 0xAE, 0x0A, 0xC2, 0x8A, 0xFD, 0x7D, 0x63, 0xC0, 0x43, 0x3B}, /* Keyblob seed 02. */ - {0x2D, 0x1F, 0x48, 0x80, 0xED, 0xEC, 0xED, 0x3E, 0x3C, 0xF2, 0x48, 0xB5, 0x65, 0x7D, 0xF7, 0xBE}, /* Keyblob seed 03. */ - {0xBB, 0x5A, 0x01, 0xF9, 0x88, 0xAF, 0xF5, 0xFC, 0x6C, 0xFF, 0x07, 0x9E, 0x13, 0x3C, 0x39, 0x80}, /* Keyblob seed 04. */ - {0xD8, 0xCC, 0xE1, 0x26, 0x6A, 0x35, 0x3F, 0xCC, 0x20, 0xF3, 0x2D, 0x3B, 0x51, 0x7D, 0xE9, 0xC0} /* Keyblob seed 05. */ -}; - -static const uint8_t AL16 keyblob_mac_seed[0x10] = { - 0x59, 0xC7, 0xFB, 0x6F, 0xBE, 0x9B, 0xBE, 0x87, 0x65, 0x6B, 0x15, 0xC0, 0x53, 0x73, 0x36, 0xA5 -}; - static const uint8_t AL16 masterkey_seed[0x10] = { 0xD8, 0xA2, 0x41, 0x0A, 0xC6, 0xC5, 0x90, 0x01, 0xC6, 0x1D, 0x6A, 0x26, 0x7C, 0x51, 0x3F, 0x3C }; @@ -55,164 +42,51 @@ static const uint8_t AL16 masterkey_4x_seed[0x10] = { 0x2D, 0xC1, 0xF4, 0x8D, 0xF3, 0x5B, 0x69, 0x33, 0x42, 0x10, 0xAC, 0x65, 0xDA, 0x90, 0x46, 0x66 }; -/* TODO: Bother adding 8.1.0 here? We'll never call into here... */ -static const uint8_t AL16 new_master_kek_seeds[MASTERKEY_REVISION_700_800 - MASTERKEY_REVISION_600_610][0x10] = { - {0x37, 0x4B, 0x77, 0x29, 0x59, 0xB4, 0x04, 0x30, 0x81, 0xF6, 0xE5, 0x8C, 0x6D, 0x36, 0x17, 0x9A}, /* MasterKek seed 06. */ - {0x9A, 0x3E, 0xA9, 0xAB, 0xFD, 0x56, 0x46, 0x1C, 0x9B, 0xF6, 0x48, 0x7F, 0x5C, 0xFA, 0x09, 0x5C}, /* MasterKek seed 07. */ +static const uint8_t AL16 keyblob_seed_00[0x10] = { + 0xDF, 0x20, 0x6F, 0x59, 0x44, 0x54, 0xEF, 0xDC, 0x70, 0x74, 0x48, 0x3B, 0x0D, 0xED, 0x9F, 0xD3 +}; + +static const uint8_t AL16 master_kek_seed_erista[0x10] = { /* TODO: Update on next change of keys. */ + 0x84, 0x67, 0xB6, 0x7F, 0x13, 0x11, 0xAE, 0xE6, 0x58, 0x9B, 0x19, 0xAF, 0x13, 0x6C, 0x80, 0x7A /* Erista MasterKek seed 0B. */ +}; + +static const uint8_t AL16 master_devkey_seed_erista[0x10] = { + 0xAA, 0xFD, 0xBC, 0xBB, 0x25, 0xC3, 0xA4, 0xEF, 0xE3, 0xEE, 0x58, 0x53, 0xB7, 0xF8, 0xDD, 0xD6 }; static const uint8_t AL16 master_kek_seed_mariko[0x10] = { /* TODO: Update on next change of keys. */ 0xE5, 0x41, 0xAC, 0xEC, 0xD1, 0xA7, 0xD1, 0xAB, 0xED, 0x03, 0x77, 0xF1, 0x27, 0xCA, 0xF8, 0xF1, /* Mariko MasterKek seed 0B. */ }; -static nx_dec_keyblob_t AL16 g_dec_keyblobs[32]; - -static int get_keyblob(nx_keyblob_t *dst, uint32_t revision, const nx_keyblob_t *keyblobs, uint32_t available_revision) { - if (revision >= 0x20) { - return -1; - /* TODO: what should we do? */ - } - - if (keyblobs != NULL) { - *dst = keyblobs[revision]; - } else { - return -1; - /* TODO: what should we do? */ - } - - return 0; -} - -static bool safe_memcmp(uint8_t *a, uint8_t *b, size_t sz) { - uint8_t different = 0; - for (unsigned int i = 0; i < sz; i++) { - different |= a[i] ^ b[i]; - } - return different != 0; -} - -static int decrypt_keyblob(const nx_keyblob_t *keyblobs, uint32_t revision, uint32_t available_revision) { - nx_keyblob_t AL16 keyblob; - uint8_t AL16 work_buffer[0x10]; - unsigned int keyslot = revision == MASTERKEY_REVISION_100_230 ? 0xF : KEYSLOT_SWITCH_TEMPKEY; - - if (get_keyblob(&keyblob, revision, keyblobs, available_revision) != 0) { - return -1; - } - - se_aes_ecb_decrypt_block(0xD, work_buffer, 0x10, keyblob_seeds[revision], 0x10); - decrypt_data_into_keyslot(keyslot, 0xE, work_buffer, 0x10); - decrypt_data_into_keyslot(0xB, keyslot, keyblob_mac_seed, 0x10); - - /* Validate keyblob. */ - se_compute_aes_128_cmac(0xB, work_buffer, 0x10, keyblob.mac + sizeof(keyblob.mac), sizeof(keyblob) - sizeof(keyblob.mac)); - if (safe_memcmp(keyblob.mac, work_buffer, 0x10)) { - return -1; - } - - /* Decrypt keyblob. */ - se_aes_ctr_crypt(keyslot, &g_dec_keyblobs[revision], sizeof(g_dec_keyblobs[revision]), keyblob.data, sizeof(keyblob.data), keyblob.ctr, sizeof(keyblob.ctr)); - return 0; -} - -int load_package1_key(uint32_t revision) { - if (revision > MASTERKEY_REVISION_600_610) { - return -1; - } - - set_aes_keyslot(0xB, g_dec_keyblobs[revision].package1_key, 0x10); - return 0; -} - /* Derive all Switch keys. */ -int derive_nx_keydata_erista(uint32_t target_firmware, const nx_keyblob_t *keyblobs, uint32_t available_revision, const void *tsec_key, void *tsec_root_keys, unsigned int *out_keygen_type) { +int derive_nx_keydata_erista(uint32_t target_firmware) { uint8_t AL16 work_buffer[0x10]; - uint8_t AL16 zeroes[0x10] = {0}; - /* Initialize keygen type. */ - *out_keygen_type = 0; + /* Get whether we're using dev keys. */ + const bool is_retail = fuse_get_hardware_state() != 0; - /* TODO: Set keyslot flags properly in preparation of derivation. */ - set_aes_keyslot_flags(0xE, 0x15); - set_aes_keyslot_flags(0xD, 0x15); + /* Derive Keyblob Key 00. */ + se_aes_ecb_decrypt_block(0xC, work_buffer, 0x10, keyblob_seed_00, 0x10); + decrypt_data_into_keyslot(0xF, 0xE, work_buffer, 0x10); - /* Set the TSEC key. */ - set_aes_keyslot(0xD, tsec_key, 0x10); + /* Derive master kek. */ + decrypt_data_into_keyslot(0xE, is_retail ? 0xD : 0xB, master_kek_seed_erista, 0x10); - /* Decrypt all keyblobs, setting keyslot 0xF correctly. */ - for (unsigned int rev = 0; rev <= MASTERKEY_REVISION_600_610; rev++) { - int ret = decrypt_keyblob(keyblobs, rev, available_revision); - if (ret) { - return ret; - } - } + /* Derive master key, device master key. */ + decrypt_data_into_keyslot(0xD, 0xE, masterkey_seed, 0x10); + decrypt_data_into_keyslot(0xE, 0xE, masterkey_4x_seed, 0x10); - /* Do 6.2.0+ keygen. */ - if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_6_2_0) { - uint32_t desired_keyblob; - - if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_8_1_0) { - /* NOTE: We load in the current key for all >= 8.1.0 firmwares to reduce sept binaries. */ - desired_keyblob = MASTERKEY_REVISION_C10_CURRENT; - } else if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_7_0_0) { - desired_keyblob = MASTERKEY_REVISION_700_800; - } else { - desired_keyblob = MASTERKEY_REVISION_620; - } - - /* Try emulation result. */ - for (unsigned int rev = MASTERKEY_REVISION_620; rev < MASTERKEY_REVISION_MAX; rev++) { - void *tsec_root_key = (void *)((uintptr_t)tsec_root_keys + 0x10 * (rev - MASTERKEY_REVISION_620)); - if (memcmp(tsec_root_key, zeroes, 0x10) != 0) { - /* We got a valid key from emulation. */ - set_aes_keyslot(0xD, tsec_root_key, 0x10); - se_aes_ecb_decrypt_block(0xD, work_buffer, 0x10, new_master_kek_seeds[rev - MASTERKEY_REVISION_620], 0x10); - memcpy(g_dec_keyblobs[rev].master_kek, work_buffer, 0x10); - } - } - - if (memcmp(g_dec_keyblobs[desired_keyblob].master_kek, zeroes, 0x10) == 0) { - /* Try reading the keys from a file. */ - const char *keyfile = fuse_get_hardware_state() != 0 ? "atmosphere/prod.keys" : "atmosphere/dev.keys"; - FILE *extkey_file = fopen(keyfile, "r"); - AL16 fusee_extkeys_t extkeys = {0}; - if (extkey_file == NULL) { - fatal_error("Error: failed to read %s, needed for 6.2.0+ key derivation!", keyfile); - } - extkeys_initialize_keyset(&extkeys, extkey_file); - fclose(extkey_file); - for (unsigned int rev = MASTERKEY_REVISION_620; rev < MASTERKEY_REVISION_MAX; rev++) { - if (memcmp(extkeys.tsec_root_keys[rev - MASTERKEY_REVISION_620], zeroes, 0x10) != 0) { - set_aes_keyslot(0xD, extkeys.tsec_root_keys[rev - MASTERKEY_REVISION_620], 0x10); - se_aes_ecb_decrypt_block(0xD, work_buffer, 0x10, new_master_kek_seeds[rev - MASTERKEY_REVISION_620], 0x10); - memcpy(g_dec_keyblobs[rev].master_kek, work_buffer, 0x10); - } else { - memcpy(g_dec_keyblobs[rev].master_kek, extkeys.master_keks[rev], 0x10); - } - } - } - - if (memcmp(g_dec_keyblobs[available_revision].master_kek, zeroes, 0x10) == 0) { - fatal_error("Error: failed to derive master_kek_%02x!", available_revision); - } - } - - /* Clear the SBK. */ - clear_aes_keyslot(0xE); - - /* Get needed data. */ - set_aes_keyslot(0xD, g_dec_keyblobs[available_revision].master_kek, 0x10); - - /* Also set the Package1 key for the revision that is stored on the eMMC boot0 partition. */ - if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_6_2_0) { - load_package1_key(available_revision); - } - - /* Derive keys for Exosphere, lock critical keyslots. */ + /* Derive device keys. */ decrypt_data_into_keyslot(0xA, 0xF, devicekey_4x_seed, 0x10); - decrypt_data_into_keyslot(0xF, 0xF, devicekey_seed, 0x10); - decrypt_data_into_keyslot(0xC, 0xD, masterkey_4x_seed, 0x10); - decrypt_data_into_keyslot(0xD, 0xD, masterkey_seed, 0x10); + decrypt_data_into_keyslot(0xF, 0xF, devicekey_seed, 0x10); + + /* Derive firmware specific device key. */ + se_aes_ecb_decrypt_block(0xA, work_buffer, 0x10, master_devkey_seed_erista, 0x10); + decrypt_data_into_keyslot(0xC, 0xE, work_buffer, 0x10); + + /* Clear keyslots 0xB/0xE. */ + clear_aes_keyslot(0xB); + clear_aes_keyslot(0xE); /* Setup master key revision, derive older master keys for use. */ return mkey_detect_revision(fuse_get_hardware_state() != 0); diff --git a/fusee/fusee-secondary/src/key_derivation.h b/fusee/fusee-secondary/src/key_derivation.h index e2b0c0f8e..6eb41115f 100644 --- a/fusee/fusee-secondary/src/key_derivation.h +++ b/fusee/fusee-secondary/src/key_derivation.h @@ -27,29 +27,8 @@ typedef enum BisPartition { BisPartition_UserSystem = 2, } BisPartition; -typedef struct { - union { - uint8_t keys[9][0x10]; - struct { - uint8_t master_kek[0x10]; - uint8_t _keys[7][0x10]; - uint8_t package1_key[0x10]; - }; - }; -} nx_dec_keyblob_t; - -typedef struct nx_keyblob_t { - uint8_t mac[0x10]; - uint8_t ctr[0x10]; - union { - uint8_t data[0x90]; - nx_dec_keyblob_t dec_blob; - }; -} nx_keyblob_t; - -int derive_nx_keydata_erista(uint32_t target_firmware, const nx_keyblob_t *keyblobs, uint32_t available_revision, const void *tsec_key, void *tsec_root_key, unsigned int *out_keygen_type); +int derive_nx_keydata_erista(uint32_t target_firmware); int derive_nx_keydata_mariko(uint32_t target_firmware); -int load_package1_key(uint32_t revision); void derive_bis_key(void *dst, BisPartition partition_id, uint32_t target_firmware); #endif diff --git a/fusee/fusee-secondary/src/masterkey.c b/fusee/fusee-secondary/src/masterkey.c index 2063484f2..c5d9db64d 100644 --- a/fusee/fusee-secondary/src/masterkey.c +++ b/fusee/fusee-secondary/src/masterkey.c @@ -185,8 +185,8 @@ void derive_new_device_keys(bool is_retail, unsigned int keygen_keyslot, unsigne if (relative_revision > mkey_get_revision()) { break; } else if (relative_revision == mkey_get_revision()) { - /* On 7.0.0 erista, sept will have derived this key for us already. */ - if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0 || is_mariko) { + /* On Erista, this will already be derived. */ + if (is_mariko) { decrypt_data_into_keyslot(is_mariko ? KEYSLOT_SWITCH_DEVICEKEY_MARIKO : KEYSLOT_SWITCH_DEVICEKEY, KEYSLOT_SWITCH_TEMPKEY, work_buffer, 0x10); } } else { diff --git a/fusee/fusee-secondary/src/nxboot.c b/fusee/fusee-secondary/src/nxboot.c index 314582f89..274af3bf1 100644 --- a/fusee/fusee-secondary/src/nxboot.c +++ b/fusee/fusee-secondary/src/nxboot.c @@ -44,7 +44,6 @@ #include "masterkey.h" #include "package1.h" #include "package2.h" -#include "smmu.h" #include "tsec.h" #include "lp0.h" #include "loader.h" @@ -59,11 +58,8 @@ #include "exosphere_bin.h" #include "mariko_fatal_bin.h" #include "mesosphere_bin.h" -#include "sept_secondary_00_enc.h" -#include "sept_secondary_01_enc.h" -#include "sept_secondary_dev_00_enc.h" -#include "sept_secondary_dev_01_enc.h" #include "warmboot_bin.h" +#include "tsec_keygen_bin.h" #include "emummc_kip.h" #undef u8 #undef u32 @@ -724,18 +720,11 @@ static void nxboot_move_bootconfig() { free(bootconfig); } -static bool get_and_clear_has_run_sept(void) { - bool has_run_sept = (MAKE_EMC_REG(EMC_SCRATCH0) & 0x80000000) != 0; - MAKE_EMC_REG(EMC_SCRATCH0) &= ~0x80000000; - return has_run_sept; -} - static void get_mariko_warmboot_path(char *dst, size_t dst_size, uint32_t version) { snprintf(dst, dst_size, "warmboot_mariko/wb_%02" PRIx32 ".bin", version); } /* This is the main function responsible for booting Horizon. */ -static nx_keyblob_t __attribute__((aligned(16))) g_keyblobs[32]; uint32_t nxboot_main(void) { volatile tegra_pmc_t *pmc = pmc_get_regs(); loader_ctx_t *loader_ctx = get_loader_ctx(); @@ -745,8 +734,6 @@ uint32_t nxboot_main(void) { size_t package2_size; void *tsec_fw; size_t tsec_fw_size; - const void *sept_secondary_enc = NULL; - size_t sept_secondary_enc_size = 0; void *warmboot_fw; size_t warmboot_fw_size; void *warmboot_memaddr; @@ -756,7 +743,6 @@ uint32_t nxboot_main(void) { size_t mesosphere_size; void *emummc; size_t emummc_size; - uint32_t available_revision; FILE *boot0, *pk2file; void *exosphere_memaddr; exo_emummc_config_t exo_emummc_cfg; @@ -844,7 +830,7 @@ uint32_t nxboot_main(void) { fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno)); } } else { - if (package1_read_and_parse_boot0_erista(&package1loader, &package1loader_size, g_keyblobs, &available_revision, boot0) == -1) { + if (package1_read_and_parse_boot0_erista(&package1loader, &package1loader_size, boot0) == -1) { fatal_error("[NXBOOT] Couldn't parse boot0: %s!\n", strerror(errno)); } } @@ -860,103 +846,26 @@ uint32_t nxboot_main(void) { } /* Handle TSEC and Sept (Erista only). */ - uint8_t tsec_key[0x10] = {0}; - uint8_t tsec_root_keys[0x20][0x10] = {0}; if (!is_mariko) { - /* Read the TSEC firmware from a file, otherwise from PK1L. */ - if (loader_ctx->tsecfw_path[0] != '\0') { - tsec_fw_size = get_file_size(loader_ctx->tsecfw_path); - if ((tsec_fw_size != 0) && (tsec_fw_size != 0xF00 && tsec_fw_size != 0x2900 && tsec_fw_size != 0x3000 && tsec_fw_size != 0x3300)) { - fatal_error("[NXBOOT] TSEC firmware from %s has a wrong size!\n", loader_ctx->tsecfw_path); - } else if (tsec_fw_size == 0) { - fatal_error("[NXBOOT] Could not read the TSEC firmware from %s!\n", loader_ctx->tsecfw_path); - } + /* Use Atmosphere's tsec_keygen implementation. */ + tsec_fw_size = tsec_keygen_bin_size; + tsec_fw = memalign(0x100, tsec_fw_size); - /* Allocate memory for the TSEC firmware. */ - tsec_fw = memalign(0x100, tsec_fw_size); - - if (tsec_fw == NULL) { - fatal_error("[NXBOOT] Out of memory!\n"); - } - if (read_from_file(tsec_fw, tsec_fw_size, loader_ctx->tsecfw_path) != tsec_fw_size) { - fatal_error("[NXBOOT] Could not read the TSEC firmware from %s!\n", loader_ctx->tsecfw_path); - } - - if (tsec_fw_size == 0x3000) { - if (fuse_get_hardware_state() != 0) { - sept_secondary_enc = sept_secondary_00_enc; - sept_secondary_enc_size = sept_secondary_00_enc_size; - } else { - sept_secondary_enc = sept_secondary_dev_00_enc; - sept_secondary_enc_size = sept_secondary_dev_00_enc_size; - } - } else if (tsec_fw_size == 0x3300) { - if (fuse_get_hardware_state() != 0) { - sept_secondary_enc = sept_secondary_01_enc; - sept_secondary_enc_size = sept_secondary_01_enc_size; - } else { - sept_secondary_enc = sept_secondary_dev_01_enc; - sept_secondary_enc_size = sept_secondary_dev_01_enc_size; - } - } else { - fatal_error("[NXBOOT] Unable to identify sept revision to run."); - } - } else { - if (!package1_get_tsec_fw(&tsec_fw, package1loader, package1loader_size)) { - fatal_error("[NXBOOT] Failed to read the TSEC firmware from Package1loader!\n"); - } - if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_8_1_0) { - if (fuse_get_hardware_state() != 0) { - sept_secondary_enc = sept_secondary_01_enc; - sept_secondary_enc_size = sept_secondary_01_enc_size; - } else { - sept_secondary_enc = sept_secondary_dev_01_enc; - sept_secondary_enc_size = sept_secondary_dev_01_enc_size; - } - tsec_fw_size = 0x3300; - } else if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_7_0_0) { - if (fuse_get_hardware_state() != 0) { - sept_secondary_enc = sept_secondary_00_enc; - sept_secondary_enc_size = sept_secondary_00_enc_size; - } else { - sept_secondary_enc = sept_secondary_dev_00_enc; - sept_secondary_enc_size = sept_secondary_dev_00_enc_size; - } - tsec_fw_size = 0x3000; - } else if (target_firmware == ATMOSPHERE_TARGET_FIRMWARE_6_2_0) { - tsec_fw_size = 0x2900; - } else { - tsec_fw_size = 0xF00; - } + if (tsec_fw == NULL) { + fatal_error("[NXBOOT] Out of memory!\n"); } - print(SCREEN_LOG_LEVEL_INFO, "[NXBOOT] Loaded firmware from eMMC...\n"); + memcpy(tsec_fw, tsec_keygen_bin, tsec_fw_size); - /* Get the TSEC keys. */ - if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_7_0_0) { - /* Detect whether we need to run sept-secondary in order to derive keys. */ - if (!get_and_clear_has_run_sept()) { - reboot_to_sept(tsec_fw, tsec_fw_size, sept_secondary_enc, sept_secondary_enc_size); - } else { - if (mkey_detect_revision(fuse_get_hardware_state() != 0) != 0) { - fatal_error("[NXBOOT] Sept derived incorrect keys!\n"); - } - } - get_and_clear_has_run_sept(); - } else if (target_firmware == ATMOSPHERE_TARGET_FIRMWARE_6_2_0) { - uint8_t tsec_keys[0x20] = {0}; + if (tsec_fw_size == 0) { + fatal_error("[NXBOOT] Could not read the warmboot firmware from Package1!\n"); + } - /* Emulate the TSEC payload on 6.2.0+. */ - smmu_emulate_tsec((void *)tsec_keys, package1loader, package1loader_size, package1loader); - - /* Copy back the keys. */ - memcpy((void *)tsec_key, (void *)tsec_keys, 0x10); - memcpy((void *)tsec_root_keys, (void *)tsec_keys + 0x10, 0x10); - } else { - /* Run the TSEC payload and get the key. */ - if (tsec_get_key(tsec_key, 1, tsec_fw, tsec_fw_size) != 0) { - fatal_error("[NXBOOT] Failed to get TSEC key!\n"); - } + /* Get the TSEC keys into the security engine. */ + int tsec_res = tsec_run_fw(tsec_fw, tsec_fw_size); + if (tsec_res != 0) { + volatile tegra_tsec_t *tsec = tsec_get_regs(); + fatal_error("[NXBOOT] Failed to run TSEC firmware %d %08x %08x!\n", tsec_res, tsec->TSEC_FALCON_MAILBOX0, tsec->TSEC_FALCON_MAILBOX1); } } @@ -969,8 +878,8 @@ uint32_t nxboot_main(void) { if (derive_nx_keydata_mariko(target_firmware) != 0) { fatal_error("[NXBOOT] Mariko key derivation failed!\n"); } - } else if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) { /* If on 7.0.0+, sept has already derived keys for us (Erista only). */ - if (derive_nx_keydata_erista(target_firmware, g_keyblobs, available_revision, tsec_key, tsec_root_keys, &keygen_type) != 0) { + } else { + if (derive_nx_keydata_erista(target_firmware) != 0) { fatal_error("[NXBOOT] Erista key derivation failed!\n"); } } @@ -1230,9 +1139,6 @@ uint32_t nxboot_main(void) { /* Clean up. */ free(package1loader); - if (loader_ctx->tsecfw_path[0] != '\0') { - free(tsec_fw); - } if (loader_ctx->warmboot_path[0] != '\0') { free(warmboot_fw); } diff --git a/fusee/fusee-secondary/src/nxboot_iram.c b/fusee/fusee-secondary/src/nxboot_iram.c index 51b7b07c6..1e711b8fc 100644 --- a/fusee/fusee-secondary/src/nxboot_iram.c +++ b/fusee/fusee-secondary/src/nxboot_iram.c @@ -24,18 +24,10 @@ #include "mc.h" #include "nxboot.h" #include "se.h" -#include "smmu.h" #include "timers.h" #include "sysreg.h" -/* Determine the current SoC for Mariko specific code. */ -static bool is_soc_mariko() { - return (fuse_get_soc_type() == 1); -} - void nxboot_finish(uint32_t boot_memaddr) { - bool is_mariko = is_soc_mariko(); - /* Boot up Exosphère. */ MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE = 0; MAILBOX_NX_BOOTLOADER_SETUP_STATE = NX_BOOTLOADER_STATE_DRAM_INITIALIZED_4X; @@ -43,26 +35,8 @@ void nxboot_finish(uint32_t boot_memaddr) { /* Terminate the display. */ display_end(); - if (is_mariko) { - /* Boot CPU0. */ - cluster_boot_cpu0(boot_memaddr); - } else { - /* Check if SMMU emulation has been used. */ - uint32_t smmu_magic = *(uint32_t *)(SMMU_AARCH64_PAYLOAD_ADDR + 0xFC); - if (smmu_magic == 0xDEADC0DE) { - /* Clear the magic. */ - *(uint32_t *)(SMMU_AARCH64_PAYLOAD_ADDR + 0xFC) = 0; - - /* Pass the boot address to the already running payload. */ - *(uint32_t *)(SMMU_AARCH64_PAYLOAD_ADDR + 0xF0) = boot_memaddr; - - /* Wait a while. */ - mdelay(500); - } else { - /* Boot CPU0. */ - cluster_boot_cpu0(boot_memaddr); - } - } + /* Boot CPU0. */ + cluster_boot_cpu0(boot_memaddr); /* Wait for Exosphère to wake up. */ while (MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE == 0) { diff --git a/fusee/fusee-secondary/src/package1.c b/fusee/fusee-secondary/src/package1.c index 4a3405bd1..2c2c59f80 100644 --- a/fusee/fusee-secondary/src/package1.c +++ b/fusee/fusee-secondary/src/package1.c @@ -58,16 +58,12 @@ bool package1_is_custom_public_key(const void *bct, bool mariko) { } } -int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1loader_size, nx_keyblob_t *keyblobs, uint32_t *revision, FILE *boot0) { +int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1loader_size, FILE *boot0) { nvboot_config_table *bct; /* Normal firmware BCT, primary. TODO: check? */ nv_bootloader_info *pk1l_info; /* TODO: check? */ size_t fpos, pk1l_offset; - union { - nx_keyblob_t keyblob; - uint8_t sector[0x200]; - } d; - if (package1loader == NULL || package1loader_size == NULL || keyblobs == NULL || revision == NULL || boot0 == NULL) { + if (package1loader == NULL || package1loader_size == NULL || boot0 == NULL) { errno = EINVAL; return -1; } @@ -105,7 +101,6 @@ int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1 return -1; } - *revision = pk1l_info->version - 1; *package1loader_size = pk1l_info->length; pk1l_offset = 0x4000 * pk1l_info->start_blk + 0x200 * pk1l_info->start_page; @@ -128,14 +123,6 @@ int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1 return -1; } - /* Read the full keyblob area.*/ - for (size_t i = 0; i < 32; i++) { - if (!fread(d.sector, 0x200, 1, boot0)) { - return -1; - } - keyblobs[i] = d.keyblob; - } - return 0; } @@ -211,24 +198,6 @@ bool package1_get_tsec_fw(void **tsec_fw, const void *package1loader, size_t pac return false; } -size_t package1_get_encrypted_package1(package1_header_t **package1, uint8_t *ctr, const void *package1loader, size_t package1loader_size) { - const uint8_t *crypt_hdr = (const uint8_t *)package1loader + 0x4000 - 0x20; - if (package1loader_size < 0x4000) { - return 0; /* Shouldn't happen, ever. */ - } - - memcpy(ctr, crypt_hdr + 0x10, 0x10); - (*package1) = (package1_header_t *)(crypt_hdr + 0x20); - return *(uint32_t *)crypt_hdr; -} - -bool package1_decrypt(package1_header_t *package1, size_t package1_size, const uint8_t *ctr) { - uint8_t __attribute__((aligned(16))) ctrbuf[16]; - memcpy(ctrbuf, ctr, 16); - se_aes_ctr_crypt(0xB, package1, package1_size, package1, package1_size, ctrbuf, 16); - return memcmp(package1->magic, "PK11", 4) == 0; -} - void *package1_get_warmboot_fw(const package1_header_t *package1) { /* The layout of pk1 changes between versions. diff --git a/fusee/fusee-secondary/src/package1.h b/fusee/fusee-secondary/src/package1.h index 14076e0d4..0e9d5b6a9 100644 --- a/fusee/fusee-secondary/src/package1.h +++ b/fusee/fusee-secondary/src/package1.h @@ -59,14 +59,10 @@ typedef struct { bool package1_is_custom_public_key(const void *bct, bool mariko); -int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1loader_size, nx_keyblob_t *keyblobs, uint32_t *revision, FILE *boot0); +int package1_read_and_parse_boot0_erista(void **package1loader, size_t *package1loader_size, FILE *boot0); int package1_read_and_parse_boot0_mariko(void **package1loader, size_t *package1loader_size, FILE *boot0); -bool package1_get_tsec_fw(void **tsec_fw, const void *package1loader, size_t package1loader_size); -size_t package1_get_encrypted_package1(package1_header_t **package1, uint8_t *ctr, const void *package1loader, size_t package1loader_size); - /* Must be aligned to 16 bytes. */ -bool package1_decrypt(package1_header_t *package1, size_t package1_size, const uint8_t *ctr); void *package1_get_warmboot_fw(const package1_header_t *package1); #endif diff --git a/fusee/fusee-secondary/src/smmu.c b/fusee/fusee-secondary/src/smmu.c deleted file mode 100644 index e42e5023e..000000000 --- a/fusee/fusee-secondary/src/smmu.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "smmu.h" -#include "cluster.h" -#include "mc.h" -#include "timers.h" -#include "tsec.h" - -#define TSEC_KEYGEN_MAX_RETRIES 25 - -void *smmu_heap = (void *)SMMU_HEAP_BASE_ADDR; - -static void safe_memcpy(void *dst, void *src, uint32_t sz) { - /* Aligned memcpy to read MMIO correctly. */ - for (size_t i = 0; i < (sz/4); i++) { - ((volatile uint32_t *)dst)[i] = ((volatile uint32_t *)src)[i]; - } -} - -static void smmu_flush_ppsb() { - /* Read-back barrier for interactions between the PPSB and the APB/AHB. */ - (void)MAKE_MC_REG(MC_SMMU_TLB_CONFIG); -} - -static void smmu_flush_regs() { - /* Flush all TLB and PTC entries. */ - MAKE_MC_REG(MC_SMMU_PTC_FLUSH) = 0; - smmu_flush_ppsb(); - MAKE_MC_REG(MC_SMMU_TLB_FLUSH) = 0; - smmu_flush_ppsb(); -} - -static void *smmu_alloc_page(uint32_t page_count) { - void *cur_page = smmu_heap; - smmu_heap += (page_count * SMMU_PAGE_SIZE); - memset(cur_page, 0, (page_count * SMMU_PAGE_SIZE)); - return cur_page; -} - -static uint32_t *smmu_alloc_pdir() { - uint32_t *pdir = (uint32_t *)smmu_alloc_page(1); - for (int pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++) { - pdir[pdn] = _PDE_VACANT(pdn); - } - return pdir; -} - -static uint32_t *smmu_locate_pte(uint32_t *pdir_page, uint32_t iova) { - uint32_t ptn = SMMU_ADDR_TO_PFN(iova); - uint32_t pdn = SMMU_ADDR_TO_PDN(iova); - uint32_t *pdir = pdir_page; - uint32_t *ptbl; - - if (pdir[pdn] != _PDE_VACANT(pdn)) { - /* Mapped entry table already exists. */ - ptbl = (uint32_t *)SMMU_EX_PTBL_PAGE(pdir[pdn]); - } else { - /* Allocate page table. */ - ptbl = (uint32_t *)smmu_alloc_page(1); - uint32_t addr = SMMU_PDN_TO_ADDR(pdn); - for (int pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SMMU_PAGE_SIZE) { - ptbl[pn] = _PTE_VACANT(addr); - } - pdir[pdn] = SMMU_MK_PDE((uint32_t)ptbl, _PDE_ATTR | _PDE_NEXT); - smmu_flush_regs(); - } - - return &ptbl[ptn % SMMU_PTBL_COUNT]; -} - -static void smmu_map(uint32_t *pdir, uint32_t addr, uint32_t ptpage, int pcount, uint32_t pte_attr) { - for (int i = 0; i < pcount; i++) { - uint32_t *pte = smmu_locate_pte(pdir, addr); - *pte = SMMU_PFN_TO_PTE(SMMU_ADDR_TO_PFN(ptpage), pte_attr); - addr += SMMU_PAGE_SIZE; - ptpage += SMMU_PAGE_SIZE; - } - smmu_flush_regs(); -} - -static uint32_t *smmu_setup_tsec_as(uint32_t asid) { - /* Allocate the page directory. */ - uint32_t *pdir_page = smmu_alloc_pdir(); - - /* Set the PTB ASID and point it to the PDIR. */ - MAKE_MC_REG(MC_SMMU_PTB_ASID) = asid; - MAKE_MC_REG(MC_SMMU_PTB_DATA) = SMMU_MK_PDIR((uint32_t)pdir_page, _PDIR_ATTR); - smmu_flush_ppsb(); - - /* Assign the ASID to TSEC. */ - MAKE_MC_REG(MC_SMMU_TSEC_ASID) = SMMU_ASID_ENABLE((asid << 24) | (asid << 16) | (asid << 8) | asid); - smmu_flush_ppsb(); - - return pdir_page; -} - -static void smmu_clear_tsec_as(uint32_t asid) { - /* Set the PTB ASID and clear it's data. */ - MAKE_MC_REG(MC_SMMU_PTB_ASID) = asid; - MAKE_MC_REG(MC_SMMU_PTB_DATA) = 0; - - /* Clear the ASID from TSEC. */ - MAKE_MC_REG(MC_SMMU_TSEC_ASID) = SMMU_ASID_DISABLE; - smmu_flush_ppsb(); -} - -static void smmu_enable() { - /* AARCH64 payload for enabling the SMMU. */ - /* Write 1 to MC_SMMU_CONFIG, read back and write the result to 0x40003F80. */ - /* This will leave the CPU waiting until 0x40003FF0 is set to Exosphère's address. */ - static const uint32_t aarch64_payload[20] = { - 0x52800020, 0x58000162, 0x58000183, 0xB9000040, - 0xB9400041, 0xB9000061, 0x58000142, 0xF9400040, - 0xF100001F, 0x54FFFFA0, 0xD61F0000, 0x00000000, - 0x70019010, 0x00000000, 0x40003F80, 0x00000000, - 0x40003FF0, 0x00000000, 0x00000000, 0x00000000 - }; - - /* Reset Translation Enable Registers. */ - MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_0) = 0xFFFFFFFF; - MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_1) = 0xFFFFFFFF; - MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_2) = 0xFFFFFFFF; - MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_3) = 0xFFFFFFFF; - MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_4) = 0xFFFFFFFF; - - /* Setup initial TLB and PTC configuration. */ - MAKE_MC_REG(MC_SMMU_PTB_ASID) = 0; - MAKE_MC_REG(MC_SMMU_PTB_DATA) = 0; - MAKE_MC_REG(MC_SMMU_TLB_CONFIG) = 0x30000030; - MAKE_MC_REG(MC_SMMU_PTC_CONFIG) = 0x2800003F; - smmu_flush_regs(); - - /* Power on the CCPLEX to enable the SMMU globally (requires a secure write). */ - volatile uint32_t *aarch64_payload_res = (volatile uint32_t *)(SMMU_AARCH64_PAYLOAD_ADDR + 0x80); - memset((void *)SMMU_AARCH64_PAYLOAD_ADDR, 0, 0x100); - memcpy((void *)SMMU_AARCH64_PAYLOAD_ADDR, aarch64_payload, 20 * 4); - cluster_boot_cpu0(SMMU_AARCH64_PAYLOAD_ADDR); - mdelay(500); - if (*aarch64_payload_res != 1) { - fatal_error("[SMMU]: Failed to enable SMMU!\n"); - } - - /* Write magic for nxboot. */ - *(uint32_t *)(SMMU_AARCH64_PAYLOAD_ADDR + 0xFC) = 0xDEADC0DE; - - /* Flush TLB and PTC entries. */ - smmu_flush_regs(); -} - -void smmu_emulate_tsec(void *tsec_keys, const void *package1, size_t package1_size, void *package1_dec) { - volatile tegra_tsec_t *tsec = tsec_get_regs(); - - /* Backup IRAM to DRAM. */ - memcpy((void *)SMMU_IRAM_BACKUP_ADDR, (void *)0x40010000, 0x30000); - - /* Copy package1 into IRAM. */ - memcpy((void *)0x40010000, package1, package1_size); - - /* Setup TSEC's address space. */ - uint32_t *pdir = smmu_setup_tsec_as(1); - - /* Allocate pages for MMIO and IRAM. */ - volatile uint32_t *car_page = smmu_alloc_page(1); - volatile uint32_t *fuse_page = smmu_alloc_page(1); - volatile uint32_t *pmc_page = smmu_alloc_page(1); - volatile uint32_t *flow_page = smmu_alloc_page(1); - volatile uint32_t *se_page = smmu_alloc_page(1); - volatile uint32_t *mc_page = smmu_alloc_page(1); - volatile uint32_t *iram_pages = smmu_alloc_page(48); - volatile uint32_t *expv_page = smmu_alloc_page(1); - - /* Map all necessary pages. */ - smmu_map(pdir, 0x60006000, (uint32_t)car_page, 1, _READABLE | _WRITABLE | _NONSECURE); - smmu_map(pdir, 0x7000F000, (uint32_t)fuse_page, 1, _READABLE | _NONSECURE); - smmu_map(pdir, 0x7000E000, (uint32_t)pmc_page, 1, _READABLE | _NONSECURE); - smmu_map(pdir, 0x60007000, (uint32_t)flow_page, 1, _WRITABLE | _NONSECURE); - smmu_map(pdir, 0x70012000, (uint32_t)se_page, 1, _READABLE | _WRITABLE | _NONSECURE); - smmu_map(pdir, 0x70019000, (uint32_t)mc_page, 1, _READABLE | _NONSECURE); - smmu_map(pdir, 0x40010000, (uint32_t)iram_pages, 48, _READABLE | _WRITABLE | _NONSECURE); - smmu_map(pdir, 0x6000F000, (uint32_t)expv_page, 1, _READABLE | _WRITABLE | _NONSECURE); - - /* Enable the SMMU. */ - smmu_enable(); - - /* Loop retrying TSEC firmware execution, in case we lose the SE keydata race. */ - uint32_t key_buf[0x20/4] = {0}; - unsigned int retries = 0; - while (true) { - if (retries++ > TSEC_KEYGEN_MAX_RETRIES) { - fatal_error("[SMMU] TSEC key generation race was lost too many times!"); - } - - /* Load the TSEC firmware from IRAM. */ - if (tsec_load_fw((void *)(0x40010000 + 0xE00), 0x2900) < 0) { - fatal_error("[SMMU]: Failed to load TSEC firmware!\n"); - } - - /* Disable the aperture since it has precedence over the SMMU. */ - mc_disable_ahb_redirect(); - - /* Clear all pages. */ - memset((void *)car_page, 0, SMMU_PAGE_SIZE); - memset((void *)fuse_page, 0, SMMU_PAGE_SIZE); - memset((void *)pmc_page, 0, SMMU_PAGE_SIZE); - memset((void *)flow_page, 0, SMMU_PAGE_SIZE); - memset((void *)se_page, 0, SMMU_PAGE_SIZE); - memset((void *)mc_page, 0, SMMU_PAGE_SIZE); - memset((void *)iram_pages, 0, 48 * SMMU_PAGE_SIZE); - memset((void *)expv_page, 0, SMMU_PAGE_SIZE); - - /* Copy CAR, MC and FUSE. */ - safe_memcpy((void *)car_page, (void *)0x60006000, 0x1000); - safe_memcpy((void *)mc_page, (void *)0x70019000, 0x1000); - safe_memcpy((void *)&fuse_page[0x800/4], (void *)0x7000F800, 0x400); - - /* Copy IRAM. */ - memcpy((void *)iram_pages, (void *)0x40010000, 0x30000); - - /* TSEC wants CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0 to be equal to 2. */ - car_page[0x1F4/4] = 2; - - /* TSEC wants the aperture fully open. */ - mc_page[0x65C/4] = 0; - mc_page[0x660/4] = 0x80000000; - - /* Run the TSEC firmware. */ - tsec_run_fw(); - - /* Extract the keys from SE. */ - volatile uint32_t *key_data = (volatile uint32_t *)((void *)se_page + 0x320); - uint32_t old_key_data = *key_data; - uint32_t buf_counter = 0; - while (!(tsec->TSEC_FALCON_CPUCTL & 0x10)) { - const uint32_t new_key_data = *key_data; - if (new_key_data != old_key_data) { - old_key_data = new_key_data; - key_buf[buf_counter] = new_key_data; - buf_counter++; - } - } - - /* Enable back the aperture. */ - mc_enable_ahb_redirect(); - - if (buf_counter == 8) { - break; - } - } - - /* Check if the TSEC firmware wrote over the exception vectors. */ - volatile uint32_t *tsec_done_check = (volatile uint32_t *)((void *)expv_page + 0x200); - if (!(*tsec_done_check)) { - fatal_error("[SMMU]: Failed to emulate the TSEC firmware!\n"); - } - - /* Copy back the extracted keys. */ - memcpy((void *)tsec_keys, (void *)key_buf, 0x20); - - /* Manually disable TSEC clocks. */ - tsec_disable_clkrst(); - - /* Clear TSEC's address space. */ - smmu_clear_tsec_as(1); - - /* Return the decrypted package1 from emulated IRAM. */ - memcpy(package1_dec, (void *)iram_pages, package1_size); - - /* Restore IRAM from DRAM. */ - memcpy((void *)0x40010000, (void *)SMMU_IRAM_BACKUP_ADDR, 0x30000); -} \ No newline at end of file diff --git a/fusee/fusee-secondary/src/smmu.h b/fusee/fusee-secondary/src/smmu.h deleted file mode 100644 index 98bc16b25..000000000 --- a/fusee/fusee-secondary/src/smmu.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_SMMU_H_ -#define FUSEE_SMMU_H_ - -#include -#include -#include - -#define SMMU_HEAP_BASE_ADDR 0x81000000 -#define SMMU_IRAM_BACKUP_ADDR 0x82000000 -#define SMMU_AARCH64_PAYLOAD_ADDR 0x40003F00 - -#define SMMU_PAGE_SHIFT 12 -#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT) -#define SMMU_PDIR_COUNT 1024 -#define SMMU_PDIR_SIZE (sizeof(uint32_t) * SMMU_PDIR_COUNT) -#define SMMU_PTBL_COUNT 1024 -#define SMMU_PTBL_SIZE (sizeof(uint32_t) * SMMU_PTBL_COUNT) -#define SMMU_PDIR_SHIFT 12 -#define SMMU_PDE_SHIFT 12 -#define SMMU_PTE_SHIFT 12 -#define SMMU_PFN_MASK 0x000fffff -#define SMMU_PDE_NEXT_SHIFT 28 -#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12) -#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22) -#define SMMU_PDN_TO_ADDR(pdn) ((pdn) << 22) -#define _READABLE (1 << 31) -#define _WRITABLE (1 << 30) -#define _NONSECURE (1 << 29) -#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT) -#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE) -#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE) -#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE) -#define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT) -#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR) -#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE) -#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR) -#define SMMU_MK_PDIR(page, attr) (((page) >> SMMU_PDIR_SHIFT) | (attr)) -#define SMMU_MK_PDE(page, attr) (((page) >> SMMU_PDE_SHIFT) | (attr)) -#define SMMU_EX_PTBL_PAGE(pde) (((pde) & SMMU_PFN_MASK) << SMMU_PDIR_SHIFT) -#define SMMU_PFN_TO_PTE(pfn, attr) ((pfn) | (attr)) -#define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31)) -#define SMMU_ASID_DISABLE 0 -#define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0)) - -void smmu_emulate_tsec(void *tsec_keys, const void *package1, size_t package1_size, void *package1_dec); - -#endif \ No newline at end of file diff --git a/fusee/fusee-secondary/src/start.s b/fusee/fusee-secondary/src/start.s index 9ddeaa8d8..8c727ac23 100644 --- a/fusee/fusee-secondary/src/start.s +++ b/fusee/fusee-secondary/src/start.s @@ -108,6 +108,7 @@ _metadata: #define CONTENT_TYPE_KLD 9 #define CONTENT_TYPE_KRN 10 #define CONTENT_TYPE_EXF 11 +#define CONTENT_TYPE_TKG 12 #define CONTENT_FLAG_NONE (0 << 0) @@ -213,39 +214,6 @@ _content_headers: .asciz "rebootstub" .align 5 -/* sept_primary content header */ -.word __sept_primary_bin_start__ -.word __sept_primary_bin_size__ -.byte CONTENT_TYPE_SP1 -.byte CONTENT_FLAG_NONE -.byte CONTENT_FLAG_NONE -.byte CONTENT_FLAG_NONE -.word 0xCCCCCCCC -.asciz "sept_primary" -.align 5 - -/* sept_secondary 00 content header */ -.word __sept_secondary_00_enc_start__ -.word __sept_secondary_00_enc_size__ -.byte CONTENT_TYPE_SP2 -.byte CONTENT_FLAG_NONE -.byte CONTENT_FLAG_NONE -.byte CONTENT_FLAG_NONE -.word 0xCCCCCCCC -.asciz "septsecondary00" -.align 5 - -/* sept_secondary 01 content header */ -.word __sept_secondary_01_enc_start__ -.word __sept_secondary_01_enc_size__ -.byte CONTENT_TYPE_SP2 -.byte CONTENT_FLAG_NONE -.byte CONTENT_FLAG_NONE -.byte CONTENT_FLAG_NONE -.word 0xCCCCCCCC -.asciz "septsecondary01" -.align 5 - /* sm content header */ .word __sm_kip_start__ .word __sm_kip_size__ @@ -301,6 +269,17 @@ _content_headers: .asciz "exosphere_fatal" .align 5 +/* tsec_keygen content header */ +.word __tsec_keygen_bin_start__ +.word __tsec_keygen_bin_size__ +.byte CONTENT_TYPE_TKG +.byte CONTENT_FLAG_NONE +.byte CONTENT_FLAG_NONE +.byte CONTENT_FLAG_NONE +.word 0xCCCCCCCC +.asciz "tsec_keygen" +.align 5 + _content_headers_end: /* No need to include this in normal programs: */ diff --git a/fusee/fusee-secondary/src/tsec.c b/fusee/fusee-secondary/src/tsec.c index e6c24f3bf..9c0487ee2 100644 --- a/fusee/fusee-secondary/src/tsec.c +++ b/fusee/fusee-secondary/src/tsec.c @@ -14,15 +14,16 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #include "tsec.h" #include "di.h" #include "timers.h" #include "car.h" +#include "mc.h" static int tsec_dma_wait_idle() { - volatile tegra_tsec_t *tsec = tsec_get_regs(); + volatile tegra_tsec_t *tsec = tsec_get_regs(); uint32_t timeout = (get_time_ms() + 10000); while (!(tsec->TSEC_FALCON_DMATRFCMD & 2)) @@ -30,13 +31,13 @@ static int tsec_dma_wait_idle() if (get_time_ms() > timeout) return 0; } - + return 1; } static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t phys_offset) { - volatile tegra_tsec_t *tsec = tsec_get_regs(); + volatile tegra_tsec_t *tsec = tsec_get_regs(); uint32_t cmd = 0; if (!is_imem) @@ -52,16 +53,16 @@ static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t ph } static int tsec_kfuse_wait_ready() -{ +{ uint32_t timeout = (get_time_ms() + 10000); - + /* Wait for STATE_DONE. */ while (!(KFUSE_STATE & 0x10000)) { if (get_time_ms() > timeout) return 0; } - + /* Check for STATE_CRCPASS. */ if (!(KFUSE_STATE & 0x20000)) return 0; @@ -91,19 +92,19 @@ void tsec_disable_clkrst() clkrst_disable(CARDEVICE_HOST1X); } -int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw, size_t tsec_fw_size) +static int tsec_run_fw_impl(const void *tsec_fw, size_t tsec_fw_size) { volatile tegra_tsec_t *tsec = tsec_get_regs(); /* Enable clocks. */ tsec_enable_clkrst(); - + /* Make sure KFUSE is ready. */ if (!tsec_kfuse_wait_ready()) { /* Disable clocks. */ tsec_disable_clkrst(); - + return -1; } @@ -112,16 +113,16 @@ int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw, size_t tsec_fw tsec->TSEC_FALCON_IRQMSET = 0xFFF2; tsec->TSEC_FALCON_IRQDEST = 0xFFF0; tsec->TSEC_FALCON_ITFEN = 3; - + /* Make sure the DMA block is idle. */ if (!tsec_dma_wait_idle()) { /* Disable clocks. */ tsec_disable_clkrst(); - + return -2; } - + /* Load firmware. */ tsec->TSEC_FALCON_DMATRFBASE = (uint32_t)tsec_fw >> 8; for (uint32_t addr = 0; addr < tsec_fw_size; addr += 0x100) @@ -130,128 +131,71 @@ int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw, size_t tsec_fw { /* Disable clocks. */ tsec_disable_clkrst(); - + return -3; } } - + /* Write magic value to HOST1X scratch register. */ MAKE_HOST1X_REG(0x3300) = 0x34C2E1DA; - + /* Execute firmware. */ tsec->TSEC_FALCON_MAILBOX1 = 0; - tsec->TSEC_FALCON_MAILBOX0 = rev; + tsec->TSEC_FALCON_MAILBOX0 = 1; tsec->TSEC_FALCON_BOOTVEC = 0; tsec->TSEC_FALCON_CPUCTL = 2; - + /* Make sure the DMA block is idle. */ if (!tsec_dma_wait_idle()) { /* Disable clocks. */ tsec_disable_clkrst(); - + return -4; } - - uint32_t timeout = (get_time_ms() + 2000); - while (!tsec->TSEC_FALCON_MAILBOX1) - { - if (get_time_ms() > timeout) - { + + uint32_t timeout = (get_time_ms() + 4000); + while (!(tsec->TSEC_FALCON_CPUCTL & 0x10)) { + if (get_time_ms() > timeout) { /* Disable clocks. */ tsec_disable_clkrst(); - + return -5; } } - + if (tsec->TSEC_FALCON_MAILBOX1 != 0xB0B0B0B0) { /* Disable clocks. */ tsec_disable_clkrst(); - + return -6; } /* Clear magic value from HOST1X scratch register. */ MAKE_HOST1X_REG(0x3300) = 0; - /* Fetch result from SOR1. */ - uint32_t tmp[0x4] = {0}; - tmp[0] = SOR1_DP_HDCP_BKSV_LSB; - tmp[1] = SOR1_TMDS_HDCP_BKSV_LSB; - tmp[2] = SOR1_TMDS_HDCP_CN_MSB; - tmp[3] = SOR1_TMDS_HDCP_CN_LSB; - - /* Clear SOR1 registers. */ - SOR1_DP_HDCP_BKSV_LSB = 0; - SOR1_TMDS_HDCP_BKSV_LSB = 0; - SOR1_TMDS_HDCP_CN_MSB = 0; - SOR1_TMDS_HDCP_CN_LSB = 0; - - /* Copy back the key. */ - memcpy(key, &tmp, 0x10); - return 0; } -int tsec_load_fw(const void *tsec_fw, size_t tsec_fw_size) -{ - volatile tegra_tsec_t *tsec = tsec_get_regs(); +int tsec_run_fw(const void *tsec_fw, size_t tsec_fw_size) { + /* Ensure that the ahb redirect is enabled. */ + mc_enable_ahb_redirect(); - /* Enable clocks. */ - tsec_enable_clkrst(); - - /* Make sure KFUSE is ready. */ - if (!tsec_kfuse_wait_ready()) - { - /* Disable clocks. */ - tsec_disable_clkrst(); - - return -1; - } + /* Get bom/tom */ + uint32_t bom = MAKE_MC_REG(MC_IRAM_BOM); + uint32_t tom = MAKE_MC_REG(MC_IRAM_TOM); - /* Configure Falcon. */ - tsec->TSEC_FALCON_DMACTL = 0; - tsec->TSEC_FALCON_IRQMSET = 0xFFF2; - tsec->TSEC_FALCON_IRQDEST = 0xFFF0; - tsec->TSEC_FALCON_ITFEN = 3; - - /* Make sure the DMA block is idle. */ - if (!tsec_dma_wait_idle()) - { - /* Disable clocks. */ - tsec_disable_clkrst(); - - return -2; - } - - /* Load firmware. */ - tsec->TSEC_FALCON_DMATRFBASE = (uint32_t)tsec_fw >> 8; - for (uint32_t addr = 0; addr < tsec_fw_size; addr += 0x100) - { - if (!tsec_dma_phys_to_flcn(true, addr, addr)) - { - /* Disable clocks. */ - tsec_disable_clkrst(); - - return -3; - } - } + /* Override the ahb redirect extents. */ + MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000; + MAKE_MC_REG(MC_IRAM_TOM) = 0x80000000; - return 0; -} + /* Run the fw. */ + int res = tsec_run_fw_impl(tsec_fw, tsec_fw_size); -void tsec_run_fw() -{ - volatile tegra_tsec_t *tsec = tsec_get_regs(); - - /* Write magic value to HOST1X scratch register. */ - MAKE_HOST1X_REG(0x3300) = 0x34C2E1DA; - - /* Execute firmware. */ - tsec->TSEC_FALCON_MAILBOX1 = 0; - tsec->TSEC_FALCON_MAILBOX0 = 1; - tsec->TSEC_FALCON_BOOTVEC = 0; - tsec->TSEC_FALCON_CPUCTL = 2; + /* Reset the ahb redirect extents. */ + MAKE_MC_REG(MC_IRAM_BOM) = bom; + MAKE_MC_REG(MC_IRAM_TOM) = tom; + + return res; } \ No newline at end of file diff --git a/fusee/fusee-secondary/src/tsec.h b/fusee/fusee-secondary/src/tsec.h index 0d776ecd9..4833eccaa 100644 --- a/fusee/fusee-secondary/src/tsec.h +++ b/fusee/fusee-secondary/src/tsec.h @@ -14,7 +14,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #ifndef FUSEE_TSEC_H_ #define FUSEE_TSEC_H_ @@ -306,8 +306,7 @@ static inline volatile tegra_tsec_t *tsec_get_regs(void) void tsec_enable_clkrst(); void tsec_disable_clkrst(); -int tsec_get_key(uint8_t *key, uint32_t rev, const void *tsec_fw, size_t tsec_fw_size); -int tsec_load_fw(const void *tsec_fw, size_t tsec_fw_size); -void tsec_run_fw(); + +int tsec_run_fw(const void *tsec_fw, size_t tsec_fw_size); #endif \ No newline at end of file diff --git a/fusee/fusee-secondary/src/utils.c b/fusee/fusee-secondary/src/utils.c index 5cd9c156d..095759e05 100644 --- a/fusee/fusee-secondary/src/utils.c +++ b/fusee/fusee-secondary/src/utils.c @@ -34,7 +34,6 @@ #define u8 uint8_t #define u32 uint32_t #include "fusee_primary_bin.h" -#include "sept_primary_bin.h" #include "rebootstub_bin.h" #undef u8 #undef u32 @@ -131,42 +130,8 @@ __attribute__((noreturn)) void reboot_to_fusee_primary(void) { reboot_to_payload(); } -__attribute__((noreturn)) void reboot_to_sept(const void *tsec_fw, size_t tsec_fw_length, const void *stage2, size_t stage2_size) { - if (is_soc_mariko()) { - /* Reboot to sept isn't possible on mariko, so just do normal reboot. */ - shutdown_system(true); - } else { - /* Copy tsec firmware. */ - for (size_t i = 0; i < tsec_fw_length; i += sizeof(uint32_t)) { - write32le((void *)0x40010F00, i, read32le(tsec_fw, i)); - } - MAKE_REG32(0x40010EFC) = tsec_fw_length; - - /* Copy stage 2. */ - for (size_t i = 0; i < stage2_size; i += sizeof(uint32_t)) { - write32le((void *)0x40016FE0, i, read32le(stage2, i)); - } - - /* Copy sept into IRAM low. */ - for (size_t i = 0; i < sept_primary_bin_size; i += sizeof(uint32_t)) { - write32le((void *)0x4003F000, i, read32le(sept_primary_bin, i)); - } - - /* Patch SDRAM init to perform an SVC immediately after second write */ - APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF; - APBDEV_PMC_SCRATCH46_0 = 0x6001DC28; - /* Set SVC handler to jump to reboot stub in IRAM. */ - APBDEV_PMC_SCRATCH33_0 = 0x4003F000; - APBDEV_PMC_SCRATCH40_0 = 0x6000F208; - - /* Trigger warm reboot. */ - pmc_reboot(1 << 0); - while (true) { } - } -} - __attribute__((noreturn)) void reboot_to_iram_payload(void *payload, size_t payload_size) { - /* Copy sept into IRAM low. */ + /* Copy payload into IRAM low. */ for (size_t i = 0; i < payload_size; i += sizeof(uint32_t)) { write32le((void *)0x40010000, i, read32le(payload, i)); } diff --git a/fusee/fusee-secondary/src/utils.h b/fusee/fusee-secondary/src/utils.h index 846d7da9c..1f517b624 100644 --- a/fusee/fusee-secondary/src/utils.h +++ b/fusee/fusee-secondary/src/utils.h @@ -13,7 +13,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #ifndef FUSEE_UTILS_H #define FUSEE_UTILS_H @@ -121,7 +121,6 @@ static inline bool check_32bit_address_range_in_program(uintptr_t addr, size_t s __attribute__((noreturn)) void watchdog_reboot(void); __attribute__((noreturn)) void pmc_reboot(uint32_t scratch0); __attribute__((noreturn)) void reboot_to_fusee_primary(void); -__attribute__((noreturn)) void reboot_to_sept(const void *tsec_fw, size_t tsec_fw_length, const void *stage2, size_t stage2_size); __attribute__((noreturn)) void reboot_to_iram_payload(void *payload, size_t payload_size); __attribute__((noreturn)) void wait_for_button_and_reboot(void); void wait_for_button(void); diff --git a/sept/Makefile b/sept/Makefile deleted file mode 100644 index 2c9cafa66..000000000 --- a/sept/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -SUBFOLDERS := sept-primary sept-secondary - -TOPTARGETS := all clean - -$(TOPTARGETS): $(SUBFOLDERS) - -$(SUBFOLDERS): - $(MAKE) -C $@ $(MAKECMDGOALS) - -.PHONY: $(TOPTARGETS) $(SUBFOLDERS) diff --git a/sept/sept-primary/Makefile b/sept/sept-primary/Makefile deleted file mode 100644 index 2cdf8394e..000000000 --- a/sept/sept-primary/Makefile +++ /dev/null @@ -1,168 +0,0 @@ -#--------------------------------------------------------------------------------- -.SUFFIXES: -#--------------------------------------------------------------------------------- - -ifeq ($(strip $(DEVKITARM)),) -$(error "Please set DEVKITARM in your environment. export DEVKITARM=devkitARM") -endif - -TOPDIR ?= $(CURDIR) - -AMS := $(TOPDIR)/../../ -include $(DEVKITARM)/base_rules - -AMSBRANCH := $(shell git symbolic-ref --short HEAD) -AMSREV := $(AMSBRANCH)-$(shell git rev-parse --short HEAD) - -ifneq (, $(strip $(shell git status --porcelain 2>/dev/null))) - AMSREV := $(AMSREV)-dirty -endif - -#--------------------------------------------------------------------------------- -# TARGET is the name of the output -# BUILD is the directory where object files & intermediate files will be placed -# SOURCES is a list of directories containing source code -# DATA is a list of directories containing data files -# INCLUDES is a list of directories containing header files -#--------------------------------------------------------------------------------- -TARGET := $(notdir $(CURDIR)) -BUILD := build -SOURCES := src -DATA := data -INCLUDES := include ../../libraries/libvapours/include - -#--------------------------------------------------------------------------------- -# options for code generation -#--------------------------------------------------------------------------------- -ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork -DEFINES := -D__BPMP__ -DSEPT_STAGE1_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\" - -CFLAGS := \ - -g \ - -gdwarf-4 \ - -Os \ - -fomit-frame-pointer \ - -ffunction-sections \ - -fdata-sections \ - -std=gnu11 \ - -Werror \ - -Wall \ - -Wno-array-bounds \ - -Wno-stringop-overflow \ - -Wno-stringop-overread \ - -fstrict-volatile-bitfields \ - $(ARCH) $(DEFINES) - -CFLAGS += $(INCLUDE) - -CXXFLAGS := $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11 - -ASFLAGS := -g -gdwarf-4 $(ARCH) -LDFLAGS = -specs=$(TOPDIR)/linker.specs -g -gdwarf-4 $(ARCH) -Wl,-Map,$(notdir $*.map) - -LIBS := - -#--------------------------------------------------------------------------------- -# list of directories containing libraries, this must be the top level containing -# include and lib -#--------------------------------------------------------------------------------- -LIBDIRS := - - -#--------------------------------------------------------------------------------- -# no real need to edit anything past this point unless you need to add additional -# rules for different file extensions -#--------------------------------------------------------------------------------- -ifneq ($(BUILD),$(notdir $(CURDIR))) -#--------------------------------------------------------------------------------- - -export OUTPUT := $(CURDIR)/$(TARGET) -export TOPDIR := $(CURDIR) - -export VPATH := $(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \ - $(foreach dir,$(DATA),$(CURDIR)/$(dir)) - -export DEPSDIR := $(CURDIR)/$(BUILD) - -CFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c))) -CPPFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp))) -SFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s))) -BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) - -#--------------------------------------------------------------------------------- -# use CXX for linking C++ projects, CC for standard C -#--------------------------------------------------------------------------------- -ifeq ($(strip $(CPPFILES)),) -#--------------------------------------------------------------------------------- - export LD := $(CC) -#--------------------------------------------------------------------------------- -else -#--------------------------------------------------------------------------------- - export LD := $(CXX) -#--------------------------------------------------------------------------------- -endif -#--------------------------------------------------------------------------------- - -export OFILES_BIN := $(addsuffix .o,$(BINFILES)) -export OFILES_SRC := $(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o) -export OFILES := $(OFILES_BIN) $(OFILES_SRC) -export HFILES_BIN := $(addsuffix .h,$(subst .,_,$(BINFILES))) - -export INCLUDE := $(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \ - $(foreach dir,$(LIBDIRS),-I$(dir)/include) \ - -I$(CURDIR)/$(BUILD) - -export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib) - -.PHONY: $(BUILD) clean all - -#--------------------------------------------------------------------------------- -all: $(BUILD) - -$(BUILD): - @[ -d $@ ] || mkdir -p $@ - @$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile - -#--------------------------------------------------------------------------------- -clean: - @echo clean ... - @rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf - - -#--------------------------------------------------------------------------------- -else -.PHONY: all - -DEPENDS := $(OFILES:.o=.d) - -#--------------------------------------------------------------------------------- -# main targets -#--------------------------------------------------------------------------------- -all : $(OUTPUT).bin - -$(OUTPUT).bin : $(OUTPUT).elf - $(OBJCOPY) -S -O binary $< $@ - @echo built ... $(notdir $@) - -$(OUTPUT).elf : $(OFILES) - -%.elf: $(OFILES) - @echo linking $(notdir $@) - @$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@ - @$(NM) -CSn $@ > $(notdir $*.lst) - -$(OFILES_SRC) : $(HFILES_BIN) - -#--------------------------------------------------------------------------------- -# you need a rule like this for each extension you use as binary data -#--------------------------------------------------------------------------------- -%.bin.o %_bin.h: %.bin -#--------------------------------------------------------------------------------- - @echo $(notdir $<) - @$(bin2o) - --include $(DEPENDS) - -#--------------------------------------------------------------------------------------- -endif -#--------------------------------------------------------------------------------------- diff --git a/sept/sept-primary/linker.ld b/sept/sept-primary/linker.ld deleted file mode 100644 index 56e9f66cd..000000000 --- a/sept/sept-primary/linker.ld +++ /dev/null @@ -1,168 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) - -PHDRS -{ - crt0 PT_LOAD; - main PT_LOAD; -} - -/* Mostly copied from https://github.com/devkitPro/buildscripts/blob/master/dkarm-eabi/crtls/3dsx.ld */ -MEMORY -{ - NULL : ORIGIN = 0x00000000, LENGTH = 0x1000 - main : ORIGIN = 0x40010000, LENGTH = 0x1000 - high_iram : ORIGIN = 0x4003F000, LENGTH = 0x1000 - low_iram : ORIGIN = 0x40003000, LENGTH = 0x8000 -} - -SECTIONS -{ - PROVIDE(__crt0_start__ = 0x4003F000); - PROVIDE(__main_start__ = 0x40010000); - PROVIDE(__stack_top__ = 0x40010000); - PROVIDE(__stack_bottom__ = 0x4000C000); - PROVIDE(__heap_start__ = 0); - PROVIDE(__heap_end__ = 0); - - . = __crt0_start__; - - .crt0 : - { - KEEP( *(.text.start) ) - KEEP( *(.text.ipatch_word) ) - KEEP( *(.init) ) - . = ALIGN(32); - } >high_iram AT>high_iram :crt0 - - __main_phys_start__ = ABSOLUTE(.) ; - - .text : - { - /* .text */ - KEEP( *(.text.jump_to_main) ) - *(.text) - *(.text.*) - *(.glue_7) - *(.glue_7t) - *(.stub) - *(.gnu.warning) - *(.gnu.linkonce.t*) - - /* .fini */ - KEEP( *(.fini) ) - . = ALIGN(8); - } >main AT>high_iram :main - - .rodata : - { - *(.rodata) - *(.roda) - *(.rodata.*) - *all.rodata*(*) - *(.gnu.linkonce.r*) - SORT(CONSTRUCTORS) - . = ALIGN(8); - } >main AT>high_iram - - .preinit_array : - { - PROVIDE (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - } >main AT>high_iram - - .init_array ALIGN(4) : - { - PROVIDE (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE (__init_array_end = .); - } >main AT>high_iram - - .fini_array ALIGN(4) : - { - PROVIDE (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE (__fini_array_end = .); - } >main AT>high_iram - - .ctors ALIGN(4) : - { - KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */ - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - . = ALIGN(4); /* REQUIRED. LD is flaky without it. */ - } >main AT>high_iram - - .dtors ALIGN(4) : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - . = ALIGN(4); /* REQUIRED. LD is flaky without it. */ - } >main AT>high_iram - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) __exidx_start = ABSOLUTE(.);} >main AT>high_iram - ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) __exidx_end = ABSOLUTE(.);} >main AT>high_iram - - .bss (NOLOAD) : - { - . = ALIGN(32); - PROVIDE (__bss_start__ = ABSOLUTE(.)); - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b*) - *(COMMON) - . = ALIGN(32); - PROVIDE (__bss_end__ = ABSOLUTE(.)); - } >main AT>high_iram :NONE - __main_end__ = ABSOLUTE(.) ; - - PROVIDE(__main_size__ = (__main_end__ - __main_start__)); - - /* ================== - ==== Metadata ==== - ================== */ - - /* Discard sections that difficult post-processing */ - /DISCARD/ : { *(.group .comment .note) } - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } -} diff --git a/sept/sept-primary/linker.specs b/sept/sept-primary/linker.specs deleted file mode 100644 index 300990418..000000000 --- a/sept/sept-primary/linker.specs +++ /dev/null @@ -1,7 +0,0 @@ -%rename link old_link - -*link: -%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections - -*startfile: -crti%O%s crtbegin%O%s diff --git a/sept/sept-primary/src/apb_misc.h b/sept/sept-primary/src/apb_misc.h deleted file mode 100644 index 3cac3c5f8..000000000 --- a/sept/sept-primary/src/apb_misc.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_APB_MISC_H -#define FUSEE_APB_MISC_H - -#include - -#define APB_MISC_BASE 0x70000000 -#define APB_PADCTL_BASE 0x70000810 -#define MAKE_APB_MISC_REG(n) MAKE_REG32(APB_MISC_BASE + n) -#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n) - -#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40) -#define APB_MISC_GP_DSI_PAD_CONTROL_0 MAKE_APB_MISC_REG(0xAC0) -#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64) -#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68) - -#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20) -#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12) -#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT (28) -#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT (30) -#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT) -#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT) -#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT) -#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT) - -#define EMMC2_PAD_DRVUP_COMP_SHIFT (8) -#define EMMC2_PAD_DRVDN_COMP_SHIFT (2) -#define EMMC2_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC2_PAD_DRVUP_COMP_SHIFT) -#define EMMC2_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC2_PAD_DRVDN_COMP_SHIFT) - -#define SDMMC2_PAD_CAL_DRVUP_SHIFT (20) -#define SDMMC2_PAD_CAL_DRVDN_SHIFT (12) -#define SDMMC2_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVUP_SHIFT) -#define SDMMC2_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVDN_SHIFT) - -#define EMMC4_PAD_DRVUP_COMP_SHIFT (8) -#define EMMC4_PAD_DRVDN_COMP_SHIFT (2) -#define EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC4_PAD_DRVUP_COMP_SHIFT) -#define EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC4_PAD_DRVDN_COMP_SHIFT) - -#define PADCTL_SDMMC1_DEEP_LOOPBACK (1 << 0) -#define PADCTL_SDMMC3_DEEP_LOOPBACK (1 << 0) -#define PADCTL_SDMMC2_ENABLE_DATA_IN (0xFF << 8) -#define PADCTL_SDMMC2_ENABLE_CLK_IN (0x3 << 4) -#define PADCTL_SDMMC2_DEEP_LOOPBACK (1 << 0) -#define PADCTL_SDMMC4_ENABLE_DATA_IN (0xFF << 8) -#define PADCTL_SDMMC4_ENABLE_CLK_IN (0x3 << 4) -#define PADCTL_SDMMC4_DEEP_LOOPBACK (1 << 0) -#define PADCTL_SDMMC1_CD_SOURCE (1 << 0) -#define PADCTL_SDMMC1_WP_SOURCE (1 << 1) -#define PADCTL_SDMMC3_CD_SOURCE (1 << 2) -#define PADCTL_SDMMC3_WP_SOURCE (1 << 3) - -typedef struct { - uint32_t asdbgreg; /* 0x810 */ - uint32_t _0x814[0x31]; - uint32_t sdmmc1_clk_lpbk_control; /* 0x8D4 */ - uint32_t sdmmc3_clk_lpbk_control; /* 0x8D8 */ - uint32_t emmc2_pad_cfg_control; /* 0x8DC */ - uint32_t emmc4_pad_cfg_control; /* 0x8E0 */ - uint32_t _0x8E4[0x6E]; - uint32_t sdmmc1_pad_cfgpadctrl; /* 0xA98 */ - uint32_t emmc2_pad_cfgpadctrl; /* 0xA9C */ - uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */ - uint32_t emmc2_pad_pupd_cfgpadctrl; /* 0xAA4 */ - uint32_t _0xAA8[0x03]; - uint32_t sdmmc3_pad_cfgpadctrl; /* 0xAB0 */ - uint32_t emmc4_pad_cfgpadctrl; /* 0xAB4 */ - uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */ - uint32_t emmc4_pad_pupd_cfgpadctrl; /* 0xABC */ - uint32_t _0xAC0[0x2E]; - uint32_t vgpio_gpio_mux_sel; /* 0xB74 */ - uint32_t qspi_sck_lpbk_control; /* 0xB78 */ -} tegra_padctl_t; - -static inline volatile tegra_padctl_t *padctl_get_regs(void) -{ - return (volatile tegra_padctl_t *)APB_PADCTL_BASE; -} - -#endif diff --git a/sept/sept-primary/src/btn.c b/sept/sept-primary/src/btn.c deleted file mode 100644 index eac933cc1..000000000 --- a/sept/sept-primary/src/btn.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "btn.h" -#include "i2c.h" -#include "gpio.h" -#include "timers.h" - -uint32_t btn_read() -{ - uint32_t res = 0; - - if (!gpio_read(GPIO_BUTTON_VOL_DOWN)) - res |= BTN_VOL_DOWN; - - if (!gpio_read(GPIO_BUTTON_VOL_UP)) - res |= BTN_VOL_UP; - - uint32_t val = 0; - if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, 0x15, &val, 1)) - { - if (val & 0x4) - res |= BTN_POWER; - } - - return res; -} - -uint32_t btn_wait() -{ - uint32_t res = 0, btn = btn_read(); - int pwr = 0; - - if (btn & BTN_POWER) - { - pwr = 1; - btn &= ~BTN_POWER; - } - - do - { - res = btn_read(); - - if (!(res & BTN_POWER) && pwr) - pwr = 0; - else if (pwr) - res &= ~BTN_POWER; - } while (btn == res); - - return res; -} - -uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask) -{ - uint32_t timeout = get_time_us() + time_ms * 1000; - uint32_t res = btn_read() & mask; - - do - { - if (!(res & mask)) - res = btn_read() & mask; - } while (get_time_us() < timeout); - - return res; -} \ No newline at end of file diff --git a/sept/sept-primary/src/btn.h b/sept/sept-primary/src/btn.h deleted file mode 100644 index a9a018eae..000000000 --- a/sept/sept-primary/src/btn.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_BTN_H_ -#define FUSEE_BTN_H_ - -#define BTN_POWER 0x1 -#define BTN_VOL_DOWN 0x2 -#define BTN_VOL_UP 0x4 - -uint32_t btn_read(); -uint32_t btn_wait(); -uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask); - -#endif \ No newline at end of file diff --git a/sept/sept-primary/src/car.c b/sept/sept-primary/src/car.c deleted file mode 100644 index 30c2d86aa..000000000 --- a/sept/sept-primary/src/car.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "car.h" -#include "timers.h" -#include "utils.h" - -static inline uint32_t get_clk_source_reg(CarDevice dev) { - switch (dev) { - case CARDEVICE_UARTA: return 0x178; - case CARDEVICE_UARTB: return 0x17C; - case CARDEVICE_UARTC: return 0x1A0; - case CARDEVICE_I2C1: return 0x124; - case CARDEVICE_I2C5: return 0x128; - case CARDEVICE_TZRAM: return 0; - case CARDEVICE_SE: return 0x42C; - case CARDEVICE_HOST1X: return 0x180; - case CARDEVICE_TSEC: return 0x1F4; - case CARDEVICE_SOR_SAFE: return 0; - case CARDEVICE_SOR0: return 0; - case CARDEVICE_SOR1: return 0x410; - case CARDEVICE_KFUSE: return 0; - case CARDEVICE_CL_DVFS: return 0; - case CARDEVICE_CORESIGHT: return 0x1D4; - case CARDEVICE_MSELECT: return 0x3B4; - case CARDEVICE_ACTMON: return 0x3E8; - case CARDEVICE_BPMP: return 0; - default: generic_panic(); - } -} - -static inline uint32_t get_clk_source_val(CarDevice dev) { - switch (dev) { - case CARDEVICE_UARTA: return 0; - case CARDEVICE_UARTB: return 0; - case CARDEVICE_UARTC: return 0; - case CARDEVICE_I2C1: return 6; - case CARDEVICE_I2C5: return 6; - case CARDEVICE_TZRAM: return 0; - case CARDEVICE_SE: return 0; - case CARDEVICE_HOST1X: return 4; - case CARDEVICE_TSEC: return 0; - case CARDEVICE_SOR_SAFE: return 0; - case CARDEVICE_SOR0: return 0; - case CARDEVICE_SOR1: return 0; - case CARDEVICE_KFUSE: return 0; - case CARDEVICE_CL_DVFS: return 0; - case CARDEVICE_CORESIGHT: return 0; - case CARDEVICE_MSELECT: return 0; - case CARDEVICE_ACTMON: return 6; - case CARDEVICE_BPMP: return 0; - default: generic_panic(); - } -} - -static inline uint32_t get_clk_source_div(CarDevice dev) { - switch (dev) { - case CARDEVICE_UARTA: return 0; - case CARDEVICE_UARTB: return 0; - case CARDEVICE_UARTC: return 0; - case CARDEVICE_I2C1: return 0; - case CARDEVICE_I2C5: return 0; - case CARDEVICE_TZRAM: return 0; - case CARDEVICE_SE: return 0; - case CARDEVICE_HOST1X: return 3; - case CARDEVICE_TSEC: return 2; - case CARDEVICE_SOR_SAFE: return 0; - case CARDEVICE_SOR0: return 0; - case CARDEVICE_SOR1: return 2; - case CARDEVICE_KFUSE: return 0; - case CARDEVICE_CL_DVFS: return 0; - case CARDEVICE_CORESIGHT: return 4; - case CARDEVICE_MSELECT: return 6; - case CARDEVICE_ACTMON: return 0; - case CARDEVICE_BPMP: return 0; - default: generic_panic(); - } -} - -static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298}; -static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4}; - -void clk_enable(CarDevice dev) { - uint32_t clk_source_reg; - if ((clk_source_reg = get_clk_source_reg(dev))) { - MAKE_CAR_REG(clk_source_reg) = (get_clk_source_val(dev) << 29) | get_clk_source_div(dev); - } - MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F); -} - -void clk_disable(CarDevice dev) { - MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F)); -} - -void rst_enable(CarDevice dev) { - MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F); -} - -void rst_disable(CarDevice dev) { - MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F)); -} - -void clkrst_enable(CarDevice dev) { - clk_enable(dev); - rst_disable(dev); -} - -void clkrst_disable(CarDevice dev) { - rst_enable(dev); - clk_disable(dev); -} - -void clkrst_reboot(CarDevice dev) { - clkrst_disable(dev); - if (dev == CARDEVICE_KFUSE) { - /* Workaround for KFUSE clock. */ - clk_enable(dev); - udelay(100); - rst_disable(dev); - udelay(200); - } else { - clkrst_enable(dev); - } -} - -void clkrst_enable_fuse_regs(bool enable) { - volatile tegra_car_t *car = car_get_regs(); - car->misc_clk_enb = ((car->misc_clk_enb & 0xEFFFFFFF) | ((enable & 1) << 28)); -} diff --git a/sept/sept-primary/src/car.h b/sept/sept-primary/src/car.h deleted file mode 100644 index 97dc3f792..000000000 --- a/sept/sept-primary/src/car.h +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_CAR_H -#define FUSEE_CAR_H - -#include -#include - -#define CAR_BASE 0x60006000 -#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n) - -#define CLK_L_SDMMC1 (1 << 14) -#define CLK_L_SDMMC2 (1 << 9) -#define CLK_U_SDMMC3 (1 << 5) -#define CLK_L_SDMMC4 (1 << 15) - -#define CLK_SOURCE_MASK (0b111 << 29) -#define CLK_SOURCE_FIRST (0b000 << 29) -#define CLK_DIVIDER_MASK (0xff << 0) -#define CLK_DIVIDER_UNITY (0x00 << 0) - -#define NUM_CAR_BANKS 7 - -/* Clock and reset devices. */ -typedef enum { - CARDEVICE_BPMP = ((0 << 5) | 0x1), - CARDEVICE_UARTA = ((0 << 5) | 0x6), - CARDEVICE_UARTB = ((0 << 5) | 0x7), - CARDEVICE_I2C1 = ((0 << 5) | 0xC), - CARDEVICE_USBD = ((0 << 5) | 0x16), - CARDEVICE_HOST1X = ((0 << 5) | 0x1C), - CARDEVICE_AHBDMA = ((1 << 5) | 0x1), - CARDEVICE_APBDMA = ((1 << 5) | 0x2), - CARDEVICE_KFUSE = ((1 << 5) | 0x8), - CARDEVICE_I2C5 = ((1 << 5) | 0xF), - CARDEVICE_UARTC = ((1 << 5) | 0x17), - CARDEVICE_USB2 = ((1 << 5) | 0x1A), - CARDEVICE_CORESIGHT = ((2 << 5) | 0x9), - CARDEVICE_TSEC = ((2 << 5) | 0x13), - CARDEVICE_MSELECT = ((3 << 5) | 0x8), - CARDEVICE_ACTMON = ((3 << 5) | 0x17), - CARDEVICE_TZRAM = ((3 << 5) | 0x1E), - CARDEVICE_SE = ((3 << 5) | 0x1F), - CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B), - CARDEVICE_SOR0 = ((5 << 5) | 0x16), - CARDEVICE_SOR1 = ((5 << 5) | 0x17), - CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E), -} CarDevice; - -/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -typedef struct { - uint32_t rst_src; /* _RST_SOURCE_0, 0x00 */ - - /* _RST_DEVICES_L/H/U_0 0x4-0xc */ - uint32_t rst_dev_l; - uint32_t rst_dev_h; - uint32_t rst_dev_u; - - /* _CLK_OUT_ENB_L/H/U_0 0x10-0x18 */ - uint32_t clk_out_enb_l; - uint32_t clk_out_enb_h; - uint32_t clk_out_enb_u; - - uint32_t _0x1C; - uint32_t cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ - uint32_t super_cclk_div; /* _SUPER_CCLK_DIVIDER_0, 0x24 */ - uint32_t sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ - uint32_t super_sclk_div; /* _SUPER_SCLK_DIVIDER_0, 0x2c */ - uint32_t clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ - uint32_t prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ - uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0, 0x38 */ - uint32_t _0x3C; - uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0, 0x40 */ - uint32_t clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ - uint32_t misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ - uint32_t clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4c */ - uint32_t osc_ctrl; /* _OSC_CTRL_0, 0x50 */ - uint32_t pll_lfsr; /* _PLL_LFSR_0, 0x54 */ - uint32_t osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ - uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0, 0x5c */ - uint32_t _0x60[2]; - uint32_t plle_ss_cntl; /* _PLLE_SS_CNTL_0, 0x68 */ - uint32_t plle_misc1; /* _PLLE_MISC1_0, 0x6c */ - uint32_t _0x70[4]; - - /* PLLC 0x80-0x8c */ - uint32_t pllc_base; - uint32_t pllc_out; - uint32_t pllc_misc0; - uint32_t pllc_misc1; - - /* PLLM 0x90-0x9c */ - uint32_t pllm_base; - uint32_t pllm_out; - uint32_t pllm_misc1; - uint32_t pllm_misc2; - - /* PLLP 0xa0-0xac */ - uint32_t pllp_base; - uint32_t pllp_outa; - uint32_t pllp_outb; - uint32_t pllp_misc; - - /* PLLA 0xb0-0xbc */ - uint32_t plla_base; - uint32_t plla_out; - uint32_t plla_misc0; - uint32_t plla_misc1; - - /* PLLU 0xc0-0xcc */ - uint32_t pllu_base; - uint32_t pllu_out; - uint32_t pllu_misc1; - uint32_t pllu_misc2; - - /* PLLD 0xd0-0xdc */ - uint32_t plld_base; - uint32_t plld_out; - uint32_t plld_misc1; - uint32_t plld_misc2; - - /* PLLX 0xe0-0xe4 */ - uint32_t pllx_base; - uint32_t pllx_misc; - - /* PLLE 0xe8-0xf4 */ - uint32_t plle_base; - uint32_t plle_misc; - uint32_t plle_ss_cntl1; - uint32_t plle_ss_cntl2; - - uint32_t lvl2_clk_gate_ovra; /* _LVL2_CLK_GATE_OVRA_0, 0xf8 */ - uint32_t lvl2_clk_gate_ovrb; /* _LVL2_CLK_GATE_OVRB_0, 0xfc */ - - uint32_t clk_source_i2s2; /* _CLK_SOURCE_I2S2_0, 0x100 */ - uint32_t clk_source_i2s3; /* _CLK_SOURCE_I2S3_0, 0x104 */ - uint32_t clk_source_spdif_out; /* _CLK_SOURCE_SPDIF_OUT_0, 0x108 */ - uint32_t clk_source_spdif_in; /* _CLK_SOURCE_SPDIF_IN_0, 0x10c */ - uint32_t clk_source_pwm; /* _CLK_SOURCE_PWM_0, 0x110 */ - uint32_t _0x114; - uint32_t clk_source_spi2; /* _CLK_SOURCE_SPI2_0, 0x118 */ - uint32_t clk_source_spi3; /* _CLK_SOURCE_SPI3_0, 0x11c */ - uint32_t _0x120; - uint32_t clk_source_i2c1; /* _CLK_SOURCE_I2C1_0, 0x124 */ - uint32_t clk_source_i2c5; /* _CLK_SOURCE_I2C5_0, 0x128 */ - uint32_t _0x12c[2]; - uint32_t clk_source_spi1; /* _CLK_SOURCE_SPI1_0, 0x134 */ - uint32_t clk_source_disp1; /* _CLK_SOURCE_DISP1_0, 0x138 */ - uint32_t clk_source_disp2; /* _CLK_SOURCE_DISP2_0, 0x13c */ - uint32_t _0x140; - uint32_t clk_source_isp; /* _CLK_SOURCE_ISP_0, 0x144 */ - uint32_t clk_source_vi; /* _CLK_SOURCE_VI_0, 0x148 */ - uint32_t _0x14c; - uint32_t clk_source_sdmmc1; /* _CLK_SOURCE_SDMMC1_0, 0x150 */ - uint32_t clk_source_sdmmc2; /* _CLK_SOURCE_SDMMC2_0, 0x154 */ - uint32_t _0x158[3]; - uint32_t clk_source_sdmmc4; /* _CLK_SOURCE_SDMMC4_0, 0x164 */ - uint32_t _0x168[4]; - uint32_t clk_source_uarta; /* _CLK_SOURCE_UARTA_0, 0x178 */ - uint32_t clk_source_uartb; /* _CLK_SOURCE_UARTB_0, 0x17c */ - uint32_t clk_source_host1x; /* _CLK_SOURCE_HOST1X_0, 0x180 */ - uint32_t _0x184[5]; - uint32_t clk_source_i2c2; /* _CLK_SOURCE_I2C2_0, 0x198 */ - uint32_t clk_source_emc; /* _CLK_SOURCE_EMC_0, 0x19c */ - uint32_t clk_source_uartc; /* _CLK_SOURCE_UARTC_0, 0x1a0 */ - uint32_t _0x1a4; - uint32_t clk_source_vi_sensor; /* _CLK_SOURCE_VI_SENSOR_0, 0x1a8 */ - uint32_t _0x1ac[2]; - uint32_t clk_source_spi4; /* _CLK_SOURCE_SPI4_0, 0x1b4 */ - uint32_t clk_source_i2c3; /* _CLK_SOURCE_I2C3_0, 0x1b8 */ - uint32_t clk_source_sdmmc3; /* _CLK_SOURCE_SDMMC3_0, 0x1bc */ - uint32_t clk_source_uartd; /* _CLK_SOURCE_UARTD_0, 0x1c0 */ - uint32_t _0x1c4[2]; - uint32_t clk_source_owr; /* _CLK_SOURCE_OWR_0, 0x1cc */ - uint32_t _0x1d0; - uint32_t clk_source_csite; /* _CLK_SOURCE_CSITE_0, 0x1d4 */ - uint32_t clk_source_i2s1; /* _CLK_SOURCE_I2S1_0, 0x1d8 */ - uint32_t clk_source_dtv; /* _CLK_SOURCE_DTV_0, 0x1dc */ - uint32_t _0x1e0[5]; - uint32_t clk_source_tsec; /* _CLK_SOURCE_TSEC_0, 0x1f4 */ - uint32_t _0x1f8; - - uint32_t clk_spare2; /* _CLK_SPARE2_0, 0x1fc */ - uint32_t _0x200[32]; - - uint32_t clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ - uint32_t clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ - uint32_t clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ - - uint32_t rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ - uint32_t rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ - uint32_t rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - - uint32_t clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ - uint32_t clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */ - uint32_t clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */ - - uint32_t rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */ - uint32_t rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */ - uint32_t rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */ - - uint32_t _0x2b0[17]; - uint32_t dfll_base; /* _DFLL_BASE_0, 0x2f4 */ - uint32_t _0x2f8[2]; - - /* _RST_DEV_L/H/U_SET_0 0x300-0x314 */ - uint32_t rst_dev_l_set; - uint32_t rst_dev_l_clr; - uint32_t rst_dev_h_set; - uint32_t rst_dev_h_clr; - uint32_t rst_dev_u_set; - uint32_t rst_dev_u_clr; - - uint32_t _0x318[2]; - - /* _CLK_ENB_L/H/U_CLR_0 0x320-0x334 */ - uint32_t clk_enb_l_set; - uint32_t clk_enb_l_clr; - uint32_t clk_enb_h_set; - uint32_t clk_enb_h_clr; - uint32_t clk_enb_u_set; - uint32_t clk_enb_u_clr; - - uint32_t _0x338; - uint32_t ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD_0, 0x33c */ - uint32_t rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ - uint32_t rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ - - /* Additional (T30) registers */ - uint32_t clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ - uint32_t clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ - - uint32_t _0x350[2]; - uint32_t rst_dev_v; /* _RST_DEVICES_V_0, 0x358 */ - uint32_t rst_dev_w; /* _RST_DEVICES_W_0, 0x35c */ - uint32_t clk_out_enb_v; /* _CLK_OUT_ENB_V_0, 0x360 */ - uint32_t clk_out_enb_w; /* _CLK_OUT_ENB_W_0, 0x364 */ - uint32_t cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ - uint32_t super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36c */ - uint32_t cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ - uint32_t super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ - uint32_t clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ - uint32_t clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37c */ - uint32_t cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - uint32_t cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ - uint32_t cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ - uint32_t _0x38c[5]; - uint32_t lvl2_clk_gate_ovrc; /* _LVL2_CLK_GATE_OVRC, 0x3a0 */ - uint32_t lvl2_clk_gate_ovrd; /* _LVL2_CLK_GATE_OVRD, 0x3a4 */ - uint32_t _0x3a8[2]; - - uint32_t _0x3b0; - uint32_t clk_source_mselect; /* _CLK_SOURCE_MSELECT_0, 0x3b4 */ - uint32_t clk_source_tsensor; /* _CLK_SOURCE_TSENSOR_0, 0x3b8 */ - uint32_t clk_source_i2s4; /* _CLK_SOURCE_I2S4_0, 0x3bc */ - uint32_t clk_source_i2s5; /* _CLK_SOURCE_I2S5_0, 0x3c0 */ - uint32_t clk_source_i2c4; /* _CLK_SOURCE_I2C4_0, 0x3c4 */ - uint32_t _0x3c8[2]; - uint32_t clk_source_ahub; /* _CLK_SOURCE_AHUB_0, 0x3d0 */ - uint32_t _0x3d4[4]; - uint32_t clk_source_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X_0, 0x3e4 */ - uint32_t clk_source_actmon; /* _CLK_SOURCE_ACTMON_0, 0x3e8 */ - uint32_t clk_source_extperiph1; /* _CLK_SOURCE_EXTPERIPH1_0, 0x3ec */ - uint32_t clk_source_extperiph2; /* _CLK_SOURCE_EXTPERIPH2_0, 0x3f0 */ - uint32_t clk_source_extperiph3; /* _CLK_SOURCE_EXTPERIPH3_0, 0x3f4 */ - uint32_t _0x3f8; - uint32_t clk_source_i2c_slow; /* _CLK_SOURCE_I2C_SLOW_0, 0x3fc */ - uint32_t clk_source_sys; /* _CLK_SOURCE_SYS_0, 0x400 */ - uint32_t clk_source_ispb; /* _CLK_SOURCE_ISPB_0, 0x404 */ - uint32_t _0x408[2]; - uint32_t clk_source_sor1; /* _CLK_SOURCE_SOR1_0, 0x410 */ - uint32_t clk_source_sor0; /* _CLK_SOURCE_SOR0_0, 0x414 */ - uint32_t _0x418[2]; - uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */ - uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */ - uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */ - uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */ - - /* _RST_DEV_V/W_SET_0 0x430-0x43c */ - uint32_t rst_dev_v_set; - uint32_t rst_dev_v_clr; - uint32_t rst_dev_w_set; - uint32_t rst_dev_w_clr; - - /* _CLK_ENB_V/W_CLR_0 0x440-0x44c */ - uint32_t clk_enb_v_set; - uint32_t clk_enb_v_clr; - uint32_t clk_enb_w_set; - uint32_t clk_enb_w_clr; - - /* Additional (T114+) registers */ - uint32_t rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ - uint32_t rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ - uint32_t rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ - uint32_t rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45c */ - uint32_t clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ - uint32_t clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ - uint32_t clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ - uint32_t clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46c */ - uint32_t cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ - uint32_t _0x474; - uint32_t intstatus; /* _INTSTATUS_0, 0x478 */ - uint32_t intmask; /* _INTMASK_0, 0x47c */ - uint32_t utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ - uint32_t utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ - uint32_t utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ - - uint32_t plle_aux; /* _PLLE_AUX_0, 0x48c */ - uint32_t sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ - uint32_t sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ - uint32_t pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ - - uint32_t prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49c */ - uint32_t audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4a0 */ - uint32_t audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4a4 */ - uint32_t audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4a8 */ - uint32_t audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4ac */ - uint32_t audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4b0 */ - uint32_t audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4b4 */ - - uint32_t plld2_base; /* _PLLD2_BASE_0, 0x4b8 */ - uint32_t plld2_misc; /* _PLLD2_MISC_0, 0x4bc */ - uint32_t utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4c0 */ - uint32_t pllrefe_base; /* _PLLREFE_BASE_0, 0x4c4 */ - uint32_t pllrefe_misc; /* _PLLREFE_MISC_0, 0x4c8 */ - uint32_t pllrefe_out; /* _PLLREFE_OUT_0, 0x4cc */ - uint32_t cpu_finetrim_byp; /* _CPU_FINETRIM_BYP_0, 0x4d0 */ - uint32_t cpu_finetrim_select; /* _CPU_FINETRIM_SELECT_0, 0x4d4 */ - uint32_t cpu_finetrim_dr; /* _CPU_FINETRIM_DR_0, 0x4d8 */ - uint32_t cpu_finetrim_df; /* _CPU_FINETRIM_DF_0, 0x4dc */ - uint32_t cpu_finetrim_f; /* _CPU_FINETRIM_F_0, 0x4e0 */ - uint32_t cpu_finetrim_r; /* _CPU_FINETRIM_R_0, 0x4e4 */ - uint32_t pllc2_base; /* _PLLC2_BASE_0, 0x4e8 */ - uint32_t pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4ec */ - uint32_t pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4f0 */ - uint32_t pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4f4 */ - uint32_t pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4f8 */ - uint32_t pllc3_base; /* _PLLC3_BASE_0, 0x4fc */ - uint32_t pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ - uint32_t pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ - uint32_t pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ - uint32_t pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50c */ - uint32_t pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ - uint32_t pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ - uint32_t pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ - uint32_t xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51c */ - uint32_t xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ - uint32_t plle_aux1; /* _PLLE_AUX1_0, 0x524 */ - uint32_t pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ - uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52c */ - uint32_t pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ - uint32_t xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ - uint32_t _0x538; - uint32_t clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53c */ - uint32_t clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ - uint32_t clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ - uint32_t pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ - uint32_t pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54c */ - uint32_t pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ - uint32_t lvl2_clk_gate_ovre; /* _LVL2_CLK_GATE_OVRE, 0x554 */ - uint32_t super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ - uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55c */ - uint32_t audio_sync_clk_dmic1; /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */ - uint32_t audio_sync_clk_dmic2; /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */ - - uint32_t _0x568[2]; - uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG, 0x570 */ - uint32_t plld2_ss_ctrl1; /* _PLLD2_SS_CTRL1_0, 0x574 */ - uint32_t plld2_ss_ctrl2; /* _PLLD2_SS_CTRL2_0, 0x578 */ - uint32_t _0x57c[5]; - - uint32_t plldp_base; /* _PLLDP_BASE, 0x590*/ - uint32_t plldp_misc; /* _PLLDP_MISC, 0x594 */ - uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ - uint32_t plldp_ss_ctrl1; /* _PLLDP_SS_CTRL1_0, 0x59c */ - uint32_t plldp_ss_ctrl2; /* _PLLDP_SS_CTRL2_0, 0x5a0 */ - uint32_t pllc4_base; /* _PLLC4_BASE_0, 0x5a4 */ - uint32_t pllc4_misc; /* _PLLC4_MISC_0, 0x5a8 */ - uint32_t _0x5ac[6]; - uint32_t clk_spare0; /* _CLK_SPARE0_0, 0x5c4 */ - uint32_t clk_spare1; /* _CLK_SPARE1_0, 0x5c8 */ - uint32_t gpu_isob_ctrl; /* _GPU_ISOB_CTRL_0, 0x5cc */ - uint32_t pllc_misc2; /* _PLLC_MISC_2_0, 0x5d0 */ - uint32_t pllc_misc3; /* _PLLC_MISC_3_0, 0x5d4 */ - uint32_t plla_misc2; /* _PLLA_MISC2_0, 0x5d8 */ - uint32_t _0x5dc[2]; - uint32_t pllc4_out; /* _PLLC4_OUT_0, 0x5e4 */ - uint32_t pllmb_base; /* _PLLMB_BASE_0, 0x5e8 */ - uint32_t pllmb_misc1; /* _PLLMB_MISC1_0, 0x5ec */ - uint32_t pllx_misc4; /* _PLLX_MISC_4_0, 0x5f0 */ - uint32_t pllx_misc5; /* _PLLX_MISC_5_0, 0x5f4 */ - uint32_t _0x5f8[2]; - - uint32_t clk_source_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST_0, 0x600 */ - uint32_t clk_source_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON_0, 0x604 */ - uint32_t clk_source_xusb_fs; /* _CLK_SOURCE_XUSB_FS_0, 0x608 */ - uint32_t clk_source_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV_0, 0x60c */ - uint32_t clk_source_xusb_ss; /* _CLK_SOURCE_XUSB_SS_0, 0x610 */ - uint32_t clk_source_cilab; /* _CLK_SOURCE_CILAB_0, 0x614 */ - uint32_t clk_source_cilcd; /* _CLK_SOURCE_CILCD_0, 0x618 */ - uint32_t clk_source_cilef; /* _CLK_SOURCE_CILEF_0, 0x61c */ - uint32_t clk_source_dsia_lp; /* _CLK_SOURCE_DSIA_LP_0, 0x620 */ - uint32_t clk_source_dsib_lp; /* _CLK_SOURCE_DSIB_LP_0, 0x624 */ - uint32_t clk_source_entropy; /* _CLK_SOURCE_ENTROPY_0, 0x628 */ - uint32_t clk_source_dvfs_ref; /* _CLK_SOURCE_DVFS_REF_0, 0x62c */ - uint32_t clk_source_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC_0, 0x630 */ - uint32_t _0x634[3]; - uint32_t clk_source_emc_latency; /* _CLK_SOURCE_EMC_LATENCY_0, 0x640 */ - uint32_t clk_source_soc_therm; /* _CLK_SOURCE_SOC_THERM_0, 0x644 */ - uint32_t _0x648; - uint32_t clk_source_dmic1; /* _CLK_SOURCE_DMIC1_0, 0x64c */ - uint32_t clk_source_dmic2; /* _CLK_SOURCE_DMIC2_0, 0x650 */ - uint32_t _0x654; - uint32_t clk_source_vi_sensor2; /* _CLK_SOURCE_VI_SENSOR2_0, 0x658 */ - uint32_t clk_source_i2c6; /* _CLK_SOURCE_I2C6_0, 0x65c */ - uint32_t clk_source_mipibif; /* _CLK_SOURCE_MIPIBIF_0, 0x660 */ - uint32_t clk_source_emc_dll; /* _CLK_SOURCE_EMC_DLL_0, 0x664 */ - uint32_t _0x668; - uint32_t clk_source_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIPI_CAL_0, 0x66c */ - uint32_t _0x670[2]; - uint32_t clk_source_vic; /* _CLK_SOURCE_VIC_0, 0x678 */ - - uint32_t pllp_outc; /* _PLLP_OUTC_0, 0x67c */ - uint32_t pllp_misc1; /* _PLLP_MISC1_0, 0x680 */ - uint32_t _0x684[2]; - uint32_t emc_div_clk_shaper_ctrl; /* _EMC_DIV_CLK_SHAPER_CTRL_0, 0x68c */ - uint32_t emc_pllc_shaper_ctrl; /* _EMC_PLLC_SHAPER_CTRL_0, 0x690 */ - - uint32_t clk_source_sdmmc_legacy_tm; /* _CLK_SOURCE_SDMMC_LEGACY_TM_0, 0x694 */ - uint32_t clk_source_nvdec; /* _CLK_SOURCE_NVDEC_0, 0x698 */ - uint32_t clk_source_nvjpg; /* _CLK_SOURCE_NVJPG_0, 0x69c */ - uint32_t clk_source_nvenc; /* _CLK_SOURCE_NVENC_0, 0x6a0 */ - - uint32_t plla1_base; /* _PLLA1_BASE_0, 0x6a4 */ - uint32_t plla1_misc0; /* _PLLA1_MISC_0_0, 0x6a8 */ - uint32_t plla1_misc1; /* _PLLA1_MISC_1_0, 0x6ac */ - uint32_t plla1_misc2; /* _PLLA1_MISC_2_0, 0x6b0 */ - uint32_t plla1_misc3; /* _PLLA1_MISC_3_0, 0x6b4 */ - uint32_t audio_sync_clk_dmic3; /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */ - - uint32_t clk_source_dmic3; /* _CLK_SOURCE_DMIC3_0, 0x6bc */ - uint32_t clk_source_ape; /* _CLK_SOURCE_APE_0, 0x6c0 */ - uint32_t clk_source_qspi; /* _CLK_SOURCE_QSPI_0, 0x6c4 */ - uint32_t clk_source_vi_i2c; /* _CLK_SOURCE_VI_I2C_0, 0x6c8 */ - uint32_t clk_source_usb2_hsic_trk; /* _CLK_SOURCE_USB2_HSIC_TRK_0, 0x6cc */ - uint32_t clk_source_pex_sata_usb_rx_byp; /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0, 0x6d0 */ - uint32_t clk_source_maud; /* _CLK_SOURCE_MAUD_0, 0x6d4 */ - uint32_t clk_source_tsecb; /* _CLK_SOURCE_TSECB_0, 0x6d8 */ - - uint32_t clk_cpug_misc1; /* _CLK_CPUG_MISC1_0, 0x6dc */ - uint32_t aclk_burst_policy; /* _ACLK_BURST_POLICY_0, 0x6e0 */ - uint32_t super_aclk_divider; /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */ - - uint32_t nvenc_super_clk_divider; /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */ - uint32_t vi_super_clk_divider; /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */ - uint32_t vic_super_clk_divider; /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */ - uint32_t nvdec_super_clk_divider; /* _NVDEC_SUPER_CLK_DIVIDER_0, 0x6f4 */ - uint32_t isp_super_clk_divider; /* _ISP_SUPER_CLK_DIVIDER_0, 0x6f8 */ - uint32_t ispb_super_clk_divider; /* _ISPB_SUPER_CLK_DIVIDER_0, 0x6fc */ - uint32_t nvjpg_super_clk_divider; /* _NVJPG_SUPER_CLK_DIVIDER_0, 0x700 */ - uint32_t se_super_clk_divider; /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */ - uint32_t tsec_super_clk_divider; /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */ - uint32_t tsecb_super_clk_divider; /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */ - - uint32_t clk_source_uartape; /* _CLK_SOURCE_UARTAPE_0, 0x710 */ - uint32_t clk_cpug_misc2; /* _CLK_CPUG_MISC2_0, 0x714 */ - uint32_t clk_source_dbgapb; /* _CLK_SOURCE_DBGAPB_0, 0x718 */ - uint32_t clk_ccplex_cc4_ret_clk_enb; /* _CLK_CCPLEX_CC4_RET_CLK_ENB_0, 0x71c */ - uint32_t actmon_cpu_clk; /* _ACTMON_CPU_CLK_0, 0x720 */ - uint32_t clk_source_emc_safe; /* _CLK_SOURCE_EMC_SAFE_0, 0x724 */ - uint32_t sdmmc2_pllc4_out0_shaper_ctrl; /* _SDMMC2_PLLC4_OUT0_SHAPER_CTRL_0, 0x728 */ - uint32_t sdmmc2_pllc4_out1_shaper_ctrl; /* _SDMMC2_PLLC4_OUT1_SHAPER_CTRL_0, 0x72c */ - uint32_t sdmmc2_pllc4_out2_shaper_ctrl; /* _SDMMC2_PLLC4_OUT2_SHAPER_CTRL_0, 0x730 */ - uint32_t sdmmc2_div_clk_shaper_ctrl; /* _SDMMC2_DIV_CLK_SHAPER_CTRL_0, 0x734 */ - uint32_t sdmmc4_pllc4_out0_shaper_ctrl; /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */ - uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */ - uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */ - uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */ -} tegra_car_t; - -static inline volatile tegra_car_t *car_get_regs(void) { - return (volatile tegra_car_t *)CAR_BASE; -} - -void clk_enable(CarDevice dev); -void clk_disable(CarDevice dev); -void rst_enable(CarDevice dev); -void rst_disable(CarDevice dev); - -void clkrst_enable(CarDevice dev); -void clkrst_disable(CarDevice dev); -void clkrst_reboot(CarDevice dev); - -void clkrst_enable_fuse_regs(bool enable); - -#endif diff --git a/sept/sept-primary/src/di.h b/sept/sept-primary/src/di.h deleted file mode 100644 index dc4ccb1a2..000000000 --- a/sept/sept-primary/src/di.h +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_DI_H_ -#define FUSEE_DI_H_ - -#include -#include - -#define HOST1X_BASE 0x50000000 -#define DI_BASE 0x54200000 -#define DSI_BASE 0x54300000 -#define VIC_BASE 0x54340000 -#define MIPI_CAL_BASE 0x700E3000 -#define MAKE_HOST1X_REG(n) MAKE_REG32(HOST1X_BASE + n) -#define MAKE_DI_REG(n) MAKE_REG32(DI_BASE + n * 4) -#define MAKE_DSI_REG(n) MAKE_REG32(DSI_BASE + n * 4) -#define MAKE_MIPI_CAL_REG(n) MAKE_REG32(MIPI_CAL_BASE + n) -#define MAKE_VIC_REG(n) MAKE_REG32(VIC_BASE + n) - -/* Display registers. */ -#define DC_CMD_GENERAL_INCR_SYNCPT 0x00 - -#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01 -#define SYNCPT_CNTRL_NO_STALL (1 << 8) -#define SYNCPT_CNTRL_SOFT_RESET (1 << 0) - -#define DC_CMD_CONT_SYNCPT_VSYNC 0x28 -#define SYNCPT_VSYNC_ENABLE (1 << 8) - -#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 - -#define DC_CMD_DISPLAY_COMMAND 0x32 -#define DISP_CTRL_MODE_STOP (0 << 5) -#define DISP_CTRL_MODE_C_DISPLAY (1 << 5) -#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) -#define DISP_CTRL_MODE_MASK (3 << 5) - -#define DC_CMD_DISPLAY_POWER_CONTROL 0x36 -#define PW0_ENABLE (1 << 0) -#define PW1_ENABLE (1 << 2) -#define PW2_ENABLE (1 << 4) -#define PW3_ENABLE (1 << 6) -#define PW4_ENABLE (1 << 8) -#define PM0_ENABLE (1 << 16) -#define PM1_ENABLE (1 << 18) - -#define DC_CMD_INT_MASK 0x38 -#define DC_CMD_INT_ENABLE 0x39 - -#define DC_CMD_STATE_ACCESS 0x40 -#define READ_MUX (1 << 0) -#define WRITE_MUX (1 << 2) - -#define DC_CMD_STATE_CONTROL 0x41 -#define GENERAL_ACT_REQ (1 << 0) -#define WIN_A_ACT_REQ (1 << 1) -#define WIN_B_ACT_REQ (1 << 2) -#define WIN_C_ACT_REQ (1 << 3) -#define CURSOR_ACT_REQ (1 << 7) -#define GENERAL_UPDATE (1 << 8) -#define WIN_A_UPDATE (1 << 9) -#define WIN_B_UPDATE (1 << 10) -#define WIN_C_UPDATE (1 << 11) -#define CURSOR_UPDATE (1 << 15) -#define NC_HOST_TRIG (1 << 24) - -#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42 -#define WINDOW_A_SELECT (1 << 4) -#define WINDOW_B_SELECT (1 << 5) -#define WINDOW_C_SELECT (1 << 6) - -#define DC_CMD_REG_ACT_CONTROL 0x043 - -#define DC_COM_CRC_CONTROL 0x300 -#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) -#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) - -#define DC_COM_DSC_TOP_CTL 0x33E - -#define DC_DISP_DISP_WIN_OPTIONS 0x402 -#define HDMI_ENABLE (1 << 30) -#define DSI_ENABLE (1 << 29) -#define SOR1_TIMING_CYA (1 << 27) -#define SOR1_ENABLE (1 << 26) -#define SOR_ENABLE (1 << 25) -#define CURSOR_ENABLE (1 << 16) - -#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 -#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 -#define DC_DISP_DISP_TIMING_OPTIONS 0x405 -#define DC_DISP_REF_TO_SYNC 0x406 -#define DC_DISP_SYNC_WIDTH 0x407 -#define DC_DISP_BACK_PORCH 0x408 -#define DC_DISP_ACTIVE 0x409 -#define DC_DISP_FRONT_PORCH 0x40A - -#define DC_DISP_DISP_CLOCK_CONTROL 0x42E -#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) -#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) -#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) -#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) -#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) -#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) -#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) -#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) -#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) -#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) -#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) -#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) -#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) -#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) - -#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F -#define DISP_DATA_FORMAT_DF1P1C (0 << 0) -#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) -#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) -#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) -#define DISP_DATA_FORMAT_DF2S (4 << 0) -#define DISP_DATA_FORMAT_DF3S (5 << 0) -#define DISP_DATA_FORMAT_DFSPI (6 << 0) -#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) -#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) -#define DISP_ALIGNMENT_MSB (0 << 8) -#define DISP_ALIGNMENT_LSB (1 << 8) -#define DISP_ORDER_RED_BLUE (0 << 9) -#define DISP_ORDER_BLUE_RED (1 << 9) - -#define DC_DISP_DISP_COLOR_CONTROL 0x430 -#define DITHER_CONTROL_MASK (3 << 8) -#define DITHER_CONTROL_DISABLE (0 << 8) -#define DITHER_CONTROL_ORDERED (2 << 8) -#define DITHER_CONTROL_ERRDIFF (3 << 8) -#define BASE_COLOR_SIZE_MASK (0xf << 0) -#define BASE_COLOR_SIZE_666 (0 << 0) -#define BASE_COLOR_SIZE_111 (1 << 0) -#define BASE_COLOR_SIZE_222 (2 << 0) -#define BASE_COLOR_SIZE_333 (3 << 0) -#define BASE_COLOR_SIZE_444 (4 << 0) -#define BASE_COLOR_SIZE_555 (5 << 0) -#define BASE_COLOR_SIZE_565 (6 << 0) -#define BASE_COLOR_SIZE_332 (7 << 0) -#define BASE_COLOR_SIZE_888 (8 << 0) - -#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 -#define SC1_H_QUALIFIER_NONE (1 << 16) -#define SC0_H_QUALIFIER_NONE (1 << 0) - -#define DC_DISP_DATA_ENABLE_OPTIONS 0x432 -#define DE_SELECT_ACTIVE_BLANK (0 << 0) -#define DE_SELECT_ACTIVE (1 << 0) -#define DE_SELECT_ACTIVE_IS (2 << 0) -#define DE_CONTROL_ONECLK (0 << 2) -#define DE_CONTROL_NORMAL (1 << 2) -#define DE_CONTROL_EARLY_EXT (2 << 2) -#define DE_CONTROL_EARLY (3 << 2) -#define DE_CONTROL_ACTIVE_BLANK (4 << 2) - -#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 -#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4 - -#define DC_WIN_CSC_YOF 0x611 -#define DC_WIN_CSC_KYRGB 0x612 -#define DC_WIN_CSC_KUR 0x613 -#define DC_WIN_CSC_KVR 0x614 -#define DC_WIN_CSC_KUG 0x615 -#define DC_WIN_CSC_KVG 0x616 -#define DC_WIN_CSC_KUB 0x617 -#define DC_WIN_CSC_KVB 0x618 -#define DC_WIN_AD_WIN_OPTIONS 0xB80 -#define DC_WIN_BD_WIN_OPTIONS 0xD80 -#define DC_WIN_CD_WIN_OPTIONS 0xF80 - -/* The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER). */ -#define DC_WIN_WIN_OPTIONS 0x700 -#define H_DIRECTION (1 << 0) -#define V_DIRECTION (1 << 2) -#define COLOR_EXPAND (1 << 6) -#define CSC_ENABLE (1 << 18) -#define WIN_ENABLE (1 << 30) - -#define DC_WIN_COLOR_DEPTH 0x703 -#define WIN_COLOR_DEPTH_P1 0x0 -#define WIN_COLOR_DEPTH_P2 0x1 -#define WIN_COLOR_DEPTH_P4 0x2 -#define WIN_COLOR_DEPTH_P8 0x3 -#define WIN_COLOR_DEPTH_B4G4R4A4 0x4 -#define WIN_COLOR_DEPTH_B5G5R5A 0x5 -#define WIN_COLOR_DEPTH_B5G6R5 0x6 -#define WIN_COLOR_DEPTH_AB5G5R5 0x7 -#define WIN_COLOR_DEPTH_B8G8R8A8 0xC -#define WIN_COLOR_DEPTH_R8G8B8A8 0xD -#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE -#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF -#define WIN_COLOR_DEPTH_YCbCr422 0x10 -#define WIN_COLOR_DEPTH_YUV422 0x11 -#define WIN_COLOR_DEPTH_YCbCr420P 0x12 -#define WIN_COLOR_DEPTH_YUV420P 0x13 -#define WIN_COLOR_DEPTH_YCbCr422P 0x14 -#define WIN_COLOR_DEPTH_YUV422P 0x15 -#define WIN_COLOR_DEPTH_YCbCr422R 0x16 -#define WIN_COLOR_DEPTH_YUV422R 0x17 -#define WIN_COLOR_DEPTH_YCbCr422RA 0x18 -#define WIN_COLOR_DEPTH_YUV422RA 0x19 - -#define DC_WIN_BUFFER_CONTROL 0x702 -#define DC_WIN_POSITION 0x704 - -#define DC_WIN_SIZE 0x705 -#define H_SIZE(x) (((x) & 0x1fff) << 0) -#define V_SIZE(x) (((x) & 0x1fff) << 16) - -#define DC_WIN_PRESCALED_SIZE 0x706 -#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) -#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) - -#define DC_WIN_H_INITIAL_DDA 0x707 -#define DC_WIN_V_INITIAL_DDA 0x708 - -#define DC_WIN_DDA_INC 0x709 -#define H_DDA_INC(x) (((x) & 0xffff) << 0) -#define V_DDA_INC(x) (((x) & 0xffff) << 16) - -#define DC_WIN_LINE_STRIDE 0x70A -#define DC_WIN_DV_CONTROL 0x70E - -/* The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */ -#define DC_WINBUF_START_ADDR 0x800 -#define DC_WINBUF_ADDR_H_OFFSET 0x806 -#define DC_WINBUF_ADDR_V_OFFSET 0x808 -#define DC_WINBUF_SURFACE_KIND 0x80B - -/* Display serial interface registers. */ -#define DSI_RD_DATA 0x9 -#define DSI_WR_DATA 0xA - -#define DSI_POWER_CONTROL 0xB -#define DSI_POWER_CONTROL_ENABLE 1 - -#define DSI_INT_ENABLE 0xC -#define DSI_INT_STATUS 0xD -#define DSI_INT_MASK 0xE - -#define DSI_HOST_CONTROL 0xF -#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21) -#define DSI_HOST_CONTROL_CRC_RESET (1 << 20) -#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12) -#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12) -#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12) -#define DSI_HOST_CONTROL_RAW (1 << 6) -#define DSI_HOST_CONTROL_HS (1 << 5) -#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4) -#define DSI_HOST_CONTROL_IMM_BTA (1 << 3) -#define DSI_HOST_CONTROL_PKT_BTA (1 << 2) -#define DSI_HOST_CONTROL_CS (1 << 1) -#define DSI_HOST_CONTROL_ECC (1 << 0) - -#define DSI_CONTROL 0x10 -#define DSI_CONTROL_HS_CLK_CTRL (1 << 20) -#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16) -#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12) -#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8) -#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4) -#define DSI_CONTROL_DCS_ENABLE (1 << 3) -#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2) -#define DSI_CONTROL_VIDEO_ENABLE (1 << 1) -#define DSI_CONTROL_HOST_ENABLE (1 << 0) - -#define DSI_SOL_DELAY 0x11 -#define DSI_MAX_THRESHOLD 0x12 - -#define DSI_TRIGGER 0x13 -#define DSI_TRIGGER_HOST (1 << 1) -#define DSI_TRIGGER_VIDEO (1 << 0) - -#define DSI_TX_CRC 0x14 -#define DSI_STATUS 0x15 -#define DSI_INIT_SEQ_CONTROL 0x1A -#define DSI_INIT_SEQ_DATA_0 0x1B -#define DSI_INIT_SEQ_DATA_1 0x1C -#define DSI_INIT_SEQ_DATA_2 0x1D -#define DSI_INIT_SEQ_DATA_3 0x1E -#define DSI_PKT_SEQ_0_LO 0x23 -#define DSI_PKT_SEQ_0_HI 0x24 -#define DSI_PKT_SEQ_1_LO 0x25 -#define DSI_PKT_SEQ_1_HI 0x26 -#define DSI_PKT_SEQ_2_LO 0x27 -#define DSI_PKT_SEQ_2_HI 0x28 -#define DSI_PKT_SEQ_3_LO 0x29 -#define DSI_PKT_SEQ_3_HI 0x2A -#define DSI_PKT_SEQ_4_LO 0x2B -#define DSI_PKT_SEQ_4_HI 0x2C -#define DSI_PKT_SEQ_5_LO 0x2D -#define DSI_PKT_SEQ_5_HI 0x2E -#define DSI_DCS_CMDS 0x33 -#define DSI_PKT_LEN_0_1 0x34 -#define DSI_PKT_LEN_2_3 0x35 -#define DSI_PKT_LEN_4_5 0x36 -#define DSI_PKT_LEN_6_7 0x37 -#define DSI_PHY_TIMING_0 0x3C -#define DSI_PHY_TIMING_1 0x3D -#define DSI_PHY_TIMING_2 0x3E -#define DSI_BTA_TIMING 0x3F - -#define DSI_TIMEOUT_0 0x44 -#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) -#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) - -#define DSI_TIMEOUT_1 0x45 -#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) -#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) - -#define DSI_TO_TALLY 0x46 - -#define DSI_PAD_CONTROL_0 0x4B -#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24) -#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) -#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) -#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) - -#define DSI_PAD_CONTROL_CD 0x4c -#define DSI_VIDEO_MODE_CONTROL 0x4E - -#define DSI_PAD_CONTROL_1 0x4F -#define DSI_PAD_CONTROL_2 0x50 - -#define DSI_PAD_CONTROL_3 0x51 -#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12) -#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8) -#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4) -#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) - -#define DSI_PAD_CONTROL_4 0x52 - -#endif diff --git a/sept/sept-primary/src/fuse.c b/sept/sept-primary/src/fuse.c deleted file mode 100644 index dd353fdb5..000000000 --- a/sept/sept-primary/src/fuse.c +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -#include "car.h" -#include "fuse.h" -#include "pmc.h" -#include "timers.h" - -/* Initialize the fuse driver */ -void fuse_init(void) { - /* Make all fuse registers visible, disable the private key and disable programming. */ - clkrst_enable_fuse_regs(true); - /* fuse_disable_private_key(); */ - /* fuse_disable_programming(); */ -} - -/* Disable access to the private key and set the TZ sticky bit. */ -void fuse_disable_private_key(void) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - fuse->FUSE_PRIVATEKEYDISABLE = 0x10; -} - -/* Disable all fuse programming. */ -void fuse_disable_programming(void) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - fuse->FUSE_DISABLEREGPROGRAM = 1; -} - -/* Enable power to the fuse hardware array. */ -void fuse_enable_power(void) { - volatile tegra_pmc_t *pmc = pmc_get_regs(); - pmc->fuse_control &= ~(0x200); /* Clear PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */ - mdelay(1); - pmc->fuse_control |= 0x100; /* Set PMC_FUSE_CTRL_PS18_LATCH_SET. */ - mdelay(1); -} - -/* Disable power to the fuse hardware array. */ -void fuse_disable_power(void) { - volatile tegra_pmc_t *pmc = pmc_get_regs(); - pmc->fuse_control &= ~(0x100); /* Clear PMC_FUSE_CTRL_PS18_LATCH_SET. */ - mdelay(1); - pmc->fuse_control |= 0x200; /* Set PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */ - mdelay(1); -} - -/* Wait for the fuse driver to go idle. */ -static void fuse_wait_idle(void) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - uint32_t ctrl_val = 0; - - /* Wait for STATE_IDLE */ - while ((ctrl_val & (0xF0000)) != 0x40000) { - ctrl_val = fuse->FUSE_FUSECTRL; - } -} - -/* Read a fuse from the hardware array. */ -uint32_t fuse_hw_read(uint32_t addr) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - - /* Wait for idle state. */ - fuse_wait_idle(); - - /* Program the target address. */ - fuse->FUSE_FUSEADDR = addr; - - /* Enable read operation in control register. */ - uint32_t ctrl_val = fuse->FUSE_FUSECTRL; - ctrl_val &= ~0x3; - ctrl_val |= 0x1; /* Set READ command. */ - fuse->FUSE_FUSECTRL = ctrl_val; - - /* Wait for idle state. */ - fuse_wait_idle(); - - return fuse->FUSE_FUSERDATA; -} - -/* Write a fuse in the hardware array. */ -void fuse_hw_write(uint32_t value, uint32_t addr) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - - /* Wait for idle state. */ - fuse_wait_idle(); - - /* Program the target address and value. */ - fuse->FUSE_FUSEADDR = addr; - fuse->FUSE_FUSEWDATA = value; - - /* Enable write operation in control register. */ - uint32_t ctrl_val = fuse->FUSE_FUSECTRL; - ctrl_val &= ~0x3; - ctrl_val |= 0x2; /* Set WRITE command. */ - fuse->FUSE_FUSECTRL = ctrl_val; - - /* Wait for idle state. */ - fuse_wait_idle(); -} - -/* Sense the fuse hardware array into the fuse cache. */ -void fuse_hw_sense(void) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - - /* Wait for idle state. */ - fuse_wait_idle(); - - /* Enable sense operation in control register */ - uint32_t ctrl_val = fuse->FUSE_FUSECTRL; - ctrl_val &= ~0x3; - ctrl_val |= 0x3; /* Set SENSE_CTRL command */ - fuse->FUSE_FUSECTRL = ctrl_val; - - /* Wait for idle state. */ - fuse_wait_idle(); -} - -/* Read the SKU info register. */ -uint32_t fuse_get_sku_info(void) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - return fuse_chip->FUSE_SKU_INFO; -} - -/* Read the bootrom patch version. */ -uint32_t fuse_get_bootrom_patch_version(void) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB; -} - -/* Read a spare bit register. */ -uint32_t fuse_get_spare_bit(uint32_t index) { - uint32_t soc_type = fuse_get_soc_type(); - if (soc_type == 0) { - if (index < 32) { - volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs(); - return fuse_chip->FUSE_SPARE_BIT[index]; - } - } else if (soc_type == 1) { - if (index < 30) { - volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); - return fuse_chip->FUSE_SPARE_BIT[index]; - } - } - return 0; -} - -/* Read a reserved ODM register. */ -uint32_t fuse_get_reserved_odm(uint32_t index) { - if (index < 8) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - return fuse_chip->FUSE_RESERVED_ODM0[index]; - } else { - uint32_t soc_type = fuse_get_soc_type(); - if (soc_type == 1) { - volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); - if (index < 22) { - return fuse_chip->FUSE_RESERVED_ODM8[index - 8]; - } else if (index < 25) { - return fuse_chip->FUSE_RESERVED_ODM22[index - 22]; - } else if (index < 26) { - return fuse_chip->FUSE_RESERVED_ODM25; - } else if (index < 29) { - return fuse_chip->FUSE_RESERVED_ODM26[index - 26]; - } else if (index < 30) { - return fuse_chip->FUSE_RESERVED_ODM29; - } - } - } - return 0; -} - -/* Get the DramId. */ -uint32_t fuse_get_dram_id(void) { - return ((fuse_get_reserved_odm(4) >> 3) & 0x1F); -} - -/* Derive the DeviceId. */ -uint64_t fuse_get_device_id(void) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - - uint64_t device_id = 0; - uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF; - uint64_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF; - uint64_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F; - uint32_t lot_code = fuse_chip->FUSE_OPT_LOT_CODE_0; - uint64_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F; - - uint64_t derived_lot_code = 0; - for (unsigned int i = 0; i < 5; i++) { - derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F); - } - derived_lot_code &= 0x03FFFFFF; - - device_id |= y_coord << 0; - device_id |= x_coord << 9; - device_id |= wafer_id << 18; - device_id |= derived_lot_code << 24; - device_id |= fab_code << 50; - - return device_id; -} - -/* Derive the HardwareType with firmware specific checks. */ -uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) { - uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4); - uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1)); - - if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1); - - switch (hardware_type) { - case 0x00: return (fuse_spare_bit9 == 0) ? 0 : 3; - case 0x01: return 0; /* HardwareType_Icosa */ - case 0x02: return 1; /* HardwareType_Copper */ - default: return 3; /* HardwareType_Undefined */ - } - } else { - hardware_type |= ((fuse_reserved_odm4 >> 14) & 0x3C); - - if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) { - switch (hardware_type) { - case 0x01: return 0; /* HardwareType_Icosa */ - case 0x02: return 1; /* HardwareType_Copper */ - case 0x04: return 3; /* HardwareType_Iowa */ - default: return 4; /* HardwareType_Undefined */ - } - } else { - if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_10_0_0) { - switch (hardware_type) { - case 0x01: return 0; /* HardwareType_Icosa */ - case 0x02: return 4; /* HardwareType_Calcio */ - case 0x04: return 3; /* HardwareType_Iowa */ - case 0x08: return 2; /* HardwareType_Hoag */ - default: return 0xF; /* HardwareType_Undefined */ - } - } else { - switch (hardware_type) { - case 0x01: return 0; /* HardwareType_Icosa */ - case 0x02: return 4; /* HardwareType_Calcio */ - case 0x04: return 3; /* HardwareType_Iowa */ - case 0x08: return 2; /* HardwareType_Hoag */ - case 0x10: return 5; /* HardwareType_Five */ - default: return 0xF; /* HardwareType_Undefined */ - } - } - } - } -} - -/* Derive the HardwareType. */ -uint32_t fuse_get_hardware_type(void) { - return fuse_get_hardware_type_with_firmware_check(ATMOSPHERE_TARGET_FIRMWARE_CURRENT); -} - -/* Derive the HardwareState. */ -uint32_t fuse_get_hardware_state(void) { - uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4); - uint32_t hardware_state = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3)); - - switch (hardware_state) { - case 0x03: return 0; /* HardwareState_Development */ - case 0x04: return 1; /* HardwareState_Production */ - default: return 2; /* HardwareState_Undefined */ - } -} - -/* Derive the 16-byte HardwareInfo and copy to output buffer. */ -void fuse_get_hardware_info(void *dst) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - uint32_t hw_info[0x4]; - - uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F; - uint32_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF; - uint32_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF; - uint32_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F; - uint32_t lot_code_0 = fuse_chip->FUSE_OPT_LOT_CODE_0; - uint32_t lot_code_1 = fuse_chip->FUSE_OPT_LOT_CODE_1 & 0x0FFFFFFF; - uint32_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F; - uint32_t vendor_code = fuse_chip->FUSE_OPT_VENDOR_CODE & 0xF; - - /* Hardware Info = OPS_RESERVED || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */ - hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (ops_reserved)); - hw_info[1] = (uint32_t)((lot_code_0 << 26) | (lot_code_1 >> 2)); - hw_info[2] = (uint32_t)((fab_code << 26) | (lot_code_0 >> 6)); - hw_info[3] = (uint32_t)(vendor_code); - - memcpy(dst, hw_info, 0x10); -} - -/* Check if have a new ODM fuse format. */ -bool fuse_is_new_format(void) { - return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)); -} - -/* Get the DeviceUniqueKeyGeneration. */ -uint32_t fuse_get_device_unique_key_generation(void) { - if (fuse_is_new_format()) { - return (fuse_get_reserved_odm(2) & 0x1F); - } else { - return 0; - } -} - -/* Get the SocType from the HardwareType. */ -uint32_t fuse_get_soc_type(void) { - switch (fuse_get_hardware_type()) { - case 0: - case 1: - return 0; /* SocType_Erista */ - case 3: - case 2: - case 4: - case 5: - return 1; /* SocType_Mariko */ - default: - return 0xF; /* SocType_Undefined */ - } -} - -/* Get the Regulator type. */ -uint32_t fuse_get_regulator(void) { - if (fuse_get_soc_type() == 1) { - return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */ - } else { - return 0; /* Regulator_Erista_Max77621 */ - } -} diff --git a/sept/sept-primary/src/fuse.h b/sept/sept-primary/src/fuse.h deleted file mode 100644 index eb590553c..000000000 --- a/sept/sept-primary/src/fuse.h +++ /dev/null @@ -1,484 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_FUSE_H -#define FUSEE_FUSE_H - -#define FUSE_BASE 0x7000F800 -#define FUSE_CHIP_BASE (FUSE_BASE + 0x98) -#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n) -#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n) - -typedef struct { - uint32_t FUSE_FUSECTRL; - uint32_t FUSE_FUSEADDR; - uint32_t FUSE_FUSERDATA; - uint32_t FUSE_FUSEWDATA; - uint32_t FUSE_FUSETIME_RD1; - uint32_t FUSE_FUSETIME_RD2; - uint32_t FUSE_FUSETIME_PGM1; - uint32_t FUSE_FUSETIME_PGM2; - uint32_t FUSE_PRIV2INTFC_START; - uint32_t FUSE_FUSEBYPASS; - uint32_t FUSE_PRIVATEKEYDISABLE; - uint32_t FUSE_DISABLEREGPROGRAM; - uint32_t FUSE_WRITE_ACCESS_SW; - uint32_t FUSE_PWR_GOOD_SW; - uint32_t _0x38; - uint32_t FUSE_PRIV2RESHIFT; - uint32_t _0x40[0x3]; - uint32_t FUSE_FUSETIME_RD3; - uint32_t _0x50[0xC]; - uint32_t FUSE_PRIVATE_KEY0_NONZERO; - uint32_t FUSE_PRIVATE_KEY1_NONZERO; - uint32_t FUSE_PRIVATE_KEY2_NONZERO; - uint32_t FUSE_PRIVATE_KEY3_NONZERO; - uint32_t FUSE_PRIVATE_KEY4_NONZERO; - uint32_t _0x94; -} tegra_fuse_t; - -typedef struct { - uint32_t _0x98[0x1A]; - uint32_t FUSE_PRODUCTION_MODE; - uint32_t FUSE_JTAG_SECUREID_VALID; - uint32_t FUSE_ODM_LOCK; - uint32_t FUSE_OPT_OPENGL_EN; - uint32_t FUSE_SKU_INFO; - uint32_t FUSE_CPU_SPEEDO_0_CALIB; - uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t _0x11C[0x3]; - uint32_t FUSE_OPT_FT_REV; - uint32_t FUSE_CPU_SPEEDO_1_CALIB; - uint32_t FUSE_CPU_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_SPEEDO_0_CALIB; - uint32_t FUSE_SOC_SPEEDO_1_CALIB; - uint32_t FUSE_SOC_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t _0x144; - uint32_t FUSE_FA; - uint32_t FUSE_RESERVED_PRODUCTION; - uint32_t FUSE_HDMI_LANE0_CALIB; - uint32_t FUSE_HDMI_LANE1_CALIB; - uint32_t FUSE_HDMI_LANE2_CALIB; - uint32_t FUSE_HDMI_LANE3_CALIB; - uint32_t FUSE_ENCRYPTION_RATE; - uint32_t FUSE_PUBLIC_KEY[0x8]; - uint32_t FUSE_TSENSOR1_CALIB; - uint32_t FUSE_TSENSOR2_CALIB; - uint32_t _0x18C; - uint32_t FUSE_OPT_CP_REV; - uint32_t FUSE_OPT_PFG; - uint32_t FUSE_TSENSOR0_CALIB; - uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; - uint32_t FUSE_SECURITY_MODE; - uint32_t FUSE_PRIVATE_KEY[0x5]; - uint32_t FUSE_ARM_JTAG_DIS; - uint32_t FUSE_BOOT_DEVICE_INFO; - uint32_t FUSE_RESERVED_SW; - uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM0[0x8]; - uint32_t FUSE_OBS_DIS; - uint32_t _0x1EC; - uint32_t FUSE_USB_CALIB; - uint32_t FUSE_SKU_DIRECT_CONFIG; - uint32_t FUSE_KFUSE_PRIVKEY_CTRL; - uint32_t FUSE_PACKAGE_INFO; - uint32_t FUSE_OPT_VENDOR_CODE; - uint32_t FUSE_OPT_FAB_CODE; - uint32_t FUSE_OPT_LOT_CODE_0; - uint32_t FUSE_OPT_LOT_CODE_1; - uint32_t FUSE_OPT_WAFER_ID; - uint32_t FUSE_OPT_X_COORDINATE; - uint32_t FUSE_OPT_Y_COORDINATE; - uint32_t FUSE_OPT_SEC_DEBUG_EN; - uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t _0x224; - uint32_t FUSE_GPU_IDDQ_CALIB; - uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_CLOCK_BOUNDOUT0; - uint32_t FUSE_CLOCK_BOUNDOUT1; - uint32_t _0x238[0x3]; - uint32_t FUSE_OPT_SAMPLE_TYPE; - uint32_t FUSE_OPT_SUBREVISION; - uint32_t FUSE_OPT_SW_RESERVED_0; - uint32_t FUSE_OPT_SW_RESERVED_1; - uint32_t FUSE_TSENSOR4_CALIB; - uint32_t FUSE_TSENSOR5_CALIB; - uint32_t FUSE_TSENSOR6_CALIB; - uint32_t FUSE_TSENSOR7_CALIB; - uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t _0x268[0x5]; - uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; - uint32_t FUSE_TSENSOR_COMMON; - uint32_t FUSE_OPT_CP_BIN; - uint32_t FUSE_OPT_GPU_DISABLE; - uint32_t FUSE_OPT_FT_BIN; - uint32_t FUSE_OPT_DONE_MAP; - uint32_t _0x294; - uint32_t FUSE_APB2JTAG_DISABLE; - uint32_t FUSE_ODM_INFO; - uint32_t _0x2A0[0x2]; - uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x2AC[0x5]; - uint32_t FUSE_WOA_SKU_FLAG; - uint32_t FUSE_ECO_RESERVE_1; - uint32_t FUSE_GCPLEX_CONFIG_FUSE; - uint32_t FUSE_PRODUCTION_MONTH; - uint32_t FUSE_RAM_REPAIR_INDICATOR; - uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x2D8; - uint32_t FUSE_VMIN_CALIBRATION; - uint32_t FUSE_AGING_SENSOR_CALIBRATION; - uint32_t FUSE_DEBUG_AUTHENTICATION; - uint32_t FUSE_SECURE_PROVISION_INDEX; - uint32_t FUSE_SECURE_PROVISION_INFO; - uint32_t FUSE_OPT_GPU_DISABLE_CP1; - uint32_t FUSE_SPARE_ENDIS; - uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x2FC[0x2]; - uint32_t FUSE_RESERVED_CALIB0; - uint32_t FUSE_RESERVED_CALIB1; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; - uint32_t FUSE_OPT_CPU_DISABLE; - uint32_t FUSE_OPT_CPU_DISABLE_CP1; - uint32_t FUSE_TSENSOR10_CALIB; - uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t _0x324[0x5]; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; - uint32_t FUSE_OPT_CPU_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_DISABLE_CP2; - uint32_t FUSE_USB_CALIB_EXT; - uint32_t FUSE_RESERVED_FIELD; - uint32_t _0x358[0x9]; - uint32_t FUSE_SPARE_REALIGNMENT_REG; - uint32_t FUSE_SPARE_BIT[0x20]; -} tegra_fuse_chip_common_t; - -typedef struct { - uint32_t _0x98[0x1A]; - uint32_t FUSE_PRODUCTION_MODE; - uint32_t FUSE_JTAG_SECUREID_VALID; - uint32_t FUSE_ODM_LOCK; - uint32_t FUSE_OPT_OPENGL_EN; - uint32_t FUSE_SKU_INFO; - uint32_t FUSE_CPU_SPEEDO_0_CALIB; - uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t _0x11C[0x3]; - uint32_t FUSE_OPT_FT_REV; - uint32_t FUSE_CPU_SPEEDO_1_CALIB; - uint32_t FUSE_CPU_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_SPEEDO_0_CALIB; - uint32_t FUSE_SOC_SPEEDO_1_CALIB; - uint32_t FUSE_SOC_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t _0x144; - uint32_t FUSE_FA; - uint32_t FUSE_RESERVED_PRODUCTION; - uint32_t FUSE_HDMI_LANE0_CALIB; - uint32_t FUSE_HDMI_LANE1_CALIB; - uint32_t FUSE_HDMI_LANE2_CALIB; - uint32_t FUSE_HDMI_LANE3_CALIB; - uint32_t FUSE_ENCRYPTION_RATE; - uint32_t FUSE_PUBLIC_KEY[0x8]; - uint32_t FUSE_TSENSOR1_CALIB; - uint32_t FUSE_TSENSOR2_CALIB; - uint32_t _0x18C; - uint32_t FUSE_OPT_CP_REV; - uint32_t FUSE_OPT_PFG; - uint32_t FUSE_TSENSOR0_CALIB; - uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; - uint32_t FUSE_SECURITY_MODE; - uint32_t FUSE_PRIVATE_KEY[0x5]; - uint32_t FUSE_ARM_JTAG_DIS; - uint32_t FUSE_BOOT_DEVICE_INFO; - uint32_t FUSE_RESERVED_SW; - uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM0[0x8]; - uint32_t FUSE_OBS_DIS; - uint32_t _0x1EC; - uint32_t FUSE_USB_CALIB; - uint32_t FUSE_SKU_DIRECT_CONFIG; - uint32_t FUSE_KFUSE_PRIVKEY_CTRL; - uint32_t FUSE_PACKAGE_INFO; - uint32_t FUSE_OPT_VENDOR_CODE; - uint32_t FUSE_OPT_FAB_CODE; - uint32_t FUSE_OPT_LOT_CODE_0; - uint32_t FUSE_OPT_LOT_CODE_1; - uint32_t FUSE_OPT_WAFER_ID; - uint32_t FUSE_OPT_X_COORDINATE; - uint32_t FUSE_OPT_Y_COORDINATE; - uint32_t FUSE_OPT_SEC_DEBUG_EN; - uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t FUSE_SATA_CALIB; /* Erista only. */ - uint32_t FUSE_GPU_IDDQ_CALIB; - uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_CLOCK_BOUNDOUT0; - uint32_t FUSE_CLOCK_BOUNDOUT1; - uint32_t _0x238[0x3]; - uint32_t FUSE_OPT_SAMPLE_TYPE; - uint32_t FUSE_OPT_SUBREVISION; - uint32_t FUSE_OPT_SW_RESERVED_0; - uint32_t FUSE_OPT_SW_RESERVED_1; - uint32_t FUSE_TSENSOR4_CALIB; - uint32_t FUSE_TSENSOR5_CALIB; - uint32_t FUSE_TSENSOR6_CALIB; - uint32_t FUSE_TSENSOR7_CALIB; - uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t FUSE_PKC_DISABLE; /* Erista only. */ - uint32_t _0x26C[0x4]; - uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; - uint32_t FUSE_TSENSOR_COMMON; - uint32_t FUSE_OPT_CP_BIN; - uint32_t FUSE_OPT_GPU_DISABLE; - uint32_t FUSE_OPT_FT_BIN; - uint32_t FUSE_OPT_DONE_MAP; - uint32_t _0x294; - uint32_t FUSE_APB2JTAG_DISABLE; - uint32_t FUSE_ODM_INFO; - uint32_t _0x2A0[0x2]; - uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x2AC[0x5]; - uint32_t FUSE_WOA_SKU_FLAG; - uint32_t FUSE_ECO_RESERVE_1; - uint32_t FUSE_GCPLEX_CONFIG_FUSE; - uint32_t FUSE_PRODUCTION_MONTH; - uint32_t FUSE_RAM_REPAIR_INDICATOR; - uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x2D8; - uint32_t FUSE_VMIN_CALIBRATION; - uint32_t FUSE_AGING_SENSOR_CALIBRATION; - uint32_t FUSE_DEBUG_AUTHENTICATION; - uint32_t FUSE_SECURE_PROVISION_INDEX; - uint32_t FUSE_SECURE_PROVISION_INFO; - uint32_t FUSE_OPT_GPU_DISABLE_CP1; - uint32_t FUSE_SPARE_ENDIS; - uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x2FC[0x2]; - uint32_t FUSE_RESERVED_CALIB0; - uint32_t FUSE_RESERVED_CALIB1; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; - uint32_t FUSE_OPT_CPU_DISABLE; - uint32_t FUSE_OPT_CPU_DISABLE_CP1; - uint32_t FUSE_TSENSOR10_CALIB; - uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */ - uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */ - uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */ - uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */ - uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */ - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; - uint32_t FUSE_OPT_CPU_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_DISABLE_CP2; - uint32_t FUSE_USB_CALIB_EXT; - uint32_t FUSE_RESERVED_FIELD; - uint32_t _0x358[0x9]; - uint32_t FUSE_SPARE_REALIGNMENT_REG; - uint32_t FUSE_SPARE_BIT[0x20]; -} tegra_fuse_chip_erista_t; - -typedef struct { - uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */ - uint32_t FUSE_KEK[0x4]; /* Mariko only. */ - uint32_t FUSE_BEK[0x4]; /* Mariko only. */ - uint32_t _0xF0; /* Mariko only. */ - uint32_t _0xF4; /* Mariko only. */ - uint32_t _0xF8; /* Mariko only. */ - uint32_t _0xFC; /* Mariko only. */ - uint32_t FUSE_PRODUCTION_MODE; - uint32_t FUSE_JTAG_SECUREID_VALID; - uint32_t FUSE_ODM_LOCK; - uint32_t FUSE_OPT_OPENGL_EN; - uint32_t FUSE_SKU_INFO; - uint32_t FUSE_CPU_SPEEDO_0_CALIB; - uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */ - uint32_t FUSE_OPT_FT_REV; - uint32_t FUSE_CPU_SPEEDO_1_CALIB; - uint32_t FUSE_CPU_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_SPEEDO_0_CALIB; - uint32_t FUSE_SOC_SPEEDO_1_CALIB; - uint32_t FUSE_SOC_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */ - uint32_t FUSE_FA; - uint32_t FUSE_RESERVED_PRODUCTION; - uint32_t FUSE_HDMI_LANE0_CALIB; - uint32_t FUSE_HDMI_LANE1_CALIB; - uint32_t FUSE_HDMI_LANE2_CALIB; - uint32_t FUSE_HDMI_LANE3_CALIB; - uint32_t FUSE_ENCRYPTION_RATE; - uint32_t FUSE_PUBLIC_KEY[0x8]; - uint32_t FUSE_TSENSOR1_CALIB; - uint32_t FUSE_TSENSOR2_CALIB; - uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */ - uint32_t FUSE_OPT_CP_REV; - uint32_t FUSE_OPT_PFG; - uint32_t FUSE_TSENSOR0_CALIB; - uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; - uint32_t FUSE_SECURITY_MODE; - uint32_t FUSE_PRIVATE_KEY[0x5]; - uint32_t FUSE_ARM_JTAG_DIS; - uint32_t FUSE_BOOT_DEVICE_INFO; - uint32_t FUSE_RESERVED_SW; - uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM0[0x8]; - uint32_t FUSE_OBS_DIS; - uint32_t _0x1EC; /* Mariko only. */ - uint32_t FUSE_USB_CALIB; - uint32_t FUSE_SKU_DIRECT_CONFIG; - uint32_t FUSE_KFUSE_PRIVKEY_CTRL; - uint32_t FUSE_PACKAGE_INFO; - uint32_t FUSE_OPT_VENDOR_CODE; - uint32_t FUSE_OPT_FAB_CODE; - uint32_t FUSE_OPT_LOT_CODE_0; - uint32_t FUSE_OPT_LOT_CODE_1; - uint32_t FUSE_OPT_WAFER_ID; - uint32_t FUSE_OPT_X_COORDINATE; - uint32_t FUSE_OPT_Y_COORDINATE; - uint32_t FUSE_OPT_SEC_DEBUG_EN; - uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t _0x224; /* Mariko only. */ - uint32_t FUSE_GPU_IDDQ_CALIB; - uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_CLOCK_BOUNDOUT0; - uint32_t FUSE_CLOCK_BOUNDOUT1; - uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */ - uint32_t FUSE_OPT_SAMPLE_TYPE; - uint32_t FUSE_OPT_SUBREVISION; - uint32_t FUSE_OPT_SW_RESERVED_0; - uint32_t FUSE_OPT_SW_RESERVED_1; - uint32_t FUSE_TSENSOR4_CALIB; - uint32_t FUSE_TSENSOR5_CALIB; - uint32_t FUSE_TSENSOR6_CALIB; - uint32_t FUSE_TSENSOR7_CALIB; - uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */ - uint32_t _0x26C; /* Mariko only. */ - uint32_t _0x270; /* Mariko only. */ - uint32_t _0x274; /* Mariko only. */ - uint32_t _0x278; /* Mariko only. */ - uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; - uint32_t FUSE_TSENSOR_COMMON; - uint32_t FUSE_OPT_CP_BIN; - uint32_t FUSE_OPT_GPU_DISABLE; - uint32_t FUSE_OPT_FT_BIN; - uint32_t FUSE_OPT_DONE_MAP; - uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */ - uint32_t FUSE_APB2JTAG_DISABLE; - uint32_t FUSE_ODM_INFO; - uint32_t _0x2A0[0x2]; - uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x2AC; - uint32_t _0x2B0; /* Mariko only. */ - uint32_t _0x2B4; /* Mariko only. */ - uint32_t _0x2B8; /* Mariko only. */ - uint32_t _0x2BC; /* Mariko only. */ - uint32_t FUSE_WOA_SKU_FLAG; - uint32_t FUSE_ECO_RESERVE_1; - uint32_t FUSE_GCPLEX_CONFIG_FUSE; - uint32_t FUSE_PRODUCTION_MONTH; - uint32_t FUSE_RAM_REPAIR_INDICATOR; - uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x2D8; - uint32_t FUSE_VMIN_CALIBRATION; - uint32_t FUSE_AGING_SENSOR_CALIBRATION; - uint32_t FUSE_DEBUG_AUTHENTICATION; - uint32_t FUSE_SECURE_PROVISION_INDEX; - uint32_t FUSE_SECURE_PROVISION_INFO; - uint32_t FUSE_OPT_GPU_DISABLE_CP1; - uint32_t FUSE_SPARE_ENDIS; - uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x2FC[0x2]; - uint32_t FUSE_RESERVED_CALIB0; - uint32_t FUSE_RESERVED_CALIB1; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; - uint32_t FUSE_OPT_CPU_DISABLE; - uint32_t FUSE_OPT_CPU_DISABLE_CP1; - uint32_t FUSE_TSENSOR10_CALIB; - uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t _0x324; /* Mariko only. */ - uint32_t _0x328; /* Mariko only. */ - uint32_t _0x32C; /* Mariko only. */ - uint32_t _0x330; /* Mariko only. */ - uint32_t _0x334; /* Mariko only. */ - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; - uint32_t FUSE_OPT_CPU_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_DISABLE_CP2; - uint32_t FUSE_USB_CALIB_EXT; - uint32_t FUSE_RESERVED_FIELD; - uint32_t _0x358[0x9]; - uint32_t FUSE_SPARE_REALIGNMENT_REG; - uint32_t FUSE_SPARE_BIT[0x1E]; -} tegra_fuse_chip_mariko_t; - -static inline volatile tegra_fuse_t *fuse_get_regs(void) -{ - return (volatile tegra_fuse_t *)FUSE_BASE; -} - -static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void) -{ - return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE; -} - -static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void) -{ - return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE; -} - -static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void) -{ - return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE; -} - -void fuse_init(void); -void fuse_disable_programming(void); -void fuse_disable_private_key(void); -void fuse_enable_power(void); -void fuse_disable_power(void); - -uint32_t fuse_get_sku_info(void); -uint32_t fuse_get_spare_bit(uint32_t index); -uint32_t fuse_get_reserved_odm(uint32_t index); -uint32_t fuse_get_bootrom_patch_version(void); -uint64_t fuse_get_device_id(void); -uint32_t fuse_get_dram_id(void); -uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware); -uint32_t fuse_get_hardware_type(void); -uint32_t fuse_get_retail_type(void); -void fuse_get_hardware_info(void *dst); -bool fuse_is_new_format(void); -uint32_t fuse_get_device_unique_key_generation(void); -uint32_t fuse_get_soc_type(void); -uint32_t fuse_get_regulator(void); - -uint32_t fuse_hw_read(uint32_t addr); -void fuse_hw_write(uint32_t value, uint32_t addr); -void fuse_hw_sense(void); - -#endif diff --git a/sept/sept-primary/src/gpio.c b/sept/sept-primary/src/gpio.c deleted file mode 100644 index 76dbb87ce..000000000 --- a/sept/sept-primary/src/gpio.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -#include "gpio.h" -#include "utils.h" - -/* Set GPIO's value. */ -static void gpio_register_set(uint32_t pin, bool do_set, uint32_t offset) { - volatile tegra_gpio_t *gpio = gpio_get_regs(); - - /* Retrieve the register set that corresponds to the given pin and offset. */ - volatile uint32_t *cluster = (uint32_t *)((uintptr_t)&gpio->bank[(pin >> GPIO_BANK_SHIFT)] + offset); - - /* Figure out the offset into the cluster, and the mask to be used. */ - uint32_t port = ((pin >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK); - uint32_t mask = (1 << (pin & GPIO_PIN_MASK)); - - /* Set or clear the bit, as appropriate. */ - if (do_set) - cluster[port] |= mask; - else - cluster[port] &= ~mask; - - /* Dummy read. */ - cluster[port]; -} - -/* Get GPIO's value. */ -static bool gpio_register_get(uint32_t pin, uint32_t offset) { - volatile tegra_gpio_t *gpio = gpio_get_regs(); - - /* Retrieve the register set that corresponds to the given pin and offset. */ - volatile uint32_t *cluster = (uint32_t *)((uintptr_t)&gpio->bank[(pin >> GPIO_BANK_SHIFT)] + offset); - - /* Figure out the offset into the cluster, and the mask to be used. */ - uint32_t port = ((pin >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK); - uint32_t mask = (1 << (pin & GPIO_PIN_MASK)); - - /* Convert the given value to a boolean. */ - return !!(cluster[port] & mask); -} - -/* Configure GPIO's mode. */ -void gpio_configure_mode(uint32_t pin, uint32_t mode) { - gpio_register_set(pin, mode == GPIO_MODE_GPIO, offsetof(tegra_gpio_bank_t, config)); -} - -/* Configure GPIO's direction. */ -void gpio_configure_direction(uint32_t pin, uint32_t dir) { - gpio_register_set(pin, dir == GPIO_DIRECTION_OUTPUT, offsetof(tegra_gpio_bank_t, direction)); -} - -/* Write to GPIO. */ -void gpio_write(uint32_t pin, uint32_t value) { - gpio_register_set(pin, value == GPIO_LEVEL_HIGH, offsetof(tegra_gpio_bank_t, out)); -} - -/* Read from GPIO. */ -uint32_t gpio_read(uint32_t pin) { - return gpio_register_get(pin, offsetof(tegra_gpio_bank_t, in)); -} diff --git a/sept/sept-primary/src/gpio.h b/sept/sept-primary/src/gpio.h deleted file mode 100644 index b187ed618..000000000 --- a/sept/sept-primary/src/gpio.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_GPIO_H -#define FUSEE_GPIO_H - -#include - -#define GPIO_BASE 0x6000D000 -#define MAKE_GPIO_REG(n) MAKE_REG32(GPIO_BASE + n) - -#define TEGRA_GPIO_PORTS 4 -#define TEGRA_GPIO_BANKS 8 -#define GPIO_BANK_SHIFT 5 -#define GPIO_PORT_SHIFT 3 -#define GPIO_PORT_MASK 0x03 -#define GPIO_PIN_MASK 0x07 - -typedef enum { - TEGRA_GPIO_PORT_A = 0, - TEGRA_GPIO_PORT_B = 1, - TEGRA_GPIO_PORT_C = 2, - TEGRA_GPIO_PORT_D = 3, - TEGRA_GPIO_PORT_E = 4, - TEGRA_GPIO_PORT_F = 5, - TEGRA_GPIO_PORT_G = 6, - TEGRA_GPIO_PORT_H = 7, - TEGRA_GPIO_PORT_I = 8, - TEGRA_GPIO_PORT_J = 9, - TEGRA_GPIO_PORT_K = 10, - TEGRA_GPIO_PORT_L = 11, - TEGRA_GPIO_PORT_M = 12, - TEGRA_GPIO_PORT_N = 13, - TEGRA_GPIO_PORT_O = 14, - TEGRA_GPIO_PORT_P = 15, - TEGRA_GPIO_PORT_Q = 16, - TEGRA_GPIO_PORT_R = 17, - TEGRA_GPIO_PORT_S = 18, - TEGRA_GPIO_PORT_T = 19, - TEGRA_GPIO_PORT_U = 20, - TEGRA_GPIO_PORT_V = 21, - TEGRA_GPIO_PORT_W = 22, - TEGRA_GPIO_PORT_X = 23, - TEGRA_GPIO_PORT_Y = 24, - TEGRA_GPIO_PORT_Z = 25, - TEGRA_GPIO_PORT_AA = 26, - TEGRA_GPIO_PORT_BB = 27, - TEGRA_GPIO_PORT_CC = 28, - TEGRA_GPIO_PORT_DD = 29, - TEGRA_GPIO_PORT_EE = 30, - TEGRA_GPIO_PORT_FF = 31, -} tegra_gpio_port; - -typedef struct { - uint32_t config[TEGRA_GPIO_PORTS]; - uint32_t direction[TEGRA_GPIO_PORTS]; - uint32_t out[TEGRA_GPIO_PORTS]; - uint32_t in[TEGRA_GPIO_PORTS]; - uint32_t int_status[TEGRA_GPIO_PORTS]; - uint32_t int_enable[TEGRA_GPIO_PORTS]; - uint32_t int_level[TEGRA_GPIO_PORTS]; - uint32_t int_clear[TEGRA_GPIO_PORTS]; - uint32_t masked_config[TEGRA_GPIO_PORTS]; - uint32_t masked_dir_out[TEGRA_GPIO_PORTS]; - uint32_t masked_out[TEGRA_GPIO_PORTS]; - uint32_t masked_in[TEGRA_GPIO_PORTS]; - uint32_t masked_int_status[TEGRA_GPIO_PORTS]; - uint32_t masked_int_enable[TEGRA_GPIO_PORTS]; - uint32_t masked_int_level[TEGRA_GPIO_PORTS]; - uint32_t masked_int_clear[TEGRA_GPIO_PORTS]; -} tegra_gpio_bank_t; - -typedef struct { - tegra_gpio_bank_t bank[TEGRA_GPIO_BANKS]; -} tegra_gpio_t; - -static inline volatile tegra_gpio_t *gpio_get_regs(void) -{ - return (volatile tegra_gpio_t *)GPIO_BASE; -} - -#define TEGRA_GPIO(port, offset) \ - ((TEGRA_GPIO_PORT_##port * 8) + offset) - -/* Mode select */ -#define GPIO_MODE_SFIO 0 -#define GPIO_MODE_GPIO 1 - -/* Direction */ -#define GPIO_DIRECTION_INPUT 0 -#define GPIO_DIRECTION_OUTPUT 1 - -/* Level */ -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -/* Named GPIOs */ -#define GPIO_BUTTON_VOL_DOWN TEGRA_GPIO(X, 7) -#define GPIO_BUTTON_VOL_UP TEGRA_GPIO(X, 6) -#define GPIO_MICROSD_CARD_DETECT TEGRA_GPIO(Z, 1) -#define GPIO_MICROSD_WRITE_PROTECT TEGRA_GPIO(Z, 4) -#define GPIO_MICROSD_SUPPLY_ENABLE TEGRA_GPIO(E, 4) -#define GPIO_LCD_BL_P5V TEGRA_GPIO(I, 0) -#define GPIO_LCD_BL_N5V TEGRA_GPIO(I, 1) -#define GPIO_LCD_BL_PWM TEGRA_GPIO(V, 0) -#define GPIO_LCD_BL_EN TEGRA_GPIO(V, 1) -#define GPIO_LCD_BL_RST TEGRA_GPIO(V, 2) - -void gpio_configure_mode(uint32_t pin, uint32_t mode); -void gpio_configure_direction(uint32_t pin, uint32_t dir); -void gpio_write(uint32_t pin, uint32_t value); -uint32_t gpio_read(uint32_t pin); - -#endif diff --git a/sept/sept-primary/src/i2c.c b/sept/sept-primary/src/i2c.c deleted file mode 100644 index e8a9d3e1b..000000000 --- a/sept/sept-primary/src/i2c.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "i2c.h" -#include "utils.h" -#include "timers.h" -#include "pinmux.h" - -/* Prototypes for internal commands. */ -volatile tegra_i2c_t *i2c_get_registers_from_id(I2CDevice id); -void i2c_load_config(volatile tegra_i2c_t *regs); - -bool i2c_query(I2CDevice id, uint8_t device, uint8_t r, void *dst, size_t dst_size); -bool i2c_send(I2CDevice id, uint8_t device, uint8_t r, void *src, size_t src_size); - -bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size); -bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size); - -/* Configure I2C pinmux. */ -void i2c_config(I2CDevice id) { - volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); - - switch (id) { - case I2C_1: - pinmux->gen1_i2c_scl = PINMUX_INPUT; - pinmux->gen1_i2c_sda = PINMUX_INPUT; - break; - case I2C_2: - pinmux->gen2_i2c_scl = PINMUX_INPUT; - pinmux->gen2_i2c_sda = PINMUX_INPUT; - break; - case I2C_3: - pinmux->gen3_i2c_scl = PINMUX_INPUT; - pinmux->gen3_i2c_sda = PINMUX_INPUT; - break; - case I2C_4: - pinmux->cam_i2c_scl = PINMUX_INPUT; - pinmux->cam_i2c_sda = PINMUX_INPUT; - break; - case I2C_5: - pinmux->pwr_i2c_scl = PINMUX_INPUT; - pinmux->pwr_i2c_sda = PINMUX_INPUT; - break; - case I2C_6: - /* Unused. */ - break; - default: break; - } -} - -/* Initialize I2C based on registers. */ -void i2c_init(I2CDevice id) { - volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id); - - /* Setup divisor, and clear the bus. */ - regs->I2C_I2C_CLK_DIVISOR_REGISTER_0 = 0x50001; - regs->I2C_I2C_BUS_CLEAR_CONFIG_0 = 0x90003; - - /* Load hardware configuration. */ - i2c_load_config(regs); - - /* Wait a while until BUS_CLEAR_DONE is set. */ - for (unsigned int i = 0; i < 10; i++) { - udelay(20000); - if (regs->I2C_INTERRUPT_STATUS_REGISTER_0 & 0x800) { - break; - } - } - - /* Read the BUS_CLEAR_STATUS. Result doesn't matter. */ - regs->I2C_I2C_BUS_CLEAR_STATUS_0; - - /* Read and set the Interrupt Status. */ - uint32_t int_status = regs->I2C_INTERRUPT_STATUS_REGISTER_0; - regs->I2C_INTERRUPT_STATUS_REGISTER_0 = int_status; -} - -/* Sets a bit in a PMIC register over I2C during CPU shutdown. */ -void i2c_send_pmic_cpu_shutdown_cmd(void) { - uint32_t val = 0; - /* PMIC == Device 4:3C. */ - i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, 0x41, &val, 1); - val |= 4; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, 0x41, &val, 1); -} - -/* Queries the value of TI charger bit over I2C. */ -bool i2c_query_ti_charger_bit_7(void) { - uint32_t val = 0; - /* TI Charger = Device 0:6B. */ - i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1); - return (val & 0x80) != 0; -} - -/* Clears TI charger bit over I2C. */ -void i2c_clear_ti_charger_bit_7(void) { - uint32_t val = 0; - /* TI Charger = Device 0:6B. */ - i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1); - val &= 0x7F; - i2c_send(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1); -} - -/* Sets TI charger bit over I2C. */ -void i2c_set_ti_charger_bit_7(void) { - uint32_t val = 0; - /* TI Charger = Device 0:6B. */ - i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1); - val |= 0x80; - i2c_send(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1); -} - -/* Get registers pointer based on I2C ID. */ -volatile tegra_i2c_t *i2c_get_registers_from_id(I2CDevice id) { - switch (id) { - case I2C_1: - return I2C1_REGS; - case I2C_2: - return I2C2_REGS; - case I2C_3: - return I2C3_REGS; - case I2C_4: - return I2C4_REGS; - case I2C_5: - return I2C5_REGS; - case I2C_6: - return I2C6_REGS; - default: - generic_panic(); - } - return NULL; -} - -/* Load hardware config for I2C4. */ -void i2c_load_config(volatile tegra_i2c_t *regs) { - /* Set MSTR_CONFIG_LOAD, TIMEOUT_CONFIG_LOAD, undocumented bit. */ - regs->I2C_I2C_CONFIG_LOAD_0 = 0x25; - - /* Wait a bit for master config to be loaded. */ - for (unsigned int i = 0; i < 20; i++) { - udelay(1); - if (!(regs->I2C_I2C_CONFIG_LOAD_0 & 1)) { - break; - } - } -} - -/* Reads a register from a device over I2C, writes result to output. */ -bool i2c_query(I2CDevice id, uint8_t device, uint8_t r, void *dst, size_t dst_size) { - volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id); - uint32_t val = r; - - /* Write single byte register ID to device. */ - if (!i2c_write(regs, device, &val, 1)) { - return false; - } - /* Limit output size to 32-bits. */ - if (dst_size > 4) { - return false; - } - - return i2c_read(regs, device, dst, dst_size); -} - -/* Writes a value to a register over I2C. */ -bool i2c_send(I2CDevice id, uint8_t device, uint8_t r, void *src, size_t src_size) { - uint32_t val = r; - if (src_size == 0) { - return true; - } else if (src_size <= 3) { - memcpy(((uint8_t *)&val) + 1, src, src_size); - return i2c_write(i2c_get_registers_from_id(id), device, &val, src_size + 1); - } else { - return false; - } -} - -/* Writes bytes to device over I2C. */ -bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size) { - if (src_size > 4) { - return false; - } else if (src_size == 0) { - return true; - } - - /* Set device for 7-bit write mode. */ - regs->I2C_I2C_CMD_ADDR0_0 = device << 1; - - /* Load in data to write. */ - regs->I2C_I2C_CMD_DATA1_0 = read32le(src, 0); - - /* Set config with LENGTH = src_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */ - regs->I2C_I2C_CNFG_0 = ((src_size << 1) - 2) | 0x2800; - - i2c_load_config(regs); - - /* Config |= SEND; */ - regs->I2C_I2C_CNFG_0 = ((regs->I2C_I2C_CNFG_0 & 0xFFFFFDFF) | 0x200); - - while (regs->I2C_I2C_STATUS_0 & 0x100) { - /* Wait until not busy. */ - } - - /* Return CMD1_STAT == SL1_XFER_SUCCESSFUL. */ - return (regs->I2C_I2C_STATUS_0 & 0xF) == 0; -} - -/* Reads bytes from device over I2C. */ -bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size) { - if (dst_size > 4) { - return false; - } else if (dst_size == 0) { - return true; - } - - /* Set device for 7-bit read mode. */ - regs->I2C_I2C_CMD_ADDR0_0 = (device << 1) | 1; - - /* Set config with LENGTH = dst_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */ - regs->I2C_I2C_CNFG_0 = ((dst_size << 1) - 2) | 0x2840; - - i2c_load_config(regs); - - /* Config |= SEND; */ - regs->I2C_I2C_CNFG_0 = ((regs->I2C_I2C_CNFG_0 & 0xFFFFFDFF) | 0x200); - - while (regs->I2C_I2C_STATUS_0 & 0x100) { - /* Wait until not busy. */ - } - - /* Ensure success. */ - if ((regs->I2C_I2C_STATUS_0 & 0xF) != 0) { - return false; - } - - uint32_t val = regs->I2C_I2C_CMD_DATA1_0; - memcpy(dst, &val, dst_size); - return true; -} diff --git a/sept/sept-primary/src/i2c.h b/sept/sept-primary/src/i2c.h deleted file mode 100644 index 4d3254333..000000000 --- a/sept/sept-primary/src/i2c.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_I2C_H -#define FUSEE_I2C_H - -#include -#include -#include - -#define I2C1234_BASE 0x7000C000 -#define I2C56_BASE 0x7000D000 - -#define MAX77621_CPU_I2C_ADDR 0x1B -#define MAX77621_GPU_I2C_ADDR 0x1C -#define MAX77812_PHASE31_CPU_I2C_ADDR 0x31 -#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 -#define MAX17050_I2C_ADDR 0x36 -#define MAX77620_PWR_I2C_ADDR 0x3C -#define MAX77620_RTC_I2C_ADDR 0x68 -#define BQ24193_I2C_ADDR 0x6B - -typedef enum { - I2C_1 = 0, - I2C_2 = 1, - I2C_3 = 2, - I2C_4 = 3, - I2C_5 = 4, - I2C_6 = 5, -} I2CDevice; - -typedef struct { - uint32_t I2C_I2C_CNFG_0; - uint32_t I2C_I2C_CMD_ADDR0_0; - uint32_t I2C_I2C_CMD_ADDR1_0; - uint32_t I2C_I2C_CMD_DATA1_0; - uint32_t I2C_I2C_CMD_DATA2_0; - uint32_t _0x14; - uint32_t _0x18; - uint32_t I2C_I2C_STATUS_0; - uint32_t I2C_I2C_SL_CNFG_0; - uint32_t I2C_I2C_SL_RCVD_0; - uint32_t I2C_I2C_SL_STATUS_0; - uint32_t I2C_I2C_SL_ADDR1_0; - uint32_t I2C_I2C_SL_ADDR2_0; - uint32_t I2C_I2C_TLOW_SEXT_0; - uint32_t _0x38; - uint32_t I2C_I2C_SL_DELAY_COUNT_0; - uint32_t I2C_I2C_SL_INT_MASK_0; - uint32_t I2C_I2C_SL_INT_SOURCE_0; - uint32_t I2C_I2C_SL_INT_SET_0; - uint32_t _0x4C; - uint32_t I2C_I2C_TX_PACKET_FIFO_0; - uint32_t I2C_I2C_RX_FIFO_0; - uint32_t I2C_PACKET_TRANSFER_STATUS_0; - uint32_t I2C_FIFO_CONTROL_0; - uint32_t I2C_FIFO_STATUS_0; - uint32_t I2C_INTERRUPT_MASK_REGISTER_0; - uint32_t I2C_INTERRUPT_STATUS_REGISTER_0; - uint32_t I2C_I2C_CLK_DIVISOR_REGISTER_0; - uint32_t I2C_I2C_INTERRUPT_SOURCE_REGISTER_0; - uint32_t I2C_I2C_INTERRUPT_SET_REGISTER_0; - uint32_t I2C_I2C_SLV_TX_PACKET_FIFO_0; - uint32_t I2C_I2C_SLV_RX_FIFO_0; - uint32_t I2C_I2C_SLV_PACKET_STATUS_0; - uint32_t I2C_I2C_BUS_CLEAR_CONFIG_0; - uint32_t I2C_I2C_BUS_CLEAR_STATUS_0; - uint32_t I2C_I2C_CONFIG_LOAD_0; - uint32_t _0x90; - uint32_t I2C_I2C_INTERFACE_TIMING_0_0; - uint32_t I2C_I2C_INTERFACE_TIMING_1_0; - uint32_t I2C_I2C_HS_INTERFACE_TIMING_0_0; - uint32_t I2C_I2C_HS_INTERFACE_TIMING_1_0; -} tegra_i2c_t; - -#define I2C1_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x000)) -#define I2C2_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x400)) -#define I2C3_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x500)) -#define I2C4_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x700)) -#define I2C5_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x000)) -#define I2C6_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x100)) - -void i2c_config(I2CDevice id); - -void i2c_init(I2CDevice id); -bool i2c_query(I2CDevice id, uint8_t device, uint8_t r, void *dst, size_t dst_size); -bool i2c_send(I2CDevice id, uint8_t device, uint8_t r, void *src, size_t src_size); - -void i2c_send_pmic_cpu_shutdown_cmd(void); -bool i2c_query_ti_charger_bit_7(void); -void i2c_clear_ti_charger_bit_7(void); -void i2c_set_ti_charger_bit_7(void); - -#endif diff --git a/sept/sept-primary/src/main.c b/sept/sept-primary/src/main.c deleted file mode 100644 index 27b465a56..000000000 --- a/sept/sept-primary/src/main.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include "utils.h" -#include "car.h" -#include "timers.h" -#include "di.h" -#include "se.h" -#include "fuse.h" -#include "pmc.h" -#include "mc.h" -#include "sysreg.h" -#include "tsec.h" - -#define I2S_BASE 0x702D1000 -#define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n) - -static void setup_exception_vectors(void) { - for (unsigned int i = 0; i < 0x20; i += 4) { - MAKE_REG32(0x6000F200u + i) = (uint32_t)generic_panic; - } -} - -static void mbist_workaround(void) -{ - volatile tegra_car_t *car = car_get_regs(); - - car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF); - car->plld_base |= 0x40800000u; - car->rst_dev_y_clr = 0x40; - car->rst_dev_x_clr = 0x40000; - car->rst_dev_l_clr = 0x18000000; - udelay(3); - - /* Setup I2S. */ - MAKE_I2S_REG(0x0A0) |= 0x400; - MAKE_I2S_REG(0x088) &= 0xFFFFFFFE; - MAKE_I2S_REG(0x1A0) |= 0x400; - MAKE_I2S_REG(0x188) &= 0xFFFFFFFE; - MAKE_I2S_REG(0x2A0) |= 0x400; - MAKE_I2S_REG(0x288) &= 0xFFFFFFFE; - MAKE_I2S_REG(0x3A0) |= 0x400; - MAKE_I2S_REG(0x388) &= 0xFFFFFFFE; - MAKE_I2S_REG(0x4A0) |= 0x400; - MAKE_I2S_REG(0x488) &= 0xFFFFFFFE; - - MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4; - MAKE_VIC_REG(0x8C) = 0xFFFFFFFF; - udelay(3); - - /* Set devices in reset. */ - car->rst_dev_y_set = 0x40; - car->rst_dev_l_set = 0x18000000; - car->rst_dev_x_set = 0x40000; - - /* Clock out enables. */ - car->clk_out_enb_h = 0xC0; - car->clk_out_enb_l = 0x80000130; - car->clk_out_enb_u = 0x1F00200; - car->clk_out_enb_v = 0x80400808; - car->clk_out_enb_w = 0x402000FC; - car->clk_out_enb_x = 0x23000780; - car->clk_out_enb_y = 0x300; - - /* LVL2 clock gate overrides. */ - car->lvl2_clk_gate_ovra = 0; - car->lvl2_clk_gate_ovrb = 0; - car->lvl2_clk_gate_ovrc = 0; - car->lvl2_clk_gate_ovrd = 0; - car->lvl2_clk_gate_ovre = 0; - - /* Configure clock sources. */ - car->plld_base &= 0x1F7FFFFF; - car->clk_source_sor1 &= 0xFFFF3FFF; - car->clk_source_vi = ((car->clk_source_vi & 0x1FFFFFFF) | 0x80000000); - car->clk_source_host1x = ((car->clk_source_host1x & 0x1FFFFFFF) | 0x80000000); - car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000); -} - -static int tsec_dma_wait_idle() -{ - volatile tegra_tsec_t *tsec = tsec_get_regs(); - uint32_t timeout = (get_time_ms() + 10000); - - while (!(tsec->TSEC_FALCON_DMATRFCMD & 2)) - { - if (get_time_ms() > timeout) - return 0; - } - - return 1; -} - -static int tsec_dma_phys_to_flcn(bool is_imem, uint32_t flcn_offset, uint32_t phys_offset) -{ - volatile tegra_tsec_t *tsec = tsec_get_regs(); - uint32_t cmd = 0; - - if (!is_imem) - cmd = 0x600; - else - cmd = 0x10; - - tsec->TSEC_FALCON_DMATRFMOFFS = flcn_offset; - tsec->TSEC_FALCON_DMATRFFBOFFS = phys_offset; - tsec->TSEC_FALCON_DMATRFCMD = cmd; - - return tsec_dma_wait_idle(); -} - -static int tsec_kfuse_wait_ready() -{ - uint32_t timeout = (get_time_ms() + 10000); - - /* Wait for STATE_DONE. */ - while (!(KFUSE_STATE & 0x10000)) - { - if (get_time_ms() > timeout) - return 0; - } - - /* Check for STATE_CRCPASS. */ - if (!(KFUSE_STATE & 0x20000)) - return 0; - - return 1; -} - -int load_tsec_fw(void) { - volatile uint32_t* tsec_fw = (volatile uint32_t*)0x40010F00; - const uint32_t tsec_fw_length = MAKE_REG32(0x40010EFC); - - volatile tegra_tsec_t *tsec = tsec_get_regs(); - - /* Enable clocks. */ - clkrst_reboot(CARDEVICE_HOST1X); - clkrst_reboot(CARDEVICE_TSEC); - clkrst_reboot(CARDEVICE_SOR_SAFE); - clkrst_reboot(CARDEVICE_SOR0); - clkrst_reboot(CARDEVICE_SOR1); - clkrst_reboot(CARDEVICE_KFUSE); - - /* Make sure KFUSE is ready. */ - if (!tsec_kfuse_wait_ready()) - { - /* Disable clocks. */ - clkrst_disable(CARDEVICE_KFUSE); - clkrst_disable(CARDEVICE_SOR1); - clkrst_disable(CARDEVICE_SOR0); - clkrst_disable(CARDEVICE_SOR_SAFE); - clkrst_disable(CARDEVICE_TSEC); - clkrst_disable(CARDEVICE_HOST1X); - - return -1; - } - - /* Configure Falcon. */ - tsec->TSEC_FALCON_DMACTL = 0; - tsec->TSEC_FALCON_IRQMSET = 0xFFF2; - tsec->TSEC_FALCON_IRQDEST = 0xFFF0; - tsec->TSEC_FALCON_ITFEN = 3; - - /* Make sure the DMA block is idle. */ - if (!tsec_dma_wait_idle()) - { - /* Disable clocks. */ - clkrst_disable(CARDEVICE_KFUSE); - clkrst_disable(CARDEVICE_SOR1); - clkrst_disable(CARDEVICE_SOR0); - clkrst_disable(CARDEVICE_SOR_SAFE); - clkrst_disable(CARDEVICE_TSEC); - clkrst_disable(CARDEVICE_HOST1X); - - return -2; - } - - /* Load firmware. */ - tsec->TSEC_FALCON_DMATRFBASE = (uint32_t)tsec_fw >> 8; - for (uint32_t addr = 0; addr < tsec_fw_length; addr += 0x100) - { - if (!tsec_dma_phys_to_flcn(true, addr, addr)) - { - /* Disable clocks. */ - clkrst_disable(CARDEVICE_KFUSE); - clkrst_disable(CARDEVICE_SOR1); - clkrst_disable(CARDEVICE_SOR0); - clkrst_disable(CARDEVICE_SOR_SAFE); - clkrst_disable(CARDEVICE_TSEC); - clkrst_disable(CARDEVICE_HOST1X); - - return -3; - } - } - - /* Write magic value to HOST1X scratch register. */ - MAKE_HOST1X_REG(0x3300) = 0x34C2E1DA; - - /* Execute firmware. */ - tsec->TSEC_FALCON_MAILBOX1 = 0; - tsec->TSEC_FALCON_MAILBOX0 = 1; - tsec->TSEC_FALCON_BOOTVEC = 0; - tsec->TSEC_FALCON_CPUCTL = 2; - - while (true) { - /* Yield to Nintendo's TSEC firmware. */ - } -} - -int main(void) { - /* Setup vectors */ - setup_exception_vectors(); - - volatile tegra_pmc_t *pmc = pmc_get_regs(); - volatile tegra_car_t *car = car_get_regs(); - - /* Clear the boot reason to avoid problems later */ - pmc->scratch200 = 0; - pmc->rst_status = 0; - - //AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F; - //pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD); - - /* Apply the memory built-in self test workaround. */ - mbist_workaround(); - - /* Reboot SE. */ - clkrst_reboot(CARDEVICE_SE); - - /* Initialize the fuse driver. */ - fuse_init(); - - /* Don't bother checking SKU, fuses, or bootloader version. */ - mc_enable_for_tsec(); - - /* 7.0.0 package1ldr holds I2C5 in reset, clears SYS clock. */ - car->clk_source_sys = 0; - rst_enable(CARDEVICE_I2C5); - - load_tsec_fw(); - - while (true) { } - return 0; -} diff --git a/sept/sept-primary/src/mc.c b/sept/sept-primary/src/mc.c deleted file mode 100644 index dc7f4917a..000000000 --- a/sept/sept-primary/src/mc.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "mc.h" -#include "car.h" -#include "timers.h" - -void mc_enable_for_tsec() -{ - volatile tegra_car_t *car = car_get_regs(); - - /* Set EMC clock source. */ - car->clk_source_emc = ((car->clk_source_emc & 0x1FFFFFFF) | 0x40000000); - - /* Enable MIPI CAL clock. */ - car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFDFFFFFF) | 0x2000000); - - /* Enable MC clock. */ - car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFFFFFFFE) | 1); - - /* Enable EMC DLL clock. */ - car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000); - - /* Clear EMC and MC reset. */ - /* NOTE: [4.0.0+] This was changed to use the right register. */ - /* car->rst_dev_h_set = 0x2000001; */ - car->rst_dev_h_clr = 0x2000001; - udelay(5); - - /* Enable AHB redirect, weird boundaries for new TSEC firmware. */ - car->lvl2_clk_gate_ovrd = ((car->lvl2_clk_gate_ovrd & 0xFFF7FFFF) | 0x80000); - - MAKE_MC_REG(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE; - MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000; - MAKE_MC_REG(MC_IRAM_TOM) = 0x80000000; -} \ No newline at end of file diff --git a/sept/sept-primary/src/mc.h b/sept/sept-primary/src/mc.h deleted file mode 100644 index fad84a8c9..000000000 --- a/sept/sept-primary/src/mc.h +++ /dev/null @@ -1,601 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA Corporation. All rights reserved. - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_MC_H_ -#define FUSEE_MC_H_ - -#include -#include - -#define MC_BASE 0x70019000 -#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n) - -#define MC_INTSTATUS 0x0 -#define MC_INTMASK 0x4 -#define MC_ERR_STATUS 0x8 -#define MC_ERR_ADR 0xc -#define MC_SMMU_CONFIG 0x10 -#define MC_SMMU_TLB_CONFIG 0x14 -#define MC_SMMU_PTC_CONFIG 0x18 -#define MC_SMMU_PTB_ASID 0x1c -#define MC_SMMU_PTB_DATA 0x20 -#define MC_SMMU_TLB_FLUSH 0x30 -#define MC_SMMU_PTC_FLUSH 0x34 -#define MC_SMMU_ASID_SECURITY 0x38 -#define MC_SMMU_ASID_SECURITY_1 0x3c -#define MC_SMMU_ASID_SECURITY_2 0x9e0 -#define MC_SMMU_ASID_SECURITY_3 0x9e4 -#define MC_SMMU_ASID_SECURITY_4 0x9e8 -#define MC_SMMU_ASID_SECURITY_5 0x9ec -#define MC_SMMU_ASID_SECURITY_6 0x9f0 -#define MC_SMMU_ASID_SECURITY_7 0x9f4 -#define MC_SMMU_AFI_ASID 0x238 -#define MC_SMMU_AVPC_ASID 0x23c -#define MC_SMMU_TSEC_ASID 0x294 -#define MC_SMMU_PPCS1_ASID 0x298 -#define MC_SMMU_TRANSLATION_ENABLE_0 0x228 -#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c -#define MC_SMMU_TRANSLATION_ENABLE_2 0x230 -#define MC_SMMU_TRANSLATION_ENABLE_3 0x234 -#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98 -#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0 -#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 -#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8 -#define MC_PCFIFO_CLIENT_CONFIG3 0xddc -#define MC_PCFIFO_CLIENT_CONFIG4 0xde0 -#define MC_EMEM_CFG 0x50 -#define MC_EMEM_ADR_CFG 0x54 -#define MC_EMEM_ADR_CFG_DEV0 0x58 -#define MC_EMEM_ADR_CFG_DEV1 0x5c -#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60 -#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64 -#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68 -#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c -#define MC_SECURITY_CFG0 0x70 -#define MC_SECURITY_CFG1 0x74 -#define MC_SECURITY_CFG3 0x9bc -#define MC_SECURITY_RSV 0x7c -#define MC_EMEM_ARB_CFG 0x90 -#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 -#define MC_EMEM_ARB_TIMING_RCD 0x98 -#define MC_EMEM_ARB_TIMING_RP 0x9c -#define MC_EMEM_ARB_TIMING_RC 0xa0 -#define MC_EMEM_ARB_TIMING_RAS 0xa4 -#define MC_EMEM_ARB_TIMING_FAW 0xa8 -#define MC_EMEM_ARB_TIMING_RRD 0xac -#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 -#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 -#define MC_EMEM_ARB_TIMING_R2R 0xb8 -#define MC_EMEM_ARB_TIMING_W2W 0xbc -#define MC_EMEM_ARB_TIMING_R2W 0xc0 -#define MC_EMEM_ARB_TIMING_W2R 0xc4 -#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0 -#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4 -#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0 -#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4 -#define MC_EMEM_ARB_DA_TURNS 0xd0 -#define MC_EMEM_ARB_DA_COVERS 0xd4 -#define MC_EMEM_ARB_MISC0 0xd8 -#define MC_EMEM_ARB_MISC1 0xdc -#define MC_EMEM_ARB_MISC2 0xc8 -#define MC_EMEM_ARB_RING1_THROTTLE 0xe0 -#define MC_EMEM_ARB_RING3_THROTTLE 0xe4 -#define MC_EMEM_ARB_NISO_THROTTLE 0x6b0 -#define MC_EMEM_ARB_OVERRIDE 0xe8 -#define MC_EMEM_ARB_RSV 0xec -#define MC_CLKEN_OVERRIDE 0xf4 -#define MC_TIMING_CONTROL_DBG 0xf8 -#define MC_TIMING_CONTROL 0xfc -#define MC_STAT_CONTROL 0x100 -#define MC_STAT_STATUS 0x104 -#define MC_STAT_EMC_CLOCK_LIMIT 0x108 -#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c -#define MC_STAT_EMC_CLOCKS 0x110 -#define MC_STAT_EMC_CLOCKS_MSBS 0x114 -#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118 -#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158 -#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c -#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c -#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20 -#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24 -#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198 -#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8 -#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c -#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac -#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28 -#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c -#define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0 -#define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0 -#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120 -#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160 -#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128 -#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168 -#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c -#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c -#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130 -#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170 -#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134 -#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88 -#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174 -#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c -#define MC_STAT_EMC_SET0_COUNT 0x138 -#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c -#define MC_STAT_EMC_SET1_COUNT 0x178 -#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c -#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140 -#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144 -#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180 -#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184 -#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148 -#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c -#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188 -#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c -#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150 -#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190 -#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8 -#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc -#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8 -#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc -#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0 -#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0 -#define MC_CLIENT_HOTRESET_CTRL 0x200 -#define MC_CLIENT_HOTRESET_CTRL_1 0x970 -#define MC_CLIENT_HOTRESET_STATUS 0x204 -#define MC_CLIENT_HOTRESET_STATUS_1 0x974 -#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208 -#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c -#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210 -#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214 -#define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94 -#define MC_EMEM_ARB_HYSTERESIS_0 0x218 -#define MC_EMEM_ARB_HYSTERESIS_1 0x21c -#define MC_EMEM_ARB_HYSTERESIS_2 0x220 -#define MC_EMEM_ARB_HYSTERESIS_3 0x224 -#define MC_EMEM_ARB_HYSTERESIS_4 0xb84 -#define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0 -#define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4 -#define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8 -#define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc -#define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0 -#define MC_EMEM_ARB_DHYST_CTRL 0xbcc -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec -#define MC_RESERVED_RSV 0x3fc -#define MC_DISB_EXTRA_SNAP_LEVELS 0x408 -#define MC_APB_EXTRA_SNAP_LEVELS 0x2a4 -#define MC_AHB_EXTRA_SNAP_LEVELS 0x2a0 -#define MC_USBD_EXTRA_SNAP_LEVELS 0xa18 -#define MC_ISP_EXTRA_SNAP_LEVELS 0xa08 -#define MC_AUD_EXTRA_SNAP_LEVELS 0xa10 -#define MC_MSE_EXTRA_SNAP_LEVELS 0x40c -#define MC_GK2_EXTRA_SNAP_LEVELS 0xa40 -#define MC_A9AVPPC_EXTRA_SNAP_LEVELS 0x414 -#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc -#define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c -#define MC_HOST_EXTRA_SNAP_LEVELS 0xa14 -#define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0 -#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac -#define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c -#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48 -#define MC_AVP_EXTRA_SNAP_LEVELS 0x2a8 -#define MC_USBX_EXTRA_SNAP_LEVELS 0x404 -#define MC_PCX_EXTRA_SNAP_LEVELS 0x2b8 -#define MC_SD_EXTRA_SNAP_LEVELS 0xa04 -#define MC_DFD_EXTRA_SNAP_LEVELS 0xa4c -#define MC_VE_EXTRA_SNAP_LEVELS 0x2d8 -#define MC_GK_EXTRA_SNAP_LEVELS 0xa00 -#define MC_VE2_EXTRA_SNAP_LEVELS 0x410 -#define MC_SDM_EXTRA_SNAP_LEVELS 0xa44 -#define MC_VIDEO_PROTECT_BOM 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c -#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978 -#define MC_VIDEO_PROTECT_REG_CTRL 0x650 -#define MC_ERR_VPR_STATUS 0x654 -#define MC_ERR_VPR_ADR 0x658 -#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418 -#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590 -#define MC_IRAM_BOM 0x65c -#define MC_IRAM_TOM 0x660 -#define MC_IRAM_ADR_HI 0x980 -#define MC_IRAM_REG_CTRL 0x964 -#define MC_EMEM_CFG_ACCESS_CTRL 0x664 -#define MC_TZ_SECURITY_CTRL 0x668 -#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c -#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4 -#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc -#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8 -#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80 -#define MC_SEC_CARVEOUT_BOM 0x670 -#define MC_SEC_CARVEOUT_SIZE_MB 0x674 -#define MC_SEC_CARVEOUT_ADR_HI 0x9d4 -#define MC_SEC_CARVEOUT_REG_CTRL 0x678 -#define MC_ERR_SEC_STATUS 0x67c -#define MC_ERR_SEC_ADR 0x680 -#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684 -#define MC_STUTTER_CONTROL 0x688 -#define MC_RESERVED_RSV_1 0x958 -#define MC_DVFS_PIPE_SELECT 0x95c -#define MC_AHB_PTSA_MIN 0x4e0 -#define MC_AUD_PTSA_MIN 0x54c -#define MC_MLL_MPCORER_PTSA_RATE 0x44c -#define MC_RING2_PTSA_RATE 0x440 -#define MC_USBD_PTSA_RATE 0x530 -#define MC_USBX_PTSA_MIN 0x528 -#define MC_USBD_PTSA_MIN 0x534 -#define MC_APB_PTSA_MAX 0x4f0 -#define MC_JPG_PTSA_RATE 0x584 -#define MC_DIS_PTSA_MIN 0x420 -#define MC_AVP_PTSA_MAX 0x4fc -#define MC_AVP_PTSA_RATE 0x4f4 -#define MC_RING1_PTSA_MIN 0x480 -#define MC_DIS_PTSA_MAX 0x424 -#define MC_SD_PTSA_MAX 0x4d8 -#define MC_MSE_PTSA_RATE 0x4c4 -#define MC_VICPC_PTSA_MIN 0x558 -#define MC_PCX_PTSA_MAX 0x4b4 -#define MC_ISP_PTSA_RATE 0x4a0 -#define MC_A9AVPPC_PTSA_MIN 0x48c -#define MC_RING2_PTSA_MAX 0x448 -#define MC_AUD_PTSA_RATE 0x548 -#define MC_HOST_PTSA_MIN 0x51c -#define MC_MLL_MPCORER_PTSA_MAX 0x454 -#define MC_SD_PTSA_MIN 0x4d4 -#define MC_RING1_PTSA_RATE 0x47c -#define MC_JPG_PTSA_MIN 0x588 -#define MC_HDAPC_PTSA_MIN 0x62c -#define MC_AVP_PTSA_MIN 0x4f8 -#define MC_JPG_PTSA_MAX 0x58c -#define MC_VE_PTSA_MAX 0x43c -#define MC_DFD_PTSA_MAX 0x63c -#define MC_VICPC_PTSA_RATE 0x554 -#define MC_GK_PTSA_MAX 0x544 -#define MC_VICPC_PTSA_MAX 0x55c -#define MC_SDM_PTSA_MAX 0x624 -#define MC_SAX_PTSA_RATE 0x4b8 -#define MC_PCX_PTSA_MIN 0x4b0 -#define MC_APB_PTSA_MIN 0x4ec -#define MC_GK2_PTSA_MIN 0x614 -#define MC_PCX_PTSA_RATE 0x4ac -#define MC_RING1_PTSA_MAX 0x484 -#define MC_HDAPC_PTSA_RATE 0x628 -#define MC_MLL_MPCORER_PTSA_MIN 0x450 -#define MC_GK2_PTSA_MAX 0x618 -#define MC_AUD_PTSA_MAX 0x550 -#define MC_GK2_PTSA_RATE 0x610 -#define MC_ISP_PTSA_MAX 0x4a8 -#define MC_DISB_PTSA_RATE 0x428 -#define MC_VE2_PTSA_MAX 0x49c -#define MC_DFD_PTSA_MIN 0x638 -#define MC_FTOP_PTSA_RATE 0x50c -#define MC_A9AVPPC_PTSA_RATE 0x488 -#define MC_VE2_PTSA_MIN 0x498 -#define MC_USBX_PTSA_MAX 0x52c -#define MC_DIS_PTSA_RATE 0x41c -#define MC_USBD_PTSA_MAX 0x538 -#define MC_A9AVPPC_PTSA_MAX 0x490 -#define MC_USBX_PTSA_RATE 0x524 -#define MC_FTOP_PTSA_MAX 0x514 -#define MC_HDAPC_PTSA_MAX 0x630 -#define MC_SD_PTSA_RATE 0x4d0 -#define MC_DFD_PTSA_RATE 0x634 -#define MC_FTOP_PTSA_MIN 0x510 -#define MC_SDM_PTSA_RATE 0x61c -#define MC_AHB_PTSA_RATE 0x4dc -#define MC_SMMU_SMMU_PTSA_MAX 0x460 -#define MC_RING2_PTSA_MIN 0x444 -#define MC_SDM_PTSA_MIN 0x620 -#define MC_APB_PTSA_RATE 0x4e8 -#define MC_MSE_PTSA_MIN 0x4c8 -#define MC_HOST_PTSA_RATE 0x518 -#define MC_VE_PTSA_RATE 0x434 -#define MC_AHB_PTSA_MAX 0x4e4 -#define MC_SAX_PTSA_MIN 0x4bc -#define MC_SMMU_SMMU_PTSA_MIN 0x45c -#define MC_ISP_PTSA_MIN 0x4a4 -#define MC_HOST_PTSA_MAX 0x520 -#define MC_SAX_PTSA_MAX 0x4c0 -#define MC_VE_PTSA_MIN 0x438 -#define MC_GK_PTSA_MIN 0x540 -#define MC_MSE_PTSA_MAX 0x4cc -#define MC_DISB_PTSA_MAX 0x430 -#define MC_DISB_PTSA_MIN 0x42c -#define MC_SMMU_SMMU_PTSA_RATE 0x458 -#define MC_VE2_PTSA_RATE 0x494 -#define MC_GK_PTSA_RATE 0x53c -#define MC_PTSA_GRANT_DECREMENT 0x960 -#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4 -#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0 -#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380 -#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384 -#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc -#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8 -#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370 -#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0 -#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374 -#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8 -#define MC_LATENCY_ALLOWANCE_VIC_0 0x394 -#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8 -#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8 -#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc -#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390 -#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0 -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694 -#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 -#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c -#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 -#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0 -#define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0 -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698 -#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec -#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0 -#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4 -#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8 -#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4 -#define MC_LATENCY_ALLOWANCE_HC_1 0x314 -#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0 -#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4 -#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c -#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec -#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 -#define MC_LATENCY_ALLOWANCE_VI2_0 0x398 -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4 -#define MC_LATENCY_ALLOWANCE_SATA_0 0x350 -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690 -#define MC_LATENCY_ALLOWANCE_HC_0 0x310 -#define MC_LATENCY_ALLOWANCE_DC_3 0x3c8 -#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac -#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4 -#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388 -#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328 -#define MC_LATENCY_ALLOWANCE_HDA_0 0x318 -#define MC_MIN_LENGTH_APE_0 0xb34 -#define MC_MIN_LENGTH_DCB_2 0x8a8 -#define MC_MIN_LENGTH_A9AVP_0 0x950 -#define MC_MIN_LENGTH_TSEC_0 0x93c -#define MC_MIN_LENGTH_DC_1 0x898 -#define MC_MIN_LENGTH_AXIAP_0 0x94c -#define MC_MIN_LENGTH_ISP2B_0 0x930 -#define MC_MIN_LENGTH_VI2_0 0x944 -#define MC_MIN_LENGTH_DCB_0 0x8a0 -#define MC_MIN_LENGTH_DCB_1 0x8a4 -#define MC_MIN_LENGTH_PPCS_1 0x8f4 -#define MC_MIN_LENGTH_NVJPG_0 0xb3c -#define MC_MIN_LENGTH_HDA_0 0x8c4 -#define MC_MIN_LENGTH_NVENC_0 0x8d4 -#define MC_MIN_LENGTH_SDMMC_0 0xb18 -#define MC_MIN_LENGTH_ISP2B_1 0x934 -#define MC_MIN_LENGTH_HC_1 0x8c0 -#define MC_MIN_LENGTH_DC_3 0xb20 -#define MC_MIN_LENGTH_AVPC_0 0x890 -#define MC_MIN_LENGTH_VIC_0 0x940 -#define MC_MIN_LENGTH_ISP2_0 0x91c -#define MC_MIN_LENGTH_HC_0 0x8bc -#define MC_MIN_LENGTH_SE_0 0xb38 -#define MC_MIN_LENGTH_NVDEC_0 0xb30 -#define MC_MIN_LENGTH_SATA_0 0x8fc -#define MC_MIN_LENGTH_DC_0 0x894 -#define MC_MIN_LENGTH_XUSB_1 0x92c -#define MC_MIN_LENGTH_DC_2 0x89c -#define MC_MIN_LENGTH_SDMMCAA_0 0xb14 -#define MC_MIN_LENGTH_GPU_0 0xb04 -#define MC_MIN_LENGTH_ETR_0 0xb44 -#define MC_MIN_LENGTH_AFI_0 0x88c -#define MC_MIN_LENGTH_PPCS_0 0x8f0 -#define MC_MIN_LENGTH_ISP2_1 0x920 -#define MC_MIN_LENGTH_XUSB_0 0x928 -#define MC_MIN_LENGTH_MPCORE_0 0x8cc -#define MC_MIN_LENGTH_TSECB_0 0xb48 -#define MC_MIN_LENGTH_SDMMCA_0 0xb10 -#define MC_MIN_LENGTH_GPU2_0 0xb40 -#define MC_MIN_LENGTH_SDMMCAB_0 0xb1c -#define MC_MIN_LENGTH_PTC_0 0x8f8 -#define MC_EMEM_ARB_OVERRIDE_1 0x968 -#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984 -#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988 -#define MC_EMEM_ARB_STATS_0 0x990 -#define MC_EMEM_ARB_STATS_1 0x994 -#define MC_MTS_CARVEOUT_BOM 0x9a0 -#define MC_MTS_CARVEOUT_SIZE_MB 0x9a4 -#define MC_MTS_CARVEOUT_ADR_HI 0x9a8 -#define MC_MTS_CARVEOUT_REG_CTRL 0x9ac -#define MC_ERR_MTS_STATUS 0x9b0 -#define MC_ERR_MTS_ADR 0x9b4 -#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 -#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 -#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd74 -#define MC_SECURITY_CARVEOUT4_CFG0 0xcf8 -#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10 -#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04 -#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28 -#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc30 -#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc8c -#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd1c -#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd70 -#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc2c -#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd7c -#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4 -#define MC_SECURITY_CARVEOUT2_CFG0 0xc58 -#define MC_SECURITY_CARVEOUT1_CFG0 0xc08 -#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc84 -#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68 -#define MC_SECURITY_CARVEOUT3_BOM 0xcac -#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70 -#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd78 -#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc7c -#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18 -#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc -#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc38 -#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc34 -#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0 -#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60 -#define MC_SECURITY_CARVEOUT3_CFG0 0xca8 -#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8 -#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc88 -#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64 -#define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50 -#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14 -#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14 -#define MC_SECURITY_CARVEOUT1_BOM 0xc0c -#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd2c -#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68 -#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8 -#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58 -#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd24 -#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4 -#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78 -#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c -#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18 -#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd28 -#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c -#define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0 -#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcd8 -#define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60 -#define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00 -#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64 -#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xcdc -#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc80 -#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54 -#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd20 -#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd4 -#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c -#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74 -#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xccc -#define MC_SECURITY_CARVEOUT4_BOM 0xcfc -#define MC_SECURITY_CARVEOUT5_CFG0 0xd48 -#define MC_SECURITY_CARVEOUT2_BOM 0xc5c -#define MC_SECURITY_CARVEOUT5_BOM 0xd4c -#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24 -#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd6c -#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd0 -#define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10 -#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20 -#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc3c -#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c -#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 -#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 -#define MC_DA_CONFIG0 0x9dc -#define MC_UNTRANSLATED_REGION_CHECK 0x948 - -/* Memory Controller clients */ -#define CLIENT_ACCESS_NUM_CLIENTS 32 -typedef enum { - /* _ACCESS0 */ - CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - - /* _ACCESS1 */ - CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - - /* _ACCESS2 */ - CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - - /* _ACCESS3 */ - CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - - /* _ACCESS4 */ - CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4)) -} McClient; - -void mc_enable_for_tsec(); - -#endif \ No newline at end of file diff --git a/sept/sept-primary/src/panic.c b/sept/sept-primary/src/panic.c deleted file mode 100644 index 99c37fe06..000000000 --- a/sept/sept-primary/src/panic.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "panic.h" -#include "di.h" -#include "pmc.h" -#include "fuse.h" -#include "utils.h" - -static uint32_t g_panic_code = 0; - -void check_panic(void) { - /* We also handle our own panics. */ - /* In the case of our own panics, we assume that the display has already been initialized. */ - bool has_panic = APBDEV_PMC_RST_STATUS_0 != 0 || g_panic_code != 0; - uint32_t code = g_panic_code == 0 ? APBDEV_PMC_SCRATCH200_0 : g_panic_code; - - has_panic = has_panic && !(APBDEV_PMC_RST_STATUS_0 != 1 && code == PANIC_CODE_SAFEMODE); - - if (has_panic) { - uint32_t color; - - /* Check for predefined codes: */ - switch (code & MASK(20)) { - case 0x01: /* Package2 signature verification failed. */ - case 0x02: /* Package2 meta verification failed. */ - case 0x03: /* Package2 version check failed. */ - case 0x04: /* Package2 payload verification failed. */ - color = PANIC_COLOR_KERNEL; - break; - case 0x05: /* Unknown SMC. */ - case 0x06: /* Unknown Abort. */ - color = PANIC_COLOR_SECMON_GENERIC; - break; - case 0x07: /* Invalid CPU context. */ - case 0x08: /* Invalid SE state. */ - case 0x09: /* CPU is already awake (2.0.0+). */ - color = PANIC_COLOR_SECMON_DEEPSLEEP; - break; - case 0x10: /* Unknown exception. */ - color = PANIC_COLOR_SECMON_EXCEPTION; - break; - case 0x30: /* General bootloader error. */ - case 0x31: /* Invalid DRAM ID. */ - case 0x32: /* Invalid size. */ - case 0x33: /* Invalid arguement. */ - case 0x34: /* Bad GPT. */ - case 0x35: /* Failed to boot SafeMode. */ - case 0x36: /* Activity monitor fired (4.0.0+). */ - color = PANIC_COLOR_BOOTLOADER_GENERIC; - break; - case 0x40: /* Kernel panic. */ - color = PANIC_COLOR_KERNEL; - break; - default: - color = code >> 20; - color |= color << 4; - break; - } - - wait_for_button_and_reboot(); - } else { - g_panic_code = 0; - APBDEV_PMC_SCRATCH200_0 = 0; - } -} - -__attribute__ ((noreturn)) void panic(uint32_t code) { - /* Set panic code. */ - if (g_panic_code == 0) { - g_panic_code = code; - APBDEV_PMC_SCRATCH200_0 = code; - } - - fuse_disable_programming(); - APBDEV_PMC_CRYPTO_OP_0 = 1; /* Disable all SE operations. */ - - check_panic(); - while(true); -} diff --git a/sept/sept-primary/src/panic.h b/sept/sept-primary/src/panic.h deleted file mode 100644 index 3aedac4bf..000000000 --- a/sept/sept-primary/src/panic.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_PANIC_H -#define FUSEE_PANIC_H - -#include - -#define PANIC_COLOR_KERNEL 0x0000FF -#define PANIC_COLOR_SECMON_EXCEPTION 0xFF7700 -#define PANIC_COLOR_SECMON_GENERIC 0x00FFFF -#define PANIC_COLOR_SECMON_DEEPSLEEP 0xFF77FF /* 4.0+ color */ -#define PANIC_COLOR_BOOTLOADER_GENERIC 0xAA00FF -#define PANIC_COLOR_BOOTLOADER_SAFEMODE 0xFFFFAA /* Removed */ - -#define PANIC_CODE_SAFEMODE 0x00000020 - -void check_and_display_panic(void); -__attribute__ ((noreturn)) void panic(uint32_t code); - -#endif diff --git a/sept/sept-primary/src/pinmux.h b/sept/sept-primary/src/pinmux.h deleted file mode 100644 index 616e90262..000000000 --- a/sept/sept-primary/src/pinmux.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_PINMUX_H -#define FUSEE_PINMUX_H - -#define PINMUX_BASE 0x70003000 -#define MAKE_PINMUX_REG(n) MAKE_REG32(PINMUX_BASE + n) - -#define PINMUX_TRISTATE (1 << 4) -#define PINMUX_PARKED (1 << 5) -#define PINMUX_INPUT (1 << 6) -#define PINMUX_PULL_NONE (0 << 2) -#define PINMUX_PULL_DOWN (1 << 2) -#define PINMUX_PULL_UP (2 << 2) -#define PINMUX_SELECT_FUNCTION0 0 -#define PINMUX_SELECT_FUNCTION1 1 -#define PINMUX_SELECT_FUNCTION2 2 -#define PINMUX_SELECT_FUNCTION3 3 -#define PINMUX_DRIVE_1X (0 << 13) -#define PINMUX_DRIVE_2X (1 << 13) -#define PINMUX_DRIVE_3X (2 << 13) -#define PINMUX_DRIVE_4X (3 << 13) - -typedef struct { - uint32_t sdmmc1_clk; - uint32_t sdmmc1_cmd; - uint32_t sdmmc1_dat3; - uint32_t sdmmc1_dat2; - uint32_t sdmmc1_dat1; - uint32_t sdmmc1_dat0; - uint32_t _r18; - uint32_t sdmmc3_clk; - uint32_t sdmmc3_cmd; - uint32_t sdmmc3_dat0; - uint32_t sdmmc3_dat1; - uint32_t sdmmc3_dat2; - uint32_t sdmmc3_dat3; - uint32_t _r34; - uint32_t pex_l0_rst_n; - uint32_t pex_l0_clkreq_n; - uint32_t pex_wake_n; - uint32_t pex_l1_rst_n; - uint32_t pex_l1_clkreq_n; - uint32_t sata_led_active; - uint32_t spi1_mosi; - uint32_t spi1_miso; - uint32_t spi1_sck; - uint32_t spi1_cs0; - uint32_t spi1_cs1; - uint32_t spi2_mosi; - uint32_t spi2_miso; - uint32_t spi2_sck; - uint32_t spi2_cs0; - uint32_t spi2_cs1; - uint32_t spi4_mosi; - uint32_t spi4_miso; - uint32_t spi4_sck; - uint32_t spi4_cs0; - uint32_t qspi_sck; - uint32_t qspi_cs_n; - uint32_t qspi_io0; - uint32_t qspi_io1; - uint32_t qspi_io2; - uint32_t qspi_io3; - uint32_t _ra0; - uint32_t dmic1_clk; - uint32_t dmic1_dat; - uint32_t dmic2_clk; - uint32_t dmic2_dat; - uint32_t dmic3_clk; - uint32_t dmic3_dat; - uint32_t gen1_i2c_scl; - uint32_t gen1_i2c_sda; - uint32_t gen2_i2c_scl; - uint32_t gen2_i2c_sda; - uint32_t gen3_i2c_scl; - uint32_t gen3_i2c_sda; - uint32_t cam_i2c_scl; - uint32_t cam_i2c_sda; - uint32_t pwr_i2c_scl; - uint32_t pwr_i2c_sda; - uint32_t uart1_tx; - uint32_t uart1_rx; - uint32_t uart1_rts; - uint32_t uart1_cts; - uint32_t uart2_tx; - uint32_t uart2_rx; - uint32_t uart2_rts; - uint32_t uart2_cts; - uint32_t uart3_tx; - uint32_t uart3_rx; - uint32_t uart3_rts; - uint32_t uart3_cts; - uint32_t uart4_tx; - uint32_t uart4_rx; - uint32_t uart4_rts; - uint32_t uart4_cts; - uint32_t dap1_fs; - uint32_t dap1_din; - uint32_t dap1_dout; - uint32_t dap1_sclk; - uint32_t dap2_fs; - uint32_t dap2_din; - uint32_t dap2_dout; - uint32_t dap2_sclk; - uint32_t dap4_fs; - uint32_t dap4_din; - uint32_t dap4_dout; - uint32_t dap4_sclk; - uint32_t cam1_mclk; - uint32_t cam2_mclk; - uint32_t jtag_rtck; - uint32_t clk_32k_in; - uint32_t clk_32k_out; - uint32_t batt_bcl; - uint32_t clk_req; - uint32_t cpu_pwr_req; - uint32_t pwr_int_n; - uint32_t shutdown; - uint32_t core_pwr_req; - uint32_t aud_mclk; - uint32_t dvfs_pwm; - uint32_t dvfs_clk; - uint32_t gpio_x1_aud; - uint32_t gpio_x3_aud; - uint32_t pcc7; - uint32_t hdmi_cec; - uint32_t hdmi_int_dp_hpd; - uint32_t spdif_out; - uint32_t spdif_in; - uint32_t usb_vbus_en0; - uint32_t usb_vbus_en1; - uint32_t dp_hpd0; - uint32_t wifi_en; - uint32_t wifi_rst; - uint32_t wifi_wake_ap; - uint32_t ap_wake_bt; - uint32_t bt_rst; - uint32_t bt_wake_ap; - uint32_t ap_wake_nfc; - uint32_t nfc_en; - uint32_t nfc_int; - uint32_t gps_en; - uint32_t gps_rst; - uint32_t cam_rst; - uint32_t cam_af_en; - uint32_t cam_flash_en; - uint32_t cam1_pwdn; - uint32_t cam2_pwdn; - uint32_t cam1_strobe; - uint32_t lcd_te; - uint32_t lcd_bl_pwm; - uint32_t lcd_bl_en; - uint32_t lcd_rst; - uint32_t lcd_gpio1; - uint32_t lcd_gpio2; - uint32_t ap_ready; - uint32_t touch_rst; - uint32_t touch_clk; - uint32_t modem_wake_ap; - uint32_t touch_int; - uint32_t motion_int; - uint32_t als_prox_int; - uint32_t temp_alert; - uint32_t button_power_on; - uint32_t button_vol_up; - uint32_t button_vol_down; - uint32_t button_slide_sw; - uint32_t button_home; - uint32_t pa6; - uint32_t pe6; - uint32_t pe7; - uint32_t ph6; - uint32_t pk0; - uint32_t pk1; - uint32_t pk2; - uint32_t pk3; - uint32_t pk4; - uint32_t pk5; - uint32_t pk6; - uint32_t pk7; - uint32_t pl0; - uint32_t pl1; - uint32_t pz0; - uint32_t pz1; - uint32_t pz2; - uint32_t pz3; - uint32_t pz4; - uint32_t pz5; -} tegra_pinmux_t; - -static inline volatile tegra_pinmux_t *pinmux_get_regs(void) -{ - return (volatile tegra_pinmux_t *)PINMUX_BASE; -} - -#endif diff --git a/sept/sept-primary/src/pmc.h b/sept/sept-primary/src/pmc.h deleted file mode 100644 index a287d85e7..000000000 --- a/sept/sept-primary/src/pmc.h +++ /dev/null @@ -1,713 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_PMC_H -#define FUSEE_PMC_H - -#include - -#define PMC_BASE 0x7000E400 -#define MAKE_PMC_REG(n) MAKE_REG32(PMC_BASE + n) - -#define PMC_CONTROL_SDMMC1 (1 << 12) -#define PMC_CONTROL_SDMMC3 (1 << 13) -#define PMC_CONTROL_SDMMC4 (1 << 14) - -#define APBDEV_PMC_CONTROL MAKE_PMC_REG(0x00) -#define APBDEV_PM_0 MAKE_PMC_REG(0x14) -#define APBDEV_PMC_DPD_ENABLE_0 MAKE_PMC_REG(0x24) -#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x30) -#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x38) -#define APBDEV_PMC_NO_IOPOWER_0 MAKE_PMC_REG(0x44) -#define APBDEV_PMC_SCRATCH0_0 MAKE_PMC_REG(0x50) -#define APBDEV_PMC_SCRATCH1_0 MAKE_PMC_REG(0x54) -#define APBDEV_PMC_SCRATCH20_0 MAKE_PMC_REG(0xA0) -#define APBDEV_PMC_PWR_DET_VAL_0 MAKE_PMC_REG(0xE4) -#define APBDEV_PMC_DDR_PWR_0 MAKE_PMC_REG(0xE8) -#define APBDEV_PMC_CRYPTO_OP_0 MAKE_PMC_REG(0xF4) -#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_PMC_REG(0x168) -#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4) -#define APBDEV_PMC_RST_STATUS_0 MAKE_PMC_REG(0x1B4) -#define APBDEV_PMC_IO_DPD_REQ_0 MAKE_PMC_REG(0x1B8) -#define APBDEV_PMC_IO_DPD2_REQ_0 MAKE_PMC_REG(0x1C0) -#define APBDEV_PMC_VDDP_SEL_0 MAKE_PMC_REG(0x1CC) -#define APBDEV_PMC_SCRATCH49_0 MAKE_PMC_REG(0x244) -#define APBDEV_PMC_TSC_MULT_0 MAKE_PMC_REG(0x2B4) -#define APBDEV_PMC_REG_SHORT_0 MAKE_PMC_REG(0x2CC) -#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8) -#define APBDEV_PMC_SECURE_SCRATCH21_0 MAKE_PMC_REG(0x334) -#define APBDEV_PMC_SECURE_SCRATCH32_0 MAKE_PMC_REG(0x360) -#define APBDEV_PMC_SECURE_SCRATCH49_0 MAKE_PMC_REG(0x3A4) -#define APBDEV_PMC_CNTRL2_0 MAKE_PMC_REG(0x440) -#define APBDEV_PMC_IO_DPD4_REQ_0 MAKE_PMC_REG(0x464) -#define APBDEV_PMC_UTMIP_PAD_CFG1_0 MAKE_PMC_REG(0x4C4) -#define APBDEV_PMC_UTMIP_PAD_CFG3_0 MAKE_PMC_REG(0x4CC) -#define APBDEV_PMC_DDR_CNTRL_0 MAKE_PMC_REG(0x4E4) -#define APBDEV_PMC_SCRATCH43_0 MAKE_PMC_REG(0x22C) -#define APBDEV_PMC_SCRATCH188_0 MAKE_PMC_REG(0x810) -#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818) -#define APBDEV_PMC_SCRATCH200_0 MAKE_PMC_REG(0x840) - -#define APBDEV_PMC_SCRATCH45_0 MAKE_PMC_REG(0x234) -#define APBDEV_PMC_SCRATCH46_0 MAKE_PMC_REG(0x238) -#define APBDEV_PMC_SCRATCH33_0 MAKE_PMC_REG(0x120) -#define APBDEV_PMC_SCRATCH40_0 MAKE_PMC_REG(0x13C) - -/* Power Management Controller (APBDEV_PMC_) regs */ -typedef struct { - uint32_t cntrl; /* _CNTRL_0, 0x00 */ - uint32_t sec_disable; /* _SEC_DISABLE_0, 0x04 */ - uint32_t pmc_swrst; /* _PMC_SWRST_0, 0x08 */ - uint32_t wake_mask; /* _WAKE_MASK_0, 0x0c */ - uint32_t wake_lvl; /* _WAKE_LVL_0, 0x10 */ - uint32_t wake_status; /* _WAKE_STATUS_0, 0x14 */ - uint32_t sw_wake_status; /* _SW_WAKE_STATUS_0, 0x18 */ - uint32_t dpd_pads_oride; /* _DPD_PADS_ORIDE_0, 0x1c */ - uint32_t dpd_sample; /* _DPD_SAMPLE_0, 0x20 */ - uint32_t dpd_enable; /* _DPD_ENABLE_0, 0x24 */ - uint32_t pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, 0x28 */ - uint32_t clamp_status; /* _CLAMP_STATUS_0, 0x2c */ - uint32_t pwrgate_toggle; /* _PWRGATE_TOGGLE_0, 0x30 */ - uint32_t remove_clamping; /* _REMOVE_CLAMPING_0, 0x34 */ - uint32_t pwrgate_status; /* _PWRGATE_STATUS_0, 0x38 */ - uint32_t pwrgood_timer; /* _PWRGOOD_TIMER_0, 0x3c */ - uint32_t blink_timer; /* _BLINK_TIMER_0, 0x40 */ - uint32_t no_iopower; /* _NO_IOPOWER_0, 0x44 */ - uint32_t pwr_det; /* _PWR_DET_0, 0x48 */ - uint32_t pwr_det_latch; /* _PWR_DET_LATCH_0, 0x4c */ - uint32_t scratch0; /* _SCRATCH0_0, 0x50 */ - uint32_t scratch1; /* _SCRATCH1_0, 0x54 */ - uint32_t scratch2; /* _SCRATCH2_0, 0x58 */ - uint32_t scratch3; /* _SCRATCH3_0, 0x5c */ - uint32_t scratch4; /* _SCRATCH4_0, 0x60 */ - uint32_t scratch5; /* _SCRATCH5_0, 0x64 */ - uint32_t scratch6; /* _SCRATCH6_0, 0x68 */ - uint32_t scratch7; /* _SCRATCH7_0, 0x6c */ - uint32_t scratch8; /* _SCRATCH8_0, 0x70 */ - uint32_t scratch9; /* _SCRATCH9_0, 0x74 */ - uint32_t scratch10; /* _SCRATCH10_0, 0x78 */ - uint32_t scratch11; /* _SCRATCH11_0, 0x7c */ - uint32_t scratch12; /* _SCRATCH12_0, 0x80 */ - uint32_t scratch13; /* _SCRATCH13_0, 0x84 */ - uint32_t scratch14; /* _SCRATCH14_0, 0x88 */ - uint32_t scratch15; /* _SCRATCH15_0, 0x8c */ - uint32_t scratch16; /* _SCRATCH16_0, 0x90 */ - uint32_t scratch17; /* _SCRATCH17_0, 0x94 */ - uint32_t scratch18; /* _SCRATCH18_0, 0x98 */ - uint32_t scratch19; /* _SCRATCH19_0, 0x9c */ - uint32_t scratch20; /* _SCRATCH20_0, 0xa0 */ - uint32_t scratch21; /* _SCRATCH21_0, 0xa4 */ - uint32_t scratch22; /* _SCRATCH22_0, 0xa8 */ - uint32_t scratch23; /* _SCRATCH23_0, 0xac */ - uint32_t secure_scratch0; /* _SECURE_SCRATCH0_0, 0xb0 */ - uint32_t secure_scratch1; /* _SECURE_SCRATCH1_0, 0xb4 */ - uint32_t secure_scratch2; /* _SECURE_SCRATCH2_0, 0xb8 */ - uint32_t secure_scratch3; /* _SECURE_SCRATCH3_0, 0xbc */ - uint32_t secure_scratch4; /* _SECURE_SCRATCH4_0, 0xc0 */ - uint32_t secure_scratch5; /* _SECURE_SCRATCH5_0, 0xc4 */ - uint32_t cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, 0xc8 */ - uint32_t cpupwroff_timer; /* _CPUPWROFF_TIMER_0, 0xcc */ - uint32_t pg_mask; /* _PG_MASK_0, 0xd0 */ - uint32_t pg_mask_1; /* _PG_MASK_1_0, 0xd4 */ - uint32_t auto_wake_lvl; /* _AUTO_WAKE_LVL_0, 0xd8 */ - uint32_t auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, 0xdc */ - uint32_t wake_delay; /* _WAKE_DELAY_0, 0xe0 */ - uint32_t pwr_det_val; /* _PWR_DET_VAL_0, 0xe4 */ - uint32_t ddr_pwr; /* _DDR_PWR_0, 0xe8 */ - uint32_t usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, 0xec */ - uint32_t usb_ao; /* _USB_AO_0, 0xf0 */ - uint32_t crypto_op; /* _CRYPTO_OP_0, 0xf4 */ - uint32_t pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, 0xf8 */ - uint32_t scratch24; /* _SCRATCH24_0, 0xfc */ - uint32_t scratch25; /* _SCRATCH25_0, 0x100 */ - uint32_t scratch26; /* _SCRATCH26_0, 0x104 */ - uint32_t scratch27; /* _SCRATCH27_0, 0x108 */ - uint32_t scratch28; /* _SCRATCH28_0, 0x10c */ - uint32_t scratch29; /* _SCRATCH29_0, 0x110 */ - uint32_t scratch30; /* _SCRATCH30_0, 0x114 */ - uint32_t scratch31; /* _SCRATCH31_0, 0x118 */ - uint32_t scratch32; /* _SCRATCH32_0, 0x11c */ - uint32_t scratch33; /* _SCRATCH33_0, 0x120 */ - uint32_t scratch34; /* _SCRATCH34_0, 0x124 */ - uint32_t scratch35; /* _SCRATCH35_0, 0x128 */ - uint32_t scratch36; /* _SCRATCH36_0, 0x12c */ - uint32_t scratch37; /* _SCRATCH37_0, 0x130 */ - uint32_t scratch38; /* _SCRATCH38_0, 0x134 */ - uint32_t scratch39; /* _SCRATCH39_0, 0x138 */ - uint32_t scratch40; /* _SCRATCH40_0, 0x13c */ - uint32_t scratch41; /* _SCRATCH41_0, 0x140 */ - uint32_t scratch42; /* _SCRATCH42_0, 0x144 */ - uint32_t bondout_mirror0; /* _BONDOUT_MIRROR0_0, 0x148 */ - uint32_t bondout_mirror1; /* _BONDOUT_MIRROR1_0, 0x14c */ - uint32_t bondout_mirror2; /* _BONDOUT_MIRROR2_0, 0x150 */ - uint32_t sys_33v_en; /* _SYS_33V_EN_0, 0x154 */ - uint32_t bondout_mirror_access; /* _BONDOUT_MIRROR_ACCESS_0, 0x158 */ - uint32_t gate; /* _GATE_0, 0x15c */ - uint32_t wake2_mask; /* _WAKE2_MASK_0, 0x160 */ - uint32_t wake2_lvl; /* _WAKE2_LVL_0, 0x164 */ - uint32_t wake2_status; /* _WAKE2_STATUS_0, 0x168 */ - uint32_t sw_wake2_status; /* _SW_WAKE2_STATUS_0, 0x16c */ - uint32_t auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, 0x170 */ - uint32_t pg_mask_2; /* _PG_MASK_2_0, 0x174 */ - uint32_t pg_mask_ce1; /* _PG_MASK_CE1_0, 0x178 */ - uint32_t pg_mask_ce2; /* _PG_MASK_CE2_0, 0x17c */ - uint32_t pg_mask_ce3; /* _PG_MASK_CE3_0, 0x180 */ - uint32_t pwrgate_timer_ce_0; /* _PWRGATE_TIMER_CE_0_0, 0x184 */ - uint32_t pwrgate_timer_ce_1; /* _PWRGATE_TIMER_CE_1_0, 0x188 */ - uint32_t pwrgate_timer_ce_2; /* _PWRGATE_TIMER_CE_2_0, 0x18c */ - uint32_t pwrgate_timer_ce_3; /* _PWRGATE_TIMER_CE_3_0, 0x190 */ - uint32_t pwrgate_timer_ce_4; /* _PWRGATE_TIMER_CE_4_0, 0x194 */ - uint32_t pwrgate_timer_ce_5; /* _PWRGATE_TIMER_CE_5_0, 0x198 */ - uint32_t pwrgate_timer_ce_6; /* _PWRGATE_TIMER_CE_6_0, 0x19c */ - uint32_t pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, 0x1a0 */ - uint32_t osc_edpd_over; /* _OSC_EDPD_OVER_0, 0x1a4 */ - uint32_t clk_out_cntrl; /* _CLK_OUT_CNTRL_0, 0x1a8 */ - uint32_t sata_pwrgt; /* _SATA_PWRGT_0, 0x1ac */ - uint32_t sensor_ctrl; /* _SENSOR_CTRL_0, 0x1b0 */ - uint32_t rst_status; /* _RST_STATUS_0, 0x1b4 */ - uint32_t io_dpd_req; /* _IO_DPD_REQ_0, 0x1b8 */ - uint32_t io_dpd_status; /* _IO_DPD_STATUS_0, 0x1bc */ - uint32_t io_dpd2_req; /* _IO_DPD2_REQ_0, 0x1c0 */ - uint32_t io_dpd2_status; /* _IO_DPD2_STATUS_0, 0x1c4 */ - uint32_t sel_dpd_tim; /* _SEL_DPD_TIM_0, 0x1c8 */ - uint32_t vddp_sel; /* _VDDP_SEL_0, 0x1cc */ - uint32_t ddr_cfg; /* _DDR_CFG_0, 0x1d0 */ - uint32_t _0x1d4[2]; - uint32_t pllm_wb0_override_freq; /* _PLLM_WB0_OVERRIDE_FREQ_0, 0x1dc */ - uint32_t _0x1e0; - uint32_t pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, 0x1e4 */ - uint32_t dsi_sel_dpd; /* _DSI_SEL_DPD_0, 0x1e8 */ - uint32_t utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, 0x1ec */ - uint32_t utmip_uhsic_saved_state; /* _UTMIP_UHSIC_SAVED_STATE_0, 0x1f0 */ - uint32_t _0x1f4; - uint32_t utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, 0x1f8 */ - uint32_t utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, 0x1fc */ - uint32_t utmip_uhsic_sleepwalk_cfg; /* _UTMIP_UHSIC_SLEEPWALK_CFG_0, 0x200 */ - uint32_t utmip_sleepwalk_p0; /* _UTMIP_SLEEPWALK_P0_0, 0x204 */ - uint32_t utmip_sleepwalk_p1; /* _UTMIP_SLEEPWALK_P1_0, 0x208 */ - uint32_t utmip_sleepwalk_p2; /* _UTMIP_SLEEPWALK_P2_0, 0x20c */ - uint32_t uhsic_sleepwalk_p0; /* _UHSIC_SLEEPWALK_P0_0, 0x210 */ - uint32_t utmip_uhsic_status; /* _UTMIP_UHSIC_STATUS_0, 0x214 */ - uint32_t utmip_uhsic_fake; /* _UTMIP_UHSIC_FAKE_0, 0x218 */ - uint32_t bondout_mirror3; /* _BONDOUT_MIRROR3_0, 0x21c */ - uint32_t bondout_mirror4; /* _BONDOUT_MIRROR4_0, 0x220 */ - uint32_t secure_scratch6; /* _SECURE_SCRATCH6_0, 0x224 */ - uint32_t secure_scratch7; /* _SECURE_SCRATCH7_0, 0x228 */ - uint32_t scratch43; /* _SCRATCH43_0, 0x22c */ - uint32_t scratch44; /* _SCRATCH44_0, 0x230 */ - uint32_t scratch45; /* _SCRATCH45_0, 0x234 */ - uint32_t scratch46; /* _SCRATCH46_0, 0x238 */ - uint32_t scratch47; /* _SCRATCH47_0, 0x23c */ - uint32_t scratch48; /* _SCRATCH48_0, 0x240 */ - uint32_t scratch49; /* _SCRATCH49_0, 0x244 */ - uint32_t scratch50; /* _SCRATCH50_0, 0x248 */ - uint32_t scratch51; /* _SCRATCH51_0, 0x24c */ - uint32_t scratch52; /* _SCRATCH52_0, 0x250 */ - uint32_t scratch53; /* _SCRATCH53_0, 0x254 */ - uint32_t scratch54; /* _SCRATCH54_0, 0x258 */ - uint32_t scratch55; /* _SCRATCH55_0, 0x25c */ - uint32_t scratch0_eco; /* _SCRATCH0_ECO_0, 0x260 */ - uint32_t por_dpd_ctrl; /* _POR_DPD_CTRL_0, 0x264 */ - uint32_t scratch2_eco; /* _SCRATCH2_ECO_0, 0x268 */ - uint32_t utmip_uhsic_line_wakeup; /* _UTMIP_UHSIC_LINE_WAKEUP_0, 0x26c */ - uint32_t utmip_bias_master_cntrl; /* _UTMIP_BIAS_MASTER_CNTRL_0, 0x270 */ - uint32_t utmip_master_config; /* _UTMIP_MASTER_CONFIG_0, 0x274 */ - uint32_t td_pwrgate_inter_part_timer; /* _TD_PWRGATE_INTER_PART_TIMER_0, 0x278 */ - uint32_t utmip_uhsic2_triggers; /* _UTMIP_UHSIC2_TRIGGERS_0, 0x27c */ - uint32_t utmip_uhsic2_saved_state; /* _UTMIP_UHSIC2_SAVED_STATE_0, 0x280 */ - uint32_t utmip_uhsic2_sleep_cfg; /* _UTMIP_UHSIC2_SLEEP_CFG_0, 0x284 */ - uint32_t utmip_uhsic2_sleepwalk_cfg; /* _UTMIP_UHSIC2_SLEEPWALK_CFG_0, 0x288 */ - uint32_t uhsic2_sleepwalk_p1; /* _UHSIC2_SLEEPWALK_P1_0, 0x28c */ - uint32_t utmip_uhsic2_status; /* _UTMIP_UHSIC2_STATUS_0, 0x290 */ - uint32_t utmip_uhsic2_fake; /* _UTMIP_UHSIC2_FAKE_0, 0x294 */ - uint32_t utmip_uhsic2_line_wakeup; /* _UTMIP_UHSIC2_LINE_WAKEUP_0, 0x298 */ - uint32_t utmip_master2_config; /* _UTMIP_MASTER2_CONFIG_0, 0x29c */ - uint32_t utmip_uhsic_rpd_cfg; /* _UTMIP_UHSIC_RPD_CFG_0, 0x2a0 */ - uint32_t pg_mask_ce0; /* _PG_MASK_CE0_0, 0x2a4 */ - uint32_t pg_mask_3; /* _PG_MASK_3_0, 0x2a8 */ - uint32_t pg_mask_4; /* _PG_MASK_4_0, 0x2ac */ - uint32_t pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2_0, 0x2b0 */ - uint32_t tsc_mult; /* _TSC_MULT_0, 0x2b4 */ - uint32_t cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, 0x2b8 */ - uint32_t glb_amap_cfg; /* _GLB_AMAP_CFG_0, 0x2bc */ - uint32_t sticky_bits; /* _STICKY_BITS_0, 0x2c0 */ - uint32_t sec_disable2; /* _SEC_DISABLE2_0, 0x2c4 */ - uint32_t weak_bias; /* _WEAK_BIAS_0, 0x2c8 */ - uint32_t reg_short; /* _REG_SHORT_0, 0x2cc */ - uint32_t pg_mask_andor; /* _PG_MASK_ANDOR_0, 0x2d0 */ - uint32_t gpu_rg_cntrl; /* _GPU_RG_CNTRL_0, 0x2d4 */ - uint32_t sec_disable3; /* _SEC_DISABLE3_0, 0x2d8 */ - uint32_t pg_mask_5; /* _PG_MASK_5_0, 0x2dc */ - uint32_t pg_mask_6; /* _PG_MASK_6_0, 0x2e0 */ - uint32_t _0x2e4[7]; - uint32_t secure_scratch8; /* _SECURE_SCRATCH8_0, 0x300 */ - uint32_t secure_scratch9; /* _SECURE_SCRATCH9_0, 0x304 */ - uint32_t secure_scratch10; /* _SECURE_SCRATCH10_0, 0x308 */ - uint32_t secure_scratch11; /* _SECURE_SCRATCH11_0, 0x30c */ - uint32_t secure_scratch12; /* _SECURE_SCRATCH12_0, 0x310 */ - uint32_t secure_scratch13; /* _SECURE_SCRATCH13_0, 0x314 */ - uint32_t secure_scratch14; /* _SECURE_SCRATCH14_0, 0x318 */ - uint32_t secure_scratch15; /* _SECURE_SCRATCH15_0, 0x31c */ - uint32_t secure_scratch16; /* _SECURE_SCRATCH16_0, 0x320 */ - uint32_t secure_scratch17; /* _SECURE_SCRATCH17_0, 0x324 */ - uint32_t secure_scratch18; /* _SECURE_SCRATCH18_0, 0x328 */ - uint32_t secure_scratch19; /* _SECURE_SCRATCH19_0, 0x32c */ - uint32_t secure_scratch20; /* _SECURE_SCRATCH20_0, 0x330 */ - uint32_t secure_scratch21; /* _SECURE_SCRATCH21_0, 0x334 */ - uint32_t secure_scratch22; /* _SECURE_SCRATCH22_0, 0x338 */ - uint32_t secure_scratch23; /* _SECURE_SCRATCH23_0, 0x33c */ - uint32_t secure_scratch24; /* _SECURE_SCRATCH24_0, 0x340 */ - uint32_t secure_scratch25; /* _SECURE_SCRATCH25_0, 0x344 */ - uint32_t secure_scratch26; /* _SECURE_SCRATCH26_0, 0x348 */ - uint32_t secure_scratch27; /* _SECURE_SCRATCH27_0, 0x34c */ - uint32_t secure_scratch28; /* _SECURE_SCRATCH28_0, 0x350 */ - uint32_t secure_scratch29; /* _SECURE_SCRATCH29_0, 0x354 */ - uint32_t secure_scratch30; /* _SECURE_SCRATCH30_0, 0x358 */ - uint32_t secure_scratch31; /* _SECURE_SCRATCH31_0, 0x35c */ - uint32_t secure_scratch32; /* _SECURE_SCRATCH32_0, 0x360 */ - uint32_t secure_scratch33; /* _SECURE_SCRATCH33_0, 0x364 */ - uint32_t secure_scratch34; /* _SECURE_SCRATCH34_0, 0x368 */ - uint32_t secure_scratch35; /* _SECURE_SCRATCH35_0, 0x36c */ - uint32_t secure_scratch36; /* _SECURE_SCRATCH36_0, 0x370 */ - uint32_t secure_scratch37; /* _SECURE_SCRATCH37_0, 0x374 */ - uint32_t secure_scratch38; /* _SECURE_SCRATCH38_0, 0x378 */ - uint32_t secure_scratch39; /* _SECURE_SCRATCH39_0, 0x37c */ - uint32_t secure_scratch40; /* _SECURE_SCRATCH40_0, 0x380 */ - uint32_t secure_scratch41; /* _SECURE_SCRATCH41_0, 0x384 */ - uint32_t secure_scratch42; /* _SECURE_SCRATCH42_0, 0x388 */ - uint32_t secure_scratch43; /* _SECURE_SCRATCH43_0, 0x38c */ - uint32_t secure_scratch44; /* _SECURE_SCRATCH44_0, 0x390 */ - uint32_t secure_scratch45; /* _SECURE_SCRATCH45_0, 0x394 */ - uint32_t secure_scratch46; /* _SECURE_SCRATCH46_0, 0x398 */ - uint32_t secure_scratch47; /* _SECURE_SCRATCH47_0, 0x39c */ - uint32_t secure_scratch48; /* _SECURE_SCRATCH48_0, 0x3a0 */ - uint32_t secure_scratch49; /* _SECURE_SCRATCH49_0, 0x3a4 */ - uint32_t secure_scratch50; /* _SECURE_SCRATCH50_0, 0x3a8 */ - uint32_t secure_scratch51; /* _SECURE_SCRATCH51_0, 0x3ac */ - uint32_t secure_scratch52; /* _SECURE_SCRATCH52_0, 0x3b0 */ - uint32_t secure_scratch53; /* _SECURE_SCRATCH53_0, 0x3b4 */ - uint32_t secure_scratch54; /* _SECURE_SCRATCH54_0, 0x3b8 */ - uint32_t secure_scratch55; /* _SECURE_SCRATCH55_0, 0x3bc */ - uint32_t secure_scratch56; /* _SECURE_SCRATCH56_0, 0x3c0 */ - uint32_t secure_scratch57; /* _SECURE_SCRATCH57_0, 0x3c4 */ - uint32_t secure_scratch58; /* _SECURE_SCRATCH58_0, 0x3c8 */ - uint32_t secure_scratch59; /* _SECURE_SCRATCH59_0, 0x3cc */ - uint32_t secure_scratch60; /* _SECURE_SCRATCH60_0, 0x3d0 */ - uint32_t secure_scratch61; /* _SECURE_SCRATCH61_0, 0x3d4 */ - uint32_t secure_scratch62; /* _SECURE_SCRATCH62_0, 0x3d8 */ - uint32_t secure_scratch63; /* _SECURE_SCRATCH63_0, 0x3dc */ - uint32_t secure_scratch64; /* _SECURE_SCRATCH64_0, 0x3e0 */ - uint32_t secure_scratch65; /* _SECURE_SCRATCH65_0, 0x3e4 */ - uint32_t secure_scratch66; /* _SECURE_SCRATCH66_0, 0x3e8 */ - uint32_t secure_scratch67; /* _SECURE_SCRATCH67_0, 0x3ec */ - uint32_t secure_scratch68; /* _SECURE_SCRATCH68_0, 0x3f0 */ - uint32_t secure_scratch69; /* _SECURE_SCRATCH69_0, 0x3f4 */ - uint32_t secure_scratch70; /* _SECURE_SCRATCH70_0, 0x3f8 */ - uint32_t secure_scratch71; /* _SECURE_SCRATCH71_0, 0x3fc */ - uint32_t secure_scratch72; /* _SECURE_SCRATCH72_0, 0x400 */ - uint32_t secure_scratch73; /* _SECURE_SCRATCH73_0, 0x404 */ - uint32_t secure_scratch74; /* _SECURE_SCRATCH74_0, 0x408 */ - uint32_t secure_scratch75; /* _SECURE_SCRATCH75_0, 0x40c */ - uint32_t secure_scratch76; /* _SECURE_SCRATCH76_0, 0x410 */ - uint32_t secure_scratch77; /* _SECURE_SCRATCH77_0, 0x414 */ - uint32_t secure_scratch78; /* _SECURE_SCRATCH78_0, 0x418 */ - uint32_t secure_scratch79; /* _SECURE_SCRATCH79_0, 0x41c */ - uint32_t _0x420[8]; - uint32_t cntrl2; /* _CNTRL2_0, 0x440 */ - uint32_t io_dpd_off_mask; /* _IO_DPD_OFF_MASK_0, 0x444 */ - uint32_t io_dpd2_off_mask; /* _IO_DPD2_OFF_MASK_0, 0x448 */ - uint32_t event_counter; /* _EVENT_COUNTER_0, 0x44c */ - uint32_t fuse_control; /* _FUSE_CONTROL_0, 0x450 */ - uint32_t scratch1_eco; /* _SCRATCH1_ECO_0, 0x454 */ - uint32_t _0x458; - uint32_t io_dpd3_req; /* _IO_DPD3_REQ_0, 0x45c */ - uint32_t io_dpd3_status; /* _IO_DPD3_STATUS_0, 0x460 */ - uint32_t io_dpd4_req; /* _IO_DPD4_REQ_0, 0x464 */ - uint32_t io_dpd4_status; /* _IO_DPD4_STATUS_0, 0x468 */ - uint32_t _0x46c[2]; - uint32_t direct_thermtrip_cfg; /* _DIRECT_THERMTRIP_CFG_0, 0x474 */ - uint32_t tsosc_delay; /* _TSOSC_DELAY_0, 0x478 */ - uint32_t set_sw_clamp; /* _SET_SW_CLAMP_0, 0x47c */ - uint32_t debug_authentication; /* _DEBUG_AUTHENTICATION_0, 0x480 */ - uint32_t aotag_cfg; /* _AOTAG_CFG_0, 0x484 */ - uint32_t aotag_thresh1_cfg; /* _AOTAG_THRESH1_CFG_0, 0x488 */ - uint32_t aotag_thresh2_cfg; /* _AOTAG_THRESH2_CFG_0, 0x48c */ - uint32_t aotag_thresh3_cfg; /* _AOTAG_THRESH3_CFG_0, 0x490 */ - uint32_t aotag_status; /* _AOTAG_STATUS_0, 0x494 */ - uint32_t aotag_security; /* _AOTAG_SECURITY_0, 0x498 */ - uint32_t tsensor_config0; /* _TSENSOR_CONFIG0_0, 0x49c */ - uint32_t tsensor_config1; /* _TSENSOR_CONFIG1_0, 0x4a0 */ - uint32_t tsensor_config2; /* _TSENSOR_CONFIG2_0, 0x4a4 */ - uint32_t tsensor_status0; /* _TSENSOR_STATUS0_0, 0x4a8 */ - uint32_t tsensor_status1; /* _TSENSOR_STATUS1_0, 0x4ac */ - uint32_t tsensor_status2; /* _TSENSOR_STATUS2_0, 0x4b0 */ - uint32_t tsensor_pdiv; /* _TSENSOR_PDIV_0, 0x4b4 */ - uint32_t aotag_intr_en; /* _AOTAG_INTR_EN_0, 0x4b8 */ - uint32_t aotag_intr_dis; /* _AOTAG_INTR_DIS_0, 0x4bc */ - uint32_t utmip_pad_cfg0; /* _UTMIP_PAD_CFG0_0, 0x4c0 */ - uint32_t utmip_pad_cfg1; /* _UTMIP_PAD_CFG1_0, 0x4c4 */ - uint32_t utmip_pad_cfg2; /* _UTMIP_PAD_CFG2_0, 0x4c8 */ - uint32_t utmip_pad_cfg3; /* _UTMIP_PAD_CFG3_0, 0x4cc */ - uint32_t utmip_uhsic_sleep_cfg1; /* _UTMIP_UHSIC_SLEEP_CFG1_0, 0x4d0 */ - uint32_t cc4_hvc_control; /* _CC4_HVC_CONTROL_0, 0x4d4 */ - uint32_t wake_debounce_en; /* _WAKE_DEBOUNCE_EN_0, 0x4d8 */ - uint32_t ramdump_ctl_status; /* _RAMDUMP_CTL_STATUS_0, 0x4dc */ - uint32_t utmip_sleepwalk_p3; /* _UTMIP_SLEEPWALK_P3_0, 0x4e0 */ - uint32_t ddr_cntrl; /* _DDR_CNTRL_0, 0x4e4 */ - uint32_t _0x4e8[50]; - uint32_t sec_disable4; /* _SEC_DISABLE4_0, 0x5b0 */ - uint32_t sec_disable5; /* _SEC_DISABLE5_0, 0x5b4 */ - uint32_t sec_disable6; /* _SEC_DISABLE6_0, 0x5b8 */ - uint32_t sec_disable7; /* _SEC_DISABLE7_0, 0x5bc */ - uint32_t sec_disable8; /* _SEC_DISABLE8_0, 0x5c0 */ - uint32_t sec_disable9; /* _SEC_DISABLE9_0, 0x5c4 */ - uint32_t sec_disable10; /* _SEC_DISABLE10_0, 0x5c8 */ - uint32_t _0x5cc[13]; - uint32_t scratch56; /* _SCRATCH56_0, 0x600 */ - uint32_t scratch57; /* _SCRATCH57_0, 0x604 */ - uint32_t scratch58; /* _SCRATCH58_0, 0x608 */ - uint32_t scratch59; /* _SCRATCH59_0, 0x60c */ - uint32_t scratch60; /* _SCRATCH60_0, 0x610 */ - uint32_t scratch61; /* _SCRATCH61_0, 0x614 */ - uint32_t scratch62; /* _SCRATCH62_0, 0x618 */ - uint32_t scratch63; /* _SCRATCH63_0, 0x61c */ - uint32_t scratch64; /* _SCRATCH64_0, 0x620 */ - uint32_t scratch65; /* _SCRATCH65_0, 0x624 */ - uint32_t scratch66; /* _SCRATCH66_0, 0x628 */ - uint32_t scratch67; /* _SCRATCH67_0, 0x62c */ - uint32_t scratch68; /* _SCRATCH68_0, 0x630 */ - uint32_t scratch69; /* _SCRATCH69_0, 0x634 */ - uint32_t scratch70; /* _SCRATCH70_0, 0x638 */ - uint32_t scratch71; /* _SCRATCH71_0, 0x63c */ - uint32_t scratch72; /* _SCRATCH72_0, 0x640 */ - uint32_t scratch73; /* _SCRATCH73_0, 0x644 */ - uint32_t scratch74; /* _SCRATCH74_0, 0x648 */ - uint32_t scratch75; /* _SCRATCH75_0, 0x64c */ - uint32_t scratch76; /* _SCRATCH76_0, 0x650 */ - uint32_t scratch77; /* _SCRATCH77_0, 0x654 */ - uint32_t scratch78; /* _SCRATCH78_0, 0x658 */ - uint32_t scratch79; /* _SCRATCH79_0, 0x65c */ - uint32_t scratch80; /* _SCRATCH80_0, 0x660 */ - uint32_t scratch81; /* _SCRATCH81_0, 0x664 */ - uint32_t scratch82; /* _SCRATCH82_0, 0x668 */ - uint32_t scratch83; /* _SCRATCH83_0, 0x66c */ - uint32_t scratch84; /* _SCRATCH84_0, 0x670 */ - uint32_t scratch85; /* _SCRATCH85_0, 0x674 */ - uint32_t scratch86; /* _SCRATCH86_0, 0x678 */ - uint32_t scratch87; /* _SCRATCH87_0, 0x67c */ - uint32_t scratch88; /* _SCRATCH88_0, 0x680 */ - uint32_t scratch89; /* _SCRATCH89_0, 0x684 */ - uint32_t scratch90; /* _SCRATCH90_0, 0x688 */ - uint32_t scratch91; /* _SCRATCH91_0, 0x68c */ - uint32_t scratch92; /* _SCRATCH92_0, 0x690 */ - uint32_t scratch93; /* _SCRATCH93_0, 0x694 */ - uint32_t scratch94; /* _SCRATCH94_0, 0x698 */ - uint32_t scratch95; /* _SCRATCH95_0, 0x69c */ - uint32_t scratch96; /* _SCRATCH96_0, 0x6a0 */ - uint32_t scratch97; /* _SCRATCH97_0, 0x6a4 */ - uint32_t scratch98; /* _SCRATCH98_0, 0x6a8 */ - uint32_t scratch99; /* _SCRATCH99_0, 0x6ac */ - uint32_t scratch100; /* _SCRATCH100_0, 0x6b0 */ - uint32_t scratch101; /* _SCRATCH101_0, 0x6b4 */ - uint32_t scratch102; /* _SCRATCH102_0, 0x6b8 */ - uint32_t scratch103; /* _SCRATCH103_0, 0x6bc */ - uint32_t scratch104; /* _SCRATCH104_0, 0x6c0 */ - uint32_t scratch105; /* _SCRATCH105_0, 0x6c4 */ - uint32_t scratch106; /* _SCRATCH106_0, 0x6c8 */ - uint32_t scratch107; /* _SCRATCH107_0, 0x6cc */ - uint32_t scratch108; /* _SCRATCH108_0, 0x6d0 */ - uint32_t scratch109; /* _SCRATCH109_0, 0x6d4 */ - uint32_t scratch110; /* _SCRATCH110_0, 0x6d8 */ - uint32_t scratch111; /* _SCRATCH111_0, 0x6dc */ - uint32_t scratch112; /* _SCRATCH112_0, 0x6e0 */ - uint32_t scratch113; /* _SCRATCH113_0, 0x6e4 */ - uint32_t scratch114; /* _SCRATCH114_0, 0x6e8 */ - uint32_t scratch115; /* _SCRATCH115_0, 0x6ec */ - uint32_t scratch116; /* _SCRATCH116_0, 0x6f0 */ - uint32_t scratch117; /* _SCRATCH117_0, 0x6f4 */ - uint32_t scratch118; /* _SCRATCH118_0, 0x6f8 */ - uint32_t scratch119; /* _SCRATCH119_0, 0x6fc */ - uint32_t scratch120; /* _SCRATCH120_0, 0x700 */ - uint32_t scratch121; /* _SCRATCH121_0, 0x704 */ - uint32_t scratch122; /* _SCRATCH122_0, 0x708 */ - uint32_t scratch123; /* _SCRATCH123_0, 0x70c */ - uint32_t scratch124; /* _SCRATCH124_0, 0x710 */ - uint32_t scratch125; /* _SCRATCH125_0, 0x714 */ - uint32_t scratch126; /* _SCRATCH126_0, 0x718 */ - uint32_t scratch127; /* _SCRATCH127_0, 0x71c */ - uint32_t scratch128; /* _SCRATCH128_0, 0x720 */ - uint32_t scratch129; /* _SCRATCH129_0, 0x724 */ - uint32_t scratch130; /* _SCRATCH130_0, 0x728 */ - uint32_t scratch131; /* _SCRATCH131_0, 0x72c */ - uint32_t scratch132; /* _SCRATCH132_0, 0x730 */ - uint32_t scratch133; /* _SCRATCH133_0, 0x734 */ - uint32_t scratch134; /* _SCRATCH134_0, 0x738 */ - uint32_t scratch135; /* _SCRATCH135_0, 0x73c */ - uint32_t scratch136; /* _SCRATCH136_0, 0x740 */ - uint32_t scratch137; /* _SCRATCH137_0, 0x744 */ - uint32_t scratch138; /* _SCRATCH138_0, 0x748 */ - uint32_t scratch139; /* _SCRATCH139_0, 0x74c */ - uint32_t scratch140; /* _SCRATCH140_0, 0x750 */ - uint32_t scratch141; /* _SCRATCH141_0, 0x754 */ - uint32_t scratch142; /* _SCRATCH142_0, 0x758 */ - uint32_t scratch143; /* _SCRATCH143_0, 0x75c */ - uint32_t scratch144; /* _SCRATCH144_0, 0x760 */ - uint32_t scratch145; /* _SCRATCH145_0, 0x764 */ - uint32_t scratch146; /* _SCRATCH146_0, 0x768 */ - uint32_t scratch147; /* _SCRATCH147_0, 0x76c */ - uint32_t scratch148; /* _SCRATCH148_0, 0x770 */ - uint32_t scratch149; /* _SCRATCH149_0, 0x774 */ - uint32_t scratch150; /* _SCRATCH150_0, 0x778 */ - uint32_t scratch151; /* _SCRATCH151_0, 0x77c */ - uint32_t scratch152; /* _SCRATCH152_0, 0x780 */ - uint32_t scratch153; /* _SCRATCH153_0, 0x784 */ - uint32_t scratch154; /* _SCRATCH154_0, 0x788 */ - uint32_t scratch155; /* _SCRATCH155_0, 0x78c */ - uint32_t scratch156; /* _SCRATCH156_0, 0x790 */ - uint32_t scratch157; /* _SCRATCH157_0, 0x794 */ - uint32_t scratch158; /* _SCRATCH158_0, 0x798 */ - uint32_t scratch159; /* _SCRATCH159_0, 0x79c */ - uint32_t scratch160; /* _SCRATCH160_0, 0x7a0 */ - uint32_t scratch161; /* _SCRATCH161_0, 0x7a4 */ - uint32_t scratch162; /* _SCRATCH162_0, 0x7a8 */ - uint32_t scratch163; /* _SCRATCH163_0, 0x7ac */ - uint32_t scratch164; /* _SCRATCH164_0, 0x7b0 */ - uint32_t scratch165; /* _SCRATCH165_0, 0x7b4 */ - uint32_t scratch166; /* _SCRATCH166_0, 0x7b8 */ - uint32_t scratch167; /* _SCRATCH167_0, 0x7bc */ - uint32_t scratch168; /* _SCRATCH168_0, 0x7c0 */ - uint32_t scratch169; /* _SCRATCH169_0, 0x7c4 */ - uint32_t scratch170; /* _SCRATCH170_0, 0x7c8 */ - uint32_t scratch171; /* _SCRATCH171_0, 0x7cc */ - uint32_t scratch172; /* _SCRATCH172_0, 0x7d0 */ - uint32_t scratch173; /* _SCRATCH173_0, 0x7d4 */ - uint32_t scratch174; /* _SCRATCH174_0, 0x7d8 */ - uint32_t scratch175; /* _SCRATCH175_0, 0x7dc */ - uint32_t scratch176; /* _SCRATCH176_0, 0x7e0 */ - uint32_t scratch177; /* _SCRATCH177_0, 0x7e4 */ - uint32_t scratch178; /* _SCRATCH178_0, 0x7e8 */ - uint32_t scratch179; /* _SCRATCH179_0, 0x7ec */ - uint32_t scratch180; /* _SCRATCH180_0, 0x7f0 */ - uint32_t scratch181; /* _SCRATCH181_0, 0x7f4 */ - uint32_t scratch182; /* _SCRATCH182_0, 0x7f8 */ - uint32_t scratch183; /* _SCRATCH183_0, 0x7fc */ - uint32_t scratch184; /* _SCRATCH184_0, 0x800 */ - uint32_t scratch185; /* _SCRATCH185_0, 0x804 */ - uint32_t scratch186; /* _SCRATCH186_0, 0x808 */ - uint32_t scratch187; /* _SCRATCH187_0, 0x80c */ - uint32_t scratch188; /* _SCRATCH188_0, 0x810 */ - uint32_t scratch189; /* _SCRATCH189_0, 0x814 */ - uint32_t scratch190; /* _SCRATCH190_0, 0x818 */ - uint32_t scratch191; /* _SCRATCH191_0, 0x81c */ - uint32_t scratch192; /* _SCRATCH192_0, 0x820 */ - uint32_t scratch193; /* _SCRATCH193_0, 0x824 */ - uint32_t scratch194; /* _SCRATCH194_0, 0x828 */ - uint32_t scratch195; /* _SCRATCH195_0, 0x82c */ - uint32_t scratch196; /* _SCRATCH196_0, 0x830 */ - uint32_t scratch197; /* _SCRATCH197_0, 0x834 */ - uint32_t scratch198; /* _SCRATCH198_0, 0x838 */ - uint32_t scratch199; /* _SCRATCH199_0, 0x83c */ - uint32_t scratch200; /* _SCRATCH200_0, 0x840 */ - uint32_t scratch201; /* _SCRATCH201_0, 0x844 */ - uint32_t scratch202; /* _SCRATCH202_0, 0x848 */ - uint32_t scratch203; /* _SCRATCH203_0, 0x84c */ - uint32_t scratch204; /* _SCRATCH204_0, 0x850 */ - uint32_t scratch205; /* _SCRATCH205_0, 0x854 */ - uint32_t scratch206; /* _SCRATCH206_0, 0x858 */ - uint32_t scratch207; /* _SCRATCH207_0, 0x85c */ - uint32_t scratch208; /* _SCRATCH208_0, 0x860 */ - uint32_t scratch209; /* _SCRATCH209_0, 0x864 */ - uint32_t scratch210; /* _SCRATCH210_0, 0x868 */ - uint32_t scratch211; /* _SCRATCH211_0, 0x86c */ - uint32_t scratch212; /* _SCRATCH212_0, 0x870 */ - uint32_t scratch213; /* _SCRATCH213_0, 0x874 */ - uint32_t scratch214; /* _SCRATCH214_0, 0x878 */ - uint32_t scratch215; /* _SCRATCH215_0, 0x87c */ - uint32_t scratch216; /* _SCRATCH216_0, 0x880 */ - uint32_t scratch217; /* _SCRATCH217_0, 0x884 */ - uint32_t scratch218; /* _SCRATCH218_0, 0x888 */ - uint32_t scratch219; /* _SCRATCH219_0, 0x88c */ - uint32_t scratch220; /* _SCRATCH220_0, 0x890 */ - uint32_t scratch221; /* _SCRATCH221_0, 0x894 */ - uint32_t scratch222; /* _SCRATCH222_0, 0x898 */ - uint32_t scratch223; /* _SCRATCH223_0, 0x89c */ - uint32_t scratch224; /* _SCRATCH224_0, 0x8a0 */ - uint32_t scratch225; /* _SCRATCH225_0, 0x8a4 */ - uint32_t scratch226; /* _SCRATCH226_0, 0x8a8 */ - uint32_t scratch227; /* _SCRATCH227_0, 0x8ac */ - uint32_t scratch228; /* _SCRATCH228_0, 0x8b0 */ - uint32_t scratch229; /* _SCRATCH229_0, 0x8b4 */ - uint32_t scratch230; /* _SCRATCH230_0, 0x8b8 */ - uint32_t scratch231; /* _SCRATCH231_0, 0x8bc */ - uint32_t scratch232; /* _SCRATCH232_0, 0x8c0 */ - uint32_t scratch233; /* _SCRATCH233_0, 0x8c4 */ - uint32_t scratch234; /* _SCRATCH234_0, 0x8c8 */ - uint32_t scratch235; /* _SCRATCH235_0, 0x8cc */ - uint32_t scratch236; /* _SCRATCH236_0, 0x8d0 */ - uint32_t scratch237; /* _SCRATCH237_0, 0x8d4 */ - uint32_t scratch238; /* _SCRATCH238_0, 0x8d8 */ - uint32_t scratch239; /* _SCRATCH239_0, 0x8dc */ - uint32_t scratch240; /* _SCRATCH240_0, 0x8e0 */ - uint32_t scratch241; /* _SCRATCH241_0, 0x8e4 */ - uint32_t scratch242; /* _SCRATCH242_0, 0x8e8 */ - uint32_t scratch243; /* _SCRATCH243_0, 0x8ec */ - uint32_t scratch244; /* _SCRATCH244_0, 0x8f0 */ - uint32_t scratch245; /* _SCRATCH245_0, 0x8f4 */ - uint32_t scratch246; /* _SCRATCH246_0, 0x8f8 */ - uint32_t scratch247; /* _SCRATCH247_0, 0x8fc */ - uint32_t scratch248; /* _SCRATCH248_0, 0x900 */ - uint32_t scratch249; /* _SCRATCH249_0, 0x904 */ - uint32_t scratch250; /* _SCRATCH250_0, 0x908 */ - uint32_t scratch251; /* _SCRATCH251_0, 0x90c */ - uint32_t scratch252; /* _SCRATCH252_0, 0x910 */ - uint32_t scratch253; /* _SCRATCH253_0, 0x914 */ - uint32_t scratch254; /* _SCRATCH254_0, 0x918 */ - uint32_t scratch255; /* _SCRATCH255_0, 0x91c */ - uint32_t scratch256; /* _SCRATCH256_0, 0x920 */ - uint32_t scratch257; /* _SCRATCH257_0, 0x924 */ - uint32_t scratch258; /* _SCRATCH258_0, 0x928 */ - uint32_t scratch259; /* _SCRATCH259_0, 0x92c */ - uint32_t scratch260; /* _SCRATCH260_0, 0x930 */ - uint32_t scratch261; /* _SCRATCH261_0, 0x934 */ - uint32_t scratch262; /* _SCRATCH262_0, 0x938 */ - uint32_t scratch263; /* _SCRATCH263_0, 0x93c */ - uint32_t scratch264; /* _SCRATCH264_0, 0x940 */ - uint32_t scratch265; /* _SCRATCH265_0, 0x944 */ - uint32_t scratch266; /* _SCRATCH266_0, 0x948 */ - uint32_t scratch267; /* _SCRATCH267_0, 0x94c */ - uint32_t scratch268; /* _SCRATCH268_0, 0x950 */ - uint32_t scratch269; /* _SCRATCH269_0, 0x954 */ - uint32_t scratch270; /* _SCRATCH270_0, 0x958 */ - uint32_t scratch271; /* _SCRATCH271_0, 0x95c */ - uint32_t scratch272; /* _SCRATCH272_0, 0x960 */ - uint32_t scratch273; /* _SCRATCH273_0, 0x964 */ - uint32_t scratch274; /* _SCRATCH274_0, 0x968 */ - uint32_t scratch275; /* _SCRATCH275_0, 0x96c */ - uint32_t scratch276; /* _SCRATCH276_0, 0x970 */ - uint32_t scratch277; /* _SCRATCH277_0, 0x974 */ - uint32_t scratch278; /* _SCRATCH278_0, 0x978 */ - uint32_t scratch279; /* _SCRATCH279_0, 0x97c */ - uint32_t scratch280; /* _SCRATCH280_0, 0x980 */ - uint32_t scratch281; /* _SCRATCH281_0, 0x984 */ - uint32_t scratch282; /* _SCRATCH282_0, 0x988 */ - uint32_t scratch283; /* _SCRATCH283_0, 0x98c */ - uint32_t scratch284; /* _SCRATCH284_0, 0x990 */ - uint32_t scratch285; /* _SCRATCH285_0, 0x994 */ - uint32_t scratch286; /* _SCRATCH286_0, 0x998 */ - uint32_t scratch287; /* _SCRATCH287_0, 0x99c */ - uint32_t scratch288; /* _SCRATCH288_0, 0x9a0 */ - uint32_t scratch289; /* _SCRATCH289_0, 0x9a4 */ - uint32_t scratch290; /* _SCRATCH290_0, 0x9a8 */ - uint32_t scratch291; /* _SCRATCH291_0, 0x9ac */ - uint32_t scratch292; /* _SCRATCH292_0, 0x9b0 */ - uint32_t scratch293; /* _SCRATCH293_0, 0x9b4 */ - uint32_t scratch294; /* _SCRATCH294_0, 0x9b8 */ - uint32_t scratch295; /* _SCRATCH295_0, 0x9bc */ - uint32_t scratch296; /* _SCRATCH296_0, 0x9c0 */ - uint32_t scratch297; /* _SCRATCH297_0, 0x9c4 */ - uint32_t scratch298; /* _SCRATCH298_0, 0x9c8 */ - uint32_t scratch299; /* _SCRATCH299_0, 0x9cc */ - uint32_t _0x9d0[50]; - uint32_t secure_scratch80; /* _SECURE_SCRATCH80_0, 0xa98 */ - uint32_t secure_scratch81; /* _SECURE_SCRATCH81_0, 0xa9c */ - uint32_t secure_scratch82; /* _SECURE_SCRATCH82_0, 0xaa0 */ - uint32_t secure_scratch83; /* _SECURE_SCRATCH83_0, 0xaa4 */ - uint32_t secure_scratch84; /* _SECURE_SCRATCH84_0, 0xaa8 */ - uint32_t secure_scratch85; /* _SECURE_SCRATCH85_0, 0xaac */ - uint32_t secure_scratch86; /* _SECURE_SCRATCH86_0, 0xab0 */ - uint32_t secure_scratch87; /* _SECURE_SCRATCH87_0, 0xab4 */ - uint32_t secure_scratch88; /* _SECURE_SCRATCH88_0, 0xab8 */ - uint32_t secure_scratch89; /* _SECURE_SCRATCH89_0, 0xabc */ - uint32_t secure_scratch90; /* _SECURE_SCRATCH90_0, 0xac0 */ - uint32_t secure_scratch91; /* _SECURE_SCRATCH91_0, 0xac4 */ - uint32_t secure_scratch92; /* _SECURE_SCRATCH92_0, 0xac8 */ - uint32_t secure_scratch93; /* _SECURE_SCRATCH93_0, 0xacc */ - uint32_t secure_scratch94; /* _SECURE_SCRATCH94_0, 0xad0 */ - uint32_t secure_scratch95; /* _SECURE_SCRATCH95_0, 0xad4 */ - uint32_t secure_scratch96; /* _SECURE_SCRATCH96_0, 0xad8 */ - uint32_t secure_scratch97; /* _SECURE_SCRATCH97_0, 0xadc */ - uint32_t secure_scratch98; /* _SECURE_SCRATCH98_0, 0xae0 */ - uint32_t secure_scratch99; /* _SECURE_SCRATCH99_0, 0xae4 */ - uint32_t secure_scratch100; /* _SECURE_SCRATCH100_0, 0xae8 */ - uint32_t secure_scratch101; /* _SECURE_SCRATCH101_0, 0xaec */ - uint32_t secure_scratch102; /* _SECURE_SCRATCH102_0, 0xaf0 */ - uint32_t secure_scratch103; /* _SECURE_SCRATCH103_0, 0xaf4 */ - uint32_t secure_scratch104; /* _SECURE_SCRATCH104_0, 0xaf8 */ - uint32_t secure_scratch105; /* _SECURE_SCRATCH105_0, 0xafc */ - uint32_t secure_scratch106; /* _SECURE_SCRATCH106_0, 0xb00 */ - uint32_t secure_scratch107; /* _SECURE_SCRATCH107_0, 0xb04 */ - uint32_t secure_scratch108; /* _SECURE_SCRATCH108_0, 0xb08 */ - uint32_t secure_scratch109; /* _SECURE_SCRATCH109_0, 0xb0c */ - uint32_t secure_scratch110; /* _SECURE_SCRATCH110_0, 0xb10 */ - uint32_t secure_scratch111; /* _SECURE_SCRATCH111_0, 0xb14 */ - uint32_t secure_scratch112; /* _SECURE_SCRATCH112_0, 0xb18 */ - uint32_t secure_scratch113; /* _SECURE_SCRATCH113_0, 0xb1c */ - uint32_t secure_scratch114; /* _SECURE_SCRATCH114_0, 0xb20 */ - uint32_t secure_scratch115; /* _SECURE_SCRATCH115_0, 0xb24 */ - uint32_t secure_scratch116; /* _SECURE_SCRATCH116_0, 0xb28 */ - uint32_t secure_scratch117; /* _SECURE_SCRATCH117_0, 0xb2c */ - uint32_t secure_scratch118; /* _SECURE_SCRATCH118_0, 0xb30 */ - uint32_t secure_scratch119; /* _SECURE_SCRATCH119_0, 0xb34 */ - uint32_t secure_scratch120; /* _SECURE_SCRATCH120_0, 0xb38 */ - uint32_t secure_scratch121; /* _SECURE_SCRATCH121_0, 0xb3c */ - uint32_t secure_scratch122; /* _SECURE_SCRATCH122_0, 0xb40 */ - uint32_t secure_scratch123; /* _SECURE_SCRATCH123_0, 0xb44 */ - uint32_t led_breathing_ctrl; /* _LED_BREATHING_CTRL_0, 0xb48 */ - uint32_t led_breathing_counter0; /* _LED_BREATHING_COUNTER0_0, 0xb4c */ - uint32_t led_breathing_counter1; /* _LED_BREATHING_COUNTER1_0, 0xb50 */ - uint32_t led_breathing_counter2; /* _LED_BREATHING_COUNTER2_0, 0xb54 */ - uint32_t led_breathing_counter3; /* _LED_BREATHING_COUNTER3_0, 0xb58 */ - uint32_t led_breathing_status; /* _LED_BREATHING_STATUS_0, 0xb5c */ - uint32_t _0xb60[2]; - uint32_t secure_scratch124; /* _SECURE_SCRATCH124_0, 0xb68 */ - uint32_t secure_scratch125; /* _SECURE_SCRATCH125_0, 0xb6c */ - uint32_t secure_scratch126; /* _SECURE_SCRATCH126_0, 0xb70 */ - uint32_t secure_scratch127; /* _SECURE_SCRATCH127_0, 0xb74 */ - uint32_t secure_scratch128; /* _SECURE_SCRATCH128_0, 0xb78 */ - uint32_t secure_scratch129; /* _SECURE_SCRATCH129_0, 0xb7c */ - uint32_t secure_scratch130; /* _SECURE_SCRATCH130_0, 0xb80 */ - uint32_t secure_scratch131; /* _SECURE_SCRATCH131_0, 0xb84 */ - uint32_t secure_scratch132; /* _SECURE_SCRATCH132_0, 0xb88 */ - uint32_t secure_scratch133; /* _SECURE_SCRATCH133_0, 0xb8c */ - uint32_t secure_scratch134; /* _SECURE_SCRATCH134_0, 0xb90 */ - uint32_t secure_scratch135; /* _SECURE_SCRATCH135_0, 0xb94 */ - uint32_t secure_scratch136; /* _SECURE_SCRATCH136_0, 0xb98 */ - uint32_t secure_scratch137; /* _SECURE_SCRATCH137_0, 0xb9c */ - uint32_t secure_scratch138; /* _SECURE_SCRATCH138_0, 0xba0 */ - uint32_t secure_scratch139; /* _SECURE_SCRATCH139_0, 0xba4 */ - uint32_t _0xba8[2]; - uint32_t sec_disable_ns; /* _SEC_DISABLE_NS_0, 0xbb0 */ - uint32_t sec_disable2_ns; /* _SEC_DISABLE2_NS_0, 0xbb4 */ - uint32_t sec_disable3_ns; /* _SEC_DISABLE3_NS_0, 0xbb8 */ - uint32_t sec_disable4_ns; /* _SEC_DISABLE4_NS_0, 0xbbc */ - uint32_t sec_disable5_ns; /* _SEC_DISABLE5_NS_0, 0xbc0 */ - uint32_t sec_disable6_ns; /* _SEC_DISABLE6_NS_0, 0xbc4 */ - uint32_t sec_disable7_ns; /* _SEC_DISABLE7_NS_0, 0xbc8 */ - uint32_t sec_disable8_ns; /* _SEC_DISABLE8_NS_0, 0xbcc */ - uint32_t sec_disable9_ns; /* _SEC_DISABLE9_NS_0, 0xbd0 */ - uint32_t sec_disable10_ns; /* _SEC_DISABLE10_NS_0, 0xbd4 */ - uint32_t _0xbd8[4]; - uint32_t tzram_pwr_cntrl; /* _TZRAM_PWR_CNTRL_0, 0xbe8 */ - uint32_t tzram_sec_disable; /* _TZRAM_SEC_DISABLE_0, 0xbec */ - uint32_t tzram_non_sec_disable; /* _TZRAM_NON_SEC_DISABLE_0, 0xbf0 */ -} tegra_pmc_t; - -static inline volatile tegra_pmc_t *pmc_get_regs(void) -{ - return (volatile tegra_pmc_t *)PMC_BASE; -} - -#endif diff --git a/sept/sept-primary/src/se.c b/sept/sept-primary/src/se.c deleted file mode 100644 index 4f82ed568..000000000 --- a/sept/sept-primary/src/se.c +++ /dev/null @@ -1,649 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "utils.h" -#include "se.h" - -void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size); - -/* Globals for driver. */ -static unsigned int g_se_modulus_sizes[KEYSLOT_RSA_MAX]; -static unsigned int g_se_exp_sizes[KEYSLOT_RSA_MAX]; - -/* Initialize a SE linked list. */ -void NOINLINE ll_init(volatile se_ll_t *ll, void *buffer, size_t size) { - ll->num_entries = 0; /* 1 Entry. */ - - if (buffer != NULL) { - ll->addr_info.address = (uint32_t) get_physical_address(buffer); - ll->addr_info.size = (uint32_t) size; - } else { - ll->addr_info.address = 0; - ll->addr_info.size = 0; - } -} - -void se_check_error_status_reg(void) { - if (se_get_regs()->SE_ERR_STATUS) { - generic_panic(); - } -} - -void se_check_for_error(void) { - volatile tegra_se_t *se = se_get_regs(); - if (se->SE_INT_STATUS & 0x10000 || se->SE_STATUS & 3 || se->SE_ERR_STATUS) { - generic_panic(); - } -} - -void se_verify_flags_cleared(void) { - if (se_get_regs()->SE_STATUS & 3) { - generic_panic(); - } -} - -/* Set the flags for an AES keyslot. */ -void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Misc flags. */ - if (flags & ~0x80) { - se->SE_CRYPTO_KEYTABLE_ACCESS[keyslot] = ~flags; - } - - /* Disable keyslot reads. */ - if (flags & 0x80) { - se->SE_CRYPTO_SECURITY_PERKEY &= ~(1 << keyslot); - } -} - -/* Set the flags for an RSA keyslot. */ -void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_RSA_MAX) { - generic_panic(); - } - - /* Misc flags. */ - if (flags & ~0x80) { - /* TODO: Why are flags assigned this way? */ - se->SE_RSA_KEYTABLE_ACCESS[keyslot] = (((flags >> 4) & 4) | (flags & 3)) ^ 7; - } - - /* Disable keyslot reads. */ - if (flags & 0x80) { - se->SE_RSA_SECURITY_PERKEY &= ~(1 << keyslot); - } -} - -void clear_aes_keyslot(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Zero out the whole keyslot and IV. */ - for (unsigned int i = 0; i < 0x10; i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | i; - se->SE_CRYPTO_KEYTABLE_DATA = 0; - } -} - -void clear_rsa_keyslot(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_RSA_MAX) { - generic_panic(); - } - - /* Zero out the whole keyslot. */ - for (unsigned int i = 0; i < 0x40; i++) { - /* Select Keyslot Modulus[i] */ - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i | 0x40; - se->SE_RSA_KEYTABLE_DATA = 0; - } - for (unsigned int i = 0; i < 0x40; i++) { - /* Select Keyslot Expontent[i] */ - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i; - se->SE_RSA_KEYTABLE_DATA = 0; - } -} - -void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || key_size > KEYSIZE_AES_MAX) { - generic_panic(); - } - - for (size_t i = 0; i < (key_size >> 2); i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | i; - se->SE_CRYPTO_KEYTABLE_DATA = read32le(key, 4 * i); - } -} - -void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_RSA_MAX || modulus_size > KEYSIZE_RSA_MAX || exp_size > KEYSIZE_RSA_MAX) { - generic_panic(); - } - - for (size_t i = 0; i < (modulus_size >> 2); i++) { - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | 0x40 | i; - se->SE_RSA_KEYTABLE_DATA = read32be(modulus, (4 * (modulus_size >> 2)) - (4 * i) - 4); - } - - for (size_t i = 0; i < (exp_size >> 2); i++) { - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i; - se->SE_RSA_KEYTABLE_DATA = read32be(exponent, (4 * (exp_size >> 2)) - (4 * i) - 4); - } - - g_se_modulus_sizes[keyslot] = modulus_size; - g_se_exp_sizes[keyslot] = exp_size; -} - -void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || iv_size > 0x10) { - generic_panic(); - } - - for (size_t i = 0; i < (iv_size >> 2); i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; - se->SE_CRYPTO_KEYTABLE_DATA = read32le(iv, 4 * i); - } -} - -void clear_aes_keyslot_iv(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - for (size_t i = 0; i < (0x10 >> 2); i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; - se->SE_CRYPTO_KEYTABLE_DATA = 0; - } -} - -void set_se_ctr(const void *ctr) { - for (unsigned int i = 0; i < 4; i++) { - se_get_regs()->SE_CRYPTO_LINEAR_CTR[i] = read32le(ctr, i * 4); - } -} - -void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot_dst >= KEYSLOT_AES_MAX || keyslot_src >= KEYSLOT_AES_MAX || wrapped_key_size > KEYSIZE_AES_MAX) { - generic_panic(); - } - - se->SE_CONFIG = (ALG_AES_DEC | DST_KEYTAB); - se->SE_CRYPTO_CONFIG = keyslot_src << 24; - se->SE_CRYPTO_LAST_BLOCK = 0; - se->SE_CRYPTO_KEYTABLE_DST = keyslot_dst << 8; - - trigger_se_blocking_op(OP_START, NULL, 0, wrapped_key, wrapped_key_size); -} - -void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - uint8_t ALIGN(16) stack_buf[KEYSIZE_RSA_MAX]; - - if (keyslot >= KEYSLOT_RSA_MAX || src_size > KEYSIZE_RSA_MAX || dst_size > KEYSIZE_RSA_MAX) { - generic_panic(); - } - - /* Endian swap the input. */ - for (size_t i = 0; i < src_size; i++) { - stack_buf[i] = *((uint8_t *)src + src_size - i - 1); - } - - se->SE_CONFIG = (ALG_RSA | DST_RSAREG); - se->SE_RSA_CONFIG = keyslot << 24; - se->SE_RSA_KEY_SIZE = (g_se_modulus_sizes[keyslot] >> 6) - 1; - se->SE_RSA_EXP_SIZE = g_se_exp_sizes[keyslot] >> 2; - - trigger_se_blocking_op(OP_START, NULL, 0, stack_buf, src_size); - se_get_exp_mod_output(dst, dst_size); -} - -void se_get_exp_mod_output(void *buf, size_t size) { - size_t num_dwords = (size >> 2); - - if (num_dwords < 1) { - return; - } - - uint32_t *p_out = ((uint32_t *)buf) + num_dwords - 1; - uint32_t offset = 0; - - /* Copy endian swapped output. */ - while (num_dwords) { - *p_out = read32be(se_get_regs()->SE_RSA_OUTPUT, offset); - offset += 4; - p_out--; - num_dwords--; - } -} - -bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const void *modulus, size_t modulus_size, const void *data, size_t data_size) { - uint8_t message[RSA_2048_BYTES]; - uint8_t h_buf[0x24]; - - /* Hardcode RSA with keyslot 0. */ - const uint8_t public_exponent[4] = {0x00, 0x01, 0x00, 0x01}; - set_rsa_keyslot(0, modulus, modulus_size, public_exponent, sizeof(public_exponent)); - se_synchronous_exp_mod(0, message, sizeof(message), signature, signature_size); - - /* Validate sanity byte. */ - if (message[RSA_2048_BYTES - 1] != 0xBC) { - return false; - } - - /* Copy Salt into MGF1 Hash Buffer. */ - memset(h_buf, 0, sizeof(h_buf)); - memcpy(h_buf, message + RSA_2048_BYTES - 0x20 - 0x1, 0x20); - - /* Decrypt maskedDB (via inline MGF1). */ - uint8_t seed = 0; - uint8_t mgf1_buf[0x20]; - for (unsigned int ofs = 0; ofs < RSA_2048_BYTES - 0x20 - 1; ofs += 0x20) { - h_buf[sizeof(h_buf) - 1] = seed++; - se_calculate_sha256(mgf1_buf, h_buf, sizeof(h_buf)); - for (unsigned int i = ofs; i < ofs + 0x20 && i < RSA_2048_BYTES - 0x20 - 1; i++) { - message[i] ^= mgf1_buf[i - ofs]; - } - } - - /* Constant lmask for rsa-2048-pss. */ - message[0] &= 0x7F; - - /* Validate DB is of the form 0000...0001. */ - for (unsigned int i = 0; i < RSA_2048_BYTES - 0x20 - 0x20 - 1 - 1; i++) { - if (message[i] != 0) { - return false; - } - } - if (message[RSA_2048_BYTES - 0x20 - 0x20 - 1 - 1] != 1) { - return false; - } - - /* Check hash correctness. */ - uint8_t validate_buf[8 + 0x20 + 0x20]; - uint8_t validate_hash[0x20]; - - memset(validate_buf, 0, sizeof(validate_buf)); - se_calculate_sha256(&validate_buf[8], data, data_size); - memcpy(&validate_buf[0x28], &message[RSA_2048_BYTES - 0x20 - 0x20 - 1], 0x20); - se_calculate_sha256(validate_hash, validate_buf, sizeof(validate_buf)); - return memcmp(h_buf, validate_hash, 0x20) == 0; -} - -void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - se_ll_t in_ll; - se_ll_t out_ll; - - ll_init(&in_ll, (void *)src, src_size); - ll_init(&out_ll, dst, dst_size); - - /* Set the LLs. */ - se->SE_IN_LL_ADDR = (uint32_t) get_physical_address(&in_ll); - se->SE_OUT_LL_ADDR = (uint32_t) get_physical_address(&out_ll); - - /* Set registers for operation. */ - se->SE_ERR_STATUS = se->SE_ERR_STATUS; - se->SE_INT_STATUS = se->SE_INT_STATUS; - se->SE_OPERATION = op; - - while (!(se->SE_INT_STATUS & 0x10)) { /* Wait a while */ } - se_check_for_error(); -} - -/* Secure AES Functionality. */ -void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, size_t src_size) { - uint8_t block[0x10] = {0}; - - if (src_size > sizeof(block) || dst_size > sizeof(block)) { - generic_panic(); - } - - /* Load src data into block. */ - if (src_size != 0) { - memcpy(block, src, src_size); - } - - /* Trigger AES operation. */ - se_get_regs()->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, block, sizeof(block), block, sizeof(block)); - - /* Copy output data into dst. */ - if (dst_size != 0) { - memcpy(dst, block, dst_size); - } -} - -void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || ctr_size != 0x10) { - generic_panic(); - } - unsigned int num_blocks = src_size >> 4; - - /* Unknown what this write does, but official code writes it for CTR mode. */ - se->SE_SPARE = 1; - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x91E; - set_se_ctr(ctr); - - /* Handle any aligned blocks. */ - size_t aligned_size = (size_t)num_blocks << 4; - if (aligned_size) { - se->SE_CRYPTO_LAST_BLOCK = num_blocks - 1; - trigger_se_blocking_op(OP_START, dst, dst_size, src, aligned_size); - } - - /* Handle final, unaligned block. */ - if (aligned_size < dst_size && aligned_size < src_size) { - size_t last_block_size = dst_size - aligned_size; - if (src_size < dst_size) { - last_block_size = src_size - aligned_size; - } - se_perform_aes_block_operation(dst + aligned_size, last_block_size, (uint8_t *)src + aligned_size, src_size - aligned_size); - } -} - -void se_aes_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, unsigned int config_high) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) { - generic_panic(); - } - - /* Set configuration high (256-bit vs 128-bit) based on parameter. */ - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY) | (config_high << 16); - se->SE_CRYPTO_CONFIG = keyslot << 24 | 0x100; - se_perform_aes_block_operation(dst, 0x10, src, 0x10); -} - -void se_aes_128_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - se_aes_ecb_encrypt_block(keyslot, dst, dst_size, src, src_size, 0); -} - -void se_aes_256_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - se_aes_ecb_encrypt_block(keyslot, dst, dst_size, src, src_size, 0x202); -} - -void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) { - generic_panic(); - } - - se->SE_CONFIG = (ALG_AES_DEC | DST_MEMORY); - se->SE_CRYPTO_CONFIG = keyslot << 24; - se_perform_aes_block_operation(dst, 0x10, src, 0x10); -} - -void shift_left_xor_rb(uint8_t *key) { - uint8_t prev_high_bit = 0; - for (unsigned int i = 0; i < 0x10; i++) { - uint8_t cur_byte = key[0xF - i]; - key[0xF - i] = (cur_byte << 1) | (prev_high_bit); - prev_high_bit = cur_byte >> 7; - } - if (prev_high_bit) { - key[0xF] ^= 0x87; - } -} - -void shift_left_xor_rb_le(uint8_t *key) { - uint8_t prev_high_bit = 0; - for (unsigned int i = 0; i < 0x10; i++) { - uint8_t cur_byte = key[i]; - key[i] = (cur_byte << 1) | (prev_high_bit); - prev_high_bit = cur_byte >> 7; - } - if (prev_high_bit) { - key[0x0] ^= 0x87; - } -} - -void aes_128_xts_nintendo_get_tweak(uint8_t *tweak, size_t sector) { - for (int i = 0xF; i >= 0; i--) { /* Nintendo LE custom tweak... */ - tweak[i] = (unsigned char)(sector & 0xFF); - sector >>= 8; - } -} - -void aes_128_xts_nintendo_xor_with_tweak(unsigned int keyslot, size_t sector, uint8_t *dst, const uint8_t *src, size_t size) { - if ((size & 0xF) || size == 0) { - generic_panic(); - } - uint8_t tweak[0x10]; - aes_128_xts_nintendo_get_tweak(tweak, sector); - se_aes_128_ecb_encrypt_block(keyslot, tweak, sizeof(tweak), tweak, sizeof(tweak)); - - for (unsigned int block = 0; block < (size >> 4); block++) { - for (unsigned int i = 0; i < 0x10; i++) { - dst[(block << 4) | i] = src[(block << 4) | i] ^ tweak[i]; - } - shift_left_xor_rb_le(tweak); - } -} - -void aes_128_xts_nintendo_crypt_sector(unsigned int keyslot_1, unsigned int keyslot_2, size_t sector, bool encrypt, void *dst, const void *src, size_t size) { - volatile tegra_se_t *se = se_get_regs(); - - if ((size & 0xF) || size == 0) { - generic_panic(); - } - - /* XOR. */ - aes_128_xts_nintendo_xor_with_tweak(keyslot_2, sector, dst, src, size); - - /* Encrypt/Decrypt. */ - if (encrypt) { - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY); - se->SE_CRYPTO_CONFIG = keyslot_1 << 24 | 0x100; - } else { - se->SE_CONFIG = (ALG_AES_DEC | DST_MEMORY); - se->SE_CRYPTO_CONFIG = keyslot_1 << 24; - } - se->SE_CRYPTO_LAST_BLOCK = (size >> 4) - 1; - trigger_se_blocking_op(OP_START, dst, size, src, size); - - /* XOR. */ - aes_128_xts_nintendo_xor_with_tweak(keyslot_2, sector, dst, dst, size); -} - -/* Encrypt with AES-XTS (Nintendo's custom tweak). */ -void se_aes_128_xts_nintendo_encrypt(unsigned int keyslot_1, unsigned int keyslot_2, size_t base_sector, void *dst, const void *src, size_t size, unsigned int sector_size) { - if ((size & 0xF) || size == 0) { - generic_panic(); - } - size_t sector = base_sector; - for (size_t ofs = 0; ofs < size; ofs += sector_size) { - aes_128_xts_nintendo_crypt_sector(keyslot_1, keyslot_2, sector, true, dst + ofs, src + ofs, sector_size); - sector++; - } -} - -/* Decrypt with AES-XTS (Nintendo's custom tweak). */ -void se_aes_128_xts_nintendo_decrypt(unsigned int keyslot_1, unsigned int keyslot_2, size_t base_sector, void *dst, const void *src, size_t size, unsigned int sector_size) { - if ((size & 0xF) || size == 0) { - generic_panic(); - } - size_t sector = base_sector; - for (size_t ofs = 0; ofs < size; ofs += sector_size) { - aes_128_xts_nintendo_crypt_sector(keyslot_1, keyslot_2, sector, false, dst + ofs, src + ofs, sector_size); - sector++; - } -} - -void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size, unsigned int config_high) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Generate the derived key, to be XOR'd with final output block. */ - uint8_t ALIGN(16) derived_key[0x10] = {0}; - se_aes_ecb_encrypt_block(keyslot, derived_key, sizeof(derived_key), derived_key, sizeof(derived_key), config_high); - shift_left_xor_rb(derived_key); - if (data_size & 0xF) { - shift_left_xor_rb(derived_key); - } - - se->SE_CONFIG = (ALG_AES_ENC | DST_HASHREG) | (config_high << 16); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | (0x145); - clear_aes_keyslot_iv(keyslot); - - unsigned int num_blocks = (data_size + 0xF) >> 4; - /* Handle aligned blocks. */ - if (num_blocks > 1) { - se->SE_CRYPTO_LAST_BLOCK = num_blocks - 2; - trigger_se_blocking_op(OP_START, NULL, 0, data, data_size); - se->SE_CRYPTO_CONFIG |= 0x80; - } - - /* Create final block. */ - uint8_t ALIGN(16) last_block[0x10] = {0}; - if (data_size & 0xF) { - memcpy(last_block, data + (data_size & ~0xF), data_size & 0xF); - last_block[data_size & 0xF] = 0x80; /* Last block = data || 100...0 */ - } else if (data_size >= 0x10) { - memcpy(last_block, data + data_size - 0x10, 0x10); - } - - for (unsigned int i = 0; i < 0x10; i++) { - last_block[i] ^= derived_key[i]; - } - - /* Perform last operation. */ - se->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, NULL, 0, last_block, sizeof(last_block)); - - /* Copy output CMAC. */ - for (unsigned int i = 0; i < (cmac_size >> 2); i++) { - ((uint32_t *)cmac)[i] = read32le(se->SE_HASH_RESULT, i << 2); - } -} - -void se_compute_aes_128_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size) { - se_compute_aes_cmac(keyslot, cmac, cmac_size, data, data_size, 0); -} -void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size) { - se_compute_aes_cmac(keyslot, cmac, cmac_size, data, data_size, 0x202); -} - -void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || src_size < 0x10) { - generic_panic(); - } - - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY) | (0x202 << 16); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x144; - set_aes_keyslot_iv(keyslot, iv, 0x10); - se->SE_CRYPTO_LAST_BLOCK = (src_size >> 4) - 1; - trigger_se_blocking_op(OP_START, dst, dst_size, src, src_size); -} - -/* SHA256 Implementation. */ -void se_calculate_sha256(void *dst, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - - /* Setup config for SHA256, size = BITS(src_size) */ - se->SE_CONFIG = (ENCMODE_SHA256 | ALG_SHA | DST_HASHREG); - se->SE_SHA_CONFIG = 1; - se->SE_SHA_MSG_LENGTH[0] = (uint32_t)(src_size << 3); - se->SE_SHA_MSG_LENGTH[1] = 0; - se->SE_SHA_MSG_LENGTH[2] = 0; - se->SE_SHA_MSG_LENGTH[3] = 0; - se->SE_SHA_MSG_LEFT[0] = (uint32_t)(src_size << 3); - se->SE_SHA_MSG_LEFT[1] = 0; - se->SE_SHA_MSG_LEFT[2] = 0; - se->SE_SHA_MSG_LEFT[3] = 0; - - /* Trigger the operation. */ - trigger_se_blocking_op(OP_START, NULL, 0, src, src_size); - - /* Copy output hash. */ - for (unsigned int i = 0; i < (0x20 >> 2); i++) { - ((uint32_t *)dst)[i] = read32be(se->SE_HASH_RESULT, i << 2); - } -} - -/* RNG API */ -void se_initialize_rng(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* To initialize the RNG, we'll perform an RNG operation into an output buffer. */ - /* This will be discarded, when done. */ - uint8_t ALIGN(16) output_buf[0x10]; - - se->SE_RNG_SRC_CONFIG = 3; /* Entropy enable + Entropy lock enable */ - se->SE_RNG_RESEED_INTERVAL = 70001; - se->SE_CONFIG = (ALG_RNG | DST_MEMORY); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x108; - se->SE_RNG_CONFIG = 5; - se->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, output_buf, 0x10, NULL, 0); -} - -void se_generate_random(unsigned int keyslot, void *dst, size_t size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - uint32_t num_blocks = size >> 4; - size_t aligned_size = num_blocks << 4; - se->SE_CONFIG = (ALG_RNG | DST_MEMORY); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x108; - se->SE_RNG_CONFIG = 4; - - if (num_blocks >= 1) { - se->SE_CRYPTO_LAST_BLOCK = num_blocks - 1; - trigger_se_blocking_op(OP_START, dst, aligned_size, NULL, 0); - } - if (size > aligned_size) { - se_perform_aes_block_operation(dst + aligned_size, size - aligned_size, NULL, 0); - } -} diff --git a/sept/sept-primary/src/se.h b/sept/sept-primary/src/se.h deleted file mode 100644 index 2cc97f8ec..000000000 --- a/sept/sept-primary/src/se.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_SE_H -#define FUSEE_SE_H - -#define SE_BASE 0x70012000 -#define MAKE_SE_REG(n) MAKE_REG32(SE_BASE + n) - -#define KEYSLOT_SWITCH_LP0TZRAMKEY 0x2 -#define KEYSLOT_SWITCH_SRKGENKEY 0x8 -#define KEYSLOT_SWITCH_PACKAGE2KEY 0x8 -#define KEYSLOT_SWITCH_TEMPKEY 0x9 -#define KEYSLOT_SWITCH_SESSIONKEY 0xA -#define KEYSLOT_SWITCH_RNGKEY 0xB -#define KEYSLOT_SWITCH_MASTERKEY 0xC -#define KEYSLOT_SWITCH_DEVICEKEY 0xD - -/* This keyslot was added in 4.0.0. */ -#define KEYSLOT_SWITCH_4XNEWDEVICEKEYGENKEY 0xD -#define KEYSLOT_SWITCH_4XNEWCONSOLEKEYGENKEY 0xE -#define KEYSLOT_SWITCH_4XOLDDEVICEKEY 0xF - -/* This keyslot was added in 5.0.0. */ -#define KEYSLOT_SWITCH_5XNEWDEVICEKEYGENKEY 0xA - -/* Mariko keyslots. */ -#define KEYSLOT_SWITCH_MASTERKEY_MARIKO 0x7 - -#define KEYSLOT_AES_MAX 0x10 -#define KEYSLOT_RSA_MAX 0x2 - -#define KEYSIZE_AES_MAX 0x20 -#define KEYSIZE_RSA_MAX 0x100 - -#define ALG_SHIFT (12) -#define ALG_DEC_SHIFT (8) -#define ALG_NOP (0 << ALG_SHIFT) -#define ALG_AES_ENC (1 << ALG_SHIFT) -#define ALG_AES_DEC ((1 << ALG_DEC_SHIFT) | ALG_NOP) -#define ALG_RNG (2 << ALG_SHIFT) -#define ALG_SHA (3 << ALG_SHIFT) -#define ALG_RSA (4 << ALG_SHIFT) - -#define DST_SHIFT (2) -#define DST_MEMORY (0 << DST_SHIFT) -#define DST_HASHREG (1 << DST_SHIFT) -#define DST_KEYTAB (2 << DST_SHIFT) -#define DST_SRK (3 << DST_SHIFT) -#define DST_RSAREG (4 << DST_SHIFT) - -#define ENCMODE_SHIFT (24) -#define DECMODE_SHIFT (16) -#define ENCMODE_SHA256 (5 << ENCMODE_SHIFT) - -#define HASH_DISABLE (0x0) -#define HASH_ENABLE (0x1) - -#define OP_ABORT 0 -#define OP_START 1 -#define OP_RESTART 2 -#define OP_CTX_SAVE 3 -#define OP_RESTART_IN 4 - -#define CTX_SAVE_SRC_SHIFT 29 -#define CTX_SAVE_SRC_STICKY_BITS (0 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_KEYTABLE_AES (2 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_KEYTABLE_RSA (1 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_MEM (4 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_SRK (6 << CTX_SAVE_SRC_SHIFT) - -#define CTX_SAVE_KEY_LOW_BITS 0 -#define CTX_SAVE_KEY_HIGH_BITS 1 -#define CTX_SAVE_KEY_ORIGINAL_IV 2 -#define CTX_SAVE_KEY_UPDATED_IV 3 - -#define CTX_SAVE_STICKY_BIT_INDEX_SHIFT 24 -#define CTX_SAVE_KEY_INDEX_SHIFT 8 -#define CTX_SAVE_RSA_KEY_INDEX_SHIFT 16 -#define CTX_SAVE_RSA_KEY_BLOCK_INDEX_SHIFT 12 - -#define RSA_2048_BYTES 0x100 - -typedef struct { - uint32_t SE_SE_SECURITY; - uint32_t SE_TZRAM_SECURITY; - uint32_t SE_OPERATION; - uint32_t SE_INT_ENABLE; - uint32_t SE_INT_STATUS; - uint32_t SE_CONFIG; - uint32_t SE_IN_LL_ADDR; - uint32_t SE_IN_CUR_BYTE_ADDR; - uint32_t SE_IN_CUR_LL_ID; - uint32_t SE_OUT_LL_ADDR; - uint32_t SE_OUT_CUR_BYTE_ADDR; - uint32_t SE_OUT_CUR_LL_ID; - uint32_t SE_HASH_RESULT[0x10]; - uint32_t SE_CTX_SAVE_CONFIG; - uint32_t _0x74[0x63]; - uint32_t SE_SHA_CONFIG; - uint32_t SE_SHA_MSG_LENGTH[0x4]; - uint32_t SE_SHA_MSG_LEFT[0x4]; - uint32_t _0x224[0x17]; - uint32_t SE_CRYPTO_SECURITY_PERKEY; - uint32_t SE_CRYPTO_KEYTABLE_ACCESS[0x10]; - uint32_t _0x2C4[0x10]; - uint32_t SE_CRYPTO_CONFIG; - uint32_t SE_CRYPTO_LINEAR_CTR[0x4]; - uint32_t SE_CRYPTO_LAST_BLOCK; - uint32_t SE_CRYPTO_KEYTABLE_ADDR; - uint32_t SE_CRYPTO_KEYTABLE_DATA; - uint32_t _0x324[0x3]; - uint32_t SE_CRYPTO_KEYTABLE_DST; - uint32_t _0x334[0x3]; - uint32_t SE_RNG_CONFIG; - uint32_t SE_RNG_SRC_CONFIG; - uint32_t SE_RNG_RESEED_INTERVAL; - uint32_t _0x34C[0x2D]; - uint32_t SE_RSA_CONFIG; - uint32_t SE_RSA_KEY_SIZE; - uint32_t SE_RSA_EXP_SIZE; - uint32_t SE_RSA_SECURITY_PERKEY; - uint32_t SE_RSA_KEYTABLE_ACCESS[0x2]; - uint32_t _0x418[0x2]; - uint32_t SE_RSA_KEYTABLE_ADDR; - uint32_t SE_RSA_KEYTABLE_DATA; - uint32_t SE_RSA_OUTPUT[0x40]; - uint32_t _0x528[0xB6]; - uint32_t SE_STATUS; - uint32_t SE_ERR_STATUS; - uint32_t SE_MISC; - uint32_t SE_SPARE; - uint32_t SE_ENTROPY_DEBUG_COUNTER; - uint32_t _0x814; - uint32_t _0x818; - uint32_t _0x81C; - uint32_t _0x820[0x5F8]; -} tegra_se_t; - -typedef struct { - uint32_t address; - uint32_t size; -} se_addr_info_t; - -typedef struct { - uint32_t num_entries; /* Set to total entries - 1 */ - se_addr_info_t addr_info; /* This should really be an array...but for our use case it works. */ -} se_ll_t; - -static inline volatile tegra_se_t *se_get_regs(void) { - return (volatile tegra_se_t *)SE_BASE; -} - -void se_check_error_status_reg(void); -void se_check_for_error(void); -void se_trigger_interrupt(void); - -void se_validate_stored_vector(void); -void se_generate_stored_vector(void); - -void se_verify_flags_cleared(void); - -void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags); -void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags); -void clear_aes_keyslot(unsigned int keyslot); -void clear_rsa_keyslot(unsigned int keyslot); - -void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size); -void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size); -void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size); -void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size); -void set_se_ctr(const void *ctr); - -/* Secure AES API */ -void se_aes_128_xts_nintendo_decrypt(unsigned int keyslot_1, unsigned int keyslot_2, unsigned int base_sector, void *dst, const void *src, size_t size, unsigned int sector_size); -void se_aes_128_xts_nintendo_encrypt(unsigned int keyslot_1, unsigned int keyslot_2, unsigned int base_sector, void *dst, const void *src, size_t size, unsigned int sector_size); -void se_compute_aes_128_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size); -void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size); -void se_aes_128_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -void se_aes_256_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size); -void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv); - -/* Hash API */ -void se_calculate_sha256(void *dst, const void *src, size_t src_size); - -/* RSA API */ -void se_get_exp_mod_output(void *buf, size_t size); -void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const void *modulus, size_t modulus_size, const void *data, size_t data_size); - -/* RNG API */ -void se_initialize_rng(unsigned int keyslot); -void se_generate_random(unsigned int keyslot, void *dst, size_t size); - -#endif diff --git a/sept/sept-primary/src/start.s b/sept/sept-primary/src/start.s deleted file mode 100644 index b5cb1c1e8..000000000 --- a/sept/sept-primary/src/start.s +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -.section .text.start, "ax", %progbits -.arm -.align 5 -.global _start -.type _start, %function -_start: - /* Set coldboot */ - mov r0, #0x0 - ldr r1, =0x7000E400 - str r0, [r1, #0x50] - - /* Tell pk1ldr normal reboot, no error */ - str r0, [r1, #0x1B4] - str r0, [r1, #0x840] - - /* Cleanup SVC handler address. */ - ldr r0, =0x40004C30 - ldr r1, =0x6000F208 - str r0, [r1] - - /* Disable RCM forcefully */ - mov r0, #0x4 - ldr r1, =0x15DC - ldr r2, =0xE020 - bl ipatch_word - - /* Patch BCT signature check */ - mov r0, #0x5 - ldr r1, =0x4AEE - ldr r2, =0xE05B - bl ipatch_word - - /* Patch bootloader read */ - mov r0, #0x6 - ldr r1, =0x4E88 - ldr r2, =0xE018 - bl ipatch_word - - ldr r0, =__main_phys_start__ - ldr r1, =__main_start__ - mov r2, #0x0 - ldr r3, =(__main_size__) - copy_panic_payload: - ldr r4, [r0, r2] - str r4, [r1, r2] - add r2, r2, #0x4 - cmp r2, r3 - bne copy_panic_payload - - - - /* Jump back to bootrom start. */ - ldr r0, =0x101010 - bx r0 - - /* Unused, but forces inclusion in binary. */ - b main - - -.section .text.ipatch_word, "ax", %progbits -.arm -.align 5 -.global ipatch_word -.type ipatch_word, %function -ipatch_word: - ldr r3, =0x6001dc00 - lsl r0, r0, #0x2 - lsr r1, r1, #0x1 - lsl r1, r1, #0x10 - orr r1, r1, r2 - str r1, [r3, r0] - bx lr - -.section .text.jump_to_main, "ax", %progbits -.arm -.align 5 -.global jump_to_main -.type jump_to_main, %function -jump_to_main: - /* Insert 0x240 of NOPs, for version compatibility. */ -.rept (0x240/4) - nop -.endr - /* Just jump to main */ - ldr sp, =__stack_top__ - b main - - diff --git a/sept/sept-primary/src/sysreg.h b/sept/sept-primary/src/sysreg.h deleted file mode 100644 index 311945b4e..000000000 --- a/sept/sept-primary/src/sysreg.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_SYSREG_H -#define FUSEE_SYSREG_H - -#include - -#define SYSREG_BASE 0x6000C000 -#define SB_BASE (SYSREG_BASE + 0x200) -#define EXCP_VEC_BASE 0x6000F000 - -#define MAKE_SYSREG(n) MAKE_REG32(SYSREG_BASE + n) -#define MAKE_SB_REG(n) MAKE_REG32(SB_BASE + n) -#define MAKE_EXCP_VEC_REG(n) MAKE_REG32(EXCP_VEC_BASE + n) - -#define AHB_ARBITRATION_DISABLE_0 MAKE_SYSREG(0x004) -#define AHB_ARBITRATION_XBAR_CTRL_0 MAKE_SYSREG(0x0E0) -#define AHB_AHB_SPARE_REG_0 MAKE_SYSREG(0x110) - -#define SB_CSR_0 MAKE_SB_REG(0x00) -#define SB_PIROM_START_0 MAKE_SB_REG(0x04) -#define SB_PFCFG_0 MAKE_SB_REG(0x08) -#define SB_SECURE_SPAREREG_0_0 MAKE_SB_REG(0x0C) -#define SB_SECURE_SPAREREG_1_0 MAKE_SB_REG(0x10) -#define SB_SECURE_SPAREREG_2_0 MAKE_SB_REG(0x14) -#define SB_SECURE_SPAREREG_3_0 MAKE_SB_REG(0x18) -#define SB_SECURE_SPAREREG_4_0 MAKE_SB_REG(0x1C) -#define SB_SECURE_SPAREREG_5_0 MAKE_SB_REG(0x20) -#define SB_SECURE_SPAREREG_6_0 MAKE_SB_REG(0x24) -#define SB_SECURE_SPAREREG_7_0 MAKE_SB_REG(0x28) -#define SB_AA64_RESET_LOW_0 MAKE_SB_REG(0x30) -#define SB_AA64_RESET_HIGH_0 MAKE_SB_REG(0x34) - -#endif diff --git a/sept/sept-primary/src/timers.h b/sept/sept-primary/src/timers.h deleted file mode 100644 index 84d6043aa..000000000 --- a/sept/sept-primary/src/timers.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_TIMERS_H -#define FUSEE_TIMERS_H - -#include "utils.h" - -#define TIMERS_BASE 0x60005000 -#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n) - -#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10) -#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14) -#define SHARED_INTR_STATUS_0 MAKE_TIMERS_REG(0x1A0) -#define SHARED_TIMER_SECURE_CFG_0 MAKE_TIMERS_REG(0x1A4) - -#define RTC_BASE 0x7000E000 -#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n) - -#define RTC_SECONDS MAKE_RTC_REG(0x08) -#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C) -#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10) - -typedef struct { - uint32_t CONFIG; - uint32_t STATUS; - uint32_t COMMAND; - uint32_t PATTERN; -} watchdog_timers_t; - -#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n)) -#define WDT_REBOOT_PATTERN 0xC45A -#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8 * n) - -void wait(uint32_t microseconds); - -static inline uint32_t get_time_s(void) { - return RTC_SECONDS; -} - -static inline uint32_t get_time_ms(void) { - return (RTC_MILLI_SECONDS | (RTC_SHADOW_SECONDS << 10)); -} - -static inline uint32_t get_time_us(void) { - return TIMERUS_CNTR_1US_0; -} - -/** - * Returns the time in microseconds. - */ -static inline uint32_t get_time(void) { - return get_time_us(); -} - -/** - * Returns the number of microseconds that have passed since a given get_time(). - */ -static inline uint32_t get_time_since(uint32_t base) { - return get_time_us() - base; -} - -/** - * Delays for a given number of microseconds. - */ -static inline void udelay(uint32_t usecs) { - uint32_t start = get_time_us(); - while (get_time_us() - start < usecs); -} - -/** - * Delays until a number of usecs have passed since an absolute start time. - */ -static inline void udelay_absolute(uint32_t start, uint32_t usecs) { - while (get_time_us() - start < usecs); -} - -/** - * Delays for a given number of milliseconds. - */ -static inline void mdelay(uint32_t msecs) { - uint32_t start = get_time_ms(); - while (get_time_ms() - start < msecs); -} - -__attribute__ ((noreturn)) void watchdog_reboot(void); - -#endif diff --git a/sept/sept-primary/src/tsec.h b/sept/sept-primary/src/tsec.h deleted file mode 100644 index 6d77ebfca..000000000 --- a/sept/sept-primary/src/tsec.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_TSEC_H_ -#define FUSEE_TSEC_H_ - -#include -#include - -#define TSEC_BASE 0x54500000 -#define SOR1_BASE 0x54580000 -#define KFUSE_BASE 0x7000FC00 - -#define SOR1_DP_HDCP_BKSV_LSB MAKE_REG32(SOR1_BASE + 0x1E8) -#define SOR1_TMDS_HDCP_BKSV_LSB MAKE_REG32(SOR1_BASE + 0x21C) -#define SOR1_TMDS_HDCP_CN_MSB MAKE_REG32(SOR1_BASE + 0x208) -#define SOR1_TMDS_HDCP_CN_LSB MAKE_REG32(SOR1_BASE + 0x20C) - -#define KFUSE_FUSECTRL MAKE_REG32(KFUSE_BASE + 0x00) -#define KFUSE_FUSEADDR MAKE_REG32(KFUSE_BASE + 0x04) -#define KFUSE_FUSEDATA0 MAKE_REG32(KFUSE_BASE + 0x08) -#define KFUSE_FUSEWRDATA0 MAKE_REG32(KFUSE_BASE + 0x0C) -#define KFUSE_FUSETIME_RD1 MAKE_REG32(KFUSE_BASE + 0x10) -#define KFUSE_FUSETIME_RD2 MAKE_REG32(KFUSE_BASE + 0x14) -#define KFUSE_FUSETIME_PGM1 MAKE_REG32(KFUSE_BASE + 0x18) -#define KFUSE_FUSETIME_PGM2 MAKE_REG32(KFUSE_BASE + 0x1C) -#define KFUSE_REGULATOR MAKE_REG32(KFUSE_BASE + 0x20) -#define KFUSE_PD MAKE_REG32(KFUSE_BASE + 0x24) -#define KFUSE_FUSETIME_RD3 MAKE_REG32(KFUSE_BASE + 0x28) -#define KFUSE_STATE MAKE_REG32(KFUSE_BASE + 0x80) -#define KFUSE_ERRCOUNT MAKE_REG32(KFUSE_BASE + 0x84) -#define KFUSE_KEYADDR MAKE_REG32(KFUSE_BASE + 0x88) -#define KFUSE_KEYS MAKE_REG32(KFUSE_BASE + 0x8C) - -typedef struct { - uint32_t TSEC_THI_INCR_SYNCPT; /* Tegra Host Interface registers. */ - uint32_t TSEC_THI_INCR_SYNCPT_CTRL; - uint32_t TSEC_THI_INCR_SYNCPT_ERR; - uint32_t TSEC_THI_CTXSW_INCR_SYNCPT; - uint32_t _0x10[0x4]; - uint32_t TSEC_THI_CTXSW; - uint32_t TSEC_THI_CTXSW_NEXT; - uint32_t TSEC_THI_CONT_SYNCPT_EOF; - uint32_t TSEC_THI_CONT_SYNCPT_L1; - uint32_t TSEC_THI_STREAMID0; - uint32_t TSEC_THI_STREAMID1; - uint32_t TSEC_THI_THI_SEC; - uint32_t _0x3C; - uint32_t TSEC_THI_METHOD0; - uint32_t TSEC_THI_METHOD1; - uint32_t _0x48[0x6]; - uint32_t TSEC_THI_CONTEXT_SWITCH; - uint32_t _0x64[0x5]; - uint32_t TSEC_THI_INT_STATUS; - uint32_t TSEC_THI_INT_MASK; - uint32_t TSEC_THI_CONFIG0; - uint32_t TSEC_THI_DBG_MISC; - uint32_t TSEC_THI_SLCG_OVERRIDE_HIGH_A; - uint32_t TSEC_THI_SLCG_OVERRIDE_LOW_A; - uint32_t _0x90[0x35C]; - uint32_t TSEC_THI_CLK_OVERRIDE; - uint32_t _0xE04[0x7F]; - uint32_t TSEC_FALCON_IRQSSET; /* Falcon microcontroller registers. */ - uint32_t TSEC_FALCON_IRQSCLR; - uint32_t TSEC_FALCON_IRQSTAT; - uint32_t TSEC_FALCON_IRQMODE; - uint32_t TSEC_FALCON_IRQMSET; - uint32_t TSEC_FALCON_IRQMCLR; - uint32_t TSEC_FALCON_IRQMASK; - uint32_t TSEC_FALCON_IRQDEST; - uint32_t TSEC_FALCON_GPTMRINT; - uint32_t TSEC_FALCON_GPTMRVAL; - uint32_t TSEC_FALCON_GPTMRCTL; - uint32_t TSEC_FALCON_PTIMER0; - uint32_t TSEC_FALCON_PTIMER1; - uint32_t TSEC_FALCON_WDTMRVAL; - uint32_t TSEC_FALCON_WDTMRCTL; - uint32_t TSEC_FALCON_IRQDEST2; - uint32_t TSEC_FALCON_MAILBOX0; - uint32_t TSEC_FALCON_MAILBOX1; - uint32_t TSEC_FALCON_ITFEN; - uint32_t TSEC_FALCON_IDLESTATE; - uint32_t TSEC_FALCON_CURCTX; - uint32_t TSEC_FALCON_NXTCTX; - uint32_t TSEC_FALCON_CTXACK; - uint32_t TSEC_FALCON_FHSTATE; - uint32_t TSEC_FALCON_PRIVSTATE; - uint32_t TSEC_FALCON_MTHDDATA; - uint32_t TSEC_FALCON_MTHDID; - uint32_t TSEC_FALCON_MTHDWDAT; - uint32_t TSEC_FALCON_MTHDCOUNT; - uint32_t TSEC_FALCON_MTHDPOP; - uint32_t TSEC_FALCON_MTHDRAMSZ; - uint32_t TSEC_FALCON_SFTRESET; - uint32_t TSEC_FALCON_OS; - uint32_t TSEC_FALCON_RM; - uint32_t TSEC_FALCON_SOFT_PM; - uint32_t TSEC_FALCON_SOFT_MODE; - uint32_t TSEC_FALCON_DEBUG1; - uint32_t TSEC_FALCON_DEBUGINFO; - uint32_t TSEC_FALCON_IBRKPT1; - uint32_t TSEC_FALCON_IBRKPT2; - uint32_t TSEC_FALCON_CGCTL; - uint32_t TSEC_FALCON_ENGCTL; - uint32_t TSEC_FALCON_PMM; - uint32_t TSEC_FALCON_ADDR; - uint32_t TSEC_FALCON_IBRKPT3; - uint32_t TSEC_FALCON_IBRKPT4; - uint32_t TSEC_FALCON_IBRKPT5; - uint32_t _0x10BC[0x5]; - uint32_t TSEC_FALCON_EXCI; - uint32_t TSEC_FALCON_SVEC_SPR; - uint32_t TSEC_FALCON_RSTAT0; - uint32_t TSEC_FALCON_RSTAT3; - uint32_t _0x10E0[0x8]; - uint32_t TSEC_FALCON_CPUCTL; - uint32_t TSEC_FALCON_BOOTVEC; - uint32_t TSEC_FALCON_HWCFG; - uint32_t TSEC_FALCON_DMACTL; - uint32_t TSEC_FALCON_DMATRFBASE; - uint32_t TSEC_FALCON_DMATRFMOFFS; - uint32_t TSEC_FALCON_DMATRFCMD; - uint32_t TSEC_FALCON_DMATRFFBOFFS; - uint32_t TSEC_FALCON_DMAPOLL_FB; - uint32_t TSEC_FALCON_DMAPOLL_CP; - uint32_t TSEC_FALCON_DBG_STATE; - uint32_t TSEC_FALCON_HWCFG1; - uint32_t TSEC_FALCON_CPUCTL_ALIAS; - uint32_t _0x1134; - uint32_t TSEC_FALCON_STACKCFG; - uint32_t _0x113C; - uint32_t TSEC_FALCON_IMCTL; - uint32_t TSEC_FALCON_IMSTAT; - uint32_t TSEC_FALCON_TRACEIDX; - uint32_t TSEC_FALCON_TRACEPC; - uint32_t TSEC_FALCON_IMFILLRNG0; - uint32_t TSEC_FALCON_IMFILLRNG1; - uint32_t TSEC_FALCON_IMFILLCTL; - uint32_t TSEC_FALCON_IMCTL_DEBUG; - uint32_t TSEC_FALCON_CMEMBASE; - uint32_t TSEC_FALCON_DMEMAPERT; - uint32_t TSEC_FALCON_EXTERRADDR; - uint32_t TSEC_FALCON_EXTERRSTAT; - uint32_t _0x1170[0x3]; - uint32_t TSEC_FALCON_CG2; - uint32_t TSEC_FALCON_IMEMC0; - uint32_t TSEC_FALCON_IMEMD0; - uint32_t TSEC_FALCON_IMEMT0; - uint32_t _0x118C; - uint32_t TSEC_FALCON_IMEMC1; - uint32_t TSEC_FALCON_IMEMD1; - uint32_t TSEC_FALCON_IMEMT1; - uint32_t _0x119C; - uint32_t TSEC_FALCON_IMEMC2; - uint32_t TSEC_FALCON_IMEMD2; - uint32_t TSEC_FALCON_IMEMT2; - uint32_t _0x11AC; - uint32_t TSEC_FALCON_IMEMC3; - uint32_t TSEC_FALCON_IMEMD3; - uint32_t TSEC_FALCON_IMEMT3; - uint32_t _0x11BC; - uint32_t TSEC_FALCON_DMEMC0; - uint32_t TSEC_FALCON_DMEMD0; - uint32_t TSEC_FALCON_DMEMC1; - uint32_t TSEC_FALCON_DMEMD1; - uint32_t TSEC_FALCON_DMEMC2; - uint32_t TSEC_FALCON_DMEMD2; - uint32_t TSEC_FALCON_DMEMC3; - uint32_t TSEC_FALCON_DMEMD3; - uint32_t TSEC_FALCON_DMEMC4; - uint32_t TSEC_FALCON_DMEMD4; - uint32_t TSEC_FALCON_DMEMC5; - uint32_t TSEC_FALCON_DMEMD5; - uint32_t TSEC_FALCON_DMEMC6; - uint32_t TSEC_FALCON_DMEMD6; - uint32_t TSEC_FALCON_DMEMC7; - uint32_t TSEC_FALCON_DMEMD7; - uint32_t TSEC_FALCON_ICD_CMD; - uint32_t TSEC_FALCON_ICD_ADDR; - uint32_t TSEC_FALCON_ICD_WDATA; - uint32_t TSEC_FALCON_ICD_RDATA; - uint32_t _0x1210[0xC]; - uint32_t TSEC_FALCON_SCTL; - uint32_t TSEC_FALCON_SSTAT; - uint32_t _0x1248[0xE]; - uint32_t TSEC_FALCON_SPROT_IMEM; - uint32_t TSEC_FALCON_SPROT_DMEM; - uint32_t TSEC_FALCON_SPROT_CPUCTL; - uint32_t TSEC_FALCON_SPROT_MISC; - uint32_t TSEC_FALCON_SPROT_IRQ; - uint32_t TSEC_FALCON_SPROT_MTHD; - uint32_t TSEC_FALCON_SPROT_SCTL; - uint32_t TSEC_FALCON_SPROT_WDTMR; - uint32_t _0x12A0[0x8]; - uint32_t TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW; - uint32_t TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH; - uint32_t TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW; - uint32_t TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH; - uint32_t TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW; - uint32_t TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH; - uint32_t TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW; - uint32_t TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH; - uint32_t TSEC_FALCON_DMAINFO_CTL; - uint32_t _0x12E4[0x47]; - uint32_t TSEC_SCP_CTL0; /* Secure Co-processor registers. */ - uint32_t TSEC_SCP_CTL1; - uint32_t TSEC_SCP_CTL_STAT; - uint32_t TSEC_SCP_CTL_LOCK; - uint32_t TSEC_SCP_CFG; - uint32_t TSEC_SCP_CTL_SCP; - uint32_t TSEC_SCP_CTL_PKEY; - uint32_t TSEC_SCP_CTL_DBG; - uint32_t TSEC_SCP_DBG0; - uint32_t TSEC_SCP_DBG1; - uint32_t TSEC_SCP_DBG2; - uint32_t _0x142C; - uint32_t TSEC_SCP_CMD; - uint32_t _0x1434[0x7]; - uint32_t TSEC_SCP_STAT0; - uint32_t TSEC_SCP_STAT1; - uint32_t TSEC_SCP_STAT2; - uint32_t _0x145C[0x5]; - uint32_t TSEC_SCP_RND_STAT0; - uint32_t TSEC_SCP_RND_STAT1; - uint32_t _0x1478[0x2]; - uint32_t TSEC_SCP_IRQSTAT; - uint32_t TSEC_SCP_IRQMASK; - uint32_t _0x1488[0x2]; - uint32_t TSEC_SCP_ACL_ERR; - uint32_t TSEC_SCP_SEC_ERR; - uint32_t TSEC_SCP_CMD_ERR; - uint32_t _0x149C[0x19]; - uint32_t TSEC_RND_CTL0; /* Random Number Generator registers. */ - uint32_t TSEC_RND_CTL1; - uint32_t TSEC_RND_CTL2; - uint32_t TSEC_RND_CTL3; - uint32_t TSEC_RND_CTL4; - uint32_t TSEC_RND_CTL5; - uint32_t TSEC_RND_CTL6; - uint32_t TSEC_RND_CTL7; - uint32_t TSEC_RND_CTL8; - uint32_t TSEC_RND_CTL9; - uint32_t TSEC_RND_CTL10; - uint32_t TSEC_RND_CTL11; - uint32_t _0x1530[0x34]; - uint32_t TSEC_TFBIF_CTL; /* Tegra Framebuffer Interface registers. */ - uint32_t TSEC_TFBIF_MCCIF_FIFOCTRL; - uint32_t TSEC_TFBIF_THROTTLE; - uint32_t TSEC_TFBIF_DBG_STAT0; - uint32_t TSEC_TFBIF_DBG_STAT1; - uint32_t TSEC_TFBIF_DBG_RDCOUNT_LO; - uint32_t TSEC_TFBIF_DBG_RDCOUNT_HI; - uint32_t TSEC_TFBIF_DBG_WRCOUNT_LO; - uint32_t TSEC_TFBIF_DBG_WRCOUNT_HI; - uint32_t TSEC_TFBIF_DBG_R32COUNT; - uint32_t TSEC_TFBIF_DBG_R64COUNT; - uint32_t TSEC_TFBIF_DBG_R128COUNT; - uint32_t _0x1630; - uint32_t TSEC_TFBIF_MCCIF_FIFOCTRL1; - uint32_t TSEC_TFBIF_WRR_RDP; - uint32_t _0x163C; - uint32_t TSEC_TFBIF_SPROT_EMEM; - uint32_t TSEC_TFBIF_TRANSCFG; - uint32_t TSEC_TFBIF_REGIONCFG; - uint32_t TSEC_TFBIF_ACTMON_ACTIVE_MASK; - uint32_t TSEC_TFBIF_ACTMON_ACTIVE_BORPS; - uint32_t TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT; - uint32_t _0x1658[0x2]; - uint32_t TSEC_TFBIF_ACTMON_MCB_MASK; - uint32_t TSEC_TFBIF_ACTMON_MCB_BORPS; - uint32_t TSEC_TFBIF_ACTMON_MCB_WEIGHT; - uint32_t _0x166C; - uint32_t TSEC_TFBIF_THI_TRANSPROP; - uint32_t _0x1674[0x17]; - uint32_t TSEC_CG; /* Clock Gate registers. */ - uint32_t _0x16D4[0xB]; - uint32_t TSEC_BAR0_CTL; /* HOST1X device DMA registers. */ - uint32_t TSEC_BAR0_ADDR; - uint32_t TSEC_BAR0_DATA; - uint32_t TSEC_BAR0_TIMEOUT; - uint32_t _0x1710[0x3C]; - uint32_t TSEC_TEGRA_FALCON_IP_VER; /* Miscellaneous registers. */ - uint32_t _0x1804[0xD]; - uint32_t TSEC_TEGRA_CTL; - uint32_t _0x183C[0x31]; -} tegra_tsec_t; - -static inline volatile tegra_tsec_t *tsec_get_regs(void) -{ - return (volatile tegra_tsec_t *)TSEC_BASE; -} - -#endif \ No newline at end of file diff --git a/sept/sept-primary/src/utils.c b/sept/sept-primary/src/utils.c deleted file mode 100644 index 5606a86c8..000000000 --- a/sept/sept-primary/src/utils.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include "utils.h" -#include "se.h" -#include "fuse.h" -#include "pmc.h" -#include "timers.h" -#include "panic.h" -#include "car.h" -#include "btn.h" - -#include - -void wait(uint32_t microseconds) { - uint32_t old_time = TIMERUS_CNTR_1US_0; - while (TIMERUS_CNTR_1US_0 - old_time <= microseconds) { - /* Spin-lock. */ - } -} - -__attribute__((noreturn)) void watchdog_reboot(void) { - volatile watchdog_timers_t *wdt = GET_WDT(4); - wdt->PATTERN = WDT_REBOOT_PATTERN; - wdt->COMMAND = 2; /* Disable Counter. */ - GET_WDT_REBOOT_CFG_REG(4) = 0xC0000000; - wdt->CONFIG = 0x8019; /* Full System Reset after Fourth Counter expires, using TIMER(9). */ - wdt->COMMAND = 1; /* Enable Counter. */ - while (true) { - /* Wait for reboot. */ - } -} - -__attribute__((noreturn)) void pmc_reboot(uint32_t scratch0) { - APBDEV_PMC_SCRATCH0_0 = scratch0; - - /* Reset the processor. */ - APBDEV_PMC_CONTROL = BIT(4); - - while (true) { - /* Wait for reboot. */ - } -} - -__attribute__((noreturn)) void wait_for_button_and_reboot(void) { - uint32_t button; - while (true) { - button = btn_read(); - if (button & BTN_POWER) { - pmc_reboot(2); - } - } -} - -__attribute__ ((noreturn)) void generic_panic(void) { - panic(0xFF000006); -} - -__attribute__((noinline)) bool overlaps(uint64_t as, uint64_t ae, uint64_t bs, uint64_t be) -{ - if(as <= bs && bs <= ae) - return true; - if(bs <= as && as <= be) - return true; - return false; -} - diff --git a/sept/sept-primary/src/utils.h b/sept/sept-primary/src/utils.h deleted file mode 100644 index 91fbf1f67..000000000 --- a/sept/sept-primary/src/utils.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_UTILS_H -#define FUSEE_UTILS_H - -#include -#include -#include -#include - -#define BIT(n) (1u << (n)) -#define BITL(n) (1ull << (n)) -#define MASK(n) (BIT(n) - 1) -#define MASKL(n) (BITL(n) - 1) -#define MASK2(a,b) (MASK(a) & ~MASK(b)) -#define MASK2L(a,b) (MASKL(a) & ~MASKL(b)) - -#define MAKE_REG32(a) (*(volatile uint32_t *)(a)) - -#define ALIGN(m) __attribute__((aligned(m))) -#define PACKED __attribute__((packed)) - -#define ALINLINE __attribute__((always_inline)) -#define NOINLINE __attribute__((noinline)) - -#define SET_SYSREG(reg, val) do { temp_reg = (val); __asm__ __volatile__ ("msr " #reg ", %0" :: "r"(temp_reg) : "memory"); } while(false) - -static inline uintptr_t get_physical_address(const void *addr) { - return (uintptr_t)addr; -} - -static inline uint32_t read32le(const volatile void *dword, size_t offset) { - uintptr_t addr = (uintptr_t)dword + offset; - volatile uint32_t *target = (uint32_t *)addr; - return *target; -} - -static inline uint32_t read32be(const volatile void *dword, size_t offset) { - return __builtin_bswap32(read32le(dword, offset)); -} - -static inline uint64_t read64le(const volatile void *qword, size_t offset) { - uintptr_t addr = (uintptr_t)qword + offset; - volatile uint64_t *target = (uint64_t *)addr; - return *target; -} - -static inline uint64_t read64be(const volatile void *qword, size_t offset) { - return __builtin_bswap64(read64le(qword, offset)); -} - -static inline void write32le(volatile void *dword, size_t offset, uint32_t value) { - uintptr_t addr = (uintptr_t)dword + offset; - volatile uint32_t *target = (uint32_t *)addr; - *target = value; -} - -static inline void write32be(volatile void *dword, size_t offset, uint32_t value) { - write32le(dword, offset, __builtin_bswap32(value)); -} - -static inline void write64le(volatile void *qword, size_t offset, uint64_t value) { - uintptr_t addr = (uintptr_t)qword + offset; - volatile uint64_t *target = (uint64_t *)addr; - *target = value; -} - -static inline void write64be(volatile void *qword, size_t offset, uint64_t value) { - write64le(qword, offset, __builtin_bswap64(value)); -} - -static inline bool check_32bit_additive_overflow(uint32_t a, uint32_t b) { - return __builtin_add_overflow_p(a, b, (uint32_t)0); -} - -static inline bool check_32bit_address_loadable(uintptr_t addr) { - /* FWIW the bootROM forbids loading anything between 0x40000000 and 0x40010000, using it for itself... */ - return (addr >= 0x40010000u && addr < 0x40040000u) || addr >= 0x80000000u; -} - -static inline bool check_32bit_address_range_loadable(uintptr_t addr, size_t size) { - return - !__builtin_add_overflow_p(addr, size, (uintptr_t)0) && /* the range doesn't overflow */ - check_32bit_address_loadable(addr) && check_32bit_address_loadable(addr + size) && /* bounds are valid */ - !(addr >= 0x40010000u && addr < 0x40040000u && addr + size >= 0x40040000u) /* the range doesn't cross MMIO */ - ; -} - -bool overlaps(uint64_t as, uint64_t ae, uint64_t bs, uint64_t be); -static inline bool overlaps_a(const void *as, const void *ae, const void *bs, const void *be) { - return overlaps((uint64_t)(uintptr_t)as, (uint64_t)(uintptr_t)ae, (uint64_t)(uintptr_t)bs, (uint64_t)(uintptr_t)be); -} - -static inline bool check_32bit_address_range_in_program(uintptr_t addr, size_t size) { - extern uint8_t __chainloader_start__[], __chainloader_end__[]; - extern uint8_t __stack_bottom__[], __stack_top__[]; - extern uint8_t __start__[], __end__[]; - uint8_t *start = (uint8_t *)addr, *end = start + size; - - return overlaps_a(start, end, __chainloader_start__, __chainloader_end__) || - overlaps_a(start, end, __stack_bottom__, __stack_top__) || - overlaps_a(start, end, (void *)0xC0000000, (void *)0xC03C0000) || /* framebuffer */ - overlaps_a(start, end, __start__, __end__); -} - -void hexdump(const void* data, size_t size, uintptr_t addrbase); - -__attribute__((noreturn)) void watchdog_reboot(void); -__attribute__((noreturn)) void pmc_reboot(uint32_t scratch0); -__attribute__((noreturn)) void wait_for_button_and_reboot(void); - -__attribute__((noreturn)) void generic_panic(void); - -#endif diff --git a/sept/sept-secondary/KEYS_template.py b/sept/sept-secondary/KEYS_template.py deleted file mode 100644 index bb605e6ef..000000000 --- a/sept/sept-secondary/KEYS_template.py +++ /dev/null @@ -1,38 +0,0 @@ -NUM_KEYS = 2 - -HOVI_ENC_KEY_PRD = [ - bytearray.fromhex('00000000000000000000000000000000'), - bytearray.fromhex('00000000000000000000000000000000'), -] - -HOVI_SIG_KEY_PRD = [ - bytearray.fromhex('00000000000000000000000000000000'), - bytearray.fromhex('00000000000000000000000000000000'), -] - -HOVI_ENC_KEY_DEV = [ - bytearray.fromhex('00000000000000000000000000000000'), - bytearray.fromhex('00000000000000000000000000000000'), -] - -HOVI_SIG_KEY_DEV = [ - bytearray.fromhex('00000000000000000000000000000000'), - bytearray.fromhex('00000000000000000000000000000000'), -] - -IV = [ - bytearray.fromhex('00000000000000000000000000000000'), - bytearray.fromhex('00000000000000000000000000000000'), -] - -IV_DEV = [ - bytearray.fromhex('00000000000000000000000000000000'), - bytearray.fromhex('00000000000000000000000000000000'), -] - -assert len(HOVI_ENC_KEY_PRD) == NUM_KEYS -assert len(HOVI_SIG_KEY_PRD) == NUM_KEYS -assert len(HOVI_ENC_KEY_DEV) == NUM_KEYS -assert len(HOVI_SIG_KEY_DEV) == NUM_KEYS -assert len(IV) == NUM_KEYS -assert len(IV_DEV) == NUM_KEYS \ No newline at end of file diff --git a/sept/sept-secondary/Makefile b/sept/sept-secondary/Makefile deleted file mode 100644 index 49ee8a605..000000000 --- a/sept/sept-secondary/Makefile +++ /dev/null @@ -1,196 +0,0 @@ -#--------------------------------------------------------------------------------- -.SUFFIXES: -#--------------------------------------------------------------------------------- - -ifeq ($(strip $(DEVKITARM)),) -$(error "Please set DEVKITARM in your environment. export DEVKITARM=devkitARM") -endif - -TOPDIR ?= $(CURDIR) - -AMS := $(TOPDIR)/../../ -include $(DEVKITARM)/base_rules - -AMSBRANCH := $(shell git symbolic-ref --short HEAD) -AMSREV := $(AMSBRANCH)-$(shell git rev-parse --short HEAD) - -ifneq (, $(strip $(shell git status --porcelain 2>/dev/null))) - AMSREV := $(AMSREV)-dirty -endif - -#--------------------------------------------------------------------------------- -# TARGET is the name of the output -# BUILD is the directory where object files & intermediate files will be placed -# SOURCES is a list of directories containing source code -# DATA is a list of directories containing data files -# INCLUDES is a list of directories containing header files -#--------------------------------------------------------------------------------- -TARGET := $(notdir $(CURDIR)) -BUILD := build -SOURCES := src ../../fusee/common ../../fusee/common/display ../../fusee/common/fatfs ../../fusee/common/sdmmc -DATA := data -INCLUDES := include ../../libraries/libvapours/include - -#--------------------------------------------------------------------------------- -# options for code generation -#--------------------------------------------------------------------------------- -ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork -DEFINES := -D__BPMP__ -DSEPT_STAGE2_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\" - -CFLAGS := \ - -g \ - -gdwarf-4 \ - -O2 \ - -fomit-frame-pointer \ - -ffunction-sections \ - -fdata-sections \ - -std=gnu11 \ - -Werror \ - -Wall \ - -Wno-array-bounds \ - -Wno-stringop-overflow \ - -Wno-stringop-overread \ - -fstrict-volatile-bitfields \ - $(ARCH) $(DEFINES) - -CFLAGS += $(INCLUDE) - -CXXFLAGS := $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11 - -ASFLAGS := -g -gdwarf-4 $(ARCH) -LDFLAGS = -specs=$(TOPDIR)/linker.specs -g -gdwarf-4 $(ARCH) -Wl,-Map,$(notdir $*.map) - -LIBS := - -#--------------------------------------------------------------------------------- -# list of directories containing libraries, this must be the top level containing -# include and lib -#--------------------------------------------------------------------------------- -LIBDIRS := - - -#--------------------------------------------------------------------------------- -# no real need to edit anything past this point unless you need to add additional -# rules for different file extensions -#--------------------------------------------------------------------------------- -ifneq ($(BUILD),$(notdir $(CURDIR))) -#--------------------------------------------------------------------------------- - -export OUTPUT := $(CURDIR)/$(TARGET) -export TOPDIR := $(CURDIR) - -export VPATH := $(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \ - $(foreach dir,$(DATA),$(CURDIR)/$(dir)) \ - $(AMS)/exosphere/program/rebootstub \ - $(TOPDIR)/key_derivation - -export DEPSDIR := $(CURDIR)/$(BUILD) - -CFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c))) -CPPFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp))) -SFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s))) -BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) rebootstub.bin key_derivation.bin - -#--------------------------------------------------------------------------------- -# use CXX for linking C++ projects, CC for standard C -#--------------------------------------------------------------------------------- -ifeq ($(strip $(CPPFILES)),) -#--------------------------------------------------------------------------------- - export LD := $(CC) -#--------------------------------------------------------------------------------- -else -#--------------------------------------------------------------------------------- - export LD := $(CXX) -#--------------------------------------------------------------------------------- -endif -#--------------------------------------------------------------------------------- - -export OFILES_BIN := $(addsuffix .o,$(BINFILES)) -export OFILES_SRC := $(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o) -export OFILES := $(OFILES_BIN) $(OFILES_SRC) -export HFILES_BIN := $(addsuffix .h,$(subst .,_,$(BINFILES))) - -export INCLUDE := $(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \ - $(foreach dir,$(LIBDIRS),-I$(dir)/include) \ - -I$(CURDIR)/$(BUILD) - -export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib) - -.PHONY: $(BUILD) clean all check_rebootstub check_key_derivation - -#--------------------------------------------------------------------------------- -all: check_rebootstub check_key_derivation $(BUILD) - -check_rebootstub: - @$(MAKE) -C $(AMS)/exosphere/program/rebootstub all - -check_key_derivation: - @$(MAKE) -C key_derivation - -$(BUILD): check_rebootstub check_key_derivation -ifeq ($(strip $(SEPT_00_ENC_PATH)),) - @[ -d $@ ] || mkdir -p $@ - @$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile -else - @touch $(TOPDIR)/$(TARGET).bin - @cp $(SEPT_00_ENC_PATH) $(TOPDIR)/$(TARGET)_00.enc - @cp $(SEPT_01_ENC_PATH) $(TOPDIR)/$(TARGET)_01.enc - @cp $(SEPT_DEV_00_ENC_PATH) $(TOPDIR)/$(TARGET)_dev_00.enc - @cp $(SEPT_DEV_01_ENC_PATH) $(TOPDIR)/$(TARGET)_dev_01.enc -endif - -#--------------------------------------------------------------------------------- -clean: - @echo clean ... - @$(MAKE) -C $(AMS)/exosphere/program/rebootstub clean - @$(MAKE) -C key_derivation clean - @rm -fr $(BUILD) $(TARGET).bin $(TARGET)_*.enc $(TARGET).elf - - -#--------------------------------------------------------------------------------- -else -.PHONY: all - -DEPENDS := $(OFILES:.o=.d) - -#--------------------------------------------------------------------------------- -# main targets -#--------------------------------------------------------------------------------- -all : $(OUTPUT)_dev_01.enc - -$(OUTPUT)_dev_01.enc : $(OUTPUT)_dev_00.enc - -$(OUTPUT)_dev_00.enc : $(OUTPUT)_01.enc - -$(OUTPUT)_01.enc : $(OUTPUT)_00.enc - -$(OUTPUT)_00.enc : $(OUTPUT).bin - @python $(TOPDIR)/sept_sign.py $(OUTPUT).bin $(OUTPUT).enc - @echo built ... $(notdir $@) - -$(OUTPUT).bin : $(OUTPUT).elf - $(OBJCOPY) -S -O binary $< $@ - @echo built ... $(notdir $@) - -$(OUTPUT).elf : $(OFILES) - -%.elf: $(OFILES) - @echo linking $(notdir $@) - @$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@ - @$(NM) -CSn $@ > $(notdir $*.lst) - -$(OFILES_SRC) : $(HFILES_BIN) - -#--------------------------------------------------------------------------------- -# you need a rule like this for each extension you use as binary data -#--------------------------------------------------------------------------------- -%.bin.o %_bin.h: %.bin -#--------------------------------------------------------------------------------- - @echo $(notdir $<) - @$(bin2o) - --include $(DEPENDS) - -#--------------------------------------------------------------------------------------- -endif -#--------------------------------------------------------------------------------------- diff --git a/sept/sept-secondary/key_derivation/Makefile b/sept/sept-secondary/key_derivation/Makefile deleted file mode 100644 index 89915e5c4..000000000 --- a/sept/sept-secondary/key_derivation/Makefile +++ /dev/null @@ -1,158 +0,0 @@ -#--------------------------------------------------------------------------------- -.SUFFIXES: -#--------------------------------------------------------------------------------- - -ifeq ($(strip $(DEVKITPRO)),) -$(error "Please set DEVKITPRO in your environment. export DEVKITPRO=/devkitpro") -endif - -TOPDIR ?= $(CURDIR) -include $(DEVKITPRO)/devkitA64/base_rules - -#--------------------------------------------------------------------------------- -# TARGET is the name of the output -# BUILD is the directory where object files & intermediate files will be placed -# SOURCES is a list of directories containing source code -# DATA is a list of directories containing data files -# INCLUDES is a list of directories containing header files -#--------------------------------------------------------------------------------- -TARGET := $(notdir $(CURDIR)) -BUILD := build -SOURCES := src -DATA := data -INCLUDES := include - -#--------------------------------------------------------------------------------- -# options for code generation -#--------------------------------------------------------------------------------- -ARCH := -march=armv8-a -mtune=cortex-a57 -mgeneral-regs-only #<- important - -CFLAGS := \ - -g \ - -gdwarf-4 \ - -Os \ - -ffunction-sections \ - -fdata-sections \ - -fomit-frame-pointer \ - -fno-inline \ - -std=gnu11 \ - -Werror \ - -Wall \ - -Wno-array-bounds \ - -Wno-stringop-overflow \ - -Wno-stringop-overread \ - $(ARCH) $(DEFINES) - -CFLAGS += $(INCLUDE) - -CXXFLAGS := $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11 - -ASFLAGS := -g -gdwarf-4 $(ARCH) -LDFLAGS = -specs=$(TOPDIR)/linker.specs -g -gdwarf-4 $(ARCH) -Wl,-Map,$(notdir $*.map) - -LIBS := - -#--------------------------------------------------------------------------------- -# list of directories containing libraries, this must be the top level containing -# include and lib -#--------------------------------------------------------------------------------- -LIBDIRS := - - -#--------------------------------------------------------------------------------- -# no real need to edit anything past this point unless you need to add additional -# rules for different file extensions -#--------------------------------------------------------------------------------- -ifneq ($(BUILD),$(notdir $(CURDIR))) -#--------------------------------------------------------------------------------- - -export OUTPUT := $(CURDIR)/$(TARGET) -export TOPDIR := $(CURDIR) - -export VPATH := $(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \ - $(foreach dir,$(DATA),$(CURDIR)/$(dir)) - -export DEPSDIR := $(CURDIR)/$(BUILD) - -CFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c))) -CPPFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp))) -SFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s))) -BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) - -#--------------------------------------------------------------------------------- -# use CXX for linking C++ projects, CC for standard C -#--------------------------------------------------------------------------------- -ifeq ($(strip $(CPPFILES)),) -#--------------------------------------------------------------------------------- - export LD := $(CC) -#--------------------------------------------------------------------------------- -else -#--------------------------------------------------------------------------------- - export LD := $(CXX) -#--------------------------------------------------------------------------------- -endif -#--------------------------------------------------------------------------------- - -export OFILES_BIN := $(addsuffix .o,$(BINFILES)) -export OFILES_SRC := $(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o) -export OFILES := $(OFILES_BIN) $(OFILES_SRC) -export HFILES_BIN := $(addsuffix .h,$(subst .,_,$(BINFILES))) - -export INCLUDE := $(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \ - $(foreach dir,$(LIBDIRS),-I$(dir)/include) \ - -I$(CURDIR)/$(BUILD) - -export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib) - -.PHONY: $(BUILD) clean all - -#--------------------------------------------------------------------------------- -all: $(BUILD) - -$(BUILD): - @[ -d $@ ] || mkdir -p $@ - @$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile - -#--------------------------------------------------------------------------------- -clean: - @echo clean ... - @rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf - - -#--------------------------------------------------------------------------------- -else -.PHONY: all - -DEPENDS := $(OFILES:.o=.d) - -#--------------------------------------------------------------------------------- -# main targets -#--------------------------------------------------------------------------------- -all : $(OUTPUT).bin - -$(OUTPUT).bin : $(OUTPUT).elf - $(OBJCOPY) -S -O binary $< $@ - @echo built ... $(notdir $@) - -$(OUTPUT).elf : $(OFILES) - -%.elf: $(OFILES) - @echo linking $(notdir $@) - @$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@ - @$(NM) -CSn $@ > $(notdir $*.lst) - -$(OFILES_SRC) : $(HFILES_BIN) - -#--------------------------------------------------------------------------------- -# you need a rule like this for each extension you use as binary data -#--------------------------------------------------------------------------------- -%.bin.o : %.bin -#--------------------------------------------------------------------------------- - @echo $(notdir $<) - @$(bin2o) - --include $(DEPENDS) - -#--------------------------------------------------------------------------------------- -endif -#--------------------------------------------------------------------------------------- diff --git a/sept/sept-secondary/key_derivation/linker.ld b/sept/sept-secondary/key_derivation/linker.ld deleted file mode 100644 index 480bad8d9..000000000 --- a/sept/sept-secondary/key_derivation/linker.ld +++ /dev/null @@ -1,17 +0,0 @@ -OUTPUT_ARCH(aarch64) - -ENTRY(_start) -SECTIONS -{ - . = 0x4003D000; - - __start__ = ABSOLUTE(.); - - .text : ALIGN(4) { *(.text.start) *(.text*); . = ALIGN(4); } - .rodata : ALIGN(4) { *(.rodata*); . = ALIGN(4); } - .bss : ALIGN(8) { __bss_start__ = .; *(.bss* COMMON); . = ALIGN(8); __bss_end__ = .; } - - . = ALIGN(4); - - __end__ = ABSOLUTE(.); -} \ No newline at end of file diff --git a/sept/sept-secondary/key_derivation/linker.specs b/sept/sept-secondary/key_derivation/linker.specs deleted file mode 100644 index 300990418..000000000 --- a/sept/sept-secondary/key_derivation/linker.specs +++ /dev/null @@ -1,7 +0,0 @@ -%rename link old_link - -*link: -%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections - -*startfile: -crti%O%s crtbegin%O%s diff --git a/sept/sept-secondary/key_derivation/src/key_derivation.c b/sept/sept-secondary/key_derivation/src/key_derivation.c deleted file mode 100644 index bc065139f..000000000 --- a/sept/sept-secondary/key_derivation/src/key_derivation.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include "pmc.h" -#include "se.h" -#include "utils.h" - -#define AL16 __attribute__((aligned(16))) - -#define DERIVATION_ID_MAX 2 - -static const uint8_t AL16 keyblob_seed_00[0x10] = { - 0xDF, 0x20, 0x6F, 0x59, 0x44, 0x54, 0xEF, 0xDC, 0x70, 0x74, 0x48, 0x3B, 0x0D, 0xED, 0x9F, 0xD3 -}; - -static const uint8_t AL16 masterkey_seed[0x10] = { - 0xD8, 0xA2, 0x41, 0x0A, 0xC6, 0xC5, 0x90, 0x01, 0xC6, 0x1D, 0x6A, 0x26, 0x7C, 0x51, 0x3F, 0x3C -}; - -static const uint8_t AL16 devicekey_seed[0x10] = { - 0x4F, 0x02, 0x5F, 0x0E, 0xB6, 0x6D, 0x11, 0x0E, 0xDC, 0x32, 0x7D, 0x41, 0x86, 0xC2, 0xF4, 0x78 -}; - -static const uint8_t AL16 devicekey_4x_seed[0x10] = { - 0x0C, 0x91, 0x09, 0xDB, 0x93, 0x93, 0x07, 0x81, 0x07, 0x3C, 0xC4, 0x16, 0x22, 0x7C, 0x6C, 0x28 -}; - -static const uint8_t AL16 masterkey_4x_seed[0x10] = { - 0x2D, 0xC1, 0xF4, 0x8D, 0xF3, 0x5B, 0x69, 0x33, 0x42, 0x10, 0xAC, 0x65, 0xDA, 0x90, 0x46, 0x66 -}; - -static const uint8_t AL16 zeroes[0x10] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -/* Note: 9.0.0 did not change the TSEC firmware. Thus, the root key is the same. */ -/* To avoid distribution of more and more sept binaries, we will simply derive the 9.0.0 master key */ -/* on 8.1.0 and 9.0.0. Exosphere supports this already with no issues. */ - -static const uint8_t AL16 master_kek_seeds[DERIVATION_ID_MAX][0x10] = { - {0x9A, 0x3E, 0xA9, 0xAB, 0xFD, 0x56, 0x46, 0x1C, 0x9B, 0xF6, 0x48, 0x7F, 0x5C, 0xFA, 0x09, 0x5C}, - /* 8.1.0: {0xDE, 0xDC, 0xE3, 0x39, 0x30, 0x88, 0x16, 0xF8, 0xAE, 0x97, 0xAD, 0xEC, 0x64, 0x2D, 0x41, 0x41}, */ - /* 9.0.0: {0x1A, 0xEC, 0x11, 0x82, 0x2B, 0x32, 0x38, 0x7A, 0x2B, 0xED, 0xBA, 0x01, 0x47, 0x7E, 0x3B, 0x67}, */ - /* 9.1.0: {0x30, 0x3F, 0x02, 0x7E, 0xD8, 0x38, 0xEC, 0xD7, 0x93, 0x25, 0x34, 0xB5, 0x30, 0xEB, 0xCA, 0x7A}, */ - {0x84, 0x67, 0xB6, 0x7F, 0x13, 0x11, 0xAE, 0xE6, 0x58, 0x9B, 0x19, 0xAF, 0x13, 0x6C, 0x80, 0x7A}, -}; - -static const uint8_t AL16 master_devkey_seeds[DERIVATION_ID_MAX][0x10] = { - {0x8F, 0x77, 0x5A, 0x96, 0xB0, 0x94, 0xFD, 0x8D, 0x28, 0xE4, 0x19, 0xC8, 0x16, 0x1C, 0xDB, 0x3D}, - /* 8.1.0: {0x67, 0x62, 0xD4, 0x8E, 0x55, 0xCF, 0xFF, 0x41, 0x31, 0x15, 0x3B, 0x24, 0x0C, 0x7C, 0x07, 0xAE}, */ - /* 9.0.0: {0x4A, 0xC3, 0x4E, 0x14, 0x8B, 0x96, 0x4A, 0xD5, 0xD4, 0x99, 0x73, 0xC4, 0x45, 0xAB, 0x8B, 0x49}, */ - /* 9.1.0: {0x14, 0xB8, 0x74, 0x12, 0xCB, 0xBD, 0x0B, 0x8F, 0x20, 0xFB, 0x30, 0xDA, 0x27, 0xE4, 0x58, 0x94}, */ - {0xAA, 0xFD, 0xBC, 0xBB, 0x25, 0xC3, 0xA4, 0xEF, 0xE3, 0xEE, 0x58, 0x53, 0xB7, 0xF8, 0xDD, 0xD6}, -}; - -static const uint8_t AL16 master_devkey_vectors[DERIVATION_ID_MAX][0x10] = { - {0xD8, 0xD3, 0x67, 0x4F, 0xF3, 0xA2, 0xA4, 0x4E, 0xE4, 0x04, 0x37, 0xC2, 0xD9, 0xCF, 0x41, 0x6F}, - /* 8.1.0: {0x72, 0xD0, 0xAD, 0xEB, 0xE1, 0xF6, 0x35, 0x90, 0xB4, 0x43, 0xCC, 0x4B, 0xC4, 0xDC, 0x88, 0x0A}, */ - /* 9.0.0: {0x8B, 0xD6, 0x13, 0x2F, 0xC3, 0x4D, 0x53, 0x2D, 0x10, 0xA1, 0x63, 0x85, 0x49, 0x2B, 0xCF, 0x3F}, */ - /* 9.1.0: {0xA8, 0x58, 0x05, 0x8D, 0xDD, 0x9A, 0xA0, 0x2F, 0x01, 0x62, 0x4A, 0x6B, 0xC6, 0x77, 0xE9, 0x86}, */ - {0x95, 0x7E, 0x99, 0xB4, 0x4B, 0xDE, 0xA0, 0xA3, 0x9A, 0x51, 0xF0, 0x32, 0xB7, 0xDF, 0x89, 0x0D}, -}; - -void derive_keys(void) { - /* Set mailbox. */ - volatile uint32_t *mailbox = (volatile uint32_t *)0x4003FF00; - const uint32_t derivation_id = *((volatile uint32_t *)0x4003E800); - - if (derivation_id < DERIVATION_ID_MAX) { - uint8_t *enc_se_state = (uint8_t *)0x4003E000; - - uint32_t AL16 work_buffer[4]; - - /* Derive Keyblob Key 00. */ - se_aes_ecb_decrypt_block(0xC, work_buffer, 0x10, keyblob_seed_00, 0x10); - decrypt_data_into_keyslot(0xF, 0xE, work_buffer, 0x10); - - /* Derive master kek. */ - decrypt_data_into_keyslot(0xE, 0xD, master_kek_seeds[derivation_id], 0x10); - - /* Clear the copy of the root key inside the SE. */ - clear_aes_keyslot(0xD); - - /* Derive master key, device master key. */ - decrypt_data_into_keyslot(0xC, 0xE, masterkey_seed, 0x10); - decrypt_data_into_keyslot(0xE, 0xE, masterkey_4x_seed, 0x10); - clear_aes_keyslot(0xD); - - /* Derive device keys. */ - decrypt_data_into_keyslot(0xA, 0xF, devicekey_4x_seed, 0x10); - decrypt_data_into_keyslot(0xF, 0xF, devicekey_seed, 0x10); - clear_aes_keyslot(0xD); - - /* Derive firmware specific device key. */ - se_aes_ecb_decrypt_block(0xA, work_buffer, 0x10, master_devkey_seeds[derivation_id], 0x10); - decrypt_data_into_keyslot(0xE, 0xE, work_buffer, 0x10); - clear_aes_keyslot(0xD); - - /* Test against a vector. */ - for (size_t i = 0; i < 4; i++) { - work_buffer[i] = 0; - } - if (memcmp(work_buffer, zeroes, 0x10) != 0) { - clear_aes_keyslot(0xE); - clear_aes_keyslot(0xD); - clear_aes_keyslot(0xC); - clear_aes_keyslot(0xA); - clear_aes_keyslot(0xF); - generic_panic(); - } - - se_aes_ecb_decrypt_block(0xE, work_buffer, 0x10, master_devkey_vectors[derivation_id], 0x10); - - if (memcmp(work_buffer, zeroes, 0x10) == 0) { - clear_aes_keyslot(0xE); - clear_aes_keyslot(0xD); - clear_aes_keyslot(0xC); - clear_aes_keyslot(0xA); - clear_aes_keyslot(0xF); - generic_panic(); - } - - /* Clear work buffer. */ - for (size_t i = 0; i < 4; i++) { - work_buffer[i] = 0xCCCCCCCC; - } - - /* Save context for real. */ - se_set_in_context_save_mode(true); - se_save_context(KEYSLOT_SWITCH_SRKGENKEY, KEYSLOT_SWITCH_RNGKEY, enc_se_state); - se_set_in_context_save_mode(false); - } - - /* Clear all keyslots. */ - for (size_t i = 0; i < 0x10; i++) { - clear_aes_keyslot(i); - } - - *mailbox = 7; - while (1) { /* Wait for sept to handle the rest. */ } -} diff --git a/sept/sept-secondary/key_derivation/src/key_derivation.h b/sept/sept-secondary/key_derivation/src/key_derivation.h deleted file mode 100644 index a74df7613..000000000 --- a/sept/sept-secondary/key_derivation/src/key_derivation.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef SEPT_KEYDERIVATION_H -#define SEPT_KEYDERIVATION_H - -#include -#include -#include - -void derive_keys(void); - -#endif diff --git a/sept/sept-secondary/key_derivation/src/pmc.h b/sept/sept-secondary/key_derivation/src/pmc.h deleted file mode 100644 index a287d85e7..000000000 --- a/sept/sept-secondary/key_derivation/src/pmc.h +++ /dev/null @@ -1,713 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_PMC_H -#define FUSEE_PMC_H - -#include - -#define PMC_BASE 0x7000E400 -#define MAKE_PMC_REG(n) MAKE_REG32(PMC_BASE + n) - -#define PMC_CONTROL_SDMMC1 (1 << 12) -#define PMC_CONTROL_SDMMC3 (1 << 13) -#define PMC_CONTROL_SDMMC4 (1 << 14) - -#define APBDEV_PMC_CONTROL MAKE_PMC_REG(0x00) -#define APBDEV_PM_0 MAKE_PMC_REG(0x14) -#define APBDEV_PMC_DPD_ENABLE_0 MAKE_PMC_REG(0x24) -#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x30) -#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x38) -#define APBDEV_PMC_NO_IOPOWER_0 MAKE_PMC_REG(0x44) -#define APBDEV_PMC_SCRATCH0_0 MAKE_PMC_REG(0x50) -#define APBDEV_PMC_SCRATCH1_0 MAKE_PMC_REG(0x54) -#define APBDEV_PMC_SCRATCH20_0 MAKE_PMC_REG(0xA0) -#define APBDEV_PMC_PWR_DET_VAL_0 MAKE_PMC_REG(0xE4) -#define APBDEV_PMC_DDR_PWR_0 MAKE_PMC_REG(0xE8) -#define APBDEV_PMC_CRYPTO_OP_0 MAKE_PMC_REG(0xF4) -#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_PMC_REG(0x168) -#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4) -#define APBDEV_PMC_RST_STATUS_0 MAKE_PMC_REG(0x1B4) -#define APBDEV_PMC_IO_DPD_REQ_0 MAKE_PMC_REG(0x1B8) -#define APBDEV_PMC_IO_DPD2_REQ_0 MAKE_PMC_REG(0x1C0) -#define APBDEV_PMC_VDDP_SEL_0 MAKE_PMC_REG(0x1CC) -#define APBDEV_PMC_SCRATCH49_0 MAKE_PMC_REG(0x244) -#define APBDEV_PMC_TSC_MULT_0 MAKE_PMC_REG(0x2B4) -#define APBDEV_PMC_REG_SHORT_0 MAKE_PMC_REG(0x2CC) -#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8) -#define APBDEV_PMC_SECURE_SCRATCH21_0 MAKE_PMC_REG(0x334) -#define APBDEV_PMC_SECURE_SCRATCH32_0 MAKE_PMC_REG(0x360) -#define APBDEV_PMC_SECURE_SCRATCH49_0 MAKE_PMC_REG(0x3A4) -#define APBDEV_PMC_CNTRL2_0 MAKE_PMC_REG(0x440) -#define APBDEV_PMC_IO_DPD4_REQ_0 MAKE_PMC_REG(0x464) -#define APBDEV_PMC_UTMIP_PAD_CFG1_0 MAKE_PMC_REG(0x4C4) -#define APBDEV_PMC_UTMIP_PAD_CFG3_0 MAKE_PMC_REG(0x4CC) -#define APBDEV_PMC_DDR_CNTRL_0 MAKE_PMC_REG(0x4E4) -#define APBDEV_PMC_SCRATCH43_0 MAKE_PMC_REG(0x22C) -#define APBDEV_PMC_SCRATCH188_0 MAKE_PMC_REG(0x810) -#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818) -#define APBDEV_PMC_SCRATCH200_0 MAKE_PMC_REG(0x840) - -#define APBDEV_PMC_SCRATCH45_0 MAKE_PMC_REG(0x234) -#define APBDEV_PMC_SCRATCH46_0 MAKE_PMC_REG(0x238) -#define APBDEV_PMC_SCRATCH33_0 MAKE_PMC_REG(0x120) -#define APBDEV_PMC_SCRATCH40_0 MAKE_PMC_REG(0x13C) - -/* Power Management Controller (APBDEV_PMC_) regs */ -typedef struct { - uint32_t cntrl; /* _CNTRL_0, 0x00 */ - uint32_t sec_disable; /* _SEC_DISABLE_0, 0x04 */ - uint32_t pmc_swrst; /* _PMC_SWRST_0, 0x08 */ - uint32_t wake_mask; /* _WAKE_MASK_0, 0x0c */ - uint32_t wake_lvl; /* _WAKE_LVL_0, 0x10 */ - uint32_t wake_status; /* _WAKE_STATUS_0, 0x14 */ - uint32_t sw_wake_status; /* _SW_WAKE_STATUS_0, 0x18 */ - uint32_t dpd_pads_oride; /* _DPD_PADS_ORIDE_0, 0x1c */ - uint32_t dpd_sample; /* _DPD_SAMPLE_0, 0x20 */ - uint32_t dpd_enable; /* _DPD_ENABLE_0, 0x24 */ - uint32_t pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, 0x28 */ - uint32_t clamp_status; /* _CLAMP_STATUS_0, 0x2c */ - uint32_t pwrgate_toggle; /* _PWRGATE_TOGGLE_0, 0x30 */ - uint32_t remove_clamping; /* _REMOVE_CLAMPING_0, 0x34 */ - uint32_t pwrgate_status; /* _PWRGATE_STATUS_0, 0x38 */ - uint32_t pwrgood_timer; /* _PWRGOOD_TIMER_0, 0x3c */ - uint32_t blink_timer; /* _BLINK_TIMER_0, 0x40 */ - uint32_t no_iopower; /* _NO_IOPOWER_0, 0x44 */ - uint32_t pwr_det; /* _PWR_DET_0, 0x48 */ - uint32_t pwr_det_latch; /* _PWR_DET_LATCH_0, 0x4c */ - uint32_t scratch0; /* _SCRATCH0_0, 0x50 */ - uint32_t scratch1; /* _SCRATCH1_0, 0x54 */ - uint32_t scratch2; /* _SCRATCH2_0, 0x58 */ - uint32_t scratch3; /* _SCRATCH3_0, 0x5c */ - uint32_t scratch4; /* _SCRATCH4_0, 0x60 */ - uint32_t scratch5; /* _SCRATCH5_0, 0x64 */ - uint32_t scratch6; /* _SCRATCH6_0, 0x68 */ - uint32_t scratch7; /* _SCRATCH7_0, 0x6c */ - uint32_t scratch8; /* _SCRATCH8_0, 0x70 */ - uint32_t scratch9; /* _SCRATCH9_0, 0x74 */ - uint32_t scratch10; /* _SCRATCH10_0, 0x78 */ - uint32_t scratch11; /* _SCRATCH11_0, 0x7c */ - uint32_t scratch12; /* _SCRATCH12_0, 0x80 */ - uint32_t scratch13; /* _SCRATCH13_0, 0x84 */ - uint32_t scratch14; /* _SCRATCH14_0, 0x88 */ - uint32_t scratch15; /* _SCRATCH15_0, 0x8c */ - uint32_t scratch16; /* _SCRATCH16_0, 0x90 */ - uint32_t scratch17; /* _SCRATCH17_0, 0x94 */ - uint32_t scratch18; /* _SCRATCH18_0, 0x98 */ - uint32_t scratch19; /* _SCRATCH19_0, 0x9c */ - uint32_t scratch20; /* _SCRATCH20_0, 0xa0 */ - uint32_t scratch21; /* _SCRATCH21_0, 0xa4 */ - uint32_t scratch22; /* _SCRATCH22_0, 0xa8 */ - uint32_t scratch23; /* _SCRATCH23_0, 0xac */ - uint32_t secure_scratch0; /* _SECURE_SCRATCH0_0, 0xb0 */ - uint32_t secure_scratch1; /* _SECURE_SCRATCH1_0, 0xb4 */ - uint32_t secure_scratch2; /* _SECURE_SCRATCH2_0, 0xb8 */ - uint32_t secure_scratch3; /* _SECURE_SCRATCH3_0, 0xbc */ - uint32_t secure_scratch4; /* _SECURE_SCRATCH4_0, 0xc0 */ - uint32_t secure_scratch5; /* _SECURE_SCRATCH5_0, 0xc4 */ - uint32_t cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, 0xc8 */ - uint32_t cpupwroff_timer; /* _CPUPWROFF_TIMER_0, 0xcc */ - uint32_t pg_mask; /* _PG_MASK_0, 0xd0 */ - uint32_t pg_mask_1; /* _PG_MASK_1_0, 0xd4 */ - uint32_t auto_wake_lvl; /* _AUTO_WAKE_LVL_0, 0xd8 */ - uint32_t auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, 0xdc */ - uint32_t wake_delay; /* _WAKE_DELAY_0, 0xe0 */ - uint32_t pwr_det_val; /* _PWR_DET_VAL_0, 0xe4 */ - uint32_t ddr_pwr; /* _DDR_PWR_0, 0xe8 */ - uint32_t usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, 0xec */ - uint32_t usb_ao; /* _USB_AO_0, 0xf0 */ - uint32_t crypto_op; /* _CRYPTO_OP_0, 0xf4 */ - uint32_t pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, 0xf8 */ - uint32_t scratch24; /* _SCRATCH24_0, 0xfc */ - uint32_t scratch25; /* _SCRATCH25_0, 0x100 */ - uint32_t scratch26; /* _SCRATCH26_0, 0x104 */ - uint32_t scratch27; /* _SCRATCH27_0, 0x108 */ - uint32_t scratch28; /* _SCRATCH28_0, 0x10c */ - uint32_t scratch29; /* _SCRATCH29_0, 0x110 */ - uint32_t scratch30; /* _SCRATCH30_0, 0x114 */ - uint32_t scratch31; /* _SCRATCH31_0, 0x118 */ - uint32_t scratch32; /* _SCRATCH32_0, 0x11c */ - uint32_t scratch33; /* _SCRATCH33_0, 0x120 */ - uint32_t scratch34; /* _SCRATCH34_0, 0x124 */ - uint32_t scratch35; /* _SCRATCH35_0, 0x128 */ - uint32_t scratch36; /* _SCRATCH36_0, 0x12c */ - uint32_t scratch37; /* _SCRATCH37_0, 0x130 */ - uint32_t scratch38; /* _SCRATCH38_0, 0x134 */ - uint32_t scratch39; /* _SCRATCH39_0, 0x138 */ - uint32_t scratch40; /* _SCRATCH40_0, 0x13c */ - uint32_t scratch41; /* _SCRATCH41_0, 0x140 */ - uint32_t scratch42; /* _SCRATCH42_0, 0x144 */ - uint32_t bondout_mirror0; /* _BONDOUT_MIRROR0_0, 0x148 */ - uint32_t bondout_mirror1; /* _BONDOUT_MIRROR1_0, 0x14c */ - uint32_t bondout_mirror2; /* _BONDOUT_MIRROR2_0, 0x150 */ - uint32_t sys_33v_en; /* _SYS_33V_EN_0, 0x154 */ - uint32_t bondout_mirror_access; /* _BONDOUT_MIRROR_ACCESS_0, 0x158 */ - uint32_t gate; /* _GATE_0, 0x15c */ - uint32_t wake2_mask; /* _WAKE2_MASK_0, 0x160 */ - uint32_t wake2_lvl; /* _WAKE2_LVL_0, 0x164 */ - uint32_t wake2_status; /* _WAKE2_STATUS_0, 0x168 */ - uint32_t sw_wake2_status; /* _SW_WAKE2_STATUS_0, 0x16c */ - uint32_t auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, 0x170 */ - uint32_t pg_mask_2; /* _PG_MASK_2_0, 0x174 */ - uint32_t pg_mask_ce1; /* _PG_MASK_CE1_0, 0x178 */ - uint32_t pg_mask_ce2; /* _PG_MASK_CE2_0, 0x17c */ - uint32_t pg_mask_ce3; /* _PG_MASK_CE3_0, 0x180 */ - uint32_t pwrgate_timer_ce_0; /* _PWRGATE_TIMER_CE_0_0, 0x184 */ - uint32_t pwrgate_timer_ce_1; /* _PWRGATE_TIMER_CE_1_0, 0x188 */ - uint32_t pwrgate_timer_ce_2; /* _PWRGATE_TIMER_CE_2_0, 0x18c */ - uint32_t pwrgate_timer_ce_3; /* _PWRGATE_TIMER_CE_3_0, 0x190 */ - uint32_t pwrgate_timer_ce_4; /* _PWRGATE_TIMER_CE_4_0, 0x194 */ - uint32_t pwrgate_timer_ce_5; /* _PWRGATE_TIMER_CE_5_0, 0x198 */ - uint32_t pwrgate_timer_ce_6; /* _PWRGATE_TIMER_CE_6_0, 0x19c */ - uint32_t pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, 0x1a0 */ - uint32_t osc_edpd_over; /* _OSC_EDPD_OVER_0, 0x1a4 */ - uint32_t clk_out_cntrl; /* _CLK_OUT_CNTRL_0, 0x1a8 */ - uint32_t sata_pwrgt; /* _SATA_PWRGT_0, 0x1ac */ - uint32_t sensor_ctrl; /* _SENSOR_CTRL_0, 0x1b0 */ - uint32_t rst_status; /* _RST_STATUS_0, 0x1b4 */ - uint32_t io_dpd_req; /* _IO_DPD_REQ_0, 0x1b8 */ - uint32_t io_dpd_status; /* _IO_DPD_STATUS_0, 0x1bc */ - uint32_t io_dpd2_req; /* _IO_DPD2_REQ_0, 0x1c0 */ - uint32_t io_dpd2_status; /* _IO_DPD2_STATUS_0, 0x1c4 */ - uint32_t sel_dpd_tim; /* _SEL_DPD_TIM_0, 0x1c8 */ - uint32_t vddp_sel; /* _VDDP_SEL_0, 0x1cc */ - uint32_t ddr_cfg; /* _DDR_CFG_0, 0x1d0 */ - uint32_t _0x1d4[2]; - uint32_t pllm_wb0_override_freq; /* _PLLM_WB0_OVERRIDE_FREQ_0, 0x1dc */ - uint32_t _0x1e0; - uint32_t pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, 0x1e4 */ - uint32_t dsi_sel_dpd; /* _DSI_SEL_DPD_0, 0x1e8 */ - uint32_t utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, 0x1ec */ - uint32_t utmip_uhsic_saved_state; /* _UTMIP_UHSIC_SAVED_STATE_0, 0x1f0 */ - uint32_t _0x1f4; - uint32_t utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, 0x1f8 */ - uint32_t utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, 0x1fc */ - uint32_t utmip_uhsic_sleepwalk_cfg; /* _UTMIP_UHSIC_SLEEPWALK_CFG_0, 0x200 */ - uint32_t utmip_sleepwalk_p0; /* _UTMIP_SLEEPWALK_P0_0, 0x204 */ - uint32_t utmip_sleepwalk_p1; /* _UTMIP_SLEEPWALK_P1_0, 0x208 */ - uint32_t utmip_sleepwalk_p2; /* _UTMIP_SLEEPWALK_P2_0, 0x20c */ - uint32_t uhsic_sleepwalk_p0; /* _UHSIC_SLEEPWALK_P0_0, 0x210 */ - uint32_t utmip_uhsic_status; /* _UTMIP_UHSIC_STATUS_0, 0x214 */ - uint32_t utmip_uhsic_fake; /* _UTMIP_UHSIC_FAKE_0, 0x218 */ - uint32_t bondout_mirror3; /* _BONDOUT_MIRROR3_0, 0x21c */ - uint32_t bondout_mirror4; /* _BONDOUT_MIRROR4_0, 0x220 */ - uint32_t secure_scratch6; /* _SECURE_SCRATCH6_0, 0x224 */ - uint32_t secure_scratch7; /* _SECURE_SCRATCH7_0, 0x228 */ - uint32_t scratch43; /* _SCRATCH43_0, 0x22c */ - uint32_t scratch44; /* _SCRATCH44_0, 0x230 */ - uint32_t scratch45; /* _SCRATCH45_0, 0x234 */ - uint32_t scratch46; /* _SCRATCH46_0, 0x238 */ - uint32_t scratch47; /* _SCRATCH47_0, 0x23c */ - uint32_t scratch48; /* _SCRATCH48_0, 0x240 */ - uint32_t scratch49; /* _SCRATCH49_0, 0x244 */ - uint32_t scratch50; /* _SCRATCH50_0, 0x248 */ - uint32_t scratch51; /* _SCRATCH51_0, 0x24c */ - uint32_t scratch52; /* _SCRATCH52_0, 0x250 */ - uint32_t scratch53; /* _SCRATCH53_0, 0x254 */ - uint32_t scratch54; /* _SCRATCH54_0, 0x258 */ - uint32_t scratch55; /* _SCRATCH55_0, 0x25c */ - uint32_t scratch0_eco; /* _SCRATCH0_ECO_0, 0x260 */ - uint32_t por_dpd_ctrl; /* _POR_DPD_CTRL_0, 0x264 */ - uint32_t scratch2_eco; /* _SCRATCH2_ECO_0, 0x268 */ - uint32_t utmip_uhsic_line_wakeup; /* _UTMIP_UHSIC_LINE_WAKEUP_0, 0x26c */ - uint32_t utmip_bias_master_cntrl; /* _UTMIP_BIAS_MASTER_CNTRL_0, 0x270 */ - uint32_t utmip_master_config; /* _UTMIP_MASTER_CONFIG_0, 0x274 */ - uint32_t td_pwrgate_inter_part_timer; /* _TD_PWRGATE_INTER_PART_TIMER_0, 0x278 */ - uint32_t utmip_uhsic2_triggers; /* _UTMIP_UHSIC2_TRIGGERS_0, 0x27c */ - uint32_t utmip_uhsic2_saved_state; /* _UTMIP_UHSIC2_SAVED_STATE_0, 0x280 */ - uint32_t utmip_uhsic2_sleep_cfg; /* _UTMIP_UHSIC2_SLEEP_CFG_0, 0x284 */ - uint32_t utmip_uhsic2_sleepwalk_cfg; /* _UTMIP_UHSIC2_SLEEPWALK_CFG_0, 0x288 */ - uint32_t uhsic2_sleepwalk_p1; /* _UHSIC2_SLEEPWALK_P1_0, 0x28c */ - uint32_t utmip_uhsic2_status; /* _UTMIP_UHSIC2_STATUS_0, 0x290 */ - uint32_t utmip_uhsic2_fake; /* _UTMIP_UHSIC2_FAKE_0, 0x294 */ - uint32_t utmip_uhsic2_line_wakeup; /* _UTMIP_UHSIC2_LINE_WAKEUP_0, 0x298 */ - uint32_t utmip_master2_config; /* _UTMIP_MASTER2_CONFIG_0, 0x29c */ - uint32_t utmip_uhsic_rpd_cfg; /* _UTMIP_UHSIC_RPD_CFG_0, 0x2a0 */ - uint32_t pg_mask_ce0; /* _PG_MASK_CE0_0, 0x2a4 */ - uint32_t pg_mask_3; /* _PG_MASK_3_0, 0x2a8 */ - uint32_t pg_mask_4; /* _PG_MASK_4_0, 0x2ac */ - uint32_t pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2_0, 0x2b0 */ - uint32_t tsc_mult; /* _TSC_MULT_0, 0x2b4 */ - uint32_t cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, 0x2b8 */ - uint32_t glb_amap_cfg; /* _GLB_AMAP_CFG_0, 0x2bc */ - uint32_t sticky_bits; /* _STICKY_BITS_0, 0x2c0 */ - uint32_t sec_disable2; /* _SEC_DISABLE2_0, 0x2c4 */ - uint32_t weak_bias; /* _WEAK_BIAS_0, 0x2c8 */ - uint32_t reg_short; /* _REG_SHORT_0, 0x2cc */ - uint32_t pg_mask_andor; /* _PG_MASK_ANDOR_0, 0x2d0 */ - uint32_t gpu_rg_cntrl; /* _GPU_RG_CNTRL_0, 0x2d4 */ - uint32_t sec_disable3; /* _SEC_DISABLE3_0, 0x2d8 */ - uint32_t pg_mask_5; /* _PG_MASK_5_0, 0x2dc */ - uint32_t pg_mask_6; /* _PG_MASK_6_0, 0x2e0 */ - uint32_t _0x2e4[7]; - uint32_t secure_scratch8; /* _SECURE_SCRATCH8_0, 0x300 */ - uint32_t secure_scratch9; /* _SECURE_SCRATCH9_0, 0x304 */ - uint32_t secure_scratch10; /* _SECURE_SCRATCH10_0, 0x308 */ - uint32_t secure_scratch11; /* _SECURE_SCRATCH11_0, 0x30c */ - uint32_t secure_scratch12; /* _SECURE_SCRATCH12_0, 0x310 */ - uint32_t secure_scratch13; /* _SECURE_SCRATCH13_0, 0x314 */ - uint32_t secure_scratch14; /* _SECURE_SCRATCH14_0, 0x318 */ - uint32_t secure_scratch15; /* _SECURE_SCRATCH15_0, 0x31c */ - uint32_t secure_scratch16; /* _SECURE_SCRATCH16_0, 0x320 */ - uint32_t secure_scratch17; /* _SECURE_SCRATCH17_0, 0x324 */ - uint32_t secure_scratch18; /* _SECURE_SCRATCH18_0, 0x328 */ - uint32_t secure_scratch19; /* _SECURE_SCRATCH19_0, 0x32c */ - uint32_t secure_scratch20; /* _SECURE_SCRATCH20_0, 0x330 */ - uint32_t secure_scratch21; /* _SECURE_SCRATCH21_0, 0x334 */ - uint32_t secure_scratch22; /* _SECURE_SCRATCH22_0, 0x338 */ - uint32_t secure_scratch23; /* _SECURE_SCRATCH23_0, 0x33c */ - uint32_t secure_scratch24; /* _SECURE_SCRATCH24_0, 0x340 */ - uint32_t secure_scratch25; /* _SECURE_SCRATCH25_0, 0x344 */ - uint32_t secure_scratch26; /* _SECURE_SCRATCH26_0, 0x348 */ - uint32_t secure_scratch27; /* _SECURE_SCRATCH27_0, 0x34c */ - uint32_t secure_scratch28; /* _SECURE_SCRATCH28_0, 0x350 */ - uint32_t secure_scratch29; /* _SECURE_SCRATCH29_0, 0x354 */ - uint32_t secure_scratch30; /* _SECURE_SCRATCH30_0, 0x358 */ - uint32_t secure_scratch31; /* _SECURE_SCRATCH31_0, 0x35c */ - uint32_t secure_scratch32; /* _SECURE_SCRATCH32_0, 0x360 */ - uint32_t secure_scratch33; /* _SECURE_SCRATCH33_0, 0x364 */ - uint32_t secure_scratch34; /* _SECURE_SCRATCH34_0, 0x368 */ - uint32_t secure_scratch35; /* _SECURE_SCRATCH35_0, 0x36c */ - uint32_t secure_scratch36; /* _SECURE_SCRATCH36_0, 0x370 */ - uint32_t secure_scratch37; /* _SECURE_SCRATCH37_0, 0x374 */ - uint32_t secure_scratch38; /* _SECURE_SCRATCH38_0, 0x378 */ - uint32_t secure_scratch39; /* _SECURE_SCRATCH39_0, 0x37c */ - uint32_t secure_scratch40; /* _SECURE_SCRATCH40_0, 0x380 */ - uint32_t secure_scratch41; /* _SECURE_SCRATCH41_0, 0x384 */ - uint32_t secure_scratch42; /* _SECURE_SCRATCH42_0, 0x388 */ - uint32_t secure_scratch43; /* _SECURE_SCRATCH43_0, 0x38c */ - uint32_t secure_scratch44; /* _SECURE_SCRATCH44_0, 0x390 */ - uint32_t secure_scratch45; /* _SECURE_SCRATCH45_0, 0x394 */ - uint32_t secure_scratch46; /* _SECURE_SCRATCH46_0, 0x398 */ - uint32_t secure_scratch47; /* _SECURE_SCRATCH47_0, 0x39c */ - uint32_t secure_scratch48; /* _SECURE_SCRATCH48_0, 0x3a0 */ - uint32_t secure_scratch49; /* _SECURE_SCRATCH49_0, 0x3a4 */ - uint32_t secure_scratch50; /* _SECURE_SCRATCH50_0, 0x3a8 */ - uint32_t secure_scratch51; /* _SECURE_SCRATCH51_0, 0x3ac */ - uint32_t secure_scratch52; /* _SECURE_SCRATCH52_0, 0x3b0 */ - uint32_t secure_scratch53; /* _SECURE_SCRATCH53_0, 0x3b4 */ - uint32_t secure_scratch54; /* _SECURE_SCRATCH54_0, 0x3b8 */ - uint32_t secure_scratch55; /* _SECURE_SCRATCH55_0, 0x3bc */ - uint32_t secure_scratch56; /* _SECURE_SCRATCH56_0, 0x3c0 */ - uint32_t secure_scratch57; /* _SECURE_SCRATCH57_0, 0x3c4 */ - uint32_t secure_scratch58; /* _SECURE_SCRATCH58_0, 0x3c8 */ - uint32_t secure_scratch59; /* _SECURE_SCRATCH59_0, 0x3cc */ - uint32_t secure_scratch60; /* _SECURE_SCRATCH60_0, 0x3d0 */ - uint32_t secure_scratch61; /* _SECURE_SCRATCH61_0, 0x3d4 */ - uint32_t secure_scratch62; /* _SECURE_SCRATCH62_0, 0x3d8 */ - uint32_t secure_scratch63; /* _SECURE_SCRATCH63_0, 0x3dc */ - uint32_t secure_scratch64; /* _SECURE_SCRATCH64_0, 0x3e0 */ - uint32_t secure_scratch65; /* _SECURE_SCRATCH65_0, 0x3e4 */ - uint32_t secure_scratch66; /* _SECURE_SCRATCH66_0, 0x3e8 */ - uint32_t secure_scratch67; /* _SECURE_SCRATCH67_0, 0x3ec */ - uint32_t secure_scratch68; /* _SECURE_SCRATCH68_0, 0x3f0 */ - uint32_t secure_scratch69; /* _SECURE_SCRATCH69_0, 0x3f4 */ - uint32_t secure_scratch70; /* _SECURE_SCRATCH70_0, 0x3f8 */ - uint32_t secure_scratch71; /* _SECURE_SCRATCH71_0, 0x3fc */ - uint32_t secure_scratch72; /* _SECURE_SCRATCH72_0, 0x400 */ - uint32_t secure_scratch73; /* _SECURE_SCRATCH73_0, 0x404 */ - uint32_t secure_scratch74; /* _SECURE_SCRATCH74_0, 0x408 */ - uint32_t secure_scratch75; /* _SECURE_SCRATCH75_0, 0x40c */ - uint32_t secure_scratch76; /* _SECURE_SCRATCH76_0, 0x410 */ - uint32_t secure_scratch77; /* _SECURE_SCRATCH77_0, 0x414 */ - uint32_t secure_scratch78; /* _SECURE_SCRATCH78_0, 0x418 */ - uint32_t secure_scratch79; /* _SECURE_SCRATCH79_0, 0x41c */ - uint32_t _0x420[8]; - uint32_t cntrl2; /* _CNTRL2_0, 0x440 */ - uint32_t io_dpd_off_mask; /* _IO_DPD_OFF_MASK_0, 0x444 */ - uint32_t io_dpd2_off_mask; /* _IO_DPD2_OFF_MASK_0, 0x448 */ - uint32_t event_counter; /* _EVENT_COUNTER_0, 0x44c */ - uint32_t fuse_control; /* _FUSE_CONTROL_0, 0x450 */ - uint32_t scratch1_eco; /* _SCRATCH1_ECO_0, 0x454 */ - uint32_t _0x458; - uint32_t io_dpd3_req; /* _IO_DPD3_REQ_0, 0x45c */ - uint32_t io_dpd3_status; /* _IO_DPD3_STATUS_0, 0x460 */ - uint32_t io_dpd4_req; /* _IO_DPD4_REQ_0, 0x464 */ - uint32_t io_dpd4_status; /* _IO_DPD4_STATUS_0, 0x468 */ - uint32_t _0x46c[2]; - uint32_t direct_thermtrip_cfg; /* _DIRECT_THERMTRIP_CFG_0, 0x474 */ - uint32_t tsosc_delay; /* _TSOSC_DELAY_0, 0x478 */ - uint32_t set_sw_clamp; /* _SET_SW_CLAMP_0, 0x47c */ - uint32_t debug_authentication; /* _DEBUG_AUTHENTICATION_0, 0x480 */ - uint32_t aotag_cfg; /* _AOTAG_CFG_0, 0x484 */ - uint32_t aotag_thresh1_cfg; /* _AOTAG_THRESH1_CFG_0, 0x488 */ - uint32_t aotag_thresh2_cfg; /* _AOTAG_THRESH2_CFG_0, 0x48c */ - uint32_t aotag_thresh3_cfg; /* _AOTAG_THRESH3_CFG_0, 0x490 */ - uint32_t aotag_status; /* _AOTAG_STATUS_0, 0x494 */ - uint32_t aotag_security; /* _AOTAG_SECURITY_0, 0x498 */ - uint32_t tsensor_config0; /* _TSENSOR_CONFIG0_0, 0x49c */ - uint32_t tsensor_config1; /* _TSENSOR_CONFIG1_0, 0x4a0 */ - uint32_t tsensor_config2; /* _TSENSOR_CONFIG2_0, 0x4a4 */ - uint32_t tsensor_status0; /* _TSENSOR_STATUS0_0, 0x4a8 */ - uint32_t tsensor_status1; /* _TSENSOR_STATUS1_0, 0x4ac */ - uint32_t tsensor_status2; /* _TSENSOR_STATUS2_0, 0x4b0 */ - uint32_t tsensor_pdiv; /* _TSENSOR_PDIV_0, 0x4b4 */ - uint32_t aotag_intr_en; /* _AOTAG_INTR_EN_0, 0x4b8 */ - uint32_t aotag_intr_dis; /* _AOTAG_INTR_DIS_0, 0x4bc */ - uint32_t utmip_pad_cfg0; /* _UTMIP_PAD_CFG0_0, 0x4c0 */ - uint32_t utmip_pad_cfg1; /* _UTMIP_PAD_CFG1_0, 0x4c4 */ - uint32_t utmip_pad_cfg2; /* _UTMIP_PAD_CFG2_0, 0x4c8 */ - uint32_t utmip_pad_cfg3; /* _UTMIP_PAD_CFG3_0, 0x4cc */ - uint32_t utmip_uhsic_sleep_cfg1; /* _UTMIP_UHSIC_SLEEP_CFG1_0, 0x4d0 */ - uint32_t cc4_hvc_control; /* _CC4_HVC_CONTROL_0, 0x4d4 */ - uint32_t wake_debounce_en; /* _WAKE_DEBOUNCE_EN_0, 0x4d8 */ - uint32_t ramdump_ctl_status; /* _RAMDUMP_CTL_STATUS_0, 0x4dc */ - uint32_t utmip_sleepwalk_p3; /* _UTMIP_SLEEPWALK_P3_0, 0x4e0 */ - uint32_t ddr_cntrl; /* _DDR_CNTRL_0, 0x4e4 */ - uint32_t _0x4e8[50]; - uint32_t sec_disable4; /* _SEC_DISABLE4_0, 0x5b0 */ - uint32_t sec_disable5; /* _SEC_DISABLE5_0, 0x5b4 */ - uint32_t sec_disable6; /* _SEC_DISABLE6_0, 0x5b8 */ - uint32_t sec_disable7; /* _SEC_DISABLE7_0, 0x5bc */ - uint32_t sec_disable8; /* _SEC_DISABLE8_0, 0x5c0 */ - uint32_t sec_disable9; /* _SEC_DISABLE9_0, 0x5c4 */ - uint32_t sec_disable10; /* _SEC_DISABLE10_0, 0x5c8 */ - uint32_t _0x5cc[13]; - uint32_t scratch56; /* _SCRATCH56_0, 0x600 */ - uint32_t scratch57; /* _SCRATCH57_0, 0x604 */ - uint32_t scratch58; /* _SCRATCH58_0, 0x608 */ - uint32_t scratch59; /* _SCRATCH59_0, 0x60c */ - uint32_t scratch60; /* _SCRATCH60_0, 0x610 */ - uint32_t scratch61; /* _SCRATCH61_0, 0x614 */ - uint32_t scratch62; /* _SCRATCH62_0, 0x618 */ - uint32_t scratch63; /* _SCRATCH63_0, 0x61c */ - uint32_t scratch64; /* _SCRATCH64_0, 0x620 */ - uint32_t scratch65; /* _SCRATCH65_0, 0x624 */ - uint32_t scratch66; /* _SCRATCH66_0, 0x628 */ - uint32_t scratch67; /* _SCRATCH67_0, 0x62c */ - uint32_t scratch68; /* _SCRATCH68_0, 0x630 */ - uint32_t scratch69; /* _SCRATCH69_0, 0x634 */ - uint32_t scratch70; /* _SCRATCH70_0, 0x638 */ - uint32_t scratch71; /* _SCRATCH71_0, 0x63c */ - uint32_t scratch72; /* _SCRATCH72_0, 0x640 */ - uint32_t scratch73; /* _SCRATCH73_0, 0x644 */ - uint32_t scratch74; /* _SCRATCH74_0, 0x648 */ - uint32_t scratch75; /* _SCRATCH75_0, 0x64c */ - uint32_t scratch76; /* _SCRATCH76_0, 0x650 */ - uint32_t scratch77; /* _SCRATCH77_0, 0x654 */ - uint32_t scratch78; /* _SCRATCH78_0, 0x658 */ - uint32_t scratch79; /* _SCRATCH79_0, 0x65c */ - uint32_t scratch80; /* _SCRATCH80_0, 0x660 */ - uint32_t scratch81; /* _SCRATCH81_0, 0x664 */ - uint32_t scratch82; /* _SCRATCH82_0, 0x668 */ - uint32_t scratch83; /* _SCRATCH83_0, 0x66c */ - uint32_t scratch84; /* _SCRATCH84_0, 0x670 */ - uint32_t scratch85; /* _SCRATCH85_0, 0x674 */ - uint32_t scratch86; /* _SCRATCH86_0, 0x678 */ - uint32_t scratch87; /* _SCRATCH87_0, 0x67c */ - uint32_t scratch88; /* _SCRATCH88_0, 0x680 */ - uint32_t scratch89; /* _SCRATCH89_0, 0x684 */ - uint32_t scratch90; /* _SCRATCH90_0, 0x688 */ - uint32_t scratch91; /* _SCRATCH91_0, 0x68c */ - uint32_t scratch92; /* _SCRATCH92_0, 0x690 */ - uint32_t scratch93; /* _SCRATCH93_0, 0x694 */ - uint32_t scratch94; /* _SCRATCH94_0, 0x698 */ - uint32_t scratch95; /* _SCRATCH95_0, 0x69c */ - uint32_t scratch96; /* _SCRATCH96_0, 0x6a0 */ - uint32_t scratch97; /* _SCRATCH97_0, 0x6a4 */ - uint32_t scratch98; /* _SCRATCH98_0, 0x6a8 */ - uint32_t scratch99; /* _SCRATCH99_0, 0x6ac */ - uint32_t scratch100; /* _SCRATCH100_0, 0x6b0 */ - uint32_t scratch101; /* _SCRATCH101_0, 0x6b4 */ - uint32_t scratch102; /* _SCRATCH102_0, 0x6b8 */ - uint32_t scratch103; /* _SCRATCH103_0, 0x6bc */ - uint32_t scratch104; /* _SCRATCH104_0, 0x6c0 */ - uint32_t scratch105; /* _SCRATCH105_0, 0x6c4 */ - uint32_t scratch106; /* _SCRATCH106_0, 0x6c8 */ - uint32_t scratch107; /* _SCRATCH107_0, 0x6cc */ - uint32_t scratch108; /* _SCRATCH108_0, 0x6d0 */ - uint32_t scratch109; /* _SCRATCH109_0, 0x6d4 */ - uint32_t scratch110; /* _SCRATCH110_0, 0x6d8 */ - uint32_t scratch111; /* _SCRATCH111_0, 0x6dc */ - uint32_t scratch112; /* _SCRATCH112_0, 0x6e0 */ - uint32_t scratch113; /* _SCRATCH113_0, 0x6e4 */ - uint32_t scratch114; /* _SCRATCH114_0, 0x6e8 */ - uint32_t scratch115; /* _SCRATCH115_0, 0x6ec */ - uint32_t scratch116; /* _SCRATCH116_0, 0x6f0 */ - uint32_t scratch117; /* _SCRATCH117_0, 0x6f4 */ - uint32_t scratch118; /* _SCRATCH118_0, 0x6f8 */ - uint32_t scratch119; /* _SCRATCH119_0, 0x6fc */ - uint32_t scratch120; /* _SCRATCH120_0, 0x700 */ - uint32_t scratch121; /* _SCRATCH121_0, 0x704 */ - uint32_t scratch122; /* _SCRATCH122_0, 0x708 */ - uint32_t scratch123; /* _SCRATCH123_0, 0x70c */ - uint32_t scratch124; /* _SCRATCH124_0, 0x710 */ - uint32_t scratch125; /* _SCRATCH125_0, 0x714 */ - uint32_t scratch126; /* _SCRATCH126_0, 0x718 */ - uint32_t scratch127; /* _SCRATCH127_0, 0x71c */ - uint32_t scratch128; /* _SCRATCH128_0, 0x720 */ - uint32_t scratch129; /* _SCRATCH129_0, 0x724 */ - uint32_t scratch130; /* _SCRATCH130_0, 0x728 */ - uint32_t scratch131; /* _SCRATCH131_0, 0x72c */ - uint32_t scratch132; /* _SCRATCH132_0, 0x730 */ - uint32_t scratch133; /* _SCRATCH133_0, 0x734 */ - uint32_t scratch134; /* _SCRATCH134_0, 0x738 */ - uint32_t scratch135; /* _SCRATCH135_0, 0x73c */ - uint32_t scratch136; /* _SCRATCH136_0, 0x740 */ - uint32_t scratch137; /* _SCRATCH137_0, 0x744 */ - uint32_t scratch138; /* _SCRATCH138_0, 0x748 */ - uint32_t scratch139; /* _SCRATCH139_0, 0x74c */ - uint32_t scratch140; /* _SCRATCH140_0, 0x750 */ - uint32_t scratch141; /* _SCRATCH141_0, 0x754 */ - uint32_t scratch142; /* _SCRATCH142_0, 0x758 */ - uint32_t scratch143; /* _SCRATCH143_0, 0x75c */ - uint32_t scratch144; /* _SCRATCH144_0, 0x760 */ - uint32_t scratch145; /* _SCRATCH145_0, 0x764 */ - uint32_t scratch146; /* _SCRATCH146_0, 0x768 */ - uint32_t scratch147; /* _SCRATCH147_0, 0x76c */ - uint32_t scratch148; /* _SCRATCH148_0, 0x770 */ - uint32_t scratch149; /* _SCRATCH149_0, 0x774 */ - uint32_t scratch150; /* _SCRATCH150_0, 0x778 */ - uint32_t scratch151; /* _SCRATCH151_0, 0x77c */ - uint32_t scratch152; /* _SCRATCH152_0, 0x780 */ - uint32_t scratch153; /* _SCRATCH153_0, 0x784 */ - uint32_t scratch154; /* _SCRATCH154_0, 0x788 */ - uint32_t scratch155; /* _SCRATCH155_0, 0x78c */ - uint32_t scratch156; /* _SCRATCH156_0, 0x790 */ - uint32_t scratch157; /* _SCRATCH157_0, 0x794 */ - uint32_t scratch158; /* _SCRATCH158_0, 0x798 */ - uint32_t scratch159; /* _SCRATCH159_0, 0x79c */ - uint32_t scratch160; /* _SCRATCH160_0, 0x7a0 */ - uint32_t scratch161; /* _SCRATCH161_0, 0x7a4 */ - uint32_t scratch162; /* _SCRATCH162_0, 0x7a8 */ - uint32_t scratch163; /* _SCRATCH163_0, 0x7ac */ - uint32_t scratch164; /* _SCRATCH164_0, 0x7b0 */ - uint32_t scratch165; /* _SCRATCH165_0, 0x7b4 */ - uint32_t scratch166; /* _SCRATCH166_0, 0x7b8 */ - uint32_t scratch167; /* _SCRATCH167_0, 0x7bc */ - uint32_t scratch168; /* _SCRATCH168_0, 0x7c0 */ - uint32_t scratch169; /* _SCRATCH169_0, 0x7c4 */ - uint32_t scratch170; /* _SCRATCH170_0, 0x7c8 */ - uint32_t scratch171; /* _SCRATCH171_0, 0x7cc */ - uint32_t scratch172; /* _SCRATCH172_0, 0x7d0 */ - uint32_t scratch173; /* _SCRATCH173_0, 0x7d4 */ - uint32_t scratch174; /* _SCRATCH174_0, 0x7d8 */ - uint32_t scratch175; /* _SCRATCH175_0, 0x7dc */ - uint32_t scratch176; /* _SCRATCH176_0, 0x7e0 */ - uint32_t scratch177; /* _SCRATCH177_0, 0x7e4 */ - uint32_t scratch178; /* _SCRATCH178_0, 0x7e8 */ - uint32_t scratch179; /* _SCRATCH179_0, 0x7ec */ - uint32_t scratch180; /* _SCRATCH180_0, 0x7f0 */ - uint32_t scratch181; /* _SCRATCH181_0, 0x7f4 */ - uint32_t scratch182; /* _SCRATCH182_0, 0x7f8 */ - uint32_t scratch183; /* _SCRATCH183_0, 0x7fc */ - uint32_t scratch184; /* _SCRATCH184_0, 0x800 */ - uint32_t scratch185; /* _SCRATCH185_0, 0x804 */ - uint32_t scratch186; /* _SCRATCH186_0, 0x808 */ - uint32_t scratch187; /* _SCRATCH187_0, 0x80c */ - uint32_t scratch188; /* _SCRATCH188_0, 0x810 */ - uint32_t scratch189; /* _SCRATCH189_0, 0x814 */ - uint32_t scratch190; /* _SCRATCH190_0, 0x818 */ - uint32_t scratch191; /* _SCRATCH191_0, 0x81c */ - uint32_t scratch192; /* _SCRATCH192_0, 0x820 */ - uint32_t scratch193; /* _SCRATCH193_0, 0x824 */ - uint32_t scratch194; /* _SCRATCH194_0, 0x828 */ - uint32_t scratch195; /* _SCRATCH195_0, 0x82c */ - uint32_t scratch196; /* _SCRATCH196_0, 0x830 */ - uint32_t scratch197; /* _SCRATCH197_0, 0x834 */ - uint32_t scratch198; /* _SCRATCH198_0, 0x838 */ - uint32_t scratch199; /* _SCRATCH199_0, 0x83c */ - uint32_t scratch200; /* _SCRATCH200_0, 0x840 */ - uint32_t scratch201; /* _SCRATCH201_0, 0x844 */ - uint32_t scratch202; /* _SCRATCH202_0, 0x848 */ - uint32_t scratch203; /* _SCRATCH203_0, 0x84c */ - uint32_t scratch204; /* _SCRATCH204_0, 0x850 */ - uint32_t scratch205; /* _SCRATCH205_0, 0x854 */ - uint32_t scratch206; /* _SCRATCH206_0, 0x858 */ - uint32_t scratch207; /* _SCRATCH207_0, 0x85c */ - uint32_t scratch208; /* _SCRATCH208_0, 0x860 */ - uint32_t scratch209; /* _SCRATCH209_0, 0x864 */ - uint32_t scratch210; /* _SCRATCH210_0, 0x868 */ - uint32_t scratch211; /* _SCRATCH211_0, 0x86c */ - uint32_t scratch212; /* _SCRATCH212_0, 0x870 */ - uint32_t scratch213; /* _SCRATCH213_0, 0x874 */ - uint32_t scratch214; /* _SCRATCH214_0, 0x878 */ - uint32_t scratch215; /* _SCRATCH215_0, 0x87c */ - uint32_t scratch216; /* _SCRATCH216_0, 0x880 */ - uint32_t scratch217; /* _SCRATCH217_0, 0x884 */ - uint32_t scratch218; /* _SCRATCH218_0, 0x888 */ - uint32_t scratch219; /* _SCRATCH219_0, 0x88c */ - uint32_t scratch220; /* _SCRATCH220_0, 0x890 */ - uint32_t scratch221; /* _SCRATCH221_0, 0x894 */ - uint32_t scratch222; /* _SCRATCH222_0, 0x898 */ - uint32_t scratch223; /* _SCRATCH223_0, 0x89c */ - uint32_t scratch224; /* _SCRATCH224_0, 0x8a0 */ - uint32_t scratch225; /* _SCRATCH225_0, 0x8a4 */ - uint32_t scratch226; /* _SCRATCH226_0, 0x8a8 */ - uint32_t scratch227; /* _SCRATCH227_0, 0x8ac */ - uint32_t scratch228; /* _SCRATCH228_0, 0x8b0 */ - uint32_t scratch229; /* _SCRATCH229_0, 0x8b4 */ - uint32_t scratch230; /* _SCRATCH230_0, 0x8b8 */ - uint32_t scratch231; /* _SCRATCH231_0, 0x8bc */ - uint32_t scratch232; /* _SCRATCH232_0, 0x8c0 */ - uint32_t scratch233; /* _SCRATCH233_0, 0x8c4 */ - uint32_t scratch234; /* _SCRATCH234_0, 0x8c8 */ - uint32_t scratch235; /* _SCRATCH235_0, 0x8cc */ - uint32_t scratch236; /* _SCRATCH236_0, 0x8d0 */ - uint32_t scratch237; /* _SCRATCH237_0, 0x8d4 */ - uint32_t scratch238; /* _SCRATCH238_0, 0x8d8 */ - uint32_t scratch239; /* _SCRATCH239_0, 0x8dc */ - uint32_t scratch240; /* _SCRATCH240_0, 0x8e0 */ - uint32_t scratch241; /* _SCRATCH241_0, 0x8e4 */ - uint32_t scratch242; /* _SCRATCH242_0, 0x8e8 */ - uint32_t scratch243; /* _SCRATCH243_0, 0x8ec */ - uint32_t scratch244; /* _SCRATCH244_0, 0x8f0 */ - uint32_t scratch245; /* _SCRATCH245_0, 0x8f4 */ - uint32_t scratch246; /* _SCRATCH246_0, 0x8f8 */ - uint32_t scratch247; /* _SCRATCH247_0, 0x8fc */ - uint32_t scratch248; /* _SCRATCH248_0, 0x900 */ - uint32_t scratch249; /* _SCRATCH249_0, 0x904 */ - uint32_t scratch250; /* _SCRATCH250_0, 0x908 */ - uint32_t scratch251; /* _SCRATCH251_0, 0x90c */ - uint32_t scratch252; /* _SCRATCH252_0, 0x910 */ - uint32_t scratch253; /* _SCRATCH253_0, 0x914 */ - uint32_t scratch254; /* _SCRATCH254_0, 0x918 */ - uint32_t scratch255; /* _SCRATCH255_0, 0x91c */ - uint32_t scratch256; /* _SCRATCH256_0, 0x920 */ - uint32_t scratch257; /* _SCRATCH257_0, 0x924 */ - uint32_t scratch258; /* _SCRATCH258_0, 0x928 */ - uint32_t scratch259; /* _SCRATCH259_0, 0x92c */ - uint32_t scratch260; /* _SCRATCH260_0, 0x930 */ - uint32_t scratch261; /* _SCRATCH261_0, 0x934 */ - uint32_t scratch262; /* _SCRATCH262_0, 0x938 */ - uint32_t scratch263; /* _SCRATCH263_0, 0x93c */ - uint32_t scratch264; /* _SCRATCH264_0, 0x940 */ - uint32_t scratch265; /* _SCRATCH265_0, 0x944 */ - uint32_t scratch266; /* _SCRATCH266_0, 0x948 */ - uint32_t scratch267; /* _SCRATCH267_0, 0x94c */ - uint32_t scratch268; /* _SCRATCH268_0, 0x950 */ - uint32_t scratch269; /* _SCRATCH269_0, 0x954 */ - uint32_t scratch270; /* _SCRATCH270_0, 0x958 */ - uint32_t scratch271; /* _SCRATCH271_0, 0x95c */ - uint32_t scratch272; /* _SCRATCH272_0, 0x960 */ - uint32_t scratch273; /* _SCRATCH273_0, 0x964 */ - uint32_t scratch274; /* _SCRATCH274_0, 0x968 */ - uint32_t scratch275; /* _SCRATCH275_0, 0x96c */ - uint32_t scratch276; /* _SCRATCH276_0, 0x970 */ - uint32_t scratch277; /* _SCRATCH277_0, 0x974 */ - uint32_t scratch278; /* _SCRATCH278_0, 0x978 */ - uint32_t scratch279; /* _SCRATCH279_0, 0x97c */ - uint32_t scratch280; /* _SCRATCH280_0, 0x980 */ - uint32_t scratch281; /* _SCRATCH281_0, 0x984 */ - uint32_t scratch282; /* _SCRATCH282_0, 0x988 */ - uint32_t scratch283; /* _SCRATCH283_0, 0x98c */ - uint32_t scratch284; /* _SCRATCH284_0, 0x990 */ - uint32_t scratch285; /* _SCRATCH285_0, 0x994 */ - uint32_t scratch286; /* _SCRATCH286_0, 0x998 */ - uint32_t scratch287; /* _SCRATCH287_0, 0x99c */ - uint32_t scratch288; /* _SCRATCH288_0, 0x9a0 */ - uint32_t scratch289; /* _SCRATCH289_0, 0x9a4 */ - uint32_t scratch290; /* _SCRATCH290_0, 0x9a8 */ - uint32_t scratch291; /* _SCRATCH291_0, 0x9ac */ - uint32_t scratch292; /* _SCRATCH292_0, 0x9b0 */ - uint32_t scratch293; /* _SCRATCH293_0, 0x9b4 */ - uint32_t scratch294; /* _SCRATCH294_0, 0x9b8 */ - uint32_t scratch295; /* _SCRATCH295_0, 0x9bc */ - uint32_t scratch296; /* _SCRATCH296_0, 0x9c0 */ - uint32_t scratch297; /* _SCRATCH297_0, 0x9c4 */ - uint32_t scratch298; /* _SCRATCH298_0, 0x9c8 */ - uint32_t scratch299; /* _SCRATCH299_0, 0x9cc */ - uint32_t _0x9d0[50]; - uint32_t secure_scratch80; /* _SECURE_SCRATCH80_0, 0xa98 */ - uint32_t secure_scratch81; /* _SECURE_SCRATCH81_0, 0xa9c */ - uint32_t secure_scratch82; /* _SECURE_SCRATCH82_0, 0xaa0 */ - uint32_t secure_scratch83; /* _SECURE_SCRATCH83_0, 0xaa4 */ - uint32_t secure_scratch84; /* _SECURE_SCRATCH84_0, 0xaa8 */ - uint32_t secure_scratch85; /* _SECURE_SCRATCH85_0, 0xaac */ - uint32_t secure_scratch86; /* _SECURE_SCRATCH86_0, 0xab0 */ - uint32_t secure_scratch87; /* _SECURE_SCRATCH87_0, 0xab4 */ - uint32_t secure_scratch88; /* _SECURE_SCRATCH88_0, 0xab8 */ - uint32_t secure_scratch89; /* _SECURE_SCRATCH89_0, 0xabc */ - uint32_t secure_scratch90; /* _SECURE_SCRATCH90_0, 0xac0 */ - uint32_t secure_scratch91; /* _SECURE_SCRATCH91_0, 0xac4 */ - uint32_t secure_scratch92; /* _SECURE_SCRATCH92_0, 0xac8 */ - uint32_t secure_scratch93; /* _SECURE_SCRATCH93_0, 0xacc */ - uint32_t secure_scratch94; /* _SECURE_SCRATCH94_0, 0xad0 */ - uint32_t secure_scratch95; /* _SECURE_SCRATCH95_0, 0xad4 */ - uint32_t secure_scratch96; /* _SECURE_SCRATCH96_0, 0xad8 */ - uint32_t secure_scratch97; /* _SECURE_SCRATCH97_0, 0xadc */ - uint32_t secure_scratch98; /* _SECURE_SCRATCH98_0, 0xae0 */ - uint32_t secure_scratch99; /* _SECURE_SCRATCH99_0, 0xae4 */ - uint32_t secure_scratch100; /* _SECURE_SCRATCH100_0, 0xae8 */ - uint32_t secure_scratch101; /* _SECURE_SCRATCH101_0, 0xaec */ - uint32_t secure_scratch102; /* _SECURE_SCRATCH102_0, 0xaf0 */ - uint32_t secure_scratch103; /* _SECURE_SCRATCH103_0, 0xaf4 */ - uint32_t secure_scratch104; /* _SECURE_SCRATCH104_0, 0xaf8 */ - uint32_t secure_scratch105; /* _SECURE_SCRATCH105_0, 0xafc */ - uint32_t secure_scratch106; /* _SECURE_SCRATCH106_0, 0xb00 */ - uint32_t secure_scratch107; /* _SECURE_SCRATCH107_0, 0xb04 */ - uint32_t secure_scratch108; /* _SECURE_SCRATCH108_0, 0xb08 */ - uint32_t secure_scratch109; /* _SECURE_SCRATCH109_0, 0xb0c */ - uint32_t secure_scratch110; /* _SECURE_SCRATCH110_0, 0xb10 */ - uint32_t secure_scratch111; /* _SECURE_SCRATCH111_0, 0xb14 */ - uint32_t secure_scratch112; /* _SECURE_SCRATCH112_0, 0xb18 */ - uint32_t secure_scratch113; /* _SECURE_SCRATCH113_0, 0xb1c */ - uint32_t secure_scratch114; /* _SECURE_SCRATCH114_0, 0xb20 */ - uint32_t secure_scratch115; /* _SECURE_SCRATCH115_0, 0xb24 */ - uint32_t secure_scratch116; /* _SECURE_SCRATCH116_0, 0xb28 */ - uint32_t secure_scratch117; /* _SECURE_SCRATCH117_0, 0xb2c */ - uint32_t secure_scratch118; /* _SECURE_SCRATCH118_0, 0xb30 */ - uint32_t secure_scratch119; /* _SECURE_SCRATCH119_0, 0xb34 */ - uint32_t secure_scratch120; /* _SECURE_SCRATCH120_0, 0xb38 */ - uint32_t secure_scratch121; /* _SECURE_SCRATCH121_0, 0xb3c */ - uint32_t secure_scratch122; /* _SECURE_SCRATCH122_0, 0xb40 */ - uint32_t secure_scratch123; /* _SECURE_SCRATCH123_0, 0xb44 */ - uint32_t led_breathing_ctrl; /* _LED_BREATHING_CTRL_0, 0xb48 */ - uint32_t led_breathing_counter0; /* _LED_BREATHING_COUNTER0_0, 0xb4c */ - uint32_t led_breathing_counter1; /* _LED_BREATHING_COUNTER1_0, 0xb50 */ - uint32_t led_breathing_counter2; /* _LED_BREATHING_COUNTER2_0, 0xb54 */ - uint32_t led_breathing_counter3; /* _LED_BREATHING_COUNTER3_0, 0xb58 */ - uint32_t led_breathing_status; /* _LED_BREATHING_STATUS_0, 0xb5c */ - uint32_t _0xb60[2]; - uint32_t secure_scratch124; /* _SECURE_SCRATCH124_0, 0xb68 */ - uint32_t secure_scratch125; /* _SECURE_SCRATCH125_0, 0xb6c */ - uint32_t secure_scratch126; /* _SECURE_SCRATCH126_0, 0xb70 */ - uint32_t secure_scratch127; /* _SECURE_SCRATCH127_0, 0xb74 */ - uint32_t secure_scratch128; /* _SECURE_SCRATCH128_0, 0xb78 */ - uint32_t secure_scratch129; /* _SECURE_SCRATCH129_0, 0xb7c */ - uint32_t secure_scratch130; /* _SECURE_SCRATCH130_0, 0xb80 */ - uint32_t secure_scratch131; /* _SECURE_SCRATCH131_0, 0xb84 */ - uint32_t secure_scratch132; /* _SECURE_SCRATCH132_0, 0xb88 */ - uint32_t secure_scratch133; /* _SECURE_SCRATCH133_0, 0xb8c */ - uint32_t secure_scratch134; /* _SECURE_SCRATCH134_0, 0xb90 */ - uint32_t secure_scratch135; /* _SECURE_SCRATCH135_0, 0xb94 */ - uint32_t secure_scratch136; /* _SECURE_SCRATCH136_0, 0xb98 */ - uint32_t secure_scratch137; /* _SECURE_SCRATCH137_0, 0xb9c */ - uint32_t secure_scratch138; /* _SECURE_SCRATCH138_0, 0xba0 */ - uint32_t secure_scratch139; /* _SECURE_SCRATCH139_0, 0xba4 */ - uint32_t _0xba8[2]; - uint32_t sec_disable_ns; /* _SEC_DISABLE_NS_0, 0xbb0 */ - uint32_t sec_disable2_ns; /* _SEC_DISABLE2_NS_0, 0xbb4 */ - uint32_t sec_disable3_ns; /* _SEC_DISABLE3_NS_0, 0xbb8 */ - uint32_t sec_disable4_ns; /* _SEC_DISABLE4_NS_0, 0xbbc */ - uint32_t sec_disable5_ns; /* _SEC_DISABLE5_NS_0, 0xbc0 */ - uint32_t sec_disable6_ns; /* _SEC_DISABLE6_NS_0, 0xbc4 */ - uint32_t sec_disable7_ns; /* _SEC_DISABLE7_NS_0, 0xbc8 */ - uint32_t sec_disable8_ns; /* _SEC_DISABLE8_NS_0, 0xbcc */ - uint32_t sec_disable9_ns; /* _SEC_DISABLE9_NS_0, 0xbd0 */ - uint32_t sec_disable10_ns; /* _SEC_DISABLE10_NS_0, 0xbd4 */ - uint32_t _0xbd8[4]; - uint32_t tzram_pwr_cntrl; /* _TZRAM_PWR_CNTRL_0, 0xbe8 */ - uint32_t tzram_sec_disable; /* _TZRAM_SEC_DISABLE_0, 0xbec */ - uint32_t tzram_non_sec_disable; /* _TZRAM_NON_SEC_DISABLE_0, 0xbf0 */ -} tegra_pmc_t; - -static inline volatile tegra_pmc_t *pmc_get_regs(void) -{ - return (volatile tegra_pmc_t *)PMC_BASE; -} - -#endif diff --git a/sept/sept-secondary/key_derivation/src/se.c b/sept/sept-secondary/key_derivation/src/se.c deleted file mode 100644 index 8eed7bf1e..000000000 --- a/sept/sept-secondary/key_derivation/src/se.c +++ /dev/null @@ -1,757 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "utils.h" -#include "se.h" - -void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size); - -/* Globals for driver. */ -static unsigned int g_se_modulus_sizes[KEYSLOT_RSA_MAX]; -static unsigned int g_se_exp_sizes[KEYSLOT_RSA_MAX]; - -/* Initialize a SE linked list. */ -void NOINLINE ll_init(volatile se_ll_t *ll, void *buffer, size_t size) { - ll->num_entries = 0; /* 1 Entry. */ - - if (buffer != NULL) { - ll->addr_info.address = (uint32_t) get_physical_address(buffer); - ll->addr_info.size = (uint32_t) size; - } else { - ll->addr_info.address = 0; - ll->addr_info.size = 0; - } -} - -void se_check_error_status_reg(void) { - if (se_get_regs()->SE_ERR_STATUS) { - generic_panic(); - } -} - -void se_check_for_error(void) { - volatile tegra_se_t *se = se_get_regs(); - if (se->SE_INT_STATUS & 0x10000 || se->SE_STATUS & 3 || se->SE_ERR_STATUS) { - generic_panic(); - } -} - -void se_verify_flags_cleared(void) { - if (se_get_regs()->SE_STATUS & 3) { - generic_panic(); - } -} - -/* Set the flags for an AES keyslot. */ -void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Misc flags. */ - if (flags & ~0x80) { - se->SE_CRYPTO_KEYTABLE_ACCESS[keyslot] = ~flags; - } - - /* Disable keyslot reads. */ - if (flags & 0x80) { - se->SE_CRYPTO_SECURITY_PERKEY &= ~(1 << keyslot); - } -} - -/* Set the flags for an RSA keyslot. */ -void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_RSA_MAX) { - generic_panic(); - } - - /* Misc flags. */ - if (flags & ~0x80) { - /* TODO: Why are flags assigned this way? */ - se->SE_RSA_KEYTABLE_ACCESS[keyslot] = (((flags >> 4) & 4) | (flags & 3)) ^ 7; - } - - /* Disable keyslot reads. */ - if (flags & 0x80) { - se->SE_RSA_SECURITY_PERKEY &= ~(1 << keyslot); - } -} - -void clear_aes_keyslot(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Zero out the whole keyslot and IV. */ - for (unsigned int i = 0; i < 0x10; i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | i; - se->SE_CRYPTO_KEYTABLE_DATA = 0; - } -} - -void clear_rsa_keyslot(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_RSA_MAX) { - generic_panic(); - } - - /* Zero out the whole keyslot. */ - for (unsigned int i = 0; i < 0x40; i++) { - /* Select Keyslot Modulus[i] */ - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i | 0x40; - se->SE_RSA_KEYTABLE_DATA = 0; - } - for (unsigned int i = 0; i < 0x40; i++) { - /* Select Keyslot Expontent[i] */ - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i; - se->SE_RSA_KEYTABLE_DATA = 0; - } -} - -void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || key_size > KEYSIZE_AES_MAX) { - generic_panic(); - } - - for (size_t i = 0; i < (key_size >> 2); i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | i; - se->SE_CRYPTO_KEYTABLE_DATA = read32le(key, 4 * i); - } -} - -void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_RSA_MAX || modulus_size > KEYSIZE_RSA_MAX || exp_size > KEYSIZE_RSA_MAX) { - generic_panic(); - } - - for (size_t i = 0; i < (modulus_size >> 2); i++) { - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | 0x40 | i; - se->SE_RSA_KEYTABLE_DATA = read32be(modulus, (4 * (modulus_size >> 2)) - (4 * i) - 4); - } - - for (size_t i = 0; i < (exp_size >> 2); i++) { - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i; - se->SE_RSA_KEYTABLE_DATA = read32be(exponent, (4 * (exp_size >> 2)) - (4 * i) - 4); - } - - g_se_modulus_sizes[keyslot] = modulus_size; - g_se_exp_sizes[keyslot] = exp_size; -} - -void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || iv_size > 0x10) { - generic_panic(); - } - - for (size_t i = 0; i < (iv_size >> 2); i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; - se->SE_CRYPTO_KEYTABLE_DATA = read32le(iv, 4 * i); - } -} - -void clear_aes_keyslot_iv(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - for (size_t i = 0; i < (0x10 >> 2); i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; - se->SE_CRYPTO_KEYTABLE_DATA = 0; - } -} - -void set_se_ctr(const void *ctr) { - for (unsigned int i = 0; i < 4; i++) { - se_get_regs()->SE_CRYPTO_LINEAR_CTR[i] = read32le(ctr, i * 4); - } -} - -void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot_dst >= KEYSLOT_AES_MAX || keyslot_src >= KEYSLOT_AES_MAX || wrapped_key_size > KEYSIZE_AES_MAX) { - generic_panic(); - } - - /* Write config, validate. */ - se->SE_CONFIG = (ALG_AES_DEC | DST_KEYTAB); - if (se->SE_CONFIG != (ALG_AES_DEC | DST_KEYTAB)) { - generic_panic(); - } - se->SE_CRYPTO_CONFIG = keyslot_src << 24; - if (se->SE_CRYPTO_CONFIG != (keyslot_src << 24)) { - generic_panic(); - } - se->SE_CRYPTO_LAST_BLOCK = 0; - if (se->SE_CRYPTO_LAST_BLOCK != 0) { - generic_panic(); - } - se->SE_CRYPTO_KEYTABLE_DST = keyslot_dst << 8; - if (se->SE_CRYPTO_KEYTABLE_DST != (keyslot_dst << 8)) { - generic_panic(); - } - - /* Clear address context. */ - se->SE_IN_LL_ADDR = 0; - se->SE_OUT_LL_ADDR = 0; - if (se->SE_IN_LL_ADDR != 0 || se->SE_OUT_LL_ADDR != 0) { - generic_panic(); - } - - trigger_se_blocking_op(OP_START, NULL, 0, wrapped_key, wrapped_key_size); - - /* Validate address context. */ - if (se->SE_IN_LL_ADDR == 0 || se->SE_OUT_LL_ADDR == 0) { - generic_panic(); - } -} - -void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - uint8_t ALIGN(16) stack_buf[KEYSIZE_RSA_MAX]; - - if (keyslot >= KEYSLOT_RSA_MAX || src_size > KEYSIZE_RSA_MAX || dst_size > KEYSIZE_RSA_MAX) { - generic_panic(); - } - - /* Endian swap the input. */ - for (size_t i = 0; i < src_size; i++) { - stack_buf[i] = *((uint8_t *)src + src_size - i - 1); - } - - se->SE_CONFIG = (ALG_RSA | DST_RSAREG); - se->SE_RSA_CONFIG = keyslot << 24; - se->SE_RSA_KEY_SIZE = (g_se_modulus_sizes[keyslot] >> 6) - 1; - se->SE_RSA_EXP_SIZE = g_se_exp_sizes[keyslot] >> 2; - - trigger_se_blocking_op(OP_START, NULL, 0, stack_buf, src_size); - se_get_exp_mod_output(dst, dst_size); -} - -void se_get_exp_mod_output(void *buf, size_t size) { - size_t num_dwords = (size >> 2); - - if (num_dwords < 1) { - return; - } - - uint32_t *p_out = ((uint32_t *)buf) + num_dwords - 1; - uint32_t offset = 0; - - /* Copy endian swapped output. */ - while (num_dwords) { - *p_out = read32be(se_get_regs()->SE_RSA_OUTPUT, offset); - offset += 4; - p_out--; - num_dwords--; - } -} - -bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const void *modulus, size_t modulus_size, const void *data, size_t data_size) { - uint8_t message[RSA_2048_BYTES]; - uint8_t h_buf[0x24]; - - /* Hardcode RSA with keyslot 0. */ - const uint8_t public_exponent[4] = {0x00, 0x01, 0x00, 0x01}; - set_rsa_keyslot(0, modulus, modulus_size, public_exponent, sizeof(public_exponent)); - se_synchronous_exp_mod(0, message, sizeof(message), signature, signature_size); - - /* Validate sanity byte. */ - if (message[RSA_2048_BYTES - 1] != 0xBC) { - return false; - } - - /* Copy Salt into MGF1 Hash Buffer. */ - memset(h_buf, 0, sizeof(h_buf)); - memcpy(h_buf, message + RSA_2048_BYTES - 0x20 - 0x1, 0x20); - - /* Decrypt maskedDB (via inline MGF1). */ - uint8_t seed = 0; - uint8_t mgf1_buf[0x20]; - for (unsigned int ofs = 0; ofs < RSA_2048_BYTES - 0x20 - 1; ofs += 0x20) { - h_buf[sizeof(h_buf) - 1] = seed++; - se_calculate_sha256(mgf1_buf, h_buf, sizeof(h_buf)); - for (unsigned int i = ofs; i < ofs + 0x20 && i < RSA_2048_BYTES - 0x20 - 1; i++) { - message[i] ^= mgf1_buf[i - ofs]; - } - } - - /* Constant lmask for rsa-2048-pss. */ - message[0] &= 0x7F; - - /* Validate DB is of the form 0000...0001. */ - for (unsigned int i = 0; i < RSA_2048_BYTES - 0x20 - 0x20 - 1 - 1; i++) { - if (message[i] != 0) { - return false; - } - } - if (message[RSA_2048_BYTES - 0x20 - 0x20 - 1 - 1] != 1) { - return false; - } - - /* Check hash correctness. */ - uint8_t validate_buf[8 + 0x20 + 0x20]; - uint8_t validate_hash[0x20]; - - memset(validate_buf, 0, sizeof(validate_buf)); - se_calculate_sha256(&validate_buf[8], data, data_size); - memcpy(&validate_buf[0x28], &message[RSA_2048_BYTES - 0x20 - 0x20 - 1], 0x20); - se_calculate_sha256(validate_hash, validate_buf, sizeof(validate_buf)); - return memcmp(h_buf, validate_hash, 0x20) == 0; -} - -void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - se_ll_t in_ll; - se_ll_t out_ll; - - ll_init(&in_ll, (void *)src, src_size); - ll_init(&out_ll, dst, dst_size); - - /* Set the LLs. */ - se->SE_IN_LL_ADDR = (uint32_t) get_physical_address(&in_ll); - se->SE_OUT_LL_ADDR = (uint32_t) get_physical_address(&out_ll); - - /* Set registers for operation. */ - se->SE_ERR_STATUS = se->SE_ERR_STATUS; - se->SE_INT_STATUS = se->SE_INT_STATUS; - - if (se->SE_IN_LL_ADDR != (uint32_t) get_physical_address(&in_ll) || se->SE_OUT_LL_ADDR != (uint32_t) get_physical_address(&out_ll) || (se->SE_INT_STATUS & 0x10) || (se->SE_STATUS & 0x3)) { - generic_panic(); - } - - se->SE_OPERATION = op; - - while (!(se->SE_INT_STATUS & 0x10)) { /* Wait a while */ } - se_check_for_error(); -} - -/* Secure AES Functionality. */ -void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, size_t src_size) { - uint8_t block[0x10] = {0}; - - if (src_size > sizeof(block) || dst_size > sizeof(block)) { - generic_panic(); - } - - /* Load src data into block. */ - if (src_size != 0) { - memcpy(block, src, src_size); - } - - /* Trigger AES operation. */ - se_get_regs()->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, block, sizeof(block), block, sizeof(block)); - - /* Copy output data into dst. */ - if (dst_size != 0) { - memcpy(dst, block, dst_size); - } -} - -void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || ctr_size != 0x10) { - generic_panic(); - } - unsigned int num_blocks = src_size >> 4; - - /* Unknown what this write does, but official code writes it for CTR mode. */ - se->SE_SPARE = 1; - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x91E; - set_se_ctr(ctr); - - /* Handle any aligned blocks. */ - size_t aligned_size = (size_t)num_blocks << 4; - if (aligned_size) { - se->SE_CRYPTO_LAST_BLOCK = num_blocks - 1; - trigger_se_blocking_op(OP_START, dst, dst_size, src, aligned_size); - } - - /* Handle final, unaligned block. */ - if (aligned_size < dst_size && aligned_size < src_size) { - size_t last_block_size = dst_size - aligned_size; - if (src_size < dst_size) { - last_block_size = src_size - aligned_size; - } - se_perform_aes_block_operation(dst + aligned_size, last_block_size, (uint8_t *)src + aligned_size, src_size - aligned_size); - } -} - -void se_aes_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, unsigned int config_high) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) { - generic_panic(); - } - - /* Set configuration high (256-bit vs 128-bit) based on parameter. */ - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY) | (config_high << 16); - se->SE_CRYPTO_CONFIG = keyslot << 24 | 0x100; - se_perform_aes_block_operation(dst, 0x10, src, 0x10); -} - -void se_aes_128_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - se_aes_ecb_encrypt_block(keyslot, dst, dst_size, src, src_size, 0); -} - -void se_aes_256_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - se_aes_ecb_encrypt_block(keyslot, dst, dst_size, src, src_size, 0x202); -} - -void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) { - generic_panic(); - } - - se->SE_CONFIG = (ALG_AES_DEC | DST_MEMORY); - se->SE_CRYPTO_CONFIG = keyslot << 24; - se_perform_aes_block_operation(dst, 0x10, src, 0x10); -} - -void shift_left_xor_rb(uint8_t *key) { - uint8_t prev_high_bit = 0; - for (unsigned int i = 0; i < 0x10; i++) { - uint8_t cur_byte = key[0xF - i]; - key[0xF - i] = (cur_byte << 1) | (prev_high_bit); - prev_high_bit = cur_byte >> 7; - } - if (prev_high_bit) { - key[0xF] ^= 0x87; - } -} - -void shift_left_xor_rb_le(uint8_t *key) { - uint8_t prev_high_bit = 0; - for (unsigned int i = 0; i < 0x10; i++) { - uint8_t cur_byte = key[i]; - key[i] = (cur_byte << 1) | (prev_high_bit); - prev_high_bit = cur_byte >> 7; - } - if (prev_high_bit) { - key[0x0] ^= 0x87; - } -} - -void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size, unsigned int config_high) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Generate the derived key, to be XOR'd with final output block. */ - uint8_t ALIGN(16) derived_key[0x10] = {0}; - se_aes_ecb_encrypt_block(keyslot, derived_key, sizeof(derived_key), derived_key, sizeof(derived_key), config_high); - shift_left_xor_rb(derived_key); - if (data_size & 0xF) { - shift_left_xor_rb(derived_key); - } - - se->SE_CONFIG = (ALG_AES_ENC | DST_HASHREG) | (config_high << 16); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | (0x145); - clear_aes_keyslot_iv(keyslot); - - unsigned int num_blocks = (data_size + 0xF) >> 4; - /* Handle aligned blocks. */ - if (num_blocks > 1) { - se->SE_CRYPTO_LAST_BLOCK = num_blocks - 2; - trigger_se_blocking_op(OP_START, NULL, 0, data, data_size); - se->SE_CRYPTO_CONFIG |= 0x80; - } - - /* Create final block. */ - uint8_t ALIGN(16) last_block[0x10] = {0}; - if (data_size & 0xF) { - memcpy(last_block, data + (data_size & ~0xF), data_size & 0xF); - last_block[data_size & 0xF] = 0x80; /* Last block = data || 100...0 */ - } else if (data_size >= 0x10) { - memcpy(last_block, data + data_size - 0x10, 0x10); - } - - for (unsigned int i = 0; i < 0x10; i++) { - last_block[i] ^= derived_key[i]; - } - - /* Perform last operation. */ - se->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, NULL, 0, last_block, sizeof(last_block)); - - /* Copy output CMAC. */ - for (unsigned int i = 0; i < (cmac_size >> 2); i++) { - ((uint32_t *)cmac)[i] = read32le(se->SE_HASH_RESULT, i << 2); - } -} - -void se_compute_aes_128_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size) { - se_compute_aes_cmac(keyslot, cmac, cmac_size, data, data_size, 0); -} -void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size) { - se_compute_aes_cmac(keyslot, cmac, cmac_size, data, data_size, 0x202); -} - -void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || src_size < 0x10) { - generic_panic(); - } - - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY) | (0x202 << 16); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x144; - set_aes_keyslot_iv(keyslot, iv, 0x10); - se->SE_CRYPTO_LAST_BLOCK = (src_size >> 4) - 1; - trigger_se_blocking_op(OP_START, dst, dst_size, src, src_size); -} - -void se_aes_128_cbc_decrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || src_size < 0x10) { - generic_panic(); - } - - se->SE_CONFIG = (ALG_AES_DEC | DST_MEMORY) | (0x000 << 16); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x66; - clear_aes_keyslot_iv(keyslot); - se->SE_CRYPTO_LAST_BLOCK = (src_size >> 4) - 1; - trigger_se_blocking_op(OP_START, dst, dst_size, src, src_size); -} - -/* SHA256 Implementation. */ -void se_calculate_sha256(void *dst, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - - /* Setup config for SHA256, size = BITS(src_size) */ - se->SE_CONFIG = (ENCMODE_SHA256 | ALG_SHA | DST_HASHREG); - se->SE_SHA_CONFIG = 1; - se->SE_SHA_MSG_LENGTH[0] = (uint32_t)(src_size << 3); - se->SE_SHA_MSG_LENGTH[1] = 0; - se->SE_SHA_MSG_LENGTH[2] = 0; - se->SE_SHA_MSG_LENGTH[3] = 0; - se->SE_SHA_MSG_LEFT[0] = (uint32_t)(src_size << 3); - se->SE_SHA_MSG_LEFT[1] = 0; - se->SE_SHA_MSG_LEFT[2] = 0; - se->SE_SHA_MSG_LEFT[3] = 0; - - /* Trigger the operation. */ - trigger_se_blocking_op(OP_START, NULL, 0, src, src_size); - - /* Copy output hash. */ - for (unsigned int i = 0; i < (0x20 >> 2); i++) { - ((uint32_t *)dst)[i] = read32be(se->SE_HASH_RESULT, i << 2); - } -} - -/* RNG API */ -void se_initialize_rng(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* To initialize the RNG, we'll perform an RNG operation into an output buffer. */ - /* This will be discarded, when done. */ - uint8_t ALIGN(16) output_buf[0x10]; - - se->SE_RNG_SRC_CONFIG = 3; /* Entropy enable + Entropy lock enable */ - se->SE_RNG_RESEED_INTERVAL = 70001; - se->SE_CONFIG = (ALG_RNG | DST_MEMORY); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x108; - se->SE_RNG_CONFIG = 5; - se->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, output_buf, 0x10, NULL, 0); -} - -void se_generate_random(unsigned int keyslot, void *dst, size_t size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - uint32_t num_blocks = size >> 4; - size_t aligned_size = num_blocks << 4; - se->SE_CONFIG = (ALG_RNG | DST_MEMORY); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x108; - se->SE_RNG_CONFIG = 4; - - if (num_blocks >= 1) { - se->SE_CRYPTO_LAST_BLOCK = num_blocks - 1; - trigger_se_blocking_op(OP_START, dst, aligned_size, NULL, 0); - } - if (size > aligned_size) { - se_perform_aes_block_operation(dst + aligned_size, size - aligned_size, NULL, 0); - } -} - -void se_generate_random_key(unsigned int dst_keyslot, unsigned int rng_keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (dst_keyslot >= KEYSLOT_AES_MAX || rng_keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Setup Config. */ - se->SE_CONFIG = (ALG_RNG | DST_KEYTAB); - se->SE_CRYPTO_CONFIG = (rng_keyslot << 24) | 0x108; - se->SE_RNG_CONFIG = 4; - se->SE_CRYPTO_LAST_BLOCK = 0; - - /* Generate low part of key. */ - se->SE_CRYPTO_KEYTABLE_DST = (dst_keyslot << 8); - trigger_se_blocking_op(OP_START, NULL, 0, NULL, 0); - /* Generate high part of key. */ - se->SE_CRYPTO_KEYTABLE_DST = (dst_keyslot << 8) | 1; - trigger_se_blocking_op(OP_START, NULL, 0, NULL, 0); -} - -/* SE context save API. */ -void se_set_in_context_save_mode(bool is_context_save_mode) { - volatile tegra_se_t *se = se_get_regs(); - - uint32_t val = se->SE_SE_SECURITY; - if (is_context_save_mode) { - val |= 0x10000; - } else { - val &= 0xFFFEFFFF; - } - se->SE_SE_SECURITY = val; - /* Perform a useless read from flags reg. */ - (void)(se->SE_STATUS); -} - -void se_generate_srk(unsigned int srkgen_keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - se->SE_CONFIG = (ALG_RNG | DST_SRK); - se->SE_CRYPTO_CONFIG = (srkgen_keyslot << 24) | 0x108; - se->SE_RNG_CONFIG = 6; - se->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, NULL, 0, NULL, 0); -} - -void se_encrypt_with_srk(void *dst, size_t dst_size, const void *src, size_t src_size) { - uint8_t output[0x80]; - uint8_t *aligned_out = (uint8_t *)(((uintptr_t)output + 0x7F) & ~0x3F); - if (dst_size > 0x10) { - generic_panic(); - } - - if (dst_size) { - trigger_se_blocking_op(OP_CTX_SAVE, aligned_out, dst_size, src, src_size); - memcpy(dst, aligned_out, dst_size); - } else { - trigger_se_blocking_op(OP_CTX_SAVE, aligned_out, 0, src, src_size); - } -} - -void se_save_context(unsigned int srkgen_keyslot, unsigned int rng_keyslot, void *dst) { - volatile tegra_se_t *se = se_get_regs(); - uint8_t _work_buf[0x80]; - uint8_t *work_buf = (uint8_t *)(((uintptr_t)_work_buf + 0x7F) & ~0x3F); - - /* Generate the SRK (context save encryption key). */ - se_generate_random_key(srkgen_keyslot, rng_keyslot); - se_generate_srk(srkgen_keyslot); - - se_generate_random(rng_keyslot, work_buf, 0x10); - - /* Save random initial block. */ - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY); - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_MEM); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst, 0x10, work_buf, 0x10); - - /* Save Sticky Bits. */ - for (unsigned int i = 0; i < 0x2; i++) { - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_STICKY_BITS) | (i << CTX_SAVE_STICKY_BIT_INDEX_SHIFT); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x10 + (i * 0x10), 0x10, NULL, 0); - } - - /* Save AES Key Table. */ - for (unsigned int i = 0; i < KEYSLOT_AES_MAX; i++) { - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_LOW_BITS); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x30 + (i * 0x20), 0x10, NULL, 0); - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_HIGH_BITS); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x40 + (i * 0x20), 0x10, NULL, 0); - } - - /* Save AES Original IVs. */ - for (unsigned int i = 0; i < KEYSLOT_AES_MAX; i++) { - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_ORIGINAL_IV); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x230 + (i * 0x10), 0x10, NULL, 0); - } - - /* Save AES Updated IVs */ - for (unsigned int i = 0; i < KEYSLOT_AES_MAX; i++) { - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_UPDATED_IV); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x330 + (i * 0x10), 0x10, NULL, 0); - } - - /* Save RSA Keytable. */ - uint8_t *rsa_ctx_out = (uint8_t *)dst + 0x430; - for (unsigned int rsa_key = 0; rsa_key < KEYSLOT_RSA_MAX; rsa_key++) { - for (unsigned int mod_exp = 0; mod_exp < 2; mod_exp++) { - for (unsigned int sub_block = 0; sub_block < 0x10; sub_block++) { - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_KEYTABLE_RSA) | ((2 * rsa_key + (1 - mod_exp)) << CTX_SAVE_RSA_KEY_INDEX_SHIFT) | (sub_block << CTX_SAVE_RSA_KEY_BLOCK_INDEX_SHIFT); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(rsa_ctx_out, 0x10, NULL, 0); - rsa_ctx_out += 0x10; - } - } - } - - /* Save "Known Pattern. " */ - static const uint8_t context_save_known_pattern[0x10] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f}; - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_MEM); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x830, 0x10, context_save_known_pattern, 0x10); - - /* Save SRK into PMC registers. */ - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_SRK); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(work_buf, 0, NULL, 0); - se->SE_CONFIG = 0; - se_encrypt_with_srk(work_buf, 0, NULL, 0); -} diff --git a/sept/sept-secondary/key_derivation/src/se.h b/sept/sept-secondary/key_derivation/src/se.h deleted file mode 100644 index 508da9fa4..000000000 --- a/sept/sept-secondary/key_derivation/src/se.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include - -#ifndef FUSEE_SE_H -#define FUSEE_SE_H - -#define SE_BASE 0x70012000 -#define MAKE_SE_REG(n) MAKE_REG32(SE_BASE + n) - -#define KEYSLOT_SWITCH_LP0TZRAMKEY 0x2 -#define KEYSLOT_SWITCH_SRKGENKEY 0x8 -#define KEYSLOT_SWITCH_PACKAGE2KEY 0x8 -#define KEYSLOT_SWITCH_TEMPKEY 0x9 -#define KEYSLOT_SWITCH_SESSIONKEY 0xA -#define KEYSLOT_SWITCH_RNGKEY 0xB -#define KEYSLOT_SWITCH_MASTERKEY 0xC -#define KEYSLOT_SWITCH_DEVICEKEY 0xD - -/* This keyslot was added in 4.0.0. */ -#define KEYSLOT_SWITCH_4XNEWDEVICEKEYGENKEY 0xD -#define KEYSLOT_SWITCH_4XNEWCONSOLEKEYGENKEY 0xE -#define KEYSLOT_SWITCH_4XOLDDEVICEKEY 0xF - -/* This keyslot was added in 5.0.0. */ -#define KEYSLOT_SWITCH_5XNEWDEVICEKEYGENKEY 0xA - -/* Mariko keyslots. */ -#define KEYSLOT_SWITCH_MASTERKEY_MARIKO 0x7 - -#define KEYSLOT_AES_MAX 0x10 -#define KEYSLOT_RSA_MAX 0x2 - -#define KEYSIZE_AES_MAX 0x20 -#define KEYSIZE_RSA_MAX 0x100 - -#define ALG_SHIFT (12) -#define ALG_DEC_SHIFT (8) -#define ALG_NOP (0 << ALG_SHIFT) -#define ALG_AES_ENC (1 << ALG_SHIFT) -#define ALG_AES_DEC ((1 << ALG_DEC_SHIFT) | ALG_NOP) -#define ALG_RNG (2 << ALG_SHIFT) -#define ALG_SHA (3 << ALG_SHIFT) -#define ALG_RSA (4 << ALG_SHIFT) - -#define DST_SHIFT (2) -#define DST_MEMORY (0 << DST_SHIFT) -#define DST_HASHREG (1 << DST_SHIFT) -#define DST_KEYTAB (2 << DST_SHIFT) -#define DST_SRK (3 << DST_SHIFT) -#define DST_RSAREG (4 << DST_SHIFT) - -#define ENCMODE_SHIFT (24) -#define DECMODE_SHIFT (16) -#define ENCMODE_SHA256 (5 << ENCMODE_SHIFT) - -#define HASH_DISABLE (0x0) -#define HASH_ENABLE (0x1) - -#define OP_ABORT 0 -#define OP_START 1 -#define OP_RESTART 2 -#define OP_CTX_SAVE 3 -#define OP_RESTART_IN 4 - -#define CTX_SAVE_SRC_SHIFT 29 -#define CTX_SAVE_SRC_STICKY_BITS (0 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_KEYTABLE_AES (2 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_KEYTABLE_RSA (1 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_MEM (4 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_SRK (6 << CTX_SAVE_SRC_SHIFT) - -#define CTX_SAVE_KEY_LOW_BITS 0 -#define CTX_SAVE_KEY_HIGH_BITS 1 -#define CTX_SAVE_KEY_ORIGINAL_IV 2 -#define CTX_SAVE_KEY_UPDATED_IV 3 - -#define CTX_SAVE_STICKY_BIT_INDEX_SHIFT 24 -#define CTX_SAVE_KEY_INDEX_SHIFT 8 -#define CTX_SAVE_RSA_KEY_INDEX_SHIFT 16 -#define CTX_SAVE_RSA_KEY_BLOCK_INDEX_SHIFT 12 - -#define RSA_2048_BYTES 0x100 - -typedef struct { - uint32_t SE_SE_SECURITY; - uint32_t SE_TZRAM_SECURITY; - uint32_t SE_OPERATION; - uint32_t SE_INT_ENABLE; - uint32_t SE_INT_STATUS; - uint32_t SE_CONFIG; - uint32_t SE_IN_LL_ADDR; - uint32_t SE_IN_CUR_BYTE_ADDR; - uint32_t SE_IN_CUR_LL_ID; - uint32_t SE_OUT_LL_ADDR; - uint32_t SE_OUT_CUR_BYTE_ADDR; - uint32_t SE_OUT_CUR_LL_ID; - uint32_t SE_HASH_RESULT[0x10]; - uint32_t SE_CTX_SAVE_CONFIG; - uint32_t _0x74[0x63]; - uint32_t SE_SHA_CONFIG; - uint32_t SE_SHA_MSG_LENGTH[0x4]; - uint32_t SE_SHA_MSG_LEFT[0x4]; - uint32_t _0x224[0x17]; - uint32_t SE_CRYPTO_SECURITY_PERKEY; - uint32_t SE_CRYPTO_KEYTABLE_ACCESS[0x10]; - uint32_t _0x2C4[0x10]; - uint32_t SE_CRYPTO_CONFIG; - uint32_t SE_CRYPTO_LINEAR_CTR[0x4]; - uint32_t SE_CRYPTO_LAST_BLOCK; - uint32_t SE_CRYPTO_KEYTABLE_ADDR; - uint32_t SE_CRYPTO_KEYTABLE_DATA; - uint32_t _0x324[0x3]; - uint32_t SE_CRYPTO_KEYTABLE_DST; - uint32_t _0x334[0x3]; - uint32_t SE_RNG_CONFIG; - uint32_t SE_RNG_SRC_CONFIG; - uint32_t SE_RNG_RESEED_INTERVAL; - uint32_t _0x34C[0x2D]; - uint32_t SE_RSA_CONFIG; - uint32_t SE_RSA_KEY_SIZE; - uint32_t SE_RSA_EXP_SIZE; - uint32_t SE_RSA_SECURITY_PERKEY; - uint32_t SE_RSA_KEYTABLE_ACCESS[0x2]; - uint32_t _0x418[0x2]; - uint32_t SE_RSA_KEYTABLE_ADDR; - uint32_t SE_RSA_KEYTABLE_DATA; - uint32_t SE_RSA_OUTPUT[0x40]; - uint32_t _0x528[0xB6]; - uint32_t SE_STATUS; - uint32_t SE_ERR_STATUS; - uint32_t SE_MISC; - uint32_t SE_SPARE; - uint32_t SE_ENTROPY_DEBUG_COUNTER; - uint32_t _0x814; - uint32_t _0x818; - uint32_t _0x81C; - uint32_t _0x820[0x5F8]; -} tegra_se_t; - -typedef struct { - uint32_t address; - uint32_t size; -} se_addr_info_t; - -typedef struct { - uint32_t num_entries; /* Set to total entries - 1 */ - se_addr_info_t addr_info; /* This should really be an array...but for our use case it works. */ -} se_ll_t; - -static inline volatile tegra_se_t *se_get_regs(void) { - return (volatile tegra_se_t *)SE_BASE; -} - -void se_check_error_status_reg(void); -void se_check_for_error(void); -void se_trigger_interrupt(void); - -void se_validate_stored_vector(void); -void se_generate_stored_vector(void); - -void se_verify_flags_cleared(void); - -void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags); -void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags); -void clear_aes_keyslot(unsigned int keyslot); -void clear_rsa_keyslot(unsigned int keyslot); - -void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size); -void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size); -void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size); -void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size); -void set_se_ctr(const void *ctr); - -/* Secure AES API */ -void se_compute_aes_128_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size); -void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size); -void se_aes_128_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -void se_aes_256_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size); -void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv); -void se_aes_128_cbc_decrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); - -/* Hash API */ -void se_calculate_sha256(void *dst, const void *src, size_t src_size); - -/* RSA API */ -void se_get_exp_mod_output(void *buf, size_t size); -void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const void *modulus, size_t modulus_size, const void *data, size_t data_size); - -/* RNG API */ -void se_initialize_rng(unsigned int keyslot); -void se_generate_random(unsigned int keyslot, void *dst, size_t size); - -/* SE context save API. */ -void se_generate_srk(unsigned int srkgen_keyslot); -void se_set_in_context_save_mode(bool is_context_save_mode); -void se_generate_random_key(unsigned int dst_keyslot, unsigned int rng_keyslot); -void se_save_context(unsigned int srk_keyslot, unsigned int rng_keyslot, void *dst); - -#endif diff --git a/sept/sept-secondary/key_derivation/src/start.s b/sept/sept-secondary/key_derivation/src/start.s deleted file mode 100644 index cc068e4b6..000000000 --- a/sept/sept-secondary/key_derivation/src/start.s +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - - /* For some reason GAS doesn't know about it, even with .cpu cortex-a57 */ -#define cpuactlr_el1 s3_1_c15_c2_0 -#define cpuectlr_el1 s3_1_c15_c2_1 - -.macro RESET_CORE - mov x0, #(1 << 63) - msr cpuactlr_el1, x0 /* disable regional clock gating */ - isb - mov x0, #3 - msr rmr_el3, x0 - isb - dsb sy - /* Nintendo forgot to copy-paste the branch instruction below. */ - 1: - wfi - b 1b -.endm - -.macro ERRATUM_INVALIDATE_BTB_AT_BOOT -/* Nintendo copy-pasted https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/nvidia/tegra/common/aarch64/tegra_helpers.S#L312 */ - /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - /* The following comments are mine. */ - /* mask all interrupts */ - msr daifset, 0b1111 - - /* - Enable invalidates of branch target buffer, then flush - the entire instruction cache at the local level, and - with the reg change, the branch target buffer, then disable - invalidates of the branch target buffer again. - */ - mrs x0, cpuactlr_el1 - orr x0, x0, #1 - msr cpuactlr_el1, x0 - - dsb sy - isb - ic iallu - dsb sy - isb - - mrs x0, cpuactlr_el1 - bic x0, x0, #1 - msr cpuactlr_el1, x0 - -.rept 7 - nop /* wait long enough for the write to cpuactlr_el1 to have completed */ -.endr - - /* if the OS lock is set, disable it and request a warm reset */ - mrs x0, oslsr_el1 - ands x0, x0, #2 - b.eq 2f - mov x0, xzr - msr oslar_el1, x0 - - RESET_CORE - -.rept 65 - nop /* guard against speculative excecution */ -.endr - - 2: - /* set the OS lock */ - mov x0, #1 - msr oslar_el1, x0 -.endm - - -.section .text.start -.align 4 -.global _start -_start: - ERRATUM_INVALIDATE_BTB_AT_BOOT - msr spsel, #0 - ldr x0, =__start__ - mov sp, x0 - mov fp, #0x0 - - bl derive_keys \ No newline at end of file diff --git a/sept/sept-secondary/key_derivation/src/utils.c b/sept/sept-secondary/key_derivation/src/utils.c deleted file mode 100644 index a35aa1ae9..000000000 --- a/sept/sept-secondary/key_derivation/src/utils.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include "utils.h" -#include "se.h" -#include - -__attribute__ ((noreturn)) void generic_panic(void) { - /* Clear keyslots. */ - clear_aes_keyslot(0xD); - clear_aes_keyslot(0xE); - for (size_t i = 0; i < 0x10; i++) { - clear_aes_keyslot(i); - } - clear_aes_keyslot(0xD); - clear_aes_keyslot(0xE); - while(1) { /* ... */ } -} diff --git a/sept/sept-secondary/key_derivation/src/utils.h b/sept/sept-secondary/key_derivation/src/utils.h deleted file mode 100644 index 19e9d66a1..000000000 --- a/sept/sept-secondary/key_derivation/src/utils.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_UTILS_H -#define FUSEE_UTILS_H - -#include -#include -#include -#include - -#define BIT(n) (1u << (n)) -#define BITL(n) (1ull << (n)) -#define MASK(n) (BIT(n) - 1) -#define MASKL(n) (BITL(n) - 1) -#define MASK2(a,b) (MASK(a) & ~MASK(b)) -#define MASK2L(a,b) (MASKL(a) & ~MASKL(b)) - -#define MAKE_REG32(a) (*(volatile uint32_t *)(a)) - -#define ALIGN(m) __attribute__((aligned(m))) -#define PACKED __attribute__((packed)) - -#define ALINLINE __attribute__((always_inline)) -#define NOINLINE __attribute__((noinline)) - -#define SET_SYSREG(reg, val) do { temp_reg = (val); __asm__ __volatile__ ("msr " #reg ", %0" :: "r"(temp_reg) : "memory"); } while(false) - -static inline uintptr_t get_physical_address(const void *addr) { - return (uintptr_t)addr; -} - -static inline uint32_t read32le(const volatile void *dword, size_t offset) { - uintptr_t addr = (uintptr_t)dword + offset; - volatile uint32_t *target = (uint32_t *)addr; - return *target; -} - -static inline uint32_t read32be(const volatile void *dword, size_t offset) { - return __builtin_bswap32(read32le(dword, offset)); -} - -static inline uint64_t read64le(const volatile void *qword, size_t offset) { - uintptr_t addr = (uintptr_t)qword + offset; - volatile uint64_t *target = (uint64_t *)addr; - return *target; -} - -static inline uint64_t read64be(const volatile void *qword, size_t offset) { - return __builtin_bswap64(read64le(qword, offset)); -} - -static inline void write32le(volatile void *dword, size_t offset, uint32_t value) { - uintptr_t addr = (uintptr_t)dword + offset; - volatile uint32_t *target = (uint32_t *)addr; - *target = value; -} - -static inline void write32be(volatile void *dword, size_t offset, uint32_t value) { - write32le(dword, offset, __builtin_bswap32(value)); -} - -static inline void write64le(volatile void *qword, size_t offset, uint64_t value) { - uintptr_t addr = (uintptr_t)qword + offset; - volatile uint64_t *target = (uint64_t *)addr; - *target = value; -} - -static inline void write64be(volatile void *qword, size_t offset, uint64_t value) { - write64le(qword, offset, __builtin_bswap64(value)); -} - -static inline bool check_32bit_additive_overflow(uint32_t a, uint32_t b) { - return __builtin_add_overflow_p(a, b, (uint32_t)0); -} - -static inline bool check_32bit_address_loadable(uintptr_t addr) { - /* FWIW the bootROM forbids loading anything between 0x40000000 and 0x40010000, using it for itself... */ - return (addr >= 0x40010000u && addr < 0x40040000u) || addr >= 0x80000000u; -} - -static inline bool check_32bit_address_range_loadable(uintptr_t addr, size_t size) { - return - !__builtin_add_overflow_p(addr, size, (uintptr_t)0) && /* the range doesn't overflow */ - check_32bit_address_loadable(addr) && check_32bit_address_loadable(addr + size) && /* bounds are valid */ - !(addr >= 0x40010000u && addr < 0x40040000u && addr + size >= 0x40040000u) /* the range doesn't cross MMIO */ - ; -} - -bool overlaps(uint64_t as, uint64_t ae, uint64_t bs, uint64_t be); -static inline bool overlaps_a(const void *as, const void *ae, const void *bs, const void *be) { - return overlaps((uint64_t)(uintptr_t)as, (uint64_t)(uintptr_t)ae, (uint64_t)(uintptr_t)bs, (uint64_t)(uintptr_t)be); -} - -static inline bool check_32bit_address_range_in_program(uintptr_t addr, size_t size) { - extern uint8_t __chainloader_start__[], __chainloader_end__[]; - extern uint8_t __stack_bottom__[], __stack_top__[]; - extern uint8_t __start__[], __end__[]; - uint8_t *start = (uint8_t *)addr, *end = start + size; - - return overlaps_a(start, end, __chainloader_start__, __chainloader_end__) || - overlaps_a(start, end, __stack_bottom__, __stack_top__) || - overlaps_a(start, end, (void *)0xC0000000, (void *)0xC03C0000) || /* framebuffer */ - overlaps_a(start, end, __start__, __end__); -} - -__attribute__((noreturn)) void generic_panic(void); - -#endif diff --git a/sept/sept-secondary/linker.ld b/sept/sept-secondary/linker.ld deleted file mode 100644 index f0c43fa38..000000000 --- a/sept/sept-secondary/linker.ld +++ /dev/null @@ -1,193 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) - -PHDRS -{ - crt0 PT_LOAD; - chainloader PT_LOAD; - main PT_LOAD; -} - -/* Mostly copied from https://github.com/devkitPro/buildscripts/blob/master/dkarm-eabi/crtls/3dsx.ld */ -MEMORY -{ - NULL : ORIGIN = 0x00000000, LENGTH = 0x1000 - main : ORIGIN = 0x40010000, LENGTH = 0x20000 - low_iram : ORIGIN = 0x40002000, LENGTH = 0x6000 -} - -SECTIONS -{ - PROVIDE(__start__ = 0x40010000); - PROVIDE(__stack_top__ = 0x40010000); - PROVIDE(__stack_bottom__ = 0x40008000); - PROVIDE(__heap_start__ = 0); - PROVIDE(__heap_end__ = 0); - - . = __start__; - - .crt0 : - { - KEEP( *(.text.start) ) - KEEP( *(.init) ) - . = ALIGN(32); - } >main :crt0 - - .chainloader_loadable : - { - . = ALIGN(32); - PROVIDE (__chainloader_start__ = ABSOLUTE(.)); - PROVIDE (__chainloader_lma__ = LOADADDR(.chainloader_loadable)); - KEEP(*(.chainloader.text.start)) - chainloader.o(.text*) - chainloader.o(.rodata*) - chainloader.o(.data*) - . = ALIGN(32); - } >low_iram AT>main :chainloader - - .chainloader_bss (NOLOAD) : - { - . = ALIGN(32); - PROVIDE (__chainloader_bss_start__ = ABSOLUTE(.)); - chainloader.o(.bss* COMMON) - . = ALIGN(32); - PROVIDE (__chainloader_end__ = ABSOLUTE(.)); - } >low_iram :NONE - - .text : - { - . = ALIGN(32); - /* .text */ - *(.text) - *(.text.*) - *(.glue_7) - *(.glue_7t) - *(.stub) - *(.gnu.warning) - *(.gnu.linkonce.t*) - - /* .fini */ - KEEP( *(.fini) ) - . = ALIGN(8); - } >main :main - - .rodata : - { - *(.rodata) - *(.roda) - *(.rodata.*) - *all.rodata*(*) - *(.gnu.linkonce.r*) - SORT(CONSTRUCTORS) - . = ALIGN(8); - } >main - - .preinit_array : - { - PROVIDE (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - } >main - - .init_array ALIGN(4) : - { - PROVIDE (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE (__init_array_end = .); - } >main - - .fini_array ALIGN(4) : - { - PROVIDE (__fini_array_start = .); - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE (__fini_array_end = .); - } >main - - .ctors ALIGN(4) : - { - KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */ - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - . = ALIGN(4); /* REQUIRED. LD is flaky without it. */ - } >main - - .dtors ALIGN(4) : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - . = ALIGN(4); /* REQUIRED. LD is flaky without it. */ - } >main - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) __exidx_start = ABSOLUTE(.);} >main - ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) __exidx_end = ABSOLUTE(.);} >main - - .data : - { - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - CONSTRUCTORS - . = ALIGN(32); - } >main - - .bss (NOLOAD) : - { - . = ALIGN(32); - PROVIDE (__bss_start__ = ABSOLUTE(.)); - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b*) - *(COMMON) - . = ALIGN(32); - PROVIDE (__bss_end__ = ABSOLUTE(.)); - } >main :NONE - . = ALIGN(32); - __end__ = ABSOLUTE(.) ; - - /* ================== - ==== Metadata ==== - ================== */ - - /* Discard sections that difficult post-processing */ - /DISCARD/ : { *(.group .comment .note) } - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } -} diff --git a/sept/sept-secondary/linker.specs b/sept/sept-secondary/linker.specs deleted file mode 100644 index 300990418..000000000 --- a/sept/sept-secondary/linker.specs +++ /dev/null @@ -1,7 +0,0 @@ -%rename link old_link - -*link: -%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections - -*startfile: -crti%O%s crtbegin%O%s diff --git a/sept/sept-secondary/sept_sign.py b/sept/sept-secondary/sept_sign.py deleted file mode 100644 index 428ee8b68..000000000 --- a/sept/sept-secondary/sept_sign.py +++ /dev/null @@ -1,84 +0,0 @@ -#!/usr/bin/env python -import sys, os -from struct import pack as pk, unpack as up -from Crypto.Cipher import AES -from Crypto.Hash import CMAC -try: - import KEYS -except ImportError: - import KEYS_template as KEYS - print('Warning: output will not work on 7.0.0+!') - - -def shift_left_xor_rb(s): - if hasattr(int, "from_bytes"): - N = int.from_bytes(s, byteorder="big") - else: - N = int(s.encode('hex'), 16) - - if N & (1 << 127): - N = ((N << 1) ^ 0x87) & 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - else: - N = ((N << 1) ^ 0x00) & 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - return bytearray.fromhex('%032x' % N) - - -def sxor(x, y): - return bytearray(a^b for a,b in zip(x, y)) - - -def get_last_block_for_desired_mac(key, data, desired_mac): - assert len(desired_mac) == 0x10 - k1 = shift_left_xor_rb(AES.new(key, AES.MODE_ECB).encrypt(bytearray(0x10))) - if len(data) & 0xF: - k1 = shift_left_xor_rb(k1) - data = data + b'\x80' - data = data + bytearray((0x10 - (len(data) & 0xF)) & 0xF) - num_blocks = (len(data) + 0xF) >> 4 - last_block = sxor(bytearray(AES.new(key, AES.MODE_ECB).decrypt(desired_mac)), bytearray(k1)) - if len(data) > 0x0: - last_block = sxor(last_block, bytearray(AES.new(key, AES.MODE_CBC, bytearray(0x10)).encrypt(data)[-0x10:])) - return last_block - - -def sign_encrypt_code(code, sig_key, enc_key, iv, desired_mac, version): - # Pad with 0x20 of zeroes. - code = code + bytearray(0x20) - code_len = len(code) - code_len += 0xFFF - code_len &= ~0xFFF - code = code + bytearray(code_len - len(code)) - - # Insert version - code = code[:8] + pk('. - */ - -#ifndef FUSEE_APB_MISC_H -#define FUSEE_APB_MISC_H - -#include - -#define APB_MISC_BASE 0x70000000 -#define APB_PADCTL_BASE 0x70000810 -#define MAKE_APB_MISC_REG(n) MAKE_REG32(APB_MISC_BASE + n) -#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n) - -#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40) -#define APB_MISC_GP_DSI_PAD_CONTROL_0 MAKE_APB_MISC_REG(0xAC0) -#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64) -#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68) - -#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20) -#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12) -#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT (28) -#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT (30) -#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT) -#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT) -#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT) -#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT) - -#define EMMC2_PAD_DRVUP_COMP_SHIFT (8) -#define EMMC2_PAD_DRVDN_COMP_SHIFT (2) -#define EMMC2_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC2_PAD_DRVUP_COMP_SHIFT) -#define EMMC2_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC2_PAD_DRVDN_COMP_SHIFT) - -#define SDMMC2_PAD_CAL_DRVUP_SHIFT (20) -#define SDMMC2_PAD_CAL_DRVDN_SHIFT (12) -#define SDMMC2_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVUP_SHIFT) -#define SDMMC2_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVDN_SHIFT) - -#define EMMC4_PAD_DRVUP_COMP_SHIFT (8) -#define EMMC4_PAD_DRVDN_COMP_SHIFT (2) -#define EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC4_PAD_DRVUP_COMP_SHIFT) -#define EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC4_PAD_DRVDN_COMP_SHIFT) - -#define PADCTL_SDMMC1_DEEP_LOOPBACK (1 << 0) -#define PADCTL_SDMMC3_DEEP_LOOPBACK (1 << 0) -#define PADCTL_SDMMC2_ENABLE_DATA_IN (0xFF << 8) -#define PADCTL_SDMMC2_ENABLE_CLK_IN (0x3 << 4) -#define PADCTL_SDMMC2_DEEP_LOOPBACK (1 << 0) -#define PADCTL_SDMMC4_ENABLE_DATA_IN (0xFF << 8) -#define PADCTL_SDMMC4_ENABLE_CLK_IN (0x3 << 4) -#define PADCTL_SDMMC4_DEEP_LOOPBACK (1 << 0) -#define PADCTL_SDMMC1_CD_SOURCE (1 << 0) -#define PADCTL_SDMMC1_WP_SOURCE (1 << 1) -#define PADCTL_SDMMC3_CD_SOURCE (1 << 2) -#define PADCTL_SDMMC3_WP_SOURCE (1 << 3) - -typedef struct { - uint32_t asdbgreg; /* 0x810 */ - uint32_t _0x814[0x31]; - uint32_t sdmmc1_clk_lpbk_control; /* 0x8D4 */ - uint32_t sdmmc3_clk_lpbk_control; /* 0x8D8 */ - uint32_t emmc2_pad_cfg_control; /* 0x8DC */ - uint32_t emmc4_pad_cfg_control; /* 0x8E0 */ - uint32_t _0x8E4[0x6E]; - uint32_t sdmmc1_pad_cfgpadctrl; /* 0xA98 */ - uint32_t emmc2_pad_cfgpadctrl; /* 0xA9C */ - uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */ - uint32_t emmc2_pad_pupd_cfgpadctrl; /* 0xAA4 */ - uint32_t _0xAA8[0x03]; - uint32_t sdmmc3_pad_cfgpadctrl; /* 0xAB0 */ - uint32_t emmc4_pad_cfgpadctrl; /* 0xAB4 */ - uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */ - uint32_t emmc4_pad_pupd_cfgpadctrl; /* 0xABC */ - uint32_t _0xAC0[0x2E]; - uint32_t vgpio_gpio_mux_sel; /* 0xB74 */ - uint32_t qspi_sck_lpbk_control; /* 0xB78 */ -} tegra_padctl_t; - -static inline volatile tegra_padctl_t *padctl_get_regs(void) -{ - return (volatile tegra_padctl_t *)APB_PADCTL_BASE; -} - -#endif diff --git a/sept/sept-secondary/src/btn.c b/sept/sept-secondary/src/btn.c deleted file mode 100644 index c157aab52..000000000 --- a/sept/sept-secondary/src/btn.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "btn.h" -#include "i2c.h" -#include "gpio.h" -#include "timers.h" - -uint32_t btn_read() -{ - uint32_t res = 0; - - if (!gpio_read(GPIO_BUTTON_VOL_DOWN)) - res |= BTN_VOL_DOWN; - - if (!gpio_read(GPIO_BUTTON_VOL_UP)) - res |= BTN_VOL_UP; - - uint32_t val = 0; - if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, 0x15, &val, 1)) - { - if (val & 0x4) - res |= BTN_POWER; - } - - return res; -} - -uint32_t btn_wait() -{ - uint32_t res = 0, btn = btn_read(); - int pwr = 0; - - if (btn & BTN_POWER) - { - pwr = 1; - btn &= ~BTN_POWER; - } - - do - { - res = btn_read(); - - if (!(res & BTN_POWER) && pwr) - pwr = 0; - else if (pwr) - res &= ~BTN_POWER; - } while (btn == res); - - return res; -} - -uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask) -{ - uint32_t timeout = get_time_ms() + time_ms; - uint32_t res = btn_read() & mask; - - do - { - if (!(res & mask)) - res = btn_read() & mask; - } while (get_time_ms() < timeout); - - return res; -} \ No newline at end of file diff --git a/sept/sept-secondary/src/btn.h b/sept/sept-secondary/src/btn.h deleted file mode 100644 index a9a018eae..000000000 --- a/sept/sept-secondary/src/btn.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_BTN_H_ -#define FUSEE_BTN_H_ - -#define BTN_POWER 0x1 -#define BTN_VOL_DOWN 0x2 -#define BTN_VOL_UP 0x4 - -uint32_t btn_read(); -uint32_t btn_wait(); -uint32_t btn_wait_timeout(uint32_t time_ms, uint32_t mask); - -#endif \ No newline at end of file diff --git a/sept/sept-secondary/src/car.c b/sept/sept-secondary/src/car.c deleted file mode 100644 index 30c2d86aa..000000000 --- a/sept/sept-secondary/src/car.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "car.h" -#include "timers.h" -#include "utils.h" - -static inline uint32_t get_clk_source_reg(CarDevice dev) { - switch (dev) { - case CARDEVICE_UARTA: return 0x178; - case CARDEVICE_UARTB: return 0x17C; - case CARDEVICE_UARTC: return 0x1A0; - case CARDEVICE_I2C1: return 0x124; - case CARDEVICE_I2C5: return 0x128; - case CARDEVICE_TZRAM: return 0; - case CARDEVICE_SE: return 0x42C; - case CARDEVICE_HOST1X: return 0x180; - case CARDEVICE_TSEC: return 0x1F4; - case CARDEVICE_SOR_SAFE: return 0; - case CARDEVICE_SOR0: return 0; - case CARDEVICE_SOR1: return 0x410; - case CARDEVICE_KFUSE: return 0; - case CARDEVICE_CL_DVFS: return 0; - case CARDEVICE_CORESIGHT: return 0x1D4; - case CARDEVICE_MSELECT: return 0x3B4; - case CARDEVICE_ACTMON: return 0x3E8; - case CARDEVICE_BPMP: return 0; - default: generic_panic(); - } -} - -static inline uint32_t get_clk_source_val(CarDevice dev) { - switch (dev) { - case CARDEVICE_UARTA: return 0; - case CARDEVICE_UARTB: return 0; - case CARDEVICE_UARTC: return 0; - case CARDEVICE_I2C1: return 6; - case CARDEVICE_I2C5: return 6; - case CARDEVICE_TZRAM: return 0; - case CARDEVICE_SE: return 0; - case CARDEVICE_HOST1X: return 4; - case CARDEVICE_TSEC: return 0; - case CARDEVICE_SOR_SAFE: return 0; - case CARDEVICE_SOR0: return 0; - case CARDEVICE_SOR1: return 0; - case CARDEVICE_KFUSE: return 0; - case CARDEVICE_CL_DVFS: return 0; - case CARDEVICE_CORESIGHT: return 0; - case CARDEVICE_MSELECT: return 0; - case CARDEVICE_ACTMON: return 6; - case CARDEVICE_BPMP: return 0; - default: generic_panic(); - } -} - -static inline uint32_t get_clk_source_div(CarDevice dev) { - switch (dev) { - case CARDEVICE_UARTA: return 0; - case CARDEVICE_UARTB: return 0; - case CARDEVICE_UARTC: return 0; - case CARDEVICE_I2C1: return 0; - case CARDEVICE_I2C5: return 0; - case CARDEVICE_TZRAM: return 0; - case CARDEVICE_SE: return 0; - case CARDEVICE_HOST1X: return 3; - case CARDEVICE_TSEC: return 2; - case CARDEVICE_SOR_SAFE: return 0; - case CARDEVICE_SOR0: return 0; - case CARDEVICE_SOR1: return 2; - case CARDEVICE_KFUSE: return 0; - case CARDEVICE_CL_DVFS: return 0; - case CARDEVICE_CORESIGHT: return 4; - case CARDEVICE_MSELECT: return 6; - case CARDEVICE_ACTMON: return 0; - case CARDEVICE_BPMP: return 0; - default: generic_panic(); - } -} - -static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298}; -static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4}; - -void clk_enable(CarDevice dev) { - uint32_t clk_source_reg; - if ((clk_source_reg = get_clk_source_reg(dev))) { - MAKE_CAR_REG(clk_source_reg) = (get_clk_source_val(dev) << 29) | get_clk_source_div(dev); - } - MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F); -} - -void clk_disable(CarDevice dev) { - MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F)); -} - -void rst_enable(CarDevice dev) { - MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F); -} - -void rst_disable(CarDevice dev) { - MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F)); -} - -void clkrst_enable(CarDevice dev) { - clk_enable(dev); - rst_disable(dev); -} - -void clkrst_disable(CarDevice dev) { - rst_enable(dev); - clk_disable(dev); -} - -void clkrst_reboot(CarDevice dev) { - clkrst_disable(dev); - if (dev == CARDEVICE_KFUSE) { - /* Workaround for KFUSE clock. */ - clk_enable(dev); - udelay(100); - rst_disable(dev); - udelay(200); - } else { - clkrst_enable(dev); - } -} - -void clkrst_enable_fuse_regs(bool enable) { - volatile tegra_car_t *car = car_get_regs(); - car->misc_clk_enb = ((car->misc_clk_enb & 0xEFFFFFFF) | ((enable & 1) << 28)); -} diff --git a/sept/sept-secondary/src/car.h b/sept/sept-secondary/src/car.h deleted file mode 100644 index 97dc3f792..000000000 --- a/sept/sept-secondary/src/car.h +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_CAR_H -#define FUSEE_CAR_H - -#include -#include - -#define CAR_BASE 0x60006000 -#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n) - -#define CLK_L_SDMMC1 (1 << 14) -#define CLK_L_SDMMC2 (1 << 9) -#define CLK_U_SDMMC3 (1 << 5) -#define CLK_L_SDMMC4 (1 << 15) - -#define CLK_SOURCE_MASK (0b111 << 29) -#define CLK_SOURCE_FIRST (0b000 << 29) -#define CLK_DIVIDER_MASK (0xff << 0) -#define CLK_DIVIDER_UNITY (0x00 << 0) - -#define NUM_CAR_BANKS 7 - -/* Clock and reset devices. */ -typedef enum { - CARDEVICE_BPMP = ((0 << 5) | 0x1), - CARDEVICE_UARTA = ((0 << 5) | 0x6), - CARDEVICE_UARTB = ((0 << 5) | 0x7), - CARDEVICE_I2C1 = ((0 << 5) | 0xC), - CARDEVICE_USBD = ((0 << 5) | 0x16), - CARDEVICE_HOST1X = ((0 << 5) | 0x1C), - CARDEVICE_AHBDMA = ((1 << 5) | 0x1), - CARDEVICE_APBDMA = ((1 << 5) | 0x2), - CARDEVICE_KFUSE = ((1 << 5) | 0x8), - CARDEVICE_I2C5 = ((1 << 5) | 0xF), - CARDEVICE_UARTC = ((1 << 5) | 0x17), - CARDEVICE_USB2 = ((1 << 5) | 0x1A), - CARDEVICE_CORESIGHT = ((2 << 5) | 0x9), - CARDEVICE_TSEC = ((2 << 5) | 0x13), - CARDEVICE_MSELECT = ((3 << 5) | 0x8), - CARDEVICE_ACTMON = ((3 << 5) | 0x17), - CARDEVICE_TZRAM = ((3 << 5) | 0x1E), - CARDEVICE_SE = ((3 << 5) | 0x1F), - CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B), - CARDEVICE_SOR0 = ((5 << 5) | 0x16), - CARDEVICE_SOR1 = ((5 << 5) | 0x17), - CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E), -} CarDevice; - -/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -typedef struct { - uint32_t rst_src; /* _RST_SOURCE_0, 0x00 */ - - /* _RST_DEVICES_L/H/U_0 0x4-0xc */ - uint32_t rst_dev_l; - uint32_t rst_dev_h; - uint32_t rst_dev_u; - - /* _CLK_OUT_ENB_L/H/U_0 0x10-0x18 */ - uint32_t clk_out_enb_l; - uint32_t clk_out_enb_h; - uint32_t clk_out_enb_u; - - uint32_t _0x1C; - uint32_t cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ - uint32_t super_cclk_div; /* _SUPER_CCLK_DIVIDER_0, 0x24 */ - uint32_t sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ - uint32_t super_sclk_div; /* _SUPER_SCLK_DIVIDER_0, 0x2c */ - uint32_t clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ - uint32_t prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ - uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0, 0x38 */ - uint32_t _0x3C; - uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0, 0x40 */ - uint32_t clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ - uint32_t misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ - uint32_t clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4c */ - uint32_t osc_ctrl; /* _OSC_CTRL_0, 0x50 */ - uint32_t pll_lfsr; /* _PLL_LFSR_0, 0x54 */ - uint32_t osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ - uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0, 0x5c */ - uint32_t _0x60[2]; - uint32_t plle_ss_cntl; /* _PLLE_SS_CNTL_0, 0x68 */ - uint32_t plle_misc1; /* _PLLE_MISC1_0, 0x6c */ - uint32_t _0x70[4]; - - /* PLLC 0x80-0x8c */ - uint32_t pllc_base; - uint32_t pllc_out; - uint32_t pllc_misc0; - uint32_t pllc_misc1; - - /* PLLM 0x90-0x9c */ - uint32_t pllm_base; - uint32_t pllm_out; - uint32_t pllm_misc1; - uint32_t pllm_misc2; - - /* PLLP 0xa0-0xac */ - uint32_t pllp_base; - uint32_t pllp_outa; - uint32_t pllp_outb; - uint32_t pllp_misc; - - /* PLLA 0xb0-0xbc */ - uint32_t plla_base; - uint32_t plla_out; - uint32_t plla_misc0; - uint32_t plla_misc1; - - /* PLLU 0xc0-0xcc */ - uint32_t pllu_base; - uint32_t pllu_out; - uint32_t pllu_misc1; - uint32_t pllu_misc2; - - /* PLLD 0xd0-0xdc */ - uint32_t plld_base; - uint32_t plld_out; - uint32_t plld_misc1; - uint32_t plld_misc2; - - /* PLLX 0xe0-0xe4 */ - uint32_t pllx_base; - uint32_t pllx_misc; - - /* PLLE 0xe8-0xf4 */ - uint32_t plle_base; - uint32_t plle_misc; - uint32_t plle_ss_cntl1; - uint32_t plle_ss_cntl2; - - uint32_t lvl2_clk_gate_ovra; /* _LVL2_CLK_GATE_OVRA_0, 0xf8 */ - uint32_t lvl2_clk_gate_ovrb; /* _LVL2_CLK_GATE_OVRB_0, 0xfc */ - - uint32_t clk_source_i2s2; /* _CLK_SOURCE_I2S2_0, 0x100 */ - uint32_t clk_source_i2s3; /* _CLK_SOURCE_I2S3_0, 0x104 */ - uint32_t clk_source_spdif_out; /* _CLK_SOURCE_SPDIF_OUT_0, 0x108 */ - uint32_t clk_source_spdif_in; /* _CLK_SOURCE_SPDIF_IN_0, 0x10c */ - uint32_t clk_source_pwm; /* _CLK_SOURCE_PWM_0, 0x110 */ - uint32_t _0x114; - uint32_t clk_source_spi2; /* _CLK_SOURCE_SPI2_0, 0x118 */ - uint32_t clk_source_spi3; /* _CLK_SOURCE_SPI3_0, 0x11c */ - uint32_t _0x120; - uint32_t clk_source_i2c1; /* _CLK_SOURCE_I2C1_0, 0x124 */ - uint32_t clk_source_i2c5; /* _CLK_SOURCE_I2C5_0, 0x128 */ - uint32_t _0x12c[2]; - uint32_t clk_source_spi1; /* _CLK_SOURCE_SPI1_0, 0x134 */ - uint32_t clk_source_disp1; /* _CLK_SOURCE_DISP1_0, 0x138 */ - uint32_t clk_source_disp2; /* _CLK_SOURCE_DISP2_0, 0x13c */ - uint32_t _0x140; - uint32_t clk_source_isp; /* _CLK_SOURCE_ISP_0, 0x144 */ - uint32_t clk_source_vi; /* _CLK_SOURCE_VI_0, 0x148 */ - uint32_t _0x14c; - uint32_t clk_source_sdmmc1; /* _CLK_SOURCE_SDMMC1_0, 0x150 */ - uint32_t clk_source_sdmmc2; /* _CLK_SOURCE_SDMMC2_0, 0x154 */ - uint32_t _0x158[3]; - uint32_t clk_source_sdmmc4; /* _CLK_SOURCE_SDMMC4_0, 0x164 */ - uint32_t _0x168[4]; - uint32_t clk_source_uarta; /* _CLK_SOURCE_UARTA_0, 0x178 */ - uint32_t clk_source_uartb; /* _CLK_SOURCE_UARTB_0, 0x17c */ - uint32_t clk_source_host1x; /* _CLK_SOURCE_HOST1X_0, 0x180 */ - uint32_t _0x184[5]; - uint32_t clk_source_i2c2; /* _CLK_SOURCE_I2C2_0, 0x198 */ - uint32_t clk_source_emc; /* _CLK_SOURCE_EMC_0, 0x19c */ - uint32_t clk_source_uartc; /* _CLK_SOURCE_UARTC_0, 0x1a0 */ - uint32_t _0x1a4; - uint32_t clk_source_vi_sensor; /* _CLK_SOURCE_VI_SENSOR_0, 0x1a8 */ - uint32_t _0x1ac[2]; - uint32_t clk_source_spi4; /* _CLK_SOURCE_SPI4_0, 0x1b4 */ - uint32_t clk_source_i2c3; /* _CLK_SOURCE_I2C3_0, 0x1b8 */ - uint32_t clk_source_sdmmc3; /* _CLK_SOURCE_SDMMC3_0, 0x1bc */ - uint32_t clk_source_uartd; /* _CLK_SOURCE_UARTD_0, 0x1c0 */ - uint32_t _0x1c4[2]; - uint32_t clk_source_owr; /* _CLK_SOURCE_OWR_0, 0x1cc */ - uint32_t _0x1d0; - uint32_t clk_source_csite; /* _CLK_SOURCE_CSITE_0, 0x1d4 */ - uint32_t clk_source_i2s1; /* _CLK_SOURCE_I2S1_0, 0x1d8 */ - uint32_t clk_source_dtv; /* _CLK_SOURCE_DTV_0, 0x1dc */ - uint32_t _0x1e0[5]; - uint32_t clk_source_tsec; /* _CLK_SOURCE_TSEC_0, 0x1f4 */ - uint32_t _0x1f8; - - uint32_t clk_spare2; /* _CLK_SPARE2_0, 0x1fc */ - uint32_t _0x200[32]; - - uint32_t clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ - uint32_t clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ - uint32_t clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ - - uint32_t rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ - uint32_t rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ - uint32_t rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - - uint32_t clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ - uint32_t clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */ - uint32_t clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */ - - uint32_t rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */ - uint32_t rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */ - uint32_t rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */ - - uint32_t _0x2b0[17]; - uint32_t dfll_base; /* _DFLL_BASE_0, 0x2f4 */ - uint32_t _0x2f8[2]; - - /* _RST_DEV_L/H/U_SET_0 0x300-0x314 */ - uint32_t rst_dev_l_set; - uint32_t rst_dev_l_clr; - uint32_t rst_dev_h_set; - uint32_t rst_dev_h_clr; - uint32_t rst_dev_u_set; - uint32_t rst_dev_u_clr; - - uint32_t _0x318[2]; - - /* _CLK_ENB_L/H/U_CLR_0 0x320-0x334 */ - uint32_t clk_enb_l_set; - uint32_t clk_enb_l_clr; - uint32_t clk_enb_h_set; - uint32_t clk_enb_h_clr; - uint32_t clk_enb_u_set; - uint32_t clk_enb_u_clr; - - uint32_t _0x338; - uint32_t ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD_0, 0x33c */ - uint32_t rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ - uint32_t rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ - - /* Additional (T30) registers */ - uint32_t clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ - uint32_t clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ - - uint32_t _0x350[2]; - uint32_t rst_dev_v; /* _RST_DEVICES_V_0, 0x358 */ - uint32_t rst_dev_w; /* _RST_DEVICES_W_0, 0x35c */ - uint32_t clk_out_enb_v; /* _CLK_OUT_ENB_V_0, 0x360 */ - uint32_t clk_out_enb_w; /* _CLK_OUT_ENB_W_0, 0x364 */ - uint32_t cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ - uint32_t super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36c */ - uint32_t cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ - uint32_t super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ - uint32_t clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ - uint32_t clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37c */ - uint32_t cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - uint32_t cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ - uint32_t cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ - uint32_t _0x38c[5]; - uint32_t lvl2_clk_gate_ovrc; /* _LVL2_CLK_GATE_OVRC, 0x3a0 */ - uint32_t lvl2_clk_gate_ovrd; /* _LVL2_CLK_GATE_OVRD, 0x3a4 */ - uint32_t _0x3a8[2]; - - uint32_t _0x3b0; - uint32_t clk_source_mselect; /* _CLK_SOURCE_MSELECT_0, 0x3b4 */ - uint32_t clk_source_tsensor; /* _CLK_SOURCE_TSENSOR_0, 0x3b8 */ - uint32_t clk_source_i2s4; /* _CLK_SOURCE_I2S4_0, 0x3bc */ - uint32_t clk_source_i2s5; /* _CLK_SOURCE_I2S5_0, 0x3c0 */ - uint32_t clk_source_i2c4; /* _CLK_SOURCE_I2C4_0, 0x3c4 */ - uint32_t _0x3c8[2]; - uint32_t clk_source_ahub; /* _CLK_SOURCE_AHUB_0, 0x3d0 */ - uint32_t _0x3d4[4]; - uint32_t clk_source_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X_0, 0x3e4 */ - uint32_t clk_source_actmon; /* _CLK_SOURCE_ACTMON_0, 0x3e8 */ - uint32_t clk_source_extperiph1; /* _CLK_SOURCE_EXTPERIPH1_0, 0x3ec */ - uint32_t clk_source_extperiph2; /* _CLK_SOURCE_EXTPERIPH2_0, 0x3f0 */ - uint32_t clk_source_extperiph3; /* _CLK_SOURCE_EXTPERIPH3_0, 0x3f4 */ - uint32_t _0x3f8; - uint32_t clk_source_i2c_slow; /* _CLK_SOURCE_I2C_SLOW_0, 0x3fc */ - uint32_t clk_source_sys; /* _CLK_SOURCE_SYS_0, 0x400 */ - uint32_t clk_source_ispb; /* _CLK_SOURCE_ISPB_0, 0x404 */ - uint32_t _0x408[2]; - uint32_t clk_source_sor1; /* _CLK_SOURCE_SOR1_0, 0x410 */ - uint32_t clk_source_sor0; /* _CLK_SOURCE_SOR0_0, 0x414 */ - uint32_t _0x418[2]; - uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */ - uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */ - uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */ - uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */ - - /* _RST_DEV_V/W_SET_0 0x430-0x43c */ - uint32_t rst_dev_v_set; - uint32_t rst_dev_v_clr; - uint32_t rst_dev_w_set; - uint32_t rst_dev_w_clr; - - /* _CLK_ENB_V/W_CLR_0 0x440-0x44c */ - uint32_t clk_enb_v_set; - uint32_t clk_enb_v_clr; - uint32_t clk_enb_w_set; - uint32_t clk_enb_w_clr; - - /* Additional (T114+) registers */ - uint32_t rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ - uint32_t rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ - uint32_t rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ - uint32_t rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45c */ - uint32_t clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ - uint32_t clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ - uint32_t clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ - uint32_t clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46c */ - uint32_t cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ - uint32_t _0x474; - uint32_t intstatus; /* _INTSTATUS_0, 0x478 */ - uint32_t intmask; /* _INTMASK_0, 0x47c */ - uint32_t utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ - uint32_t utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ - uint32_t utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ - - uint32_t plle_aux; /* _PLLE_AUX_0, 0x48c */ - uint32_t sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ - uint32_t sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ - uint32_t pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ - - uint32_t prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49c */ - uint32_t audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4a0 */ - uint32_t audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4a4 */ - uint32_t audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4a8 */ - uint32_t audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4ac */ - uint32_t audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4b0 */ - uint32_t audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4b4 */ - - uint32_t plld2_base; /* _PLLD2_BASE_0, 0x4b8 */ - uint32_t plld2_misc; /* _PLLD2_MISC_0, 0x4bc */ - uint32_t utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4c0 */ - uint32_t pllrefe_base; /* _PLLREFE_BASE_0, 0x4c4 */ - uint32_t pllrefe_misc; /* _PLLREFE_MISC_0, 0x4c8 */ - uint32_t pllrefe_out; /* _PLLREFE_OUT_0, 0x4cc */ - uint32_t cpu_finetrim_byp; /* _CPU_FINETRIM_BYP_0, 0x4d0 */ - uint32_t cpu_finetrim_select; /* _CPU_FINETRIM_SELECT_0, 0x4d4 */ - uint32_t cpu_finetrim_dr; /* _CPU_FINETRIM_DR_0, 0x4d8 */ - uint32_t cpu_finetrim_df; /* _CPU_FINETRIM_DF_0, 0x4dc */ - uint32_t cpu_finetrim_f; /* _CPU_FINETRIM_F_0, 0x4e0 */ - uint32_t cpu_finetrim_r; /* _CPU_FINETRIM_R_0, 0x4e4 */ - uint32_t pllc2_base; /* _PLLC2_BASE_0, 0x4e8 */ - uint32_t pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4ec */ - uint32_t pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4f0 */ - uint32_t pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4f4 */ - uint32_t pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4f8 */ - uint32_t pllc3_base; /* _PLLC3_BASE_0, 0x4fc */ - uint32_t pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ - uint32_t pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ - uint32_t pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ - uint32_t pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50c */ - uint32_t pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ - uint32_t pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ - uint32_t pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ - uint32_t xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51c */ - uint32_t xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ - uint32_t plle_aux1; /* _PLLE_AUX1_0, 0x524 */ - uint32_t pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ - uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52c */ - uint32_t pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ - uint32_t xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ - uint32_t _0x538; - uint32_t clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53c */ - uint32_t clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ - uint32_t clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ - uint32_t pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ - uint32_t pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54c */ - uint32_t pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ - uint32_t lvl2_clk_gate_ovre; /* _LVL2_CLK_GATE_OVRE, 0x554 */ - uint32_t super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ - uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55c */ - uint32_t audio_sync_clk_dmic1; /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */ - uint32_t audio_sync_clk_dmic2; /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */ - - uint32_t _0x568[2]; - uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG, 0x570 */ - uint32_t plld2_ss_ctrl1; /* _PLLD2_SS_CTRL1_0, 0x574 */ - uint32_t plld2_ss_ctrl2; /* _PLLD2_SS_CTRL2_0, 0x578 */ - uint32_t _0x57c[5]; - - uint32_t plldp_base; /* _PLLDP_BASE, 0x590*/ - uint32_t plldp_misc; /* _PLLDP_MISC, 0x594 */ - uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ - uint32_t plldp_ss_ctrl1; /* _PLLDP_SS_CTRL1_0, 0x59c */ - uint32_t plldp_ss_ctrl2; /* _PLLDP_SS_CTRL2_0, 0x5a0 */ - uint32_t pllc4_base; /* _PLLC4_BASE_0, 0x5a4 */ - uint32_t pllc4_misc; /* _PLLC4_MISC_0, 0x5a8 */ - uint32_t _0x5ac[6]; - uint32_t clk_spare0; /* _CLK_SPARE0_0, 0x5c4 */ - uint32_t clk_spare1; /* _CLK_SPARE1_0, 0x5c8 */ - uint32_t gpu_isob_ctrl; /* _GPU_ISOB_CTRL_0, 0x5cc */ - uint32_t pllc_misc2; /* _PLLC_MISC_2_0, 0x5d0 */ - uint32_t pllc_misc3; /* _PLLC_MISC_3_0, 0x5d4 */ - uint32_t plla_misc2; /* _PLLA_MISC2_0, 0x5d8 */ - uint32_t _0x5dc[2]; - uint32_t pllc4_out; /* _PLLC4_OUT_0, 0x5e4 */ - uint32_t pllmb_base; /* _PLLMB_BASE_0, 0x5e8 */ - uint32_t pllmb_misc1; /* _PLLMB_MISC1_0, 0x5ec */ - uint32_t pllx_misc4; /* _PLLX_MISC_4_0, 0x5f0 */ - uint32_t pllx_misc5; /* _PLLX_MISC_5_0, 0x5f4 */ - uint32_t _0x5f8[2]; - - uint32_t clk_source_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST_0, 0x600 */ - uint32_t clk_source_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON_0, 0x604 */ - uint32_t clk_source_xusb_fs; /* _CLK_SOURCE_XUSB_FS_0, 0x608 */ - uint32_t clk_source_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV_0, 0x60c */ - uint32_t clk_source_xusb_ss; /* _CLK_SOURCE_XUSB_SS_0, 0x610 */ - uint32_t clk_source_cilab; /* _CLK_SOURCE_CILAB_0, 0x614 */ - uint32_t clk_source_cilcd; /* _CLK_SOURCE_CILCD_0, 0x618 */ - uint32_t clk_source_cilef; /* _CLK_SOURCE_CILEF_0, 0x61c */ - uint32_t clk_source_dsia_lp; /* _CLK_SOURCE_DSIA_LP_0, 0x620 */ - uint32_t clk_source_dsib_lp; /* _CLK_SOURCE_DSIB_LP_0, 0x624 */ - uint32_t clk_source_entropy; /* _CLK_SOURCE_ENTROPY_0, 0x628 */ - uint32_t clk_source_dvfs_ref; /* _CLK_SOURCE_DVFS_REF_0, 0x62c */ - uint32_t clk_source_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC_0, 0x630 */ - uint32_t _0x634[3]; - uint32_t clk_source_emc_latency; /* _CLK_SOURCE_EMC_LATENCY_0, 0x640 */ - uint32_t clk_source_soc_therm; /* _CLK_SOURCE_SOC_THERM_0, 0x644 */ - uint32_t _0x648; - uint32_t clk_source_dmic1; /* _CLK_SOURCE_DMIC1_0, 0x64c */ - uint32_t clk_source_dmic2; /* _CLK_SOURCE_DMIC2_0, 0x650 */ - uint32_t _0x654; - uint32_t clk_source_vi_sensor2; /* _CLK_SOURCE_VI_SENSOR2_0, 0x658 */ - uint32_t clk_source_i2c6; /* _CLK_SOURCE_I2C6_0, 0x65c */ - uint32_t clk_source_mipibif; /* _CLK_SOURCE_MIPIBIF_0, 0x660 */ - uint32_t clk_source_emc_dll; /* _CLK_SOURCE_EMC_DLL_0, 0x664 */ - uint32_t _0x668; - uint32_t clk_source_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIPI_CAL_0, 0x66c */ - uint32_t _0x670[2]; - uint32_t clk_source_vic; /* _CLK_SOURCE_VIC_0, 0x678 */ - - uint32_t pllp_outc; /* _PLLP_OUTC_0, 0x67c */ - uint32_t pllp_misc1; /* _PLLP_MISC1_0, 0x680 */ - uint32_t _0x684[2]; - uint32_t emc_div_clk_shaper_ctrl; /* _EMC_DIV_CLK_SHAPER_CTRL_0, 0x68c */ - uint32_t emc_pllc_shaper_ctrl; /* _EMC_PLLC_SHAPER_CTRL_0, 0x690 */ - - uint32_t clk_source_sdmmc_legacy_tm; /* _CLK_SOURCE_SDMMC_LEGACY_TM_0, 0x694 */ - uint32_t clk_source_nvdec; /* _CLK_SOURCE_NVDEC_0, 0x698 */ - uint32_t clk_source_nvjpg; /* _CLK_SOURCE_NVJPG_0, 0x69c */ - uint32_t clk_source_nvenc; /* _CLK_SOURCE_NVENC_0, 0x6a0 */ - - uint32_t plla1_base; /* _PLLA1_BASE_0, 0x6a4 */ - uint32_t plla1_misc0; /* _PLLA1_MISC_0_0, 0x6a8 */ - uint32_t plla1_misc1; /* _PLLA1_MISC_1_0, 0x6ac */ - uint32_t plla1_misc2; /* _PLLA1_MISC_2_0, 0x6b0 */ - uint32_t plla1_misc3; /* _PLLA1_MISC_3_0, 0x6b4 */ - uint32_t audio_sync_clk_dmic3; /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */ - - uint32_t clk_source_dmic3; /* _CLK_SOURCE_DMIC3_0, 0x6bc */ - uint32_t clk_source_ape; /* _CLK_SOURCE_APE_0, 0x6c0 */ - uint32_t clk_source_qspi; /* _CLK_SOURCE_QSPI_0, 0x6c4 */ - uint32_t clk_source_vi_i2c; /* _CLK_SOURCE_VI_I2C_0, 0x6c8 */ - uint32_t clk_source_usb2_hsic_trk; /* _CLK_SOURCE_USB2_HSIC_TRK_0, 0x6cc */ - uint32_t clk_source_pex_sata_usb_rx_byp; /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0, 0x6d0 */ - uint32_t clk_source_maud; /* _CLK_SOURCE_MAUD_0, 0x6d4 */ - uint32_t clk_source_tsecb; /* _CLK_SOURCE_TSECB_0, 0x6d8 */ - - uint32_t clk_cpug_misc1; /* _CLK_CPUG_MISC1_0, 0x6dc */ - uint32_t aclk_burst_policy; /* _ACLK_BURST_POLICY_0, 0x6e0 */ - uint32_t super_aclk_divider; /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */ - - uint32_t nvenc_super_clk_divider; /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */ - uint32_t vi_super_clk_divider; /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */ - uint32_t vic_super_clk_divider; /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */ - uint32_t nvdec_super_clk_divider; /* _NVDEC_SUPER_CLK_DIVIDER_0, 0x6f4 */ - uint32_t isp_super_clk_divider; /* _ISP_SUPER_CLK_DIVIDER_0, 0x6f8 */ - uint32_t ispb_super_clk_divider; /* _ISPB_SUPER_CLK_DIVIDER_0, 0x6fc */ - uint32_t nvjpg_super_clk_divider; /* _NVJPG_SUPER_CLK_DIVIDER_0, 0x700 */ - uint32_t se_super_clk_divider; /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */ - uint32_t tsec_super_clk_divider; /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */ - uint32_t tsecb_super_clk_divider; /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */ - - uint32_t clk_source_uartape; /* _CLK_SOURCE_UARTAPE_0, 0x710 */ - uint32_t clk_cpug_misc2; /* _CLK_CPUG_MISC2_0, 0x714 */ - uint32_t clk_source_dbgapb; /* _CLK_SOURCE_DBGAPB_0, 0x718 */ - uint32_t clk_ccplex_cc4_ret_clk_enb; /* _CLK_CCPLEX_CC4_RET_CLK_ENB_0, 0x71c */ - uint32_t actmon_cpu_clk; /* _ACTMON_CPU_CLK_0, 0x720 */ - uint32_t clk_source_emc_safe; /* _CLK_SOURCE_EMC_SAFE_0, 0x724 */ - uint32_t sdmmc2_pllc4_out0_shaper_ctrl; /* _SDMMC2_PLLC4_OUT0_SHAPER_CTRL_0, 0x728 */ - uint32_t sdmmc2_pllc4_out1_shaper_ctrl; /* _SDMMC2_PLLC4_OUT1_SHAPER_CTRL_0, 0x72c */ - uint32_t sdmmc2_pllc4_out2_shaper_ctrl; /* _SDMMC2_PLLC4_OUT2_SHAPER_CTRL_0, 0x730 */ - uint32_t sdmmc2_div_clk_shaper_ctrl; /* _SDMMC2_DIV_CLK_SHAPER_CTRL_0, 0x734 */ - uint32_t sdmmc4_pllc4_out0_shaper_ctrl; /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */ - uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */ - uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */ - uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */ -} tegra_car_t; - -static inline volatile tegra_car_t *car_get_regs(void) { - return (volatile tegra_car_t *)CAR_BASE; -} - -void clk_enable(CarDevice dev); -void clk_disable(CarDevice dev); -void rst_enable(CarDevice dev); -void rst_disable(CarDevice dev); - -void clkrst_enable(CarDevice dev); -void clkrst_disable(CarDevice dev); -void clkrst_reboot(CarDevice dev); - -void clkrst_enable_fuse_regs(bool enable); - -#endif diff --git a/sept/sept-secondary/src/chainloader.c b/sept/sept-secondary/src/chainloader.c deleted file mode 100644 index aa9979982..000000000 --- a/sept/sept-secondary/src/chainloader.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "chainloader.h" - -int g_chainloader_argc = 0; -char g_chainloader_arg_data[CHAINLOADER_ARG_DATA_MAX_SIZE] = {0}; -chainloader_entry_t g_chainloader_entries[CHAINLOADER_MAX_ENTRIES] = {0}; /* keep them sorted */ -size_t g_chainloader_num_entries = 0; -uintptr_t g_chainloader_entrypoint = 0; - -#pragma GCC optimize (3) - -static void *xmemmove(void *dst, const void *src, size_t len) -{ - const uint8_t *src8 = (const uint8_t *)src; - uint8_t *dst8 = (uint8_t *)dst; - - if (dst8 < src8) { - for (size_t i = 0; i < len; i++) { - dst8[i] = src8[i]; - } - } else if (dst8 > src8) { - for (size_t i = len; len > 0; len--) - dst8[i - 1] = src8[i - 1]; - } - - return dst; -} - -void relocate_and_chainload_main(void) { - for(size_t i = 0; i < g_chainloader_num_entries; i++) { - chainloader_entry_t *entry = &g_chainloader_entries[i]; - xmemmove((void *)entry->load_address, (const void *)entry->src_address, entry->size); - } - - ((void (*)(int, void *))g_chainloader_entrypoint)(g_chainloader_argc, g_chainloader_arg_data); -} diff --git a/sept/sept-secondary/src/chainloader.h b/sept/sept-secondary/src/chainloader.h deleted file mode 100644 index f08bf6396..000000000 --- a/sept/sept-secondary/src/chainloader.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_CHAINLOADER_H -#define FUSEE_CHAINLOADER_H - -#include -#include - -#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x5400 -#define CHAINLOADER_MAX_ENTRIES 128 - -typedef struct chainloader_entry_t { - uintptr_t load_address; - uintptr_t src_address; - size_t size; - size_t num; -} chainloader_entry_t; - -extern int g_chainloader_argc; -extern chainloader_entry_t g_chainloader_entries[CHAINLOADER_MAX_ENTRIES]; /* keep them sorted */ -extern size_t g_chainloader_num_entries; -extern uintptr_t g_chainloader_entrypoint; - -extern char g_chainloader_arg_data[CHAINLOADER_ARG_DATA_MAX_SIZE]; - -void relocate_and_chainload(void); - -#endif diff --git a/sept/sept-secondary/src/cluster.c b/sept/sept-secondary/src/cluster.c deleted file mode 100644 index 8a0c395df..000000000 --- a/sept/sept-secondary/src/cluster.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "cluster.h" -#include "flow.h" -#include "sysreg.h" -#include "i2c.h" -#include "car.h" -#include "mc.h" -#include "timers.h" -#include "pmc.h" -#include "max77620.h" - -void _cluster_enable_power() -{ - /* Reboot I2C5. */ - clkrst_reboot(CARDEVICE_I2C5); - i2c_init(I2C_5); - - uint8_t val = 0; - i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1); - - val &= 0xDF; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_AME_GPIO, &val, 1); - val = 0x09; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO5, &val, 1); - - /* Enable power. */ - val = 0x20; - i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x02, &val, 1); - val = 0x8D; - i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x03, &val, 1); - val = 0xB7; - i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x00, &val, 1); - val = 0xB7; - i2c_send(I2C_5, MAX77621_CPU_I2C_ADDR, 0x01, &val, 1); -} - -int _cluster_pmc_enable_partition(uint32_t part, uint32_t toggle) -{ - volatile tegra_pmc_t *pmc = pmc_get_regs(); - - /* Check if the partition has already been turned on. */ - if (pmc->pwrgate_status & part) - return 1; - - uint32_t i = 5001; - while (pmc->pwrgate_toggle & 0x100) - { - udelay(1); - i--; - if (i < 1) - return 0; - } - - pmc->pwrgate_toggle = (toggle | 0x100); - - i = 5001; - while (i > 0) - { - if (pmc->pwrgate_status & part) - break; - - udelay(1); - i--; - } - - return 1; -} - -void cluster_boot_cpu0(uint32_t entry) -{ - volatile tegra_car_t *car = car_get_regs(); - - /* Set ACTIVE_CLUSER to FAST. */ - FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 &= 0xFFFFFFFE; - - _cluster_enable_power(); - - if (!(car->pllx_base & 0x40000000)) - { - car->pllx_misc3 &= 0xFFFFFFF7; - udelay(2); - car->pllx_base = 0x80404E02; - car->pllx_base = 0x404E02; - car->pllx_misc = ((car->pllx_misc & 0xFFFBFFFF) | 0x40000); - car->pllx_base = 0x40404E02; - } - - while (!(car->pllx_base & 0x8000000)) { - /* Wait. */ - } - - /* Configure MSELECT source and enable clock. */ - car->clk_source_mselect = ((car->clk_source_mselect & 0x1FFFFF00) | 6); - car->clk_out_enb_v = ((car->clk_out_enb_v & 0xFFFFFFF7) | 8); - - /* Configure initial CPU clock frequency and enable clock. */ - car->cclk_brst_pol = 0x20008888; - car->super_cclk_div = 0x80000000; - car->clk_enb_v_set = 1; - - clkrst_reboot(CARDEVICE_CORESIGHT); - - /* CAR2PMC_CPU_ACK_WIDTH should be set to 0. */ - car->cpu_softrst_ctrl2 &= 0xFFFFF000; - - /* Enable CPU rail. */ - _cluster_pmc_enable_partition(1, 0); - - /* Enable cluster 0 non-CPU. */ - _cluster_pmc_enable_partition(0x8000, 15); - - /* Enable CE0. */ - _cluster_pmc_enable_partition(0x4000, 14); - - /* Request and wait for RAM repair. */ - FLOW_CTLR_RAM_REPAIR_0 = 1; - while (!(FLOW_CTLR_RAM_REPAIR_0 & 2)) { - /* Wait. */ - } - - MAKE_EXCP_VEC_REG(0x100) = 0; - - /* Check for reset vector lock. */ - if (SB_CSR_0 & 2) { - generic_panic(); - } - - /* Set reset vector. */ - SB_AA64_RESET_LOW_0 = (entry | 1); - SB_AA64_RESET_HIGH_0 = 0; - - /* Non-secure reset vector write disable. */ - SB_CSR_0 = 2; - (void)SB_CSR_0; - - /* Validate reset vector lock + RESET_LOW/HIGH values. */ - if (!(SB_CSR_0 & 2)) { - generic_panic(); - } - - /* TODO: Should we even bother taking as a parameter? */ - if (SB_AA64_RESET_LOW_0 != (0x4003D000 | 1) || SB_AA64_RESET_HIGH_0 != 0) { - generic_panic(); - } - - /* Set CPU_STRICT_TZ_APERTURE_CHECK. */ - /* NOTE: [4.0.0+] This was added, but it breaks Exosphère. */ - /* MAKE_MC_REG(MC_TZ_SECURITY_CTRL) = 1; */ - - /* Clear MSELECT reset. */ - car->rst_dev_v &= 0xFFFFFFF7; - - /* Clear NONCPU reset. */ - car->rst_cpug_cmplx_clr = 0x20000000; - - /* Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.*/ - /* NOTE: [5.0.0+] This was changed so only CPU0 reset is cleared. */ - /* car->rst_cpug_cmplx_clr = 0x411F000F; */ - car->rst_cpug_cmplx_clr = 0x41010001; -} diff --git a/sept/sept-secondary/src/cluster.h b/sept/sept-secondary/src/cluster.h deleted file mode 100644 index 802b54396..000000000 --- a/sept/sept-secondary/src/cluster.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_CLUSTER_H_ -#define FUSEE_CLUSTER_H_ - -void cluster_boot_cpu0(uint32_t entry); - -#endif diff --git a/sept/sept-secondary/src/di.c b/sept/sept-secondary/src/di.c deleted file mode 100644 index 59cc1e44f..000000000 --- a/sept/sept-secondary/src/di.c +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "di.h" -#include "fuse.h" -#include "timers.h" -#include "i2c.h" -#include "pmc.h" -#include "max77620.h" -#include "gpio.h" -#include "pinmux.h" -#include "car.h" -#include "apb_misc.h" - -#include "di.inl" - -static uint32_t g_lcd_vendor = 0; - -/* Determine the current SoC for Mariko specific code. */ -static bool is_soc_mariko() { - return (fuse_get_soc_type() == 1); -} - -static void do_dsi_sleep_or_register_writes(const dsi_sleep_or_register_write_t *writes, uint32_t num_writes) { - for (uint32_t i = 0; i < num_writes; i++) { - if (writes[i].kind == 1) { - udelay(1000 * writes[i].offset); - } else { - *(volatile uint32_t *)(DSI_BASE + sizeof(uint32_t) * writes[i].offset) = writes[i].value; - } - } -} - -static void do_register_writes(uint32_t base_address, const register_write_t *writes, uint32_t num_writes) { - for (uint32_t i = 0; i < num_writes; i++) { - *(volatile uint32_t *)(base_address + writes[i].offset) = writes[i].value; - } -} - -static void dsi_wait(uint32_t timeout, uint32_t offset, uint32_t mask, uint32_t delay) { - uint32_t end = get_time_us() + timeout; - while ((get_time_us() < end) && (MAKE_DSI_REG(offset) & mask)) { - /* Wait. */ - } - udelay(delay); -} - -void display_init(void) { - volatile tegra_car_t *car = car_get_regs(); - volatile tegra_pmc_t *pmc = pmc_get_regs(); - volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); - bool is_mariko = is_soc_mariko(); - uint32_t hardware_type = fuse_get_hardware_type(); - - /* Power on. */ - if (is_mariko) { - uint8_t val = 0x3A; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2, &val, 1); - val = 0x71; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2_CFG, &val, 1); - val = 0xD0; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1); - } else { - uint8_t val = 0xD0; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1); - } - - /* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */ - car->rst_dev_h_clr = 0x1010000; - car->clk_enb_h_set = 0x1010000; - car->rst_dev_l_clr = 0x18000000; - car->clk_enb_l_set = 0x18000000; - car->clk_enb_x_set = 0x20000; - car->clk_source_uart_fst_mipi_cal = 0xA; - car->clk_enb_w_set = 0x80000; - car->clk_source_dsia_lp = 0xA; - - /* DPD idle. */ - pmc->io_dpd_req = 0x40000000; - pmc->io_dpd2_req = 0x40000000; - - /* Configure pins. */ - pinmux->nfc_en &= ~PINMUX_TRISTATE; - pinmux->nfc_int &= ~PINMUX_TRISTATE; - pinmux->lcd_bl_pwm &= ~PINMUX_TRISTATE; - pinmux->lcd_bl_en &= ~PINMUX_TRISTATE; - pinmux->lcd_rst &= ~PINMUX_TRISTATE; - - if (is_mariko && (hardware_type == 5)) { - /* HardwareType_Five only configures GPIO_LCD_BL_RST. */ - gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO); - gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT); - } else { - /* Configure Backlight +-5V GPIOs. */ - gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO); - gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO); - gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT); - gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT); - - /* Enable Backlight +5V. */ - gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH); - - udelay(10000); - - /* Enable Backlight -5V. */ - gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH); - - udelay(10000); - - /* Configure Backlight PWM, EN and RST GPIOs. */ - gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO); - gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO); - gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO); - gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT); - gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT); - gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT); - - /* Enable Backlight EN. */ - gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH); - } - - /* Configure display interface and display. */ - MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0; - if (is_mariko) { - MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG0) = 0; - APB_MISC_GP_DSI_PAD_CONTROL_0 = 0; - } - - if (is_mariko) { - do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4); - } else { - do_register_writes(CAR_BASE, display_config_plld_01_erista, 4); - } - do_register_writes(DI_BASE, display_config_dc_01, 94); - do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); - if (is_mariko) { - do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1); - } else { - do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1); - } - do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 14); - if (is_mariko) { - do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7); - } else { - do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0); - } - do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 10); - if (is_mariko) { - do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); - } else { - do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); - } - do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); - if (is_mariko) { - do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); - } else { - do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); - } - do_register_writes(DSI_BASE, display_config_dsi_01_init_07, 14); - - udelay(10000); - - /* Enable Backlight RST. */ - gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH); - - udelay(60000); - - if (is_mariko && (hardware_type == 5)) { - MAKE_DSI_REG(DSI_BTA_TIMING) = 0x40103; - } else { - MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204; - } - MAKE_DSI_REG(DSI_WR_DATA) = 0x337; - MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); - - MAKE_DSI_REG(DSI_WR_DATA) = 0x406; - MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5); - - MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC); - dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA, 5000); - - /* Parse LCD vendor. */ - uint32_t host_response[3]; - for (uint32_t i = 0; i < 3; i++) { - host_response[i] = MAKE_DSI_REG(DSI_RD_DATA); - } - - /* The last word from host response is: - Bits 0-7: FAB - Bits 8-15: REV - Bits 16-23: Minor REV - */ - if ((host_response[2] & 0xFF) == 0x10) { - g_lcd_vendor = 0; - } else { - g_lcd_vendor = (host_response[2] >> 8) & 0xFF00; - } - g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF); - - /* LCD vendor specific configuration. */ - switch (g_lcd_vendor) { - case 0x10: /* Japan Display Inc screens. */ - do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48); - break; - case 0xF20: /* Innolux nx-abca2 screens. */ - do_dsi_sleep_or_register_writes(display_config_innolux_nx_abca2_specific_init_01, 14); - break; - case 0xF30: /* AUO nx-abca2 screens. */ - do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_init_01, 14); - break; - case 0x2050: /* Unknown nx-abcd screens. */ - do_dsi_sleep_or_register_writes(display_config_50_nx_abcd_specific_init_01, 13); - break; - case 0x1020: /* Innolux nx-abcc screens. */ - case 0x1030: /* AUO nx-abcc screens. */ - case 0x1040: /* Unknown nx-abcc screens. */ - default: - do_dsi_sleep_or_register_writes(display_config_innolux_auo_40_nx_abcc_specific_init_01, 5); - break; - } - - udelay(20000); - - if (is_mariko) { - do_register_writes(CAR_BASE, display_config_plld_02_mariko, 3); - } else { - do_register_writes(CAR_BASE, display_config_plld_02_erista, 3); - } - do_register_writes(DSI_BASE, display_config_dsi_01_init_08, 1); - if (is_mariko) { - do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); - } else { - do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); - } - do_register_writes(DSI_BASE, display_config_dsi_01_init_09, 19); - MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4; - do_register_writes(DSI_BASE, display_config_dsi_01_init_10, 10); - - udelay(10000); - - if (is_mariko) { - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4); - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2); - do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7); - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6); - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2); - do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7); - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6); - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); - } else { - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4); - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_erista, 2); - do_register_writes(DSI_BASE, display_config_dsi_01_init_11_erista, 4); - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_erista, 6); - do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10); - } - - udelay(10000); - - do_register_writes(DI_BASE, display_config_dc_02, 113); -} - -void display_end(void) { - volatile tegra_car_t *car = car_get_regs(); - volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); - bool is_mariko = is_soc_mariko(); - - /* Disable Backlight. */ - display_backlight(false); - - MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; - MAKE_DSI_REG(DSI_WR_DATA) = 0x2805; - - /* Wait 5 frames. */ - uint32_t start_val = MAKE_HOST1X_REG(0x30A4); - while (MAKE_HOST1X_REG(0x30A4) < start_val + 5) { - /* Wait. */ - } - - MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX); - MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; - - do_register_writes(DI_BASE, display_config_dc_01_fini_01, 13); - udelay(40000); - - if (is_mariko) { - do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4); - } else { - do_register_writes(CAR_BASE, display_config_plld_01_erista, 4); - } - do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2); - if (is_mariko) { - do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); - } else { - do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); - } - do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13); - - if (g_lcd_vendor != 0x2050) { - udelay(10000); - } - - /* LCD vendor specific shutdown. */ - switch (g_lcd_vendor) { - case 0x10: /* Japan Display Inc screens. */ - do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22); - break; - case 0xF30: /* AUO nx-abca2 screens. */ - do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_fini_01, 38); - break; - case 0x1020: /* Innolux nx-abcc screens. */ - do_dsi_sleep_or_register_writes(display_config_innolux_nx_abcc_specific_fini_01, 10); - break; - case 0x1030: /* AUO nx-abcc screens. */ - do_dsi_sleep_or_register_writes(display_config_auo_nx_abcc_specific_fini_01, 10); - break; - case 0x1040: /* Unknown nx-abcc screens. */ - do_dsi_sleep_or_register_writes(display_config_40_nx_abcc_specific_fini_01, 10); - break; - default: - break; - } - - MAKE_DSI_REG(DSI_WR_DATA) = 0x1005; - MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST; - udelay((g_lcd_vendor == 0x2050) ? 120000 : 50000); - - /* Disable Backlight RST. */ - gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW); - - if (g_lcd_vendor == 0x2050) { - udelay(30000); - } else { - udelay(10000); - - /* Disable Backlight -5V. */ - gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW); - - udelay(10000); - - /* Disable Backlight +5V. */ - gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW); - - udelay(10000); - } - - /* Disable clocks. */ - car->rst_dev_h_set = 0x1010000; - car->clk_enb_h_clr = 0x1010000; - car->rst_dev_l_set = 0x18000000; - car->clk_enb_l_clr = 0x18000000; - - MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF)); - MAKE_DSI_REG(DSI_POWER_CONTROL) = 0; - - if (!is_mariko) { - /* Backlight PWM. */ - gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO); - - pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE); - pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1); - } -} - -void display_backlight(bool enable) { - if (g_lcd_vendor == 0x2050) { - int brightness = enable ? 100 : 0; - - /* Enable FRAME_END_INT */ - MAKE_DI_REG(DC_CMD_INT_ENABLE) = 2; - - /* Configure DSI_LINE_TYPE as FOUR */ - MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1; - MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 9; - - /* Set and wait for FRAME_END_INT */ - MAKE_DI_REG(DC_CMD_INT_STATUS) = 2; - while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) { - /* Wait */ - } - - /* Configure display brightness. */ - const uint32_t brightness_val = ((0x7FF * brightness) / 100); - MAKE_DSI_REG(DSI_WR_DATA) = 0x339; - MAKE_DSI_REG(DSI_WR_DATA) = (brightness_val & 0x700) | ((brightness_val & 0xFF) << 16) | 0x51; - - /* Set and wait for FRAME_END_INT */ - MAKE_DI_REG(DC_CMD_INT_STATUS) = 2; - while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) { - /* Wait */ - } - - /* Set client sync point block reset. */ - MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 1; - udelay(300000); - - /* Clear client sync point block resest. */ - MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 0; - udelay(300000); - - /* Clear DSI_LINE_TYPE config. */ - MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0; - - /* Disable FRAME_END_INT */ - MAKE_DI_REG(DC_CMD_INT_ENABLE) = 0; - MAKE_DI_REG(DC_CMD_INT_STATUS) = 2; - } else { - /* Enable Backlight PWM. */ - gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); - } -} - -void display_color_screen(uint32_t color) { - do_register_writes(DI_BASE, display_config_solid_color, 8); - - /* Configure display to show single color. */ - MAKE_DI_REG(DC_WIN_AD_WIN_OPTIONS) = 0; - MAKE_DI_REG(DC_WIN_BD_WIN_OPTIONS) = 0; - MAKE_DI_REG(DC_WIN_CD_WIN_OPTIONS) = 0; - MAKE_DI_REG(DC_DISP_BLEND_BACKGROUND_COLOR) = color; - MAKE_DI_REG(DC_CMD_STATE_CONTROL) = ((MAKE_DI_REG(DC_CMD_STATE_CONTROL) & 0xFFFFFFFE) | GENERAL_ACT_REQ); - - udelay(35000); - - display_backlight(true); -} - -uint32_t *display_init_framebuffer(void *address) { - static register_write_t conf[sizeof(display_config_frame_buffer)/sizeof(register_write_t)] = {0}; - if (conf[0].value == 0) { - for (uint32_t i = 0; i < sizeof(display_config_frame_buffer)/sizeof(register_write_t); i++) { - conf[i] = display_config_frame_buffer[i]; - } - } - - uint32_t *lfb_addr = (uint32_t *)address; - conf[19].value = (uint32_t)address; - - /* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */ - do_register_writes(DI_BASE, conf, 32); - - udelay(35000); - - return lfb_addr; -} diff --git a/sept/sept-secondary/src/di.h b/sept/sept-secondary/src/di.h deleted file mode 100644 index 4beeb862c..000000000 --- a/sept/sept-secondary/src/di.h +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_DI_H_ -#define FUSEE_DI_H_ - -#include -#include - -#define HOST1X_BASE 0x50000000 -#define DI_BASE 0x54200000 -#define DSI_BASE 0x54300000 -#define VIC_BASE 0x54340000 -#define MIPI_CAL_BASE 0x700E3000 -#define MAKE_HOST1X_REG(n) MAKE_REG32(HOST1X_BASE + n) -#define MAKE_DI_REG(n) MAKE_REG32(DI_BASE + n * 4) -#define MAKE_DSI_REG(n) MAKE_REG32(DSI_BASE + n * 4) -#define MAKE_MIPI_CAL_REG(n) MAKE_REG32(MIPI_CAL_BASE + n) -#define MAKE_VIC_REG(n) MAKE_REG32(VIC_BASE + n) - -/* Clock and reset registers. */ -#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138 -#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0 -#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8 -#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC - -/* Display registers. */ -#define DC_CMD_GENERAL_INCR_SYNCPT 0x00 - -#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01 -#define SYNCPT_CNTRL_NO_STALL (1 << 8) -#define SYNCPT_CNTRL_SOFT_RESET (1 << 0) - -#define DC_CMD_CONT_SYNCPT_VSYNC 0x28 -#define SYNCPT_VSYNC_ENABLE (1 << 8) - -#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 - -#define DC_CMD_DISPLAY_COMMAND 0x32 -#define DISP_CTRL_MODE_STOP (0 << 5) -#define DISP_CTRL_MODE_C_DISPLAY (1 << 5) -#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) -#define DISP_CTRL_MODE_MASK (3 << 5) - -#define DC_CMD_DISPLAY_POWER_CONTROL 0x36 -#define PW0_ENABLE (1 << 0) -#define PW1_ENABLE (1 << 2) -#define PW2_ENABLE (1 << 4) -#define PW3_ENABLE (1 << 6) -#define PW4_ENABLE (1 << 8) -#define PM0_ENABLE (1 << 16) -#define PM1_ENABLE (1 << 18) - -#define DC_CMD_INT_STATUS 0x37 -#define DC_CMD_INT_MASK 0x38 -#define DC_CMD_INT_ENABLE 0x39 - -#define DC_CMD_STATE_ACCESS 0x40 -#define READ_MUX (1 << 0) -#define WRITE_MUX (1 << 2) - -#define DC_CMD_STATE_CONTROL 0x41 -#define GENERAL_ACT_REQ (1 << 0) -#define WIN_A_ACT_REQ (1 << 1) -#define WIN_B_ACT_REQ (1 << 2) -#define WIN_C_ACT_REQ (1 << 3) -#define CURSOR_ACT_REQ (1 << 7) -#define GENERAL_UPDATE (1 << 8) -#define WIN_A_UPDATE (1 << 9) -#define WIN_B_UPDATE (1 << 10) -#define WIN_C_UPDATE (1 << 11) -#define CURSOR_UPDATE (1 << 15) -#define NC_HOST_TRIG (1 << 24) - -#define DC_CMD_DISPLAY_WINDOW_HEADER 0x42 -#define WINDOW_A_SELECT (1 << 4) -#define WINDOW_B_SELECT (1 << 5) -#define WINDOW_C_SELECT (1 << 6) - -#define DC_CMD_REG_ACT_CONTROL 0x043 - -#define DC_COM_CRC_CONTROL 0x300 -#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) -#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) - -#define DC_COM_DSC_TOP_CTL 0x33E - -#define DC_DISP_DISP_WIN_OPTIONS 0x402 -#define HDMI_ENABLE (1 << 30) -#define DSI_ENABLE (1 << 29) -#define SOR1_TIMING_CYA (1 << 27) -#define SOR1_ENABLE (1 << 26) -#define SOR_ENABLE (1 << 25) -#define CURSOR_ENABLE (1 << 16) - -#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 -#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 -#define DC_DISP_DISP_TIMING_OPTIONS 0x405 -#define DC_DISP_REF_TO_SYNC 0x406 -#define DC_DISP_SYNC_WIDTH 0x407 -#define DC_DISP_BACK_PORCH 0x408 -#define DC_DISP_ACTIVE 0x409 -#define DC_DISP_FRONT_PORCH 0x40A - -#define DC_DISP_DISP_CLOCK_CONTROL 0x42E -#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) -#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) -#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) -#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) -#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) -#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) -#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) -#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) -#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) -#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) -#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) -#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) -#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) -#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) - -#define DC_DISP_DISP_INTERFACE_CONTROL 0x42F -#define DISP_DATA_FORMAT_DF1P1C (0 << 0) -#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) -#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) -#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) -#define DISP_DATA_FORMAT_DF2S (4 << 0) -#define DISP_DATA_FORMAT_DF3S (5 << 0) -#define DISP_DATA_FORMAT_DFSPI (6 << 0) -#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) -#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) -#define DISP_ALIGNMENT_MSB (0 << 8) -#define DISP_ALIGNMENT_LSB (1 << 8) -#define DISP_ORDER_RED_BLUE (0 << 9) -#define DISP_ORDER_BLUE_RED (1 << 9) - -#define DC_DISP_DISP_COLOR_CONTROL 0x430 -#define DITHER_CONTROL_MASK (3 << 8) -#define DITHER_CONTROL_DISABLE (0 << 8) -#define DITHER_CONTROL_ORDERED (2 << 8) -#define DITHER_CONTROL_ERRDIFF (3 << 8) -#define BASE_COLOR_SIZE_MASK (0xf << 0) -#define BASE_COLOR_SIZE_666 (0 << 0) -#define BASE_COLOR_SIZE_111 (1 << 0) -#define BASE_COLOR_SIZE_222 (2 << 0) -#define BASE_COLOR_SIZE_333 (3 << 0) -#define BASE_COLOR_SIZE_444 (4 << 0) -#define BASE_COLOR_SIZE_555 (5 << 0) -#define BASE_COLOR_SIZE_565 (6 << 0) -#define BASE_COLOR_SIZE_332 (7 << 0) -#define BASE_COLOR_SIZE_888 (8 << 0) - -#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 -#define SC1_H_QUALIFIER_NONE (1 << 16) -#define SC0_H_QUALIFIER_NONE (1 << 0) - -#define DC_DISP_DATA_ENABLE_OPTIONS 0x432 -#define DE_SELECT_ACTIVE_BLANK (0 << 0) -#define DE_SELECT_ACTIVE (1 << 0) -#define DE_SELECT_ACTIVE_IS (2 << 0) -#define DE_CONTROL_ONECLK (0 << 2) -#define DE_CONTROL_NORMAL (1 << 2) -#define DE_CONTROL_EARLY_EXT (2 << 2) -#define DE_CONTROL_EARLY (3 << 2) -#define DE_CONTROL_ACTIVE_BLANK (4 << 2) - -#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 -#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4 - -#define DC_WIN_CSC_YOF 0x611 -#define DC_WIN_CSC_KYRGB 0x612 -#define DC_WIN_CSC_KUR 0x613 -#define DC_WIN_CSC_KVR 0x614 -#define DC_WIN_CSC_KUG 0x615 -#define DC_WIN_CSC_KVG 0x616 -#define DC_WIN_CSC_KUB 0x617 -#define DC_WIN_CSC_KVB 0x618 -#define DC_WIN_AD_WIN_OPTIONS 0xB80 -#define DC_WIN_BD_WIN_OPTIONS 0xD80 -#define DC_WIN_CD_WIN_OPTIONS 0xF80 - -/* The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER). */ -#define DC_WIN_WIN_OPTIONS 0x700 -#define H_DIRECTION (1 << 0) -#define V_DIRECTION (1 << 2) -#define COLOR_EXPAND (1 << 6) -#define CSC_ENABLE (1 << 18) -#define WIN_ENABLE (1 << 30) - -#define DC_WIN_COLOR_DEPTH 0x703 -#define WIN_COLOR_DEPTH_P1 0x0 -#define WIN_COLOR_DEPTH_P2 0x1 -#define WIN_COLOR_DEPTH_P4 0x2 -#define WIN_COLOR_DEPTH_P8 0x3 -#define WIN_COLOR_DEPTH_B4G4R4A4 0x4 -#define WIN_COLOR_DEPTH_B5G5R5A 0x5 -#define WIN_COLOR_DEPTH_B5G6R5 0x6 -#define WIN_COLOR_DEPTH_AB5G5R5 0x7 -#define WIN_COLOR_DEPTH_B8G8R8A8 0xC -#define WIN_COLOR_DEPTH_R8G8B8A8 0xD -#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 0xE -#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 0xF -#define WIN_COLOR_DEPTH_YCbCr422 0x10 -#define WIN_COLOR_DEPTH_YUV422 0x11 -#define WIN_COLOR_DEPTH_YCbCr420P 0x12 -#define WIN_COLOR_DEPTH_YUV420P 0x13 -#define WIN_COLOR_DEPTH_YCbCr422P 0x14 -#define WIN_COLOR_DEPTH_YUV422P 0x15 -#define WIN_COLOR_DEPTH_YCbCr422R 0x16 -#define WIN_COLOR_DEPTH_YUV422R 0x17 -#define WIN_COLOR_DEPTH_YCbCr422RA 0x18 -#define WIN_COLOR_DEPTH_YUV422RA 0x19 - -#define DC_WIN_BUFFER_CONTROL 0x702 -#define DC_WIN_POSITION 0x704 - -#define DC_WIN_SIZE 0x705 -#define H_SIZE(x) (((x) & 0x1fff) << 0) -#define V_SIZE(x) (((x) & 0x1fff) << 16) - -#define DC_WIN_PRESCALED_SIZE 0x706 -#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) -#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) - -#define DC_WIN_H_INITIAL_DDA 0x707 -#define DC_WIN_V_INITIAL_DDA 0x708 - -#define DC_WIN_DDA_INC 0x709 -#define H_DDA_INC(x) (((x) & 0xffff) << 0) -#define V_DDA_INC(x) (((x) & 0xffff) << 16) - -#define DC_WIN_LINE_STRIDE 0x70A -#define DC_WIN_DV_CONTROL 0x70E -#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716 - -/* The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */ -#define DC_WINBUF_START_ADDR 0x800 -#define DC_WINBUF_ADDR_H_OFFSET 0x806 -#define DC_WINBUF_ADDR_V_OFFSET 0x808 -#define DC_WINBUF_SURFACE_KIND 0x80B - -/* Display serial interface registers. */ -#define DSI_INCR_SYNCPT_CNTRL 0x1 - -#define DSI_RD_DATA 0x9 -#define DSI_WR_DATA 0xA - -#define DSI_POWER_CONTROL 0xB -#define DSI_POWER_CONTROL_ENABLE 1 - -#define DSI_INT_ENABLE 0xC -#define DSI_INT_STATUS 0xD -#define DSI_INT_MASK 0xE - -#define DSI_HOST_CONTROL 0xF -#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21) -#define DSI_HOST_CONTROL_CRC_RESET (1 << 20) -#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12) -#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12) -#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12) -#define DSI_HOST_CONTROL_RAW (1 << 6) -#define DSI_HOST_CONTROL_HS (1 << 5) -#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4) -#define DSI_HOST_CONTROL_IMM_BTA (1 << 3) -#define DSI_HOST_CONTROL_PKT_BTA (1 << 2) -#define DSI_HOST_CONTROL_CS (1 << 1) -#define DSI_HOST_CONTROL_ECC (1 << 0) - -#define DSI_CONTROL 0x10 -#define DSI_CONTROL_HS_CLK_CTRL (1 << 20) -#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16) -#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12) -#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8) -#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4) -#define DSI_CONTROL_DCS_ENABLE (1 << 3) -#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2) -#define DSI_CONTROL_VIDEO_ENABLE (1 << 1) -#define DSI_CONTROL_HOST_ENABLE (1 << 0) - -#define DSI_SOL_DELAY 0x11 -#define DSI_MAX_THRESHOLD 0x12 - -#define DSI_TRIGGER 0x13 -#define DSI_TRIGGER_HOST (1 << 1) -#define DSI_TRIGGER_VIDEO (1 << 0) - -#define DSI_TX_CRC 0x14 -#define DSI_STATUS 0x15 -#define DSI_INIT_SEQ_CONTROL 0x1A -#define DSI_INIT_SEQ_DATA_0 0x1B -#define DSI_INIT_SEQ_DATA_1 0x1C -#define DSI_INIT_SEQ_DATA_2 0x1D -#define DSI_INIT_SEQ_DATA_3 0x1E -#define DSI_PKT_SEQ_0_LO 0x23 -#define DSI_PKT_SEQ_0_HI 0x24 -#define DSI_PKT_SEQ_1_LO 0x25 -#define DSI_PKT_SEQ_1_HI 0x26 -#define DSI_PKT_SEQ_2_LO 0x27 -#define DSI_PKT_SEQ_2_HI 0x28 -#define DSI_PKT_SEQ_3_LO 0x29 -#define DSI_PKT_SEQ_3_HI 0x2A -#define DSI_PKT_SEQ_4_LO 0x2B -#define DSI_PKT_SEQ_4_HI 0x2C -#define DSI_PKT_SEQ_5_LO 0x2D -#define DSI_PKT_SEQ_5_HI 0x2E -#define DSI_DCS_CMDS 0x33 -#define DSI_PKT_LEN_0_1 0x34 -#define DSI_PKT_LEN_2_3 0x35 -#define DSI_PKT_LEN_4_5 0x36 -#define DSI_PKT_LEN_6_7 0x37 -#define DSI_PHY_TIMING_0 0x3C -#define DSI_PHY_TIMING_1 0x3D -#define DSI_PHY_TIMING_2 0x3E -#define DSI_BTA_TIMING 0x3F - -#define DSI_TIMEOUT_0 0x44 -#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) -#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) - -#define DSI_TIMEOUT_1 0x45 -#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) -#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) - -#define DSI_TO_TALLY 0x46 - -#define DSI_PAD_CONTROL_0 0x4B -#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24) -#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) -#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) -#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) - -#define DSI_PAD_CONTROL_CD 0x4C -#define DSI_VIDEO_MODE_CONTROL 0x4E - -#define DSI_PAD_CONTROL_1 0x4F -#define DSI_PAD_CONTROL_2 0x50 - -#define DSI_PAD_CONTROL_3 0x51 -#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12) -#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8) -#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4) -#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) - -#define DSI_PAD_CONTROL_4 0x52 -#define DSI_PAD_CONTROL_5_MARIKO 0x53 -#define DSI_PAD_CONTROL_6_MARIKO 0x54 -#define DSI_PAD_CONTROL_7_MARIKO 0x55 -#define DSI_INIT_SEQ_DATA_15 0x5F -#define DSI_INIT_SEQ_DATA_15_MARIKO 0x62 - -/* MIPI calibration registers. */ -#define MIPI_CAL_MIPI_CAL_CTRL 0x0 -#define MIPI_CAL_MIPI_CAL_AUTOCAL_CTRL0 0x4 -#define MIPI_CAL_CIL_MIPI_CAL_STATUS 0x8 -#define MIPI_CAL_CIL_MIPI_CAL_STATUS_2 0xC -#define MIPI_CAL_CILA_MIPI_CAL_CONFIG 0x14 -#define MIPI_CAL_CILB_MIPI_CAL_CONFIG 0x18 -#define MIPI_CAL_CILC_MIPI_CAL_CONFIG 0x1C -#define MIPI_CAL_CILD_MIPI_CAL_CONFIG 0x20 -#define MIPI_CAL_CILE_MIPI_CAL_CONFIG 0x24 -#define MIPI_CAL_CILF_MIPI_CAL_CONFIG 0x28 -#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG 0x38 -#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG 0x3C -#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG 0x40 -#define MIPI_CAL_DSID_MIPI_CAL_CONFIG 0x44 -#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 0x58 -#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 0x5C -#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60 -#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 0x64 -#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 0x68 -#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 0x70 -#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 0x74 - -void display_init(void); -void display_end(void); - -/* Switches screen backlight ON/OFF. */ -void display_backlight(bool enable); - -/* Show one single color on the display. */ -void display_color_screen(uint32_t color); - -/* Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */ -uint32_t *display_init_framebuffer(void *address); - -#endif diff --git a/sept/sept-secondary/src/di.inl b/sept/sept-secondary/src/di.inl deleted file mode 100644 index 3ea8dc5df..000000000 --- a/sept/sept-secondary/src/di.inl +++ /dev/null @@ -1,773 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -typedef struct { - uint32_t offset; - uint32_t value; -} register_write_t; - -typedef struct { - uint16_t kind; - uint16_t offset; - uint32_t value; -} dsi_sleep_or_register_write_t; - -static const uint32_t display_config_frame_buffer_address = 0xC0000000; - -static const register_write_t display_config_plld_01_erista[4] = { - {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000}, - {CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001}, - {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020}, - {CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA}, -}; - -static const register_write_t display_config_plld_01_mariko[4] = { - {CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000}, - {CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001}, - {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000}, - {CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00}, -}; - -static const register_write_t display_config_dc_01[94] = { - {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(uint32_t) * DC_CMD_REG_ACT_CONTROL, 0x54}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_DISP_DC_MCCIF_FIFOCTRL, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, - {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, - {sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, - {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, - {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, - {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0}, - {sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, -}; - -static const register_write_t display_config_dsi_01_init_01[8] = { - {sizeof(uint32_t) * DSI_WR_DATA, 0x0}, - {sizeof(uint32_t) * DSI_INT_ENABLE, 0x0}, - {sizeof(uint32_t) * DSI_INT_STATUS, 0x0}, - {sizeof(uint32_t) * DSI_INT_MASK, 0x0}, - {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_0, 0x0}, - {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_1, 0x0}, - {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_2, 0x0}, - {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_3, 0x0}, -}; - -static const register_write_t display_config_dsi_01_init_02_erista[1] = { - {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15, 0x0}, -}; - -static const register_write_t display_config_dsi_01_init_02_mariko[1] = { - {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0}, -}; - -static const register_write_t display_config_dsi_01_init_03[14] = { - {sizeof(uint32_t) * DSI_DCS_CMDS, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_0_HI, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_1_HI, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_2_HI, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0}, - {sizeof(uint32_t) * DSI_CONTROL, 0}, -}; - -static const register_write_t display_config_dsi_01_init_04_erista[0] = { - /* No register writes. */ -}; - -static const register_write_t display_config_dsi_01_init_04_mariko[7] = { - {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_3, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, -}; - -static const register_write_t display_config_dsi_01_init_05[10] = { - {sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0}, - {sizeof(uint32_t) * DSI_SOL_DELAY, 0x18}, - {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, - {sizeof(uint32_t) * DSI_TRIGGER, 0}, - {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0}, - {sizeof(uint32_t) * DSI_PKT_LEN_0_1, 0}, - {sizeof(uint32_t) * DSI_PKT_LEN_2_3, 0}, - {sizeof(uint32_t) * DSI_PKT_LEN_4_5, 0}, - {sizeof(uint32_t) * DSI_PKT_LEN_6_7, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, -}; - -static const register_write_t display_config_dsi_01_init_06[12] = { - {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, - {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30109}, - {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, - {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, - {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, - {sizeof(uint32_t) * DSI_TO_TALLY, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, - {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, - {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, -}; - -static const register_write_t display_config_dsi_01_init_07[14] = { - {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, - {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30118}, - {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, - {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, - {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, - {sizeof(uint32_t) * DSI_TO_TALLY, 0}, - {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, - {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x40}, - {sizeof(uint32_t) * DSI_TRIGGER, 0}, - {sizeof(uint32_t) * DSI_TX_CRC, 0}, - {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0}, -}; - -static const register_write_t display_config_dsi_phy_timing_erista[1] = { - {sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070601}, -}; - -static const register_write_t display_config_dsi_phy_timing_mariko[1] = { - {sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070603}, -}; - -static const dsi_sleep_or_register_write_t display_config_jdi_specific_init_01[48] = { - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0x9483FFB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0xBD15}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x1939}, - {0, DSI_WR_DATA, 0xAAAAAAD8}, - {0, DSI_WR_DATA, 0xAAAAAAEB}, - {0, DSI_WR_DATA, 0xAAEBAAAA}, - {0, DSI_WR_DATA, 0xAAAAAAAA}, - {0, DSI_WR_DATA, 0xAAAAAAEB}, - {0, DSI_WR_DATA, 0xAAEBAAAA}, - {0, DSI_WR_DATA, 0xAA}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x1BD15}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x2739}, - {0, DSI_WR_DATA, 0xFFFFFFD8}, - {0, DSI_WR_DATA, 0xFFFFFFFF}, - {0, DSI_WR_DATA, 0xFFFFFFFF}, - {0, DSI_WR_DATA, 0xFFFFFFFF}, - {0, DSI_WR_DATA, 0xFFFFFFFF}, - {0, DSI_WR_DATA, 0xFFFFFFFF}, - {0, DSI_WR_DATA, 0xFFFFFFFF}, - {0, DSI_WR_DATA, 0xFFFFFFFF}, - {0, DSI_WR_DATA, 0xFFFFFFFF}, - {0, DSI_WR_DATA, 0xFFFFFF}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x2BD15}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0xF39}, - {0, DSI_WR_DATA, 0xFFFFFFD8}, - {0, DSI_WR_DATA, 0xFFFFFFFF}, - {0, DSI_WR_DATA, 0xFFFFFFFF}, - {0, DSI_WR_DATA, 0xFFFFFF}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0xBD15}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x6D915}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0xB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x1105}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0xB4, 0}, - {0, DSI_WR_DATA, 0x2905}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, -}; - -static const dsi_sleep_or_register_write_t display_config_innolux_nx_abca2_specific_init_01[14] = { - {0, DSI_WR_DATA, 0x1105}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0xB4, 0}, - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0x9483FFB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, - {0, DSI_WR_DATA, 0x739}, - {0, DSI_WR_DATA, 0x751548B1}, - {0, DSI_WR_DATA, 0x143209}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, - {0, DSI_WR_DATA, 0x2905}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, -}; - -static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_init_01[14] = { - {0, DSI_WR_DATA, 0x1105}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0xB4, 0}, - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0x9483FFB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, - {0, DSI_WR_DATA, 0x739}, - {0, DSI_WR_DATA, 0x711148B1}, - {0, DSI_WR_DATA, 0x143209}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, - {0, DSI_WR_DATA, 0x2905}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, -}; - -static const dsi_sleep_or_register_write_t display_config_innolux_auo_40_nx_abcc_specific_init_01[5] = { - {0, DSI_WR_DATA, 0x1105}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x78, 0}, - {0, DSI_WR_DATA, 0x2905}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, -}; - -static const dsi_sleep_or_register_write_t display_config_50_nx_abcd_specific_init_01[13] = { - {0, DSI_WR_DATA, 0x1105}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0xB4, 0}, - {0, DSI_WR_DATA, 0xA015}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x205315}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x339}, - {0, DSI_WR_DATA, 0xFF0751}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, - {0, DSI_WR_DATA, 0x2905}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, -}; - -static const register_write_t display_config_plld_02_erista[3] = { - {CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001}, - {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020}, - {CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA}, -}; - -static const register_write_t display_config_plld_02_mariko[3] = { - {CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001}, - {CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000}, - {CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00}, -}; - -static const register_write_t display_config_dsi_01_init_08[1] = { - {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, -}; - -static const register_write_t display_config_dsi_01_init_09[19] = { - {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, - {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30172}, - {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, - {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, - {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, - {sizeof(uint32_t) * DSI_TO_TALLY, 0}, - {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0x40000208}, - {sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0x40000308}, - {sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0x40000308}, - {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0x40000308}, - {sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0x3F3B2B08}, - {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0x2CC}, - {sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, - {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0x2CC}, - {sizeof(uint32_t) * DSI_PKT_LEN_0_1, 0xCE0000}, - {sizeof(uint32_t) * DSI_PKT_LEN_2_3, 0x87001A2}, - {sizeof(uint32_t) * DSI_PKT_LEN_4_5, 0x190}, - {sizeof(uint32_t) * DSI_PKT_LEN_6_7, 0x190}, - {sizeof(uint32_t) * DSI_HOST_CONTROL, 0}, -}; - -static const register_write_t display_config_dsi_01_init_10[10] = { - {sizeof(uint32_t) * DSI_TRIGGER, 0}, - {sizeof(uint32_t) * DSI_CONTROL, 0}, - {sizeof(uint32_t) * DSI_SOL_DELAY, 6}, - {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, - {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} -}; - -static const register_write_t display_config_dsi_01_init_11_erista[4] = { - {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0} -}; - -static const register_write_t display_config_dsi_01_init_11_mariko[7] = { - {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_3, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0x77777}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0x77777}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, DSI_PAD_PREEMP_PD_CLK(0x1) | DSI_PAD_PREEMP_PU_CLK(0x1) | DSI_PAD_PREEMP_PD(0x01) | DSI_PAD_PREEMP_PU(0x1)}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, -}; - -static const register_write_t display_config_mipi_cal_01[4] = { - {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, - {MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000}, - {MIPI_CAL_MIPI_BIAS_PAD_CFG0, 1}, - {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, -}; - -static const register_write_t display_config_mipi_cal_02_erista[2] = { - {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, - {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0x300}, -}; - -static const register_write_t display_config_mipi_cal_02_mariko[2] = { - {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010}, - {MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0}, -}; - -static const register_write_t display_config_mipi_cal_03_erista[6] = { - {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200}, - {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200}, - {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002}, - {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002}, - {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, - {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, -}; - -static const register_write_t display_config_mipi_cal_03_mariko[6] = { - {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200006}, - {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200006}, - {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000}, - {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000}, - {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, - {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, -}; - -static const register_write_t display_config_mipi_cal_04[10] = { - {MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0}, - {MIPI_CAL_CILD_MIPI_CAL_CONFIG, 0}, - {MIPI_CAL_CILE_MIPI_CAL_CONFIG, 0}, - {MIPI_CAL_CILF_MIPI_CAL_CONFIG, 0}, - {MIPI_CAL_DSIC_MIPI_CAL_CONFIG, 0}, - {MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0}, - {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0}, - {MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0}, - {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0}, - {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001}, -}; - -static const register_write_t display_config_dc_02[113] = { - {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, - {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, - {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0}, - {sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A}, - {sizeof(uint32_t) * DC_WIN_CSC_KUR, 0}, - {sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198}, - {sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B}, - {sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F}, - {sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204}, - {sizeof(uint32_t) * DC_WIN_CSC_KVB, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0}, - {sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_TIMING_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_REF_TO_SYNC, (1 << 16)}, - {sizeof(uint32_t) * DC_DISP_SYNC_WIDTH, 0x10048}, - {sizeof(uint32_t) * DC_DISP_BACK_PORCH, 0x90048}, - {sizeof(uint32_t) * DC_DISP_ACTIVE, 0x50002D0}, - {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088}, - {sizeof(uint32_t) * DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, - {sizeof(uint32_t) * DC_COM_PIN_OUTPUT_ENABLE(1), 0}, - {sizeof(uint32_t) * DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, - {sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, - {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088}, - {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, - {sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, -}; - -static const register_write_t display_config_frame_buffer[32] = { - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {sizeof(uint32_t) * DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_WIN_POSITION, 0}, - {sizeof(uint32_t) * DC_WIN_H_INITIAL_DDA, 0}, - {sizeof(uint32_t) * DC_WIN_V_INITIAL_DDA, 0}, - {sizeof(uint32_t) * DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)}, - {sizeof(uint32_t) * DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, - {sizeof(uint32_t) * DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, - {sizeof(uint32_t) * DC_WIN_LINE_STRIDE, 0x6000C00}, - {sizeof(uint32_t) * DC_WIN_BUFFER_CONTROL, 0}, - {sizeof(uint32_t) * DC_WINBUF_SURFACE_KIND, 0}, - {sizeof(uint32_t) * DC_WINBUF_START_ADDR, display_config_frame_buffer_address}, - {sizeof(uint32_t) * DC_WINBUF_ADDR_H_OFFSET, 0}, - {sizeof(uint32_t) * DC_WINBUF_ADDR_V_OFFSET, 0}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, WIN_ENABLE}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ}, -}; - -static const register_write_t display_config_solid_color[8] = { - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0}, - {sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, -}; - -static const register_write_t display_config_dc_01_fini_01[13] = { - {sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088}, - {sizeof(uint32_t) * DC_CMD_INT_MASK, 0}, - {sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0}, - {sizeof(uint32_t) * DC_CMD_INT_ENABLE, 0}, - {sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, 0}, - {sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, - {sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, -}; - -static const register_write_t display_config_dsi_01_fini_01[2] = { - {sizeof(uint32_t) * DSI_POWER_CONTROL, 0}, - {sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0}, -}; - -static const register_write_t display_config_dsi_01_fini_02[13] = { - {sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05}, - {sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30109}, - {sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14}, - {sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, - {sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, - {sizeof(uint32_t) * DSI_TO_TALLY, 0}, - {sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, - {sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x40}, - {sizeof(uint32_t) * DSI_TRIGGER, 0}, - {sizeof(uint32_t) * DSI_TX_CRC, 0}, - {sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0} -}; - -static const dsi_sleep_or_register_write_t display_config_jdi_specific_fini_01[22] = { - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0x9483FFB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x2139}, - {0, DSI_WR_DATA, 0x191919D5}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0xB39}, - {0, DSI_WR_DATA, 0x4F0F41B1}, - {0, DSI_WR_DATA, 0xF179A433}, - {0, DSI_WR_DATA, 0x2D81}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0xB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, -}; - -static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_fini_01[38] = { - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0x9483FFB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x2C39}, - {0, DSI_WR_DATA, 0x191919D5}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x2C39}, - {0, DSI_WR_DATA, 0x191919D6}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_WR_DATA, 0x19191919}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0xB39}, - {0, DSI_WR_DATA, 0x711148B1}, - {0, DSI_WR_DATA, 0x71143209}, - {0, DSI_WR_DATA, 0x114D31}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0xB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, -}; - -static const dsi_sleep_or_register_write_t display_config_innolux_nx_abcc_specific_fini_01[10] = { - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0x9483FFB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, - {0, DSI_WR_DATA, 0xB39}, - {0, DSI_WR_DATA, 0x751548B1}, - {0, DSI_WR_DATA, 0x71143209}, - {0, DSI_WR_DATA, 0x115631}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, -}; - -static const dsi_sleep_or_register_write_t display_config_auo_nx_abcc_specific_fini_01[10] = { - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0x9483FFB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, - {0, DSI_WR_DATA, 0xB39}, - {0, DSI_WR_DATA, 0x711148B1}, - {0, DSI_WR_DATA, 0x71143209}, - {0, DSI_WR_DATA, 0x114D31}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, -}; - -static const dsi_sleep_or_register_write_t display_config_40_nx_abcc_specific_fini_01[10] = { - {0, DSI_WR_DATA, 0x439}, - {0, DSI_WR_DATA, 0x9483FFB9}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, - {0, DSI_WR_DATA, 0xB39}, - {0, DSI_WR_DATA, 0x731348B1}, - {0, DSI_WR_DATA, 0x71243209}, - {0, DSI_WR_DATA, 0x4C31}, - {0, DSI_TRIGGER, DSI_TRIGGER_HOST}, - {1, 0x5, 0}, -}; \ No newline at end of file diff --git a/sept/sept-secondary/src/emc.h b/sept/sept-secondary/src/emc.h deleted file mode 100644 index 274d8213f..000000000 --- a/sept/sept-secondary/src/emc.h +++ /dev/null @@ -1,1129 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra21_emc.h - * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - */ - -#ifndef FUSEE_EMC_H_ -#define FUSEE_EMC_H_ - -#define EMC_BASE 0x7001B000 -#define EMC0_BASE 0x7001E000 -#define EMC1_BASE 0x7001F000 -#define MAKE_EMC_REG(n) MAKE_REG32(EMC_BASE + n) -#define MAKE_EMC0_REG(n) MAKE_REG32(EMC0_BASE + n) -#define MAKE_EMC1_REG(n) MAKE_REG32(EMC1_BASE + n) - -#define EMC_INTSTATUS 0x0 -#define EMC_INTSTATUS_MRR_DIVLD (0x1 << 5) -#define EMC_INTSTATUS_CLKCHANGE_COMPLETE (0x1 << 4) - -#define EMC_INTMASK 0x4 -#define EMC_DBG 0x8 -#define EMC_DBG_WRITE_MUX_ACTIVE (1 << 1) -#define EMC_DBG_CFG_SWAP_SHIFT 26 -#define EMC_DBG_CFG_SWAP_MASK \ - (0x3 << EMC_DBG_CFG_SWAP_SHIFT) -#define EMC_DBG_WRITE_ACTIVE_ONLY (1 << 30) - -#define EMC_CONFIG_SAMPLE_DELAY 0x5f0 -#define EMC_CFG_UPDATE 0x5f4 -#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT 9 -#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK \ - (0x3 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT) -#define EMC_CFG 0xc -#define EMC_CFG_DRAM_CLKSTOP_PD (1 << 31) -#define EMC_CFG_DRAM_CLKSTOP_SR (1 << 30) -#define EMC_CFG_DRAM_ACPD (1 << 29) -#define EMC_CFG_DYN_SELF_REF (1 << 28) -#define EMC_CFG_REQACT_ASYNC (1 << 26) -#define EMC_CFG_AUTO_PRE_WR (1 << 25) -#define EMC_CFG_AUTO_PRE_RD (1 << 24) -#define EMC_CFG_MAM_PRE_WR (1 << 23) -#define EMC_CFG_MAN_PRE_RD (1 << 22) -#define EMC_CFG_PERIODIC_QRST (1 << 21) -#define EMC_CFG_PERIODIC_QRST_SHIFT (21) -#define EMC_CFG_EN_DYNAMIC_PUTERM (1 << 20) -#define EMC_CFG_DLY_WR_DQ_HALF_CLOCK (1 << 19) -#define EMC_CFG_DSR_VTTGEN_DRV_EN (1 << 18) -#define EMC_CFG_EMC2MC_CLK_RATIO (3 << 16) -#define EMC_CFG_WAIT_FOR_ISP2B_READY_B4_CC (1 << 9) -#define EMC_CFG_WAIT_FOR_VI2_READY_B4_CC (1 << 8) -#define EMC_CFG_WAIT_FOR_ISP2_READY_B4_CC (1 << 7) -#define EMC_CFG_INVERT_DQM (1 << 6) -#define EMC_CFG_WAIT_FOR_DISPLAYB_READY_B4_CC (1 << 5) -#define EMC_CFG_WAIT_FOR_DISPLAY_READY_B4_CC (1 << 4) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (1 << 3) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (1 << 2) -#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE (1 << 1) - -#define EMC_ADR_CFG 0x10 -#define EMC_REFCTRL 0x20 -#define EMC_REFCTRL_DEV_SEL_SHIFT 0 -#define EMC_REFCTRL_DEV_SEL_MASK \ - (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT) -#define EMC_REFCTRL_ENABLE (0x1 << 31) -#define EMC_REFCTRL_ENABLE_ALL(num) \ - (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \ - | EMC_REFCTRL_ENABLE) -#define EMC_REFCTRL_DISABLE_ALL(num) \ - ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) - -#define EMC_PIN 0x24 -#define EMC_PIN_PIN_CKE_PER_DEV (1 << 2) -#define EMC_PIN_PIN_CKEB (1 << 1) -#define EMC_PIN_PIN_CKE (1 << 0) - -#define EMC_CLK_FORCE_CC_TRIGGER (1 << 27) - -#define EMC_TIMING_CONTROL 0x28 -#define EMC_RC 0x2c -#define EMC_RFC 0x30 -#define EMC_RFCPB 0x590 -#define EMC_RAS 0x34 -#define EMC_RP 0x38 -#define EMC_R2W 0x3c -#define EMC_W2R 0x40 -#define EMC_R2P 0x44 -#define EMC_W2P 0x48 -#define EMC_CCDMW 0x5c0 -#define EMC_RD_RCD 0x4c -#define EMC_WR_RCD 0x50 -#define EMC_RRD 0x54 -#define EMC_REXT 0x58 -#define EMC_WDV 0x5c -#define EMC_QUSE 0x60 -#define EMC_QRST 0x64 -#define EMC_ISSUE_QRST 0x428 -#define EMC_QSAFE 0x68 -#define EMC_RDV 0x6c -#define EMC_REFRESH 0x70 -#define EMC_BURST_REFRESH_NUM 0x74 -#define EMC_PDEX2WR 0x78 -#define EMC_PDEX2RD 0x7c -#define EMC_PDEX2CKE 0x118 -#define EMC_PCHG2PDEN 0x80 -#define EMC_ACT2PDEN 0x84 -#define EMC_AR2PDEN 0x88 -#define EMC_RW2PDEN 0x8c -#define EMC_CKE2PDEN 0x11c -#define EMC_TXSR 0x90 -#define EMC_TCKE 0x94 -#define EMC_TFAW 0x98 -#define EMC_TRPAB 0x9c -#define EMC_TCLKSTABLE 0xa0 -#define EMC_TCLKSTOP 0xa4 -#define EMC_TREFBW 0xa8 -#define EMC_TPPD 0xac -#define EMC_PDEX2MRR 0xb4 -#define EMC_ODT_WRITE 0xb0 -#define EMC_WEXT 0xb8 -#define EMC_RFC_SLR 0xc0 -#define EMC_MRS_WAIT_CNT2 0xc4 -#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT 16 -#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_MASK \ - (0x7ff << EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT) -#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT 0 -#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_MASK \ - (0x3ff << EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT) - -#define EMC_MRS_WAIT_CNT 0xc8 -#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 -#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ - (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) -#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 -#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ - (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) - -#define EMC_MRS 0xcc -#define EMC_MODE_SET_DLL_RESET (1 << 8) -#define EMC_MRS_USE_MRS_LONG_CNT (1 << 26) - -#define EMC_EMRS 0xd0 -#define EMC_EMRS_USE_EMRS_LONG_CNT (1 << 26) - -#define EMC_REF 0xd4 -#define EMC_REF_FORCE_CMD 1 - -#define EMC_PRE 0xd8 -#define EMC_NOP 0xdc -#define EMC_SELF_REF 0xe0 -#define EMC_SELF_REF_CMD_ENABLED (1 << 0) -#define EMC_SELF_REF_ACTIVE_SELF_REF (1 << 8) -#define EMC_SELF_REF_DEV_SEL_SHIFT 30 -#define EMC_SELF_REF_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) - -#define EMC_DPD 0xe4 -#define EMC_MRW 0xe8 -#define EMC_MRW_MRW_OP_SHIFT 0 -#define EMC_MRW_MRW_OP_MASK \ - (0xff << EMC_MRW_MRW_OP_SHIFT) -#define EMC_MRW_MRW_MA_SHIFT 16 -#define EMC_MRW_MRW_MA_MASK \ - (0xff << EMC_MRW_MRW_MA_SHIFT) -#define EMC_MRW_USE_MRW_LONG_CNT 26 -#define EMC_MRW_USE_MRW_EXT_CNT 27 -#define EMC_MRW_MRW_DEV_SELECTN_SHIFT 30 -#define EMC_MRW_MRW_DEV_SELECTN_MASK \ - (0x3 << EMC_MRW_MRW_DEV_SELECTN_SHIFT) - -#define EMC_MRR 0xec -#define EMC_MRR_DEV_SEL_SHIFT 30 -#define EMC_MRR_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) -#define EMC_MRR_MA_SHIFT 16 -#define EMC_MRR_MA_MASK \ - (0xff << EMC_MRR_MA_SHIFT) -#define EMC_MRR_DATA_SHIFT 0 -#define EMC_MRR_DATA_MASK \ - (0xffff << EMC_MRR_DATA_SHIFT) -#define LPDDR2_MR4_TEMP_SHIFT 0 -#define LPDDR2_MR4_TEMP_MASK \ - (0x7 << LPDDR2_MR4_TEMP_SHIFT) - -#define EMC_CMDQ 0xf0 -#define EMC_MC2EMCQ 0xf4 -#define EMC_FBIO_SPARE 0x100 -#define EMC_FBIO_CFG5 0x104 -#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 -#define EMC_FBIO_CFG5_DRAM_TYPE_MASK \ - (0x3 << EMC_FBIO_CFG5_DRAM_TYPE_SHIFT) -#define EMC_FBIO_CFG5_CMD_TX_DIS (1 << 8) -#define EMC_FBIO_CFG5_CMD_BUS_RETURN_TO_ZERO (1 << 27) - -#define EMC_CFG5_QUSE_MODE_SHIFT 13 -#define EMC_CFG5_QUSE_MODE_MASK \ - (0x7 << EMC_CFG5_QUSE_MODE_SHIFT) - -#define EMC_CFG_RSV 0x120 -#define EMC_ACPD_CONTROL 0x124 -#define EMC_MPC 0x128 -#define EMC_EMRS2 0x12c -#define EMC_EMRS2_USE_EMRS2_LONG_CNT (1 << 26) - -#define EMC_EMRS3 0x130 -#define EMC_MRW2 0x134 -#define EMC_MRW3 0x138 -#define EMC_MRW4 0x13c -#define EMC_MRW5 0x4a0 -#define EMC_MRW6 0x4a4 -#define EMC_MRW7 0x4a8 -#define EMC_MRW8 0x4ac -#define EMC_MRW9 0x4b0 -#define EMC_MRW10 0x4b4 -#define EMC_MRW11 0x4b8 -#define EMC_MRW12 0x4bc -#define EMC_MRW13 0x4c0 -#define EMC_MRW14 0x4c4 -#define EMC_MRW15 0x4d0 -#define EMC_CFG_SYNC 0x4d4 -#define EMC_CLKEN_OVERRIDE 0x140 -#define EMC_R2R 0x144 -#define EMC_W2W 0x148 -#define EMC_EINPUT 0x14c -#define EMC_EINPUT_DURATION 0x150 -#define EMC_PUTERM_EXTRA 0x154 -#define EMC_TCKESR 0x158 -#define EMC_TPD 0x15c -#define EMC_STAT_CONTROL 0x160 -#define EMC_STAT_STATUS 0x164 -#define EMC_STAT_DRAM_CLOCK_LIMIT_LO 0x19c -#define EMC_STAT_DRAM_CLOCK_LIMIT_HI 0x1a0 -#define EMC_STAT_DRAM_CLOCKS_LO 0x1a4 -#define EMC_STAT_DRAM_CLOCKS_HI 0x1a8 -#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO 0x1ac -#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI 0x1b0 -#define EMC_STAT_DRAM_DEV0_READ_CNT_LO 0x1b4 -#define EMC_STAT_DRAM_DEV0_READ_CNT_HI 0x1b8 -#define EMC_STAT_DRAM_DEV0_READ8_CNT_LO 0x1bc -#define EMC_STAT_DRAM_DEV0_READ8_CNT_HI 0x1c0 -#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO 0x1c4 -#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI 0x1c8 -#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_LO 0x1cc -#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_HI 0x1d0 -#define EMC_STAT_DRAM_DEV0_REF_CNT_LO 0x1d4 -#define EMC_STAT_DRAM_DEV0_REF_CNT_HI 0x1d8 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1dc -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e0 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1e4 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e8 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1ec -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f0 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1f4 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f8 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x1fc -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x200 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x204 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x208 -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x20c -#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x210 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x214 -#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x218 -#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_LO 0x21c -#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_HI 0x220 -#define EMC_STAT_DRAM_DEV0_DSR 0x224 -#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO 0x228 -#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI 0x22c -#define EMC_STAT_DRAM_DEV1_READ_CNT_LO 0x230 -#define EMC_STAT_DRAM_DEV1_READ_CNT_HI 0x234 -#define EMC_STAT_DRAM_DEV1_READ8_CNT_LO 0x238 -#define EMC_STAT_DRAM_DEV1_READ8_CNT_HI 0x23c -#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO 0x240 -#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI 0x244 -#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_LO 0x248 -#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_HI 0x24c -#define EMC_STAT_DRAM_DEV1_REF_CNT_LO 0x250 -#define EMC_STAT_DRAM_DEV1_REF_CNT_HI 0x254 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x258 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x25c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x260 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x264 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x268 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x26c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x270 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x274 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x278 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x27c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x280 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x284 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x288 -#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x28c -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x290 -#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x294 -#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_LO 0x298 -#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_HI 0x29c -#define EMC_STAT_DRAM_DEV1_DSR 0x2a0 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc8c -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc90 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc94 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc98 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xc9c -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca0 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xca4 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca8 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcac -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb0 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcb4 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb8 -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcbc -#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc0 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcc4 -#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc8 -#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_LO 0xccc -#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI 0xcd0 -#define EMC_STAT_DRAM_IO_DSR 0xcd4 -#define EMC_AUTO_CAL_CONFIG 0x2a4 -#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START (1 << 0) -#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL (1 << 9) -#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL (1 << 10) -#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE (1 << 29) -#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START (1 << 31) - -#define EMC_AUTO_CAL_CONFIG2 0x458 -#define EMC_AUTO_CAL_CONFIG3 0x45c -#define EMC_AUTO_CAL_CONFIG4 0x5b0 -#define EMC_AUTO_CAL_CONFIG5 0x5b4 -#define EMC_AUTO_CAL_CONFIG6 0x5cc -#define EMC_AUTO_CAL_CONFIG7 0x574 -#define EMC_AUTO_CAL_CONFIG8 0x2dc -#define EMC_AUTO_CAL_VREF_SEL_0 0x2f8 -#define EMC_AUTO_CAL_VREF_SEL_1 0x300 -#define EMC_AUTO_CAL_INTERVAL 0x2a8 -#define EMC_AUTO_CAL_STATUS 0x2ac -#define EMC_AUTO_CAL_STATUS2 0x3d4 -#define EMC_AUTO_CAL_CHANNEL 0x464 -#define EMC_PMACRO_RX_TERM 0xc48 -#define EMC_PMACRO_DQ_TX_DRV 0xc70 -#define EMC_PMACRO_CA_TX_DRV 0xc74 -#define EMC_PMACRO_CMD_TX_DRV 0xc4c -#define EMC_PMACRO_AUTOCAL_CFG_0 0x700 -#define EMC_PMACRO_AUTOCAL_CFG_1 0x704 -#define EMC_PMACRO_AUTOCAL_CFG_2 0x708 -#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78 -#define EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS (1 << 16) - -#define EMC_PMACRO_ZCTRL 0xc44 -#define EMC_XM2COMPPADCTRL 0x30c -#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE (1 << 10) - -#define EMC_XM2COMPPADCTRL2 0x578 -#define EMC_XM2COMPPADCTRL3 0x2f4 -#define EMC_COMP_PAD_SW_CTRL 0x57c -#define EMC_REQ_CTRL 0x2b0 -#define EMC_EMC_STATUS 0x2b4 -#define EMC_EMC_STATUS_MRR_DIVLD (1 << 20) -#define EMC_EMC_STATUS_TIMING_UPDATE_STALLED (1 << 23) -#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT 4 -#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK \ - (0x3 << EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT) -#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT 8 -#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK \ - (0x3 << EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT) - -#define EMC_CFG_2 0x2b8 -#define EMC_CFG_DIG_DLL 0x2bc -#define EMC_CFG_DIG_DLL_CFG_DLL_EN (1 << 0) -#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK (1 << 1) -#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC (1 << 3) -#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK (1 << 4) -#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT 6 -#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK \ - (0x3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT) -#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT 8 -#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK \ - (0x7 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT) - -#define EMC_CFG_DIG_DLL_PERIOD 0x2c0 -#define EMC_DIG_DLL_STATUS 0x2c4 -#define EMC_DIG_DLL_STATUS_DLL_LOCK (1 << 15) -#define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED (1 << 17) -#define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0 -#define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \ - (0x7ff << EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT) - -#define EMC_CFG_DIG_DLL_1 0x2c8 -#define EMC_RDV_MASK 0x2cc -#define EMC_WDV_MASK 0x2d0 -#define EMC_RDV_EARLY_MASK 0x2d4 -#define EMC_RDV_EARLY 0x2d8 -#define EMC_WDV_CHK 0x4e0 -#define EMC_ZCAL_INTERVAL 0x2e0 -#define EMC_ZCAL_WAIT_CNT 0x2e4 -#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK 0x7ff -#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT 0 - -#define EMC_ZCAL_MRW_CMD 0x2e8 -#define EMC_ZQ_CAL 0x2ec -#define EMC_ZQ_CAL_DEV_SEL_SHIFT 30 -#define EMC_ZQ_CAL_DEV_SEL_MASK \ - (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT) -#define EMC_ZQ_CAL_LONG (1 << 4) -#define EMC_ZQ_CAL_ZQ_LATCH_CMD (1 << 1) -#define EMC_ZQ_CAL_ZQ_CAL_CMD (1 << 0) -#define EMC_ZQ_CAL_LONG_CMD_DEV0 \ - (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) -#define EMC_ZQ_CAL_LONG_CMD_DEV1 \ - (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) - -#define EMC_SCRATCH0 0x324 -#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8 -#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc -#define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0 -#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8 -#define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE (1 << 0) - -#define EMC_SEL_DPD_CTRL 0x3d8 -#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN (1 << 8) -#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN (1 << 5) -#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN (1 << 4) -#define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN (1 << 3) -#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN (1 << 2) -#define EMC_SEL_DPD_CTRL_DDR3_MASK \ - ((0xf << 2) | (0x1 << 8)) -#define EMC_SEL_DPD_CTRL_MAS \ - ((0x3 << 2) | (0x1 << 5) | (0x1 << 8)) - -#define EMC_FDPD_CTRL_DQ 0x310 -#define EMC_FDPD_CTRL_CMD 0x314 -#define EMC_PRE_REFRESH_REQ_CNT 0x3dc -#define EMC_REFCTRL2 0x580 -#define EMC_FBIO_CFG7 0x584 -#define EMC_FBIO_CFG7_CH0_ENABLE (1 << 1) -#define EMC_FBIO_CFG7_CH1_ENABLE (1 << 2) - -#define EMC_DATA_BRLSHFT_0 0x588 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0 -#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT) - -#define EMC_DATA_BRLSHFT_1 0x58c -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT) -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0 -#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK \ - (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT) - -#define EMC_DQS_BRLSHFT_0 0x594 -#define EMC_DQS_BRLSHFT_1 0x598 -#define EMC_CMD_BRLSHFT_0 0x59c -#define EMC_CMD_BRLSHFT_1 0x5a0 -#define EMC_CMD_BRLSHFT_2 0x5a4 -#define EMC_CMD_BRLSHFT_3 0x5a8 -#define EMC_QUSE_BRLSHFT_0 0x5ac -#define EMC_QUSE_BRLSHFT_1 0x5b8 -#define EMC_QUSE_BRLSHFT_2 0x5bc -#define EMC_QUSE_BRLSHFT_3 0x5c4 -#define EMC_FBIO_CFG8 0x5c8 -#define EMC_CMD_MAPPING_CMD0_0 0x380 -#define EMC_CMD_MAPPING_CMD0_1 0x384 -#define EMC_CMD_MAPPING_CMD0_2 0x388 -#define EMC_CMD_MAPPING_CMD1_0 0x38c -#define EMC_CMD_MAPPING_CMD1_1 0x390 -#define EMC_CMD_MAPPING_CMD1_2 0x394 -#define EMC_CMD_MAPPING_CMD2_0 0x398 -#define EMC_CMD_MAPPING_CMD2_1 0x39c -#define EMC_CMD_MAPPING_CMD2_2 0x3a0 -#define EMC_CMD_MAPPING_CMD3_0 0x3a4 -#define EMC_CMD_MAPPING_CMD3_1 0x3a8 -#define EMC_CMD_MAPPING_CMD3_2 0x3ac -#define EMC_CMD_MAPPING_BYTE 0x3b0 -#define EMC_DYN_SELF_REF_CONTROL 0x3e0 -#define EMC_TXSRDLL 0x3e4 -#define EMC_CCFIFO_ADDR 0x3e8 -#define EMC_CCFIFO_DATA 0x3ec -#define EMC_CCFIFO_STATUS 0x3f0 -#define EMC_SWIZZLE_RANK0_BYTE0 0x404 -#define EMC_SWIZZLE_RANK0_BYTE1 0x408 -#define EMC_SWIZZLE_RANK0_BYTE2 0x40c -#define EMC_SWIZZLE_RANK0_BYTE3 0x410 -#define EMC_SWIZZLE_RANK1_BYTE0 0x418 -#define EMC_SWIZZLE_RANK1_BYTE1 0x41c -#define EMC_SWIZZLE_RANK1_BYTE2 0x420 -#define EMC_SWIZZLE_RANK1_BYTE3 0x424 -#define EMC_TR_TIMING_0 0x3b4 -#define EMC_TR_CTRL_0 0x3b8 -#define EMC_TR_CTRL_1 0x3bc -#define EMC_TR_DVFS 0x460 -#define EMC_TR_DVFS_TRAINING_DVFS (1 << 0) - -#define EMC_SWITCH_BACK_CTRL 0x3c0 -#define EMC_TR_RDV 0x3c4 -#define EMC_TR_QPOP 0x3f4 -#define EMC_TR_RDV_MASK 0x3f8 -#define EMC_TR_QSAFE 0x3fc -#define EMC_TR_QRST 0x400 -#define EMC_IBDLY 0x468 -#define EMC_OBDLY 0x46c -#define EMC_TXDSRVTTGEN 0x480 -#define EMC_WE_DURATION 0x48c -#define EMC_WS_DURATION 0x490 -#define EMC_WEV 0x494 -#define EMC_WSV 0x498 -#define EMC_CFG_3 0x49c -#define EMC_CFG_PIPE_2 0x554 -#define EMC_CFG_PIPE_CLK 0x558 -#define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON (1 << 0) - -#define EMC_CFG_PIPE_1 0x55c -#define EMC_CFG_PIPE 0x560 -#define EMC_QPOP 0x564 -#define EMC_QUSE_WIDTH 0x568 -#define EMC_PUTERM_WIDTH 0x56c -#define EMC_PROTOBIST_CONFIG_ADR_1 0x5d0 -#define EMC_PROTOBIST_CONFIG_ADR_2 0x5d4 -#define EMC_PROTOBIST_MISC 0x5d8 -#define EMC_PROTOBIST_WDATA_LOWER 0x5dc -#define EMC_PROTOBIST_WDATA_UPPER 0x5e0 -#define EMC_PROTOBIST_RDATA 0x5ec -#define EMC_DLL_CFG_0 0x5e4 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_IGNORE_START (1 << 29) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_DUAL_PASS_LOCK (1 << 28) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_SHIFT 24 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_MASK \ - (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_SHIFT) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_SHIFT 20 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_MASK \ - (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_SHIFT) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_SHIFT 16 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_MASK \ - (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_SHIFT) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_SHIFT 12 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_MASK \ - (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_SHIFT) -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_SHIFT 4 -#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_MASK \ - (0xff << EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_SHIFT) -#define EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_SHIFT 0 -#define EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_MASK \ - (0xf << EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_SHIFT) - -#define EMC_DLL_CFG_1 0x5e8 -#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT 10 -#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK \ - (0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT) - -#define EMC_TRAINING_CMD 0xe00 -#define EMC_TRAINING_CMD_PRIME (1 << 0) -#define EMC_TRAINING_CMD_CA (1 << 1) -#define EMC_TRAINING_CMD_RD (1 << 2) -#define EMC_TRAINING_CMD_WR (1 << 3) -#define EMC_TRAINING_CMD_QUSE (1 << 4) -#define EMC_TRAINING_CMD_CA_VREF (1 << 5) -#define EMC_TRAINING_CMD_RD_VREF (1 << 6) -#define EMC_TRAINING_CMD_WR_VREF (1 << 7) -#define EMC_TRAINING_CMD_QUSE_VREF (1 << 8) -#define EMC_TRAINING_CMD_GO (1 << 31) - -#define EMC_TRAINING_CTRL 0xe04 -#define EMC_TRAINING_CTRL_SWAP_RANK (1 << 14) - -#define EMC_TRAINING_STATUS 0xe08 -#define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c -#define EMC_TRAINING_QUSE_FINE_CTRL 0xe10 -#define EMC_TRAINING_QUSE_CTRL_MISC 0xe14 -#define EMC_TRAINING_WRITE_FINE_CTRL 0xe18 -#define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c -#define EMC_TRAINING_WRITE_VREF_CTRL 0xe20 -#define EMC_TRAINING_READ_FINE_CTRL 0xe24 -#define EMC_TRAINING_READ_CTRL_MISC 0xe28 -#define EMC_TRAINING_READ_VREF_CTRL 0xe2c -#define EMC_TRAINING_CA_FINE_CTRL 0xe30 -#define EMC_TRAINING_CA_CTRL_MISC 0xe34 -#define EMC_TRAINING_CA_CTRL_MISC1 0xe38 -#define EMC_TRAINING_CA_VREF_CTRL 0xe3c -#define EMC_TRAINING_CA_TADR_CTRL 0xe40 -#define EMC_TRAINING_SETTLE 0xe44 -#define EMC_TRAINING_DEBUG_CTRL 0xe48 -#define EMC_TRAINING_DEBUG_DQ0 0xe4c -#define EMC_TRAINING_DEBUG_DQ1 0xe50 -#define EMC_TRAINING_DEBUG_DQ2 0xe54 -#define EMC_TRAINING_DEBUG_DQ3 0xe58 -#define EMC_TRAINING_MPC 0xe5c -#define EMC_TRAINING_PATRAM_CTRL 0xe60 -#define EMC_TRAINING_PATRAM_DQ 0xe64 -#define EMC_TRAINING_PATRAM_DMI 0xe68 -#define EMC_TRAINING_VREF_SETTLE 0xe6c -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE0 0xe70 -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE1 0xe74 -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE2 0xe78 -#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE3 0xe7c -#define EMC_TRAINING_RW_EYE_CENTER_IB_MISC 0xe80 -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE0 0xe84 -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE1 0xe88 -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE2 0xe8c -#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE3 0xe90 -#define EMC_TRAINING_RW_EYE_CENTER_OB_MISC 0xe94 -#define EMC_TRAINING_RW_OFFSET_IB_BYTE0 0xe98 -#define EMC_TRAINING_RW_OFFSET_IB_BYTE1 0xe9c -#define EMC_TRAINING_RW_OFFSET_IB_BYTE2 0xea0 -#define EMC_TRAINING_RW_OFFSET_IB_BYTE3 0xea4 -#define EMC_TRAINING_RW_OFFSET_IB_MISC 0xea8 -#define EMC_TRAINING_RW_OFFSET_OB_BYTE0 0xeac -#define EMC_TRAINING_RW_OFFSET_OB_BYTE1 0xeb0 -#define EMC_TRAINING_RW_OFFSET_OB_BYTE2 0xeb4 -#define EMC_TRAINING_RW_OFFSET_OB_BYTE3 0xeb8 -#define EMC_TRAINING_RW_OFFSET_OB_MISC 0xebc -#define EMC_TRAINING_OPT_CA_VREF 0xec0 -#define EMC_TRAINING_OPT_DQ_OB_VREF 0xec4 -#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK0 0xec8 -#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK1 0xecc -#define EMC_TRAINING_QUSE_VREF_CTRL 0xed0 -#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4 -#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8 -#define EMC_TRAINING_DRAMC_TIMING 0xedc -#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600 -#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604 -#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608 -#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c -#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610 -#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614 -#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620 -#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624 -#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628 -#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c -#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630 -#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654 - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT \ - 16 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT \ - 0 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_MASK \ - 0x3ff << \ - EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT - -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670 -#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0 -#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4 0x6d0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5 0x6d4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4 0x6f0 -#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5 0x6f4 -#define EMC_PMACRO_TX_PWRD_0 0x720 -#define EMC_PMACRO_TX_PWRD_1 0x724 -#define EMC_PMACRO_TX_PWRD_2 0x728 -#define EMC_PMACRO_TX_PWRD_3 0x72c -#define EMC_PMACRO_TX_PWRD_4 0x730 -#define EMC_PMACRO_TX_PWRD_5 0x734 -#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740 -#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744 -#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c -#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748 -#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750 -#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754 -#define EMC_PMACRO_DDLL_BYPASS 0x760 -#define EMC_PMACRO_DDLL_PWRD_0 0x770 -#define EMC_PMACRO_DDLL_PWRD_1 0x774 -#define EMC_PMACRO_DDLL_PWRD_2 0x778 -#define EMC_PMACRO_CMD_CTRL_0 0x780 -#define EMC_PMACRO_CMD_CTRL_1 0x784 -#define EMC_PMACRO_CMD_CTRL_2 0x788 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8 -#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0 0xa80 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1 0xa84 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2 0xa88 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0 0xa90 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1 0xa94 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2 0xa98 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0 0xaa0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1 0xaa4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2 0xaa8 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0 0xab0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1 0xab4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2 0xab8 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0 0xb80 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1 0xb84 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2 0xb88 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0 0xb90 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1 0xb94 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2 0xb98 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0 0xba0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1 0xba4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2 0xba8 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0 0xbb0 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1 0xbb4 -#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2 0xbb8 -#define EMC_PMACRO_IB_VREF_DQ_0 0xbe0 -#define EMC_PMACRO_IB_VREF_DQ_1 0xbe4 -#define EMC_PMACRO_IB_VREF_DQ_2 0xbe8 -#define EMC_PMACRO_IB_VREF_DQS_0 0xbf0 -#define EMC_PMACRO_IB_VREF_DQS_1 0xbf4 -#define EMC_PMACRO_IB_VREF_DQS_2 0xbf8 -#define EMC_PMACRO_IB_RXRT 0xcf4 -#define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00 -#define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04 -#define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08 -#define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c -#define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10 -#define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14 -#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20 -#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24 -#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28 -#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30 -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0 (1 << 16) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1 (1 << 17) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2 (1 << 18) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3 (1 << 19) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4 (1 << 20) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5 (1 << 21) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6 (1 << 22) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7 (1 << 23) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD0 (1 << 24) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD1 (1 << 25) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD2 (1 << 26) -#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD3 (1 << 27) - -#define EMC_PMACRO_VTTGEN_CTRL_0 0xc34 -#define EMC_PMACRO_VTTGEN_CTRL_1 0xc38 -#define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0 -#define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c -#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD (1 << 0) -#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_MODE (1 << 1) -#define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD (1 << 2) - -#define EMC_PMACRO_PAD_CFG_CTRL 0xc40 -#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50 -#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54 -#define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58 -#define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_SHIFT 8 -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_MASK (0x3 << \ - EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_SHIFT) -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_SHIFT 4 -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_MASK (0x3 << \ - EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_SHIFT) -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_SHIFT 0 -#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_MASK (0x3 << \ - EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_SHIFT) - -#define RX_TERM_MODE \ - ~(EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_MASK | \ - EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_MASK | \ - EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_MASK) - -#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60 -#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC (1 << 1) -#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC (1 << 9) -#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC (1 << 16) -#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC (1 << 24) -#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON (1 << 26) - -#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64 -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF (1 << 0) -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC (1 << 1) -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF (1 << 8) -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC (1 << 9) -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC (1 << 16) -#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC (1 << 24) - -#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68 -#define EMC_PMACRO_BRICK_MAPPING_0 0xc80 -#define EMC_PMACRO_BRICK_MAPPING_1 0xc84 -#define EMC_PMACRO_BRICK_MAPPING_2 0xc88 -#define EMC_PMACRO_DDLLCAL_CAL 0xce0 -#define EMC_PMACRO_DDLL_OFFSET 0xce4 -#define EMC_PMACRO_DDLL_PERIODIC_OFFSET 0xce8 -#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330 -#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334 -#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318 -#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c -#define EMC_PMACRO_TRAINING_CTRL_0 0xcf8 -#define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR (1 << 3) - -#define EMC_PMACRO_TRAINING_CTRL_1 0xcfc -#define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR (1 << 3) - -#define EMC_PMC_SCRATCH1 0x440 -#define EMC_PMC_SCRATCH2 0x444 -#define EMC_PMC_SCRATCH3 0x448 - -#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xd40 -#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xd44 -#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xd48 -#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xd4c -#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xd50 -#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xd54 -#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xd60 -#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xd64 -#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xd68 -#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xd6c -#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xd70 -#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xd74 -#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xd80 -#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xd84 -#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xd88 -#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xd8c -#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xd90 -#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xd94 - -#define EMC_PMACRO_PMU_OUT_EOFF1_0 0xda0 -#define EMC_PMACRO_PMU_OUT_EOFF1_1 0xda4 -#define EMC_PMACRO_PMU_OUT_EOFF1_2 0xda8 -#define EMC_PMACRO_PMU_OUT_EOFF1_3 0xdac -#define EMC_PMACRO_PMU_OUT_EOFF1_4 0xdb0 -#define EMC_PMACRO_PMU_OUT_EOFF1_5 0xdb4 - -#define EMC_PMACRO_COMP_PMU_OUT 0xdc0 -#define EMC_PMACRO_DATA_PI_CTRL 0x110 -#define EMC_PMACRO_CMD_PI_CTRL 0x114 - -#define EMC_AUTO_CAL_CONFIG9 0x42c - -#define EMC_TRTM 0xbc -#define EMC_TWTM 0xf8 -#define EMC_TRATM 0xfc -#define EMC_TWATM 0x108 -#define EMC_TR2REF 0x10c - -#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c - -#endif diff --git a/sept/sept-secondary/src/exception_handlers.c b/sept/sept-secondary/src/exception_handlers.c deleted file mode 100644 index 88c01c812..000000000 --- a/sept/sept-secondary/src/exception_handlers.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "exception_handlers.h" -#include "utils.h" -#include "../../../fusee/common/log.h" -#include "../../../fusee/common/vsprintf.h" - -#define CODE_DUMP_SIZE 0x30 -#define STACK_DUMP_SIZE 0x30 - -extern const uint32_t exception_handler_table[]; - -static const char *exception_names[] = { - "Reset", "Undefined instruction", "SWI", "Prefetch abort", "Data abort", "Reserved", "IRQ", "FIQ", -}; - -static const char *register_names[] = { - "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R8", "R9", "R10", "R11", "R12", - "SP", "LR", "PC", "CPSR", -}; - -/* Adapted from https://gist.github.com/ccbrown/9722406 */ -static void hexdump(const void* data, size_t size, uintptr_t addrbase, char* strbuf) { - const uint8_t *d = (const uint8_t *)data; - char ascii[17] = {0}; - ascii[16] = '\0'; - - for (size_t i = 0; i < size; i++) { - if (i % 16 == 0) { - strbuf += sprintf(strbuf, "%0*" PRIXPTR ": | ", 2 * sizeof(addrbase), addrbase + i); - } - strbuf += sprintf(strbuf, "%02X ", d[i]); - if (d[i] >= ' ' && d[i] <= '~') { - ascii[i % 16] = d[i]; - } else { - ascii[i % 16] = '.'; - } - if ((i+1) % 8 == 0 || i+1 == size) { - strbuf += sprintf(strbuf, " "); - if ((i+1) % 16 == 0) { - strbuf += sprintf(strbuf, "| %s \n", ascii); - } else if (i+1 == size) { - ascii[(i+1) % 16] = '\0'; - if ((i+1) % 16 <= 8) { - strbuf += sprintf(strbuf, " "); - } - for (size_t j = (i+1) % 16; j < 16; j++) { - strbuf += sprintf(strbuf, " "); - } - strbuf += sprintf(strbuf, "| %s \n", ascii); - } - } - } -} - -void setup_exception_handlers(void) { - volatile uint32_t *bpmp_exception_handler_table = (volatile uint32_t *)0x6000F200; - for (int i = 0; i < 8; i++) { - if (exception_handler_table[i] != 0) { - bpmp_exception_handler_table[i] = exception_handler_table[i]; - } - } -} - -void exception_handler_main(uint32_t *registers, unsigned int exception_type) { - char exception_log[0x400] = {0}; - uint8_t code_dump[CODE_DUMP_SIZE] = {0}; - uint8_t stack_dump[STACK_DUMP_SIZE] = {0}; - size_t code_dump_size = 0; - size_t stack_dump_size = 0; - - uint32_t pc = registers[15]; - uint32_t cpsr = registers[16]; - uint32_t instr_addr = pc + ((cpsr & 0x20) ? 2 : 4) - CODE_DUMP_SIZE; - - sprintf(exception_log, "An exception occurred!\n"); - - code_dump_size = safecpy(code_dump, (const void *)instr_addr, CODE_DUMP_SIZE); - stack_dump_size = safecpy(stack_dump, (const void *)registers[13], STACK_DUMP_SIZE); - - sprintf(exception_log + strlen(exception_log), "\nException type: %s\n", exception_names[exception_type]); - sprintf(exception_log + strlen(exception_log), "\nRegisters:\n"); - - /* Print r0 to pc. */ - for (int i = 0; i < 16; i += 2) { - sprintf(exception_log + strlen(exception_log), "%-7s%08"PRIX32" %-7s%08"PRIX32"\n", - register_names[i], registers[i], register_names[i+1], registers[i+1]); - } - - /* Print cpsr. */ - sprintf(exception_log + strlen(exception_log), "%-7s%08"PRIX32"\n", register_names[16], registers[16]); - - /* Print code and stack regions. */ - sprintf(exception_log + strlen(exception_log), "\nCode dump:\n"); - hexdump(code_dump, code_dump_size, instr_addr, exception_log + strlen(exception_log)); - sprintf(exception_log + strlen(exception_log), "\nStack dump:\n"); - hexdump(stack_dump, stack_dump_size, registers[13], exception_log + strlen(exception_log)); - sprintf(exception_log + strlen(exception_log), "\n"); - - /* Throw fatal error with the full exception log. */ - fatal_error(exception_log); -} diff --git a/sept/sept-secondary/src/exception_handlers.h b/sept/sept-secondary/src/exception_handlers.h deleted file mode 100644 index 8cbd1c07f..000000000 --- a/sept/sept-secondary/src/exception_handlers.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_EXCEPTION_HANDLERS_H -#define FUSEE_EXCEPTION_HANDLERS_H - -#include -#include - -/* Copies up to len bytes, stops and returns the read length on data fault. */ -size_t safecpy(void *dst, const void *src, size_t len); - -void setup_exception_handlers(void); - -#endif diff --git a/sept/sept-secondary/src/exception_handlers_asm.s b/sept/sept-secondary/src/exception_handlers_asm.s deleted file mode 100644 index 4404c565a..000000000 --- a/sept/sept-secondary/src/exception_handlers_asm.s +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -.macro GEN_USUAL_HANDLER name, index, lr_arm_displ, lr_thumb_displ - _exception_handler_\name: - ldr sp, =_regs - stmia sp!, {r0-r7} - - /* Adjust lr to make it point to the location where the exception occured. */ - mrs r1, spsr - tst r1, #0x20 - subeq lr, lr, #\lr_arm_displ - subne lr, lr, #\lr_thumb_displ - - mov r0, sp - mov r1, #\index - b _exception_handler_common -.endm - -.section .text.exception_handlers_asm, "ax", %progbits -.arm -.align 5 - -_exception_handler_common: - mrs r2, spsr - mrs r3, cpsr - - /* Mask interrupts. */ - orr r3, #0xC0 - msr cpsr_cx, r3 - - /* Switch to the mode that triggered the interrupt, get the remaining regs, switch back. */ - ands r4, r2, #0xF - moveq r4, #0xF /* usr => sys */ - bic r5, r3, #0xF - orr r5, r4 - msr cpsr_c, r5 - stmia r0!, {r8-lr} - msr cpsr_c, r3 - - str lr, [r0], #4 - str r2, [r0] - - /* Finally, switch to system mode, setting interrupts and clearing the flags; set sp as well. */ - msr cpsr_cxsf, #0xDF - ldr sp, =(_exception_handler_stack + 0x1000) - ldr r0, =_regs - bl exception_handler_main - b . - -GEN_USUAL_HANDLER undefined_instruction, 1, 4, 2 -GEN_USUAL_HANDLER swi, 2, 4, 2 -GEN_USUAL_HANDLER prefetch_abort, 3, 4, 4 -GEN_USUAL_HANDLER data_abort_normal, 4, 8, 8 -GEN_USUAL_HANDLER fiq, 7, 4, 4 - -_exception_handler_data_abort: - /* Mask interrupts (abort mode). */ - msr cpsr_cx, #0xD7 - - adr sp, safecpy+8 - cmp lr, sp - blo _exception_handler_data_abort_normal - adr sp, _safecpy_end+8 - cmp lr, sp - bhs _exception_handler_data_abort_normal - - /* Set the flags, set r12 to 0 for safecpy, return from exception. */ - msr spsr_f, #(1 << 30) - mov r12, #0 - subs pc, lr, #4 - -.global safecpy -.type safecpy, %function -safecpy: - push {r4, lr} - mov r3, #0 - movs r12, #1 - - _safecpy_loop: - ldrb r4, [r1, r3] - cmp r12, #0 - beq _safecpy_loop_end - strb r4, [r0, r3] - add r3, #1 - cmp r3, r2 - blo _safecpy_loop - - _safecpy_loop_end: - mov r0, r3 - pop {r4, lr} - bx lr /* Need to do that separately on ARMv4. */ - -_safecpy_end: - -.section .rodata.exception_handlers_asm, "a", %progbits -.align 2 -.global exception_handler_table -exception_handler_table: - .word 0 /* Reset */ - .word _exception_handler_undefined_instruction - .word _exception_handler_swi - .word _exception_handler_prefetch_abort - .word _exception_handler_data_abort - .word 0 /* Reserved */ - .word 0 /* IRQ */ - .word _exception_handler_fiq - -.section .bss.exception_handlers_asm, "w", %nobits -.align 4 -_exception_handler_stack: .skip 0x1000 -_regs: .skip (4 * 17) diff --git a/sept/sept-secondary/src/flow.h b/sept/sept-secondary/src/flow.h deleted file mode 100644 index 3b083bf1e..000000000 --- a/sept/sept-secondary/src/flow.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_FLOW_CTLR_H -#define FUSEE_FLOW_CTLR_H - -#include - -#define FLOW_CTLR_BASE 0x60007000 -#define MAKE_FLOW_REG(n) MAKE_REG32(FLOW_CTLR_BASE + n) - -#define FLOW_CTLR_HALT_COP_EVENTS_0 MAKE_FLOW_REG(0x004) -#define FLOW_CTLR_RAM_REPAIR_0 MAKE_FLOW_REG(0x040) -#define FLOW_CTLR_FLOW_DBG_QUAL_0 MAKE_FLOW_REG(0x050) -#define FLOW_CTLR_L2FLUSH_CONTROL_0 MAKE_FLOW_REG(0x094) -#define FLOW_CTLR_BPMP_CLUSTER_CONTROL_0 MAKE_FLOW_REG(0x098) - -#endif diff --git a/sept/sept-secondary/src/fs_utils.c b/sept/sept-secondary/src/fs_utils.c deleted file mode 100644 index 7e9b19ea7..000000000 --- a/sept/sept-secondary/src/fs_utils.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "fs_utils.h" -#include "mc.h" -#include "../../../fusee/common/fatfs/ff.h" -#include "../../../fusee/common/log.h" - -FATFS sd_fs; -static bool g_sd_mounted = false; -static bool g_sd_initialized = false; -static bool g_ahb_redirect_enabled = false; -sdmmc_t g_sd_sdmmc; -sdmmc_device_t g_sd_device; - -bool mount_sd(void) -{ - /* Already mounted. */ - if (g_sd_mounted) - return true; - - /* Enable AHB redirection if necessary. */ - if (!g_ahb_redirect_enabled) { - mc_enable_ahb_redirect(); - g_ahb_redirect_enabled = true; - } - - if (!g_sd_initialized) { - /* Initialize SD. */ - if (sdmmc_device_sd_init(&g_sd_device, &g_sd_sdmmc, SDMMC_BUS_WIDTH_4BIT, SDMMC_SPEED_SD_SDR104)) - { - g_sd_initialized = true; - - /* Mount SD. */ - if (f_mount(&sd_fs, "", 1) == FR_OK) { - print(SCREEN_LOG_LEVEL_INFO, "Mounted SD card!\n"); - g_sd_mounted = true; - } - } - else - fatal_error("Failed to initialize the SD card!.\n"); - } - - return g_sd_mounted; -} - -void unmount_sd(void) -{ - if (g_sd_mounted) - { - f_mount(NULL, "", 1); - sdmmc_device_finish(&g_sd_device); - g_sd_mounted = false; - } - - /* Disable AHB redirection if necessary. */ - if (g_ahb_redirect_enabled) { - mc_disable_ahb_redirect(); - g_ahb_redirect_enabled = false; - } -} - -uint32_t get_file_size(const char *filename) -{ - /* SD card hasn't been mounted yet. */ - if (!g_sd_mounted) - return 0; - - /* Open the file for reading. */ - FIL f; - if (f_open(&f, filename, FA_READ) != FR_OK) - return 0; - - /* Get the file size. */ - uint32_t file_size = f_size(&f); - - /* Close the file. */ - f_close(&f); - - return file_size; -} - -int read_from_file(void *dst, uint32_t dst_size, const char *filename) -{ - /* SD card hasn't been mounted yet. */ - if (!g_sd_mounted) - return 0; - - /* Open the file for reading. */ - FIL f; - if (f_open(&f, filename, FA_READ) != FR_OK) - return 0; - - /* Sync. */ - f_sync(&f); - - /* Read from file. */ - UINT br = 0; - int res = f_read(&f, dst, dst_size, &br); - f_close(&f); - - return (res == FR_OK) ? (int)br : 0; -} - -int write_to_file(void *src, uint32_t src_size, const char *filename) -{ - /* SD card hasn't been mounted yet. */ - if (!g_sd_mounted) - return 0; - - /* Open the file for writing. */ - FIL f; - if (f_open(&f, filename, FA_CREATE_ALWAYS | FA_WRITE) != FR_OK) - return 0; - - /* Sync. */ - f_sync(&f); - - /* Write to file. */ - UINT bw = 0; - int res = f_write(&f, src, src_size, &bw); - f_close(&f); - - return (res == FR_OK) ? (int)bw : 0; -} \ No newline at end of file diff --git a/sept/sept-secondary/src/fs_utils.h b/sept/sept-secondary/src/fs_utils.h deleted file mode 100644 index 057cff991..000000000 --- a/sept/sept-secondary/src/fs_utils.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_FS_UTILS_H -#define FUSEE_FS_UTILS_H - -#include -#include - -#include "../../../fusee/common/sdmmc/sdmmc.h" -#include "utils.h" - -extern sdmmc_t g_sd_sdmmc; -extern sdmmc_device_t g_sd_device; - -bool mount_sd(void); -void unmount_sd(void); -uint32_t get_file_size(const char *filename); -int read_from_file(void *dst, uint32_t dst_size, const char *filename); -int write_to_file(void *src, uint32_t src_size, const char *filename); - -#endif diff --git a/sept/sept-secondary/src/fuse.c b/sept/sept-secondary/src/fuse.c deleted file mode 100644 index 4de1635b2..000000000 --- a/sept/sept-secondary/src/fuse.c +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -#include "car.h" -#include "fuse.h" -#include "pmc.h" -#include "timers.h" - -/* Initialize the fuse driver */ -void fuse_init(void) { - /* Make all fuse registers visible, disable the private key and disable programming. */ - clkrst_enable_fuse_regs(true); - /* fuse_disable_private_key(); */ - fuse_disable_programming(); -} - -/* Disable access to the private key and set the TZ sticky bit. */ -void fuse_disable_private_key(void) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - fuse->FUSE_PRIVATEKEYDISABLE = 0x10; -} - -/* Disable all fuse programming. */ -void fuse_disable_programming(void) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - fuse->FUSE_DISABLEREGPROGRAM = 1; -} - -/* Enable power to the fuse hardware array. */ -void fuse_enable_power(void) { - volatile tegra_pmc_t *pmc = pmc_get_regs(); - pmc->fuse_control &= ~(0x200); /* Clear PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */ - mdelay(1); - pmc->fuse_control |= 0x100; /* Set PMC_FUSE_CTRL_PS18_LATCH_SET. */ - mdelay(1); -} - -/* Disable power to the fuse hardware array. */ -void fuse_disable_power(void) { - volatile tegra_pmc_t *pmc = pmc_get_regs(); - pmc->fuse_control &= ~(0x100); /* Clear PMC_FUSE_CTRL_PS18_LATCH_SET. */ - mdelay(1); - pmc->fuse_control |= 0x200; /* Set PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */ - mdelay(1); -} - -/* Wait for the fuse driver to go idle. */ -static void fuse_wait_idle(void) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - uint32_t ctrl_val = 0; - - /* Wait for STATE_IDLE */ - while ((ctrl_val & (0xF0000)) != 0x40000) { - ctrl_val = fuse->FUSE_FUSECTRL; - } -} - -/* Read a fuse from the hardware array. */ -uint32_t fuse_hw_read(uint32_t addr) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - - /* Wait for idle state. */ - fuse_wait_idle(); - - /* Program the target address. */ - fuse->FUSE_FUSEADDR = addr; - - /* Enable read operation in control register. */ - uint32_t ctrl_val = fuse->FUSE_FUSECTRL; - ctrl_val &= ~0x3; - ctrl_val |= 0x1; /* Set READ command. */ - fuse->FUSE_FUSECTRL = ctrl_val; - - /* Wait for idle state. */ - fuse_wait_idle(); - - return fuse->FUSE_FUSERDATA; -} - -/* Write a fuse in the hardware array. */ -void fuse_hw_write(uint32_t value, uint32_t addr) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - - /* Wait for idle state. */ - fuse_wait_idle(); - - /* Program the target address and value. */ - fuse->FUSE_FUSEADDR = addr; - fuse->FUSE_FUSEWDATA = value; - - /* Enable write operation in control register. */ - uint32_t ctrl_val = fuse->FUSE_FUSECTRL; - ctrl_val &= ~0x3; - ctrl_val |= 0x2; /* Set WRITE command. */ - fuse->FUSE_FUSECTRL = ctrl_val; - - /* Wait for idle state. */ - fuse_wait_idle(); -} - -/* Sense the fuse hardware array into the fuse cache. */ -void fuse_hw_sense(void) { - volatile tegra_fuse_t *fuse = fuse_get_regs(); - - /* Wait for idle state. */ - fuse_wait_idle(); - - /* Enable sense operation in control register */ - uint32_t ctrl_val = fuse->FUSE_FUSECTRL; - ctrl_val &= ~0x3; - ctrl_val |= 0x3; /* Set SENSE_CTRL command */ - fuse->FUSE_FUSECTRL = ctrl_val; - - /* Wait for idle state. */ - fuse_wait_idle(); -} - -/* Read the SKU info register. */ -uint32_t fuse_get_sku_info(void) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - return fuse_chip->FUSE_SKU_INFO; -} - -/* Read the bootrom patch version. */ -uint32_t fuse_get_bootrom_patch_version(void) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB; -} - -/* Read a spare bit register. */ -uint32_t fuse_get_spare_bit(uint32_t index) { - uint32_t soc_type = fuse_get_soc_type(); - if (soc_type == 0) { - if (index < 32) { - volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs(); - return fuse_chip->FUSE_SPARE_BIT[index]; - } - } else if (soc_type == 1) { - if (index < 30) { - volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); - return fuse_chip->FUSE_SPARE_BIT[index]; - } - } - return 0; -} - -/* Read a reserved ODM register. */ -uint32_t fuse_get_reserved_odm(uint32_t index) { - if (index < 8) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - return fuse_chip->FUSE_RESERVED_ODM0[index]; - } else { - uint32_t soc_type = fuse_get_soc_type(); - if (soc_type == 1) { - volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs(); - if (index < 22) { - return fuse_chip->FUSE_RESERVED_ODM8[index - 8]; - } else if (index < 25) { - return fuse_chip->FUSE_RESERVED_ODM22[index - 22]; - } else if (index < 26) { - return fuse_chip->FUSE_RESERVED_ODM25; - } else if (index < 29) { - return fuse_chip->FUSE_RESERVED_ODM26[index - 26]; - } else if (index < 30) { - return fuse_chip->FUSE_RESERVED_ODM29; - } - } - } - return 0; -} - -/* Get the DramId. */ -uint32_t fuse_get_dram_id(void) { - return ((fuse_get_reserved_odm(4) >> 3) & 0x1F); -} - -/* Derive the DeviceId. */ -uint64_t fuse_get_device_id(void) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - - uint64_t device_id = 0; - uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF; - uint64_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF; - uint64_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F; - uint32_t lot_code = fuse_chip->FUSE_OPT_LOT_CODE_0; - uint64_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F; - - uint64_t derived_lot_code = 0; - for (unsigned int i = 0; i < 5; i++) { - derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F); - } - derived_lot_code &= 0x03FFFFFF; - - device_id |= y_coord << 0; - device_id |= x_coord << 9; - device_id |= wafer_id << 18; - device_id |= derived_lot_code << 24; - device_id |= fab_code << 50; - - return device_id; -} - -/* Derive the HardwareType with firmware specific checks. */ -uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) { - uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4); - uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1)); - - if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1); - - switch (hardware_type) { - case 0x00: return (fuse_spare_bit9 == 0) ? 0 : 3; - case 0x01: return 0; /* HardwareType_Icosa */ - case 0x02: return 1; /* HardwareType_Copper */ - default: return 3; /* HardwareType_Undefined */ - } - } else { - hardware_type |= ((fuse_reserved_odm4 >> 14) & 0x3C); - - if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) { - switch (hardware_type) { - case 0x01: return 0; /* HardwareType_Icosa */ - case 0x02: return 1; /* HardwareType_Copper */ - case 0x04: return 3; /* HardwareType_Iowa */ - default: return 4; /* HardwareType_Undefined */ - } - } else { - if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_10_0_0) { - switch (hardware_type) { - case 0x01: return 0; /* HardwareType_Icosa */ - case 0x02: return 4; /* HardwareType_Calcio */ - case 0x04: return 3; /* HardwareType_Iowa */ - case 0x08: return 2; /* HardwareType_Hoag */ - default: return 0xF; /* HardwareType_Undefined */ - } - } else { - switch (hardware_type) { - case 0x01: return 0; /* HardwareType_Icosa */ - case 0x02: return 4; /* HardwareType_Calcio */ - case 0x04: return 3; /* HardwareType_Iowa */ - case 0x08: return 2; /* HardwareType_Hoag */ - case 0x10: return 5; /* HardwareType_Five */ - default: return 0xF; /* HardwareType_Undefined */ - } - } - } - } -} - -/* Derive the HardwareType. */ -uint32_t fuse_get_hardware_type(void) { - return fuse_get_hardware_type_with_firmware_check(ATMOSPHERE_TARGET_FIRMWARE_CURRENT); -} - -/* Derive the HardwareState. */ -uint32_t fuse_get_hardware_state(void) { - uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4); - uint32_t hardware_state = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3)); - - switch (hardware_state) { - case 0x03: return 0; /* HardwareState_Development */ - case 0x04: return 1; /* HardwareState_Production */ - default: return 2; /* HardwareState_Undefined */ - } -} - -/* Derive the 16-byte HardwareInfo and copy to output buffer. */ -void fuse_get_hardware_info(void *dst) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - uint32_t hw_info[0x4]; - - uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F; - uint32_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF; - uint32_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF; - uint32_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F; - uint32_t lot_code_0 = fuse_chip->FUSE_OPT_LOT_CODE_0; - uint32_t lot_code_1 = fuse_chip->FUSE_OPT_LOT_CODE_1 & 0x0FFFFFFF; - uint32_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F; - uint32_t vendor_code = fuse_chip->FUSE_OPT_VENDOR_CODE & 0xF; - - /* Hardware Info = OPS_RESERVED || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */ - hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (ops_reserved)); - hw_info[1] = (uint32_t)((lot_code_0 << 26) | (lot_code_1 >> 2)); - hw_info[2] = (uint32_t)((fab_code << 26) | (lot_code_0 >> 6)); - hw_info[3] = (uint32_t)(vendor_code); - - memcpy(dst, hw_info, 0x10); -} - -/* Check if have a new ODM fuse format. */ -bool fuse_is_new_format(void) { - return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2)); -} - -/* Get the DeviceUniqueKeyGeneration. */ -uint32_t fuse_get_device_unique_key_generation(void) { - if (fuse_is_new_format()) { - return (fuse_get_reserved_odm(2) & 0x1F); - } else { - return 0; - } -} - -/* Get the SocType from the HardwareType. */ -uint32_t fuse_get_soc_type(void) { - switch (fuse_get_hardware_type()) { - case 0: - case 1: - return 0; /* SocType_Erista */ - case 3: - case 2: - case 4: - case 5: - return 1; /* SocType_Mariko */ - default: - return 0xF; /* SocType_Undefined */ - } -} - -/* Get the Regulator type. */ -uint32_t fuse_get_regulator(void) { - if (fuse_get_soc_type() == 1) { - return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */ - } else { - return 0; /* Regulator_Erista_Max77621 */ - } -} diff --git a/sept/sept-secondary/src/fuse.h b/sept/sept-secondary/src/fuse.h deleted file mode 100644 index eb590553c..000000000 --- a/sept/sept-secondary/src/fuse.h +++ /dev/null @@ -1,484 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_FUSE_H -#define FUSEE_FUSE_H - -#define FUSE_BASE 0x7000F800 -#define FUSE_CHIP_BASE (FUSE_BASE + 0x98) -#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n) -#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n) - -typedef struct { - uint32_t FUSE_FUSECTRL; - uint32_t FUSE_FUSEADDR; - uint32_t FUSE_FUSERDATA; - uint32_t FUSE_FUSEWDATA; - uint32_t FUSE_FUSETIME_RD1; - uint32_t FUSE_FUSETIME_RD2; - uint32_t FUSE_FUSETIME_PGM1; - uint32_t FUSE_FUSETIME_PGM2; - uint32_t FUSE_PRIV2INTFC_START; - uint32_t FUSE_FUSEBYPASS; - uint32_t FUSE_PRIVATEKEYDISABLE; - uint32_t FUSE_DISABLEREGPROGRAM; - uint32_t FUSE_WRITE_ACCESS_SW; - uint32_t FUSE_PWR_GOOD_SW; - uint32_t _0x38; - uint32_t FUSE_PRIV2RESHIFT; - uint32_t _0x40[0x3]; - uint32_t FUSE_FUSETIME_RD3; - uint32_t _0x50[0xC]; - uint32_t FUSE_PRIVATE_KEY0_NONZERO; - uint32_t FUSE_PRIVATE_KEY1_NONZERO; - uint32_t FUSE_PRIVATE_KEY2_NONZERO; - uint32_t FUSE_PRIVATE_KEY3_NONZERO; - uint32_t FUSE_PRIVATE_KEY4_NONZERO; - uint32_t _0x94; -} tegra_fuse_t; - -typedef struct { - uint32_t _0x98[0x1A]; - uint32_t FUSE_PRODUCTION_MODE; - uint32_t FUSE_JTAG_SECUREID_VALID; - uint32_t FUSE_ODM_LOCK; - uint32_t FUSE_OPT_OPENGL_EN; - uint32_t FUSE_SKU_INFO; - uint32_t FUSE_CPU_SPEEDO_0_CALIB; - uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t _0x11C[0x3]; - uint32_t FUSE_OPT_FT_REV; - uint32_t FUSE_CPU_SPEEDO_1_CALIB; - uint32_t FUSE_CPU_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_SPEEDO_0_CALIB; - uint32_t FUSE_SOC_SPEEDO_1_CALIB; - uint32_t FUSE_SOC_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t _0x144; - uint32_t FUSE_FA; - uint32_t FUSE_RESERVED_PRODUCTION; - uint32_t FUSE_HDMI_LANE0_CALIB; - uint32_t FUSE_HDMI_LANE1_CALIB; - uint32_t FUSE_HDMI_LANE2_CALIB; - uint32_t FUSE_HDMI_LANE3_CALIB; - uint32_t FUSE_ENCRYPTION_RATE; - uint32_t FUSE_PUBLIC_KEY[0x8]; - uint32_t FUSE_TSENSOR1_CALIB; - uint32_t FUSE_TSENSOR2_CALIB; - uint32_t _0x18C; - uint32_t FUSE_OPT_CP_REV; - uint32_t FUSE_OPT_PFG; - uint32_t FUSE_TSENSOR0_CALIB; - uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; - uint32_t FUSE_SECURITY_MODE; - uint32_t FUSE_PRIVATE_KEY[0x5]; - uint32_t FUSE_ARM_JTAG_DIS; - uint32_t FUSE_BOOT_DEVICE_INFO; - uint32_t FUSE_RESERVED_SW; - uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM0[0x8]; - uint32_t FUSE_OBS_DIS; - uint32_t _0x1EC; - uint32_t FUSE_USB_CALIB; - uint32_t FUSE_SKU_DIRECT_CONFIG; - uint32_t FUSE_KFUSE_PRIVKEY_CTRL; - uint32_t FUSE_PACKAGE_INFO; - uint32_t FUSE_OPT_VENDOR_CODE; - uint32_t FUSE_OPT_FAB_CODE; - uint32_t FUSE_OPT_LOT_CODE_0; - uint32_t FUSE_OPT_LOT_CODE_1; - uint32_t FUSE_OPT_WAFER_ID; - uint32_t FUSE_OPT_X_COORDINATE; - uint32_t FUSE_OPT_Y_COORDINATE; - uint32_t FUSE_OPT_SEC_DEBUG_EN; - uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t _0x224; - uint32_t FUSE_GPU_IDDQ_CALIB; - uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_CLOCK_BOUNDOUT0; - uint32_t FUSE_CLOCK_BOUNDOUT1; - uint32_t _0x238[0x3]; - uint32_t FUSE_OPT_SAMPLE_TYPE; - uint32_t FUSE_OPT_SUBREVISION; - uint32_t FUSE_OPT_SW_RESERVED_0; - uint32_t FUSE_OPT_SW_RESERVED_1; - uint32_t FUSE_TSENSOR4_CALIB; - uint32_t FUSE_TSENSOR5_CALIB; - uint32_t FUSE_TSENSOR6_CALIB; - uint32_t FUSE_TSENSOR7_CALIB; - uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t _0x268[0x5]; - uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; - uint32_t FUSE_TSENSOR_COMMON; - uint32_t FUSE_OPT_CP_BIN; - uint32_t FUSE_OPT_GPU_DISABLE; - uint32_t FUSE_OPT_FT_BIN; - uint32_t FUSE_OPT_DONE_MAP; - uint32_t _0x294; - uint32_t FUSE_APB2JTAG_DISABLE; - uint32_t FUSE_ODM_INFO; - uint32_t _0x2A0[0x2]; - uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x2AC[0x5]; - uint32_t FUSE_WOA_SKU_FLAG; - uint32_t FUSE_ECO_RESERVE_1; - uint32_t FUSE_GCPLEX_CONFIG_FUSE; - uint32_t FUSE_PRODUCTION_MONTH; - uint32_t FUSE_RAM_REPAIR_INDICATOR; - uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x2D8; - uint32_t FUSE_VMIN_CALIBRATION; - uint32_t FUSE_AGING_SENSOR_CALIBRATION; - uint32_t FUSE_DEBUG_AUTHENTICATION; - uint32_t FUSE_SECURE_PROVISION_INDEX; - uint32_t FUSE_SECURE_PROVISION_INFO; - uint32_t FUSE_OPT_GPU_DISABLE_CP1; - uint32_t FUSE_SPARE_ENDIS; - uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x2FC[0x2]; - uint32_t FUSE_RESERVED_CALIB0; - uint32_t FUSE_RESERVED_CALIB1; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; - uint32_t FUSE_OPT_CPU_DISABLE; - uint32_t FUSE_OPT_CPU_DISABLE_CP1; - uint32_t FUSE_TSENSOR10_CALIB; - uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t _0x324[0x5]; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; - uint32_t FUSE_OPT_CPU_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_DISABLE_CP2; - uint32_t FUSE_USB_CALIB_EXT; - uint32_t FUSE_RESERVED_FIELD; - uint32_t _0x358[0x9]; - uint32_t FUSE_SPARE_REALIGNMENT_REG; - uint32_t FUSE_SPARE_BIT[0x20]; -} tegra_fuse_chip_common_t; - -typedef struct { - uint32_t _0x98[0x1A]; - uint32_t FUSE_PRODUCTION_MODE; - uint32_t FUSE_JTAG_SECUREID_VALID; - uint32_t FUSE_ODM_LOCK; - uint32_t FUSE_OPT_OPENGL_EN; - uint32_t FUSE_SKU_INFO; - uint32_t FUSE_CPU_SPEEDO_0_CALIB; - uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t _0x11C[0x3]; - uint32_t FUSE_OPT_FT_REV; - uint32_t FUSE_CPU_SPEEDO_1_CALIB; - uint32_t FUSE_CPU_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_SPEEDO_0_CALIB; - uint32_t FUSE_SOC_SPEEDO_1_CALIB; - uint32_t FUSE_SOC_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t _0x144; - uint32_t FUSE_FA; - uint32_t FUSE_RESERVED_PRODUCTION; - uint32_t FUSE_HDMI_LANE0_CALIB; - uint32_t FUSE_HDMI_LANE1_CALIB; - uint32_t FUSE_HDMI_LANE2_CALIB; - uint32_t FUSE_HDMI_LANE3_CALIB; - uint32_t FUSE_ENCRYPTION_RATE; - uint32_t FUSE_PUBLIC_KEY[0x8]; - uint32_t FUSE_TSENSOR1_CALIB; - uint32_t FUSE_TSENSOR2_CALIB; - uint32_t _0x18C; - uint32_t FUSE_OPT_CP_REV; - uint32_t FUSE_OPT_PFG; - uint32_t FUSE_TSENSOR0_CALIB; - uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; - uint32_t FUSE_SECURITY_MODE; - uint32_t FUSE_PRIVATE_KEY[0x5]; - uint32_t FUSE_ARM_JTAG_DIS; - uint32_t FUSE_BOOT_DEVICE_INFO; - uint32_t FUSE_RESERVED_SW; - uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM0[0x8]; - uint32_t FUSE_OBS_DIS; - uint32_t _0x1EC; - uint32_t FUSE_USB_CALIB; - uint32_t FUSE_SKU_DIRECT_CONFIG; - uint32_t FUSE_KFUSE_PRIVKEY_CTRL; - uint32_t FUSE_PACKAGE_INFO; - uint32_t FUSE_OPT_VENDOR_CODE; - uint32_t FUSE_OPT_FAB_CODE; - uint32_t FUSE_OPT_LOT_CODE_0; - uint32_t FUSE_OPT_LOT_CODE_1; - uint32_t FUSE_OPT_WAFER_ID; - uint32_t FUSE_OPT_X_COORDINATE; - uint32_t FUSE_OPT_Y_COORDINATE; - uint32_t FUSE_OPT_SEC_DEBUG_EN; - uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t FUSE_SATA_CALIB; /* Erista only. */ - uint32_t FUSE_GPU_IDDQ_CALIB; - uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_CLOCK_BOUNDOUT0; - uint32_t FUSE_CLOCK_BOUNDOUT1; - uint32_t _0x238[0x3]; - uint32_t FUSE_OPT_SAMPLE_TYPE; - uint32_t FUSE_OPT_SUBREVISION; - uint32_t FUSE_OPT_SW_RESERVED_0; - uint32_t FUSE_OPT_SW_RESERVED_1; - uint32_t FUSE_TSENSOR4_CALIB; - uint32_t FUSE_TSENSOR5_CALIB; - uint32_t FUSE_TSENSOR6_CALIB; - uint32_t FUSE_TSENSOR7_CALIB; - uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t FUSE_PKC_DISABLE; /* Erista only. */ - uint32_t _0x26C[0x4]; - uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; - uint32_t FUSE_TSENSOR_COMMON; - uint32_t FUSE_OPT_CP_BIN; - uint32_t FUSE_OPT_GPU_DISABLE; - uint32_t FUSE_OPT_FT_BIN; - uint32_t FUSE_OPT_DONE_MAP; - uint32_t _0x294; - uint32_t FUSE_APB2JTAG_DISABLE; - uint32_t FUSE_ODM_INFO; - uint32_t _0x2A0[0x2]; - uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x2AC[0x5]; - uint32_t FUSE_WOA_SKU_FLAG; - uint32_t FUSE_ECO_RESERVE_1; - uint32_t FUSE_GCPLEX_CONFIG_FUSE; - uint32_t FUSE_PRODUCTION_MONTH; - uint32_t FUSE_RAM_REPAIR_INDICATOR; - uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x2D8; - uint32_t FUSE_VMIN_CALIBRATION; - uint32_t FUSE_AGING_SENSOR_CALIBRATION; - uint32_t FUSE_DEBUG_AUTHENTICATION; - uint32_t FUSE_SECURE_PROVISION_INDEX; - uint32_t FUSE_SECURE_PROVISION_INFO; - uint32_t FUSE_OPT_GPU_DISABLE_CP1; - uint32_t FUSE_SPARE_ENDIS; - uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x2FC[0x2]; - uint32_t FUSE_RESERVED_CALIB0; - uint32_t FUSE_RESERVED_CALIB1; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; - uint32_t FUSE_OPT_CPU_DISABLE; - uint32_t FUSE_OPT_CPU_DISABLE_CP1; - uint32_t FUSE_TSENSOR10_CALIB; - uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */ - uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */ - uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */ - uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */ - uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */ - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; - uint32_t FUSE_OPT_CPU_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_DISABLE_CP2; - uint32_t FUSE_USB_CALIB_EXT; - uint32_t FUSE_RESERVED_FIELD; - uint32_t _0x358[0x9]; - uint32_t FUSE_SPARE_REALIGNMENT_REG; - uint32_t FUSE_SPARE_BIT[0x20]; -} tegra_fuse_chip_erista_t; - -typedef struct { - uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */ - uint32_t FUSE_KEK[0x4]; /* Mariko only. */ - uint32_t FUSE_BEK[0x4]; /* Mariko only. */ - uint32_t _0xF0; /* Mariko only. */ - uint32_t _0xF4; /* Mariko only. */ - uint32_t _0xF8; /* Mariko only. */ - uint32_t _0xFC; /* Mariko only. */ - uint32_t FUSE_PRODUCTION_MODE; - uint32_t FUSE_JTAG_SECUREID_VALID; - uint32_t FUSE_ODM_LOCK; - uint32_t FUSE_OPT_OPENGL_EN; - uint32_t FUSE_SKU_INFO; - uint32_t FUSE_CPU_SPEEDO_0_CALIB; - uint32_t FUSE_CPU_IDDQ_CALIB; - uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */ - uint32_t FUSE_OPT_FT_REV; - uint32_t FUSE_CPU_SPEEDO_1_CALIB; - uint32_t FUSE_CPU_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_SPEEDO_0_CALIB; - uint32_t FUSE_SOC_SPEEDO_1_CALIB; - uint32_t FUSE_SOC_SPEEDO_2_CALIB; - uint32_t FUSE_SOC_IDDQ_CALIB; - uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */ - uint32_t FUSE_FA; - uint32_t FUSE_RESERVED_PRODUCTION; - uint32_t FUSE_HDMI_LANE0_CALIB; - uint32_t FUSE_HDMI_LANE1_CALIB; - uint32_t FUSE_HDMI_LANE2_CALIB; - uint32_t FUSE_HDMI_LANE3_CALIB; - uint32_t FUSE_ENCRYPTION_RATE; - uint32_t FUSE_PUBLIC_KEY[0x8]; - uint32_t FUSE_TSENSOR1_CALIB; - uint32_t FUSE_TSENSOR2_CALIB; - uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */ - uint32_t FUSE_OPT_CP_REV; - uint32_t FUSE_OPT_PFG; - uint32_t FUSE_TSENSOR0_CALIB; - uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE; - uint32_t FUSE_SECURITY_MODE; - uint32_t FUSE_PRIVATE_KEY[0x5]; - uint32_t FUSE_ARM_JTAG_DIS; - uint32_t FUSE_BOOT_DEVICE_INFO; - uint32_t FUSE_RESERVED_SW; - uint32_t FUSE_OPT_VP9_DISABLE; - uint32_t FUSE_RESERVED_ODM0[0x8]; - uint32_t FUSE_OBS_DIS; - uint32_t _0x1EC; /* Mariko only. */ - uint32_t FUSE_USB_CALIB; - uint32_t FUSE_SKU_DIRECT_CONFIG; - uint32_t FUSE_KFUSE_PRIVKEY_CTRL; - uint32_t FUSE_PACKAGE_INFO; - uint32_t FUSE_OPT_VENDOR_CODE; - uint32_t FUSE_OPT_FAB_CODE; - uint32_t FUSE_OPT_LOT_CODE_0; - uint32_t FUSE_OPT_LOT_CODE_1; - uint32_t FUSE_OPT_WAFER_ID; - uint32_t FUSE_OPT_X_COORDINATE; - uint32_t FUSE_OPT_Y_COORDINATE; - uint32_t FUSE_OPT_SEC_DEBUG_EN; - uint32_t FUSE_OPT_OPS_RESERVED; - uint32_t _0x224; /* Mariko only. */ - uint32_t FUSE_GPU_IDDQ_CALIB; - uint32_t FUSE_TSENSOR3_CALIB; - uint32_t FUSE_CLOCK_BOUNDOUT0; - uint32_t FUSE_CLOCK_BOUNDOUT1; - uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */ - uint32_t FUSE_OPT_SAMPLE_TYPE; - uint32_t FUSE_OPT_SUBREVISION; - uint32_t FUSE_OPT_SW_RESERVED_0; - uint32_t FUSE_OPT_SW_RESERVED_1; - uint32_t FUSE_TSENSOR4_CALIB; - uint32_t FUSE_TSENSOR5_CALIB; - uint32_t FUSE_TSENSOR6_CALIB; - uint32_t FUSE_TSENSOR7_CALIB; - uint32_t FUSE_OPT_PRIV_SEC_EN; - uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */ - uint32_t _0x26C; /* Mariko only. */ - uint32_t _0x270; /* Mariko only. */ - uint32_t _0x274; /* Mariko only. */ - uint32_t _0x278; /* Mariko only. */ - uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE; - uint32_t FUSE_TSENSOR_COMMON; - uint32_t FUSE_OPT_CP_BIN; - uint32_t FUSE_OPT_GPU_DISABLE; - uint32_t FUSE_OPT_FT_BIN; - uint32_t FUSE_OPT_DONE_MAP; - uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */ - uint32_t FUSE_APB2JTAG_DISABLE; - uint32_t FUSE_ODM_INFO; - uint32_t _0x2A0[0x2]; - uint32_t FUSE_ARM_CRYPT_DE_FEATURE; - uint32_t _0x2AC; - uint32_t _0x2B0; /* Mariko only. */ - uint32_t _0x2B4; /* Mariko only. */ - uint32_t _0x2B8; /* Mariko only. */ - uint32_t _0x2BC; /* Mariko only. */ - uint32_t FUSE_WOA_SKU_FLAG; - uint32_t FUSE_ECO_RESERVE_1; - uint32_t FUSE_GCPLEX_CONFIG_FUSE; - uint32_t FUSE_PRODUCTION_MONTH; - uint32_t FUSE_RAM_REPAIR_INDICATOR; - uint32_t FUSE_TSENSOR9_CALIB; - uint32_t _0x2D8; - uint32_t FUSE_VMIN_CALIBRATION; - uint32_t FUSE_AGING_SENSOR_CALIBRATION; - uint32_t FUSE_DEBUG_AUTHENTICATION; - uint32_t FUSE_SECURE_PROVISION_INDEX; - uint32_t FUSE_SECURE_PROVISION_INFO; - uint32_t FUSE_OPT_GPU_DISABLE_CP1; - uint32_t FUSE_SPARE_ENDIS; - uint32_t FUSE_ECO_RESERVE_0; - uint32_t _0x2FC[0x2]; - uint32_t FUSE_RESERVED_CALIB0; - uint32_t FUSE_RESERVED_CALIB1; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE; - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1; - uint32_t FUSE_OPT_CPU_DISABLE; - uint32_t FUSE_OPT_CPU_DISABLE_CP1; - uint32_t FUSE_TSENSOR10_CALIB; - uint32_t FUSE_TSENSOR10_CALIB_AUX; - uint32_t _0x324; /* Mariko only. */ - uint32_t _0x328; /* Mariko only. */ - uint32_t _0x32C; /* Mariko only. */ - uint32_t _0x330; /* Mariko only. */ - uint32_t _0x334; /* Mariko only. */ - uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1; - uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2; - uint32_t FUSE_OPT_CPU_DISABLE_CP2; - uint32_t FUSE_OPT_GPU_DISABLE_CP2; - uint32_t FUSE_USB_CALIB_EXT; - uint32_t FUSE_RESERVED_FIELD; - uint32_t _0x358[0x9]; - uint32_t FUSE_SPARE_REALIGNMENT_REG; - uint32_t FUSE_SPARE_BIT[0x1E]; -} tegra_fuse_chip_mariko_t; - -static inline volatile tegra_fuse_t *fuse_get_regs(void) -{ - return (volatile tegra_fuse_t *)FUSE_BASE; -} - -static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void) -{ - return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE; -} - -static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void) -{ - return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE; -} - -static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void) -{ - return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE; -} - -void fuse_init(void); -void fuse_disable_programming(void); -void fuse_disable_private_key(void); -void fuse_enable_power(void); -void fuse_disable_power(void); - -uint32_t fuse_get_sku_info(void); -uint32_t fuse_get_spare_bit(uint32_t index); -uint32_t fuse_get_reserved_odm(uint32_t index); -uint32_t fuse_get_bootrom_patch_version(void); -uint64_t fuse_get_device_id(void); -uint32_t fuse_get_dram_id(void); -uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware); -uint32_t fuse_get_hardware_type(void); -uint32_t fuse_get_retail_type(void); -void fuse_get_hardware_info(void *dst); -bool fuse_is_new_format(void); -uint32_t fuse_get_device_unique_key_generation(void); -uint32_t fuse_get_soc_type(void); -uint32_t fuse_get_regulator(void); - -uint32_t fuse_hw_read(uint32_t addr); -void fuse_hw_write(uint32_t value, uint32_t addr); -void fuse_hw_sense(void); - -#endif diff --git a/sept/sept-secondary/src/gpio.c b/sept/sept-secondary/src/gpio.c deleted file mode 100644 index 76dbb87ce..000000000 --- a/sept/sept-secondary/src/gpio.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -#include "gpio.h" -#include "utils.h" - -/* Set GPIO's value. */ -static void gpio_register_set(uint32_t pin, bool do_set, uint32_t offset) { - volatile tegra_gpio_t *gpio = gpio_get_regs(); - - /* Retrieve the register set that corresponds to the given pin and offset. */ - volatile uint32_t *cluster = (uint32_t *)((uintptr_t)&gpio->bank[(pin >> GPIO_BANK_SHIFT)] + offset); - - /* Figure out the offset into the cluster, and the mask to be used. */ - uint32_t port = ((pin >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK); - uint32_t mask = (1 << (pin & GPIO_PIN_MASK)); - - /* Set or clear the bit, as appropriate. */ - if (do_set) - cluster[port] |= mask; - else - cluster[port] &= ~mask; - - /* Dummy read. */ - cluster[port]; -} - -/* Get GPIO's value. */ -static bool gpio_register_get(uint32_t pin, uint32_t offset) { - volatile tegra_gpio_t *gpio = gpio_get_regs(); - - /* Retrieve the register set that corresponds to the given pin and offset. */ - volatile uint32_t *cluster = (uint32_t *)((uintptr_t)&gpio->bank[(pin >> GPIO_BANK_SHIFT)] + offset); - - /* Figure out the offset into the cluster, and the mask to be used. */ - uint32_t port = ((pin >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK); - uint32_t mask = (1 << (pin & GPIO_PIN_MASK)); - - /* Convert the given value to a boolean. */ - return !!(cluster[port] & mask); -} - -/* Configure GPIO's mode. */ -void gpio_configure_mode(uint32_t pin, uint32_t mode) { - gpio_register_set(pin, mode == GPIO_MODE_GPIO, offsetof(tegra_gpio_bank_t, config)); -} - -/* Configure GPIO's direction. */ -void gpio_configure_direction(uint32_t pin, uint32_t dir) { - gpio_register_set(pin, dir == GPIO_DIRECTION_OUTPUT, offsetof(tegra_gpio_bank_t, direction)); -} - -/* Write to GPIO. */ -void gpio_write(uint32_t pin, uint32_t value) { - gpio_register_set(pin, value == GPIO_LEVEL_HIGH, offsetof(tegra_gpio_bank_t, out)); -} - -/* Read from GPIO. */ -uint32_t gpio_read(uint32_t pin) { - return gpio_register_get(pin, offsetof(tegra_gpio_bank_t, in)); -} diff --git a/sept/sept-secondary/src/gpio.h b/sept/sept-secondary/src/gpio.h deleted file mode 100644 index b187ed618..000000000 --- a/sept/sept-secondary/src/gpio.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_GPIO_H -#define FUSEE_GPIO_H - -#include - -#define GPIO_BASE 0x6000D000 -#define MAKE_GPIO_REG(n) MAKE_REG32(GPIO_BASE + n) - -#define TEGRA_GPIO_PORTS 4 -#define TEGRA_GPIO_BANKS 8 -#define GPIO_BANK_SHIFT 5 -#define GPIO_PORT_SHIFT 3 -#define GPIO_PORT_MASK 0x03 -#define GPIO_PIN_MASK 0x07 - -typedef enum { - TEGRA_GPIO_PORT_A = 0, - TEGRA_GPIO_PORT_B = 1, - TEGRA_GPIO_PORT_C = 2, - TEGRA_GPIO_PORT_D = 3, - TEGRA_GPIO_PORT_E = 4, - TEGRA_GPIO_PORT_F = 5, - TEGRA_GPIO_PORT_G = 6, - TEGRA_GPIO_PORT_H = 7, - TEGRA_GPIO_PORT_I = 8, - TEGRA_GPIO_PORT_J = 9, - TEGRA_GPIO_PORT_K = 10, - TEGRA_GPIO_PORT_L = 11, - TEGRA_GPIO_PORT_M = 12, - TEGRA_GPIO_PORT_N = 13, - TEGRA_GPIO_PORT_O = 14, - TEGRA_GPIO_PORT_P = 15, - TEGRA_GPIO_PORT_Q = 16, - TEGRA_GPIO_PORT_R = 17, - TEGRA_GPIO_PORT_S = 18, - TEGRA_GPIO_PORT_T = 19, - TEGRA_GPIO_PORT_U = 20, - TEGRA_GPIO_PORT_V = 21, - TEGRA_GPIO_PORT_W = 22, - TEGRA_GPIO_PORT_X = 23, - TEGRA_GPIO_PORT_Y = 24, - TEGRA_GPIO_PORT_Z = 25, - TEGRA_GPIO_PORT_AA = 26, - TEGRA_GPIO_PORT_BB = 27, - TEGRA_GPIO_PORT_CC = 28, - TEGRA_GPIO_PORT_DD = 29, - TEGRA_GPIO_PORT_EE = 30, - TEGRA_GPIO_PORT_FF = 31, -} tegra_gpio_port; - -typedef struct { - uint32_t config[TEGRA_GPIO_PORTS]; - uint32_t direction[TEGRA_GPIO_PORTS]; - uint32_t out[TEGRA_GPIO_PORTS]; - uint32_t in[TEGRA_GPIO_PORTS]; - uint32_t int_status[TEGRA_GPIO_PORTS]; - uint32_t int_enable[TEGRA_GPIO_PORTS]; - uint32_t int_level[TEGRA_GPIO_PORTS]; - uint32_t int_clear[TEGRA_GPIO_PORTS]; - uint32_t masked_config[TEGRA_GPIO_PORTS]; - uint32_t masked_dir_out[TEGRA_GPIO_PORTS]; - uint32_t masked_out[TEGRA_GPIO_PORTS]; - uint32_t masked_in[TEGRA_GPIO_PORTS]; - uint32_t masked_int_status[TEGRA_GPIO_PORTS]; - uint32_t masked_int_enable[TEGRA_GPIO_PORTS]; - uint32_t masked_int_level[TEGRA_GPIO_PORTS]; - uint32_t masked_int_clear[TEGRA_GPIO_PORTS]; -} tegra_gpio_bank_t; - -typedef struct { - tegra_gpio_bank_t bank[TEGRA_GPIO_BANKS]; -} tegra_gpio_t; - -static inline volatile tegra_gpio_t *gpio_get_regs(void) -{ - return (volatile tegra_gpio_t *)GPIO_BASE; -} - -#define TEGRA_GPIO(port, offset) \ - ((TEGRA_GPIO_PORT_##port * 8) + offset) - -/* Mode select */ -#define GPIO_MODE_SFIO 0 -#define GPIO_MODE_GPIO 1 - -/* Direction */ -#define GPIO_DIRECTION_INPUT 0 -#define GPIO_DIRECTION_OUTPUT 1 - -/* Level */ -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -/* Named GPIOs */ -#define GPIO_BUTTON_VOL_DOWN TEGRA_GPIO(X, 7) -#define GPIO_BUTTON_VOL_UP TEGRA_GPIO(X, 6) -#define GPIO_MICROSD_CARD_DETECT TEGRA_GPIO(Z, 1) -#define GPIO_MICROSD_WRITE_PROTECT TEGRA_GPIO(Z, 4) -#define GPIO_MICROSD_SUPPLY_ENABLE TEGRA_GPIO(E, 4) -#define GPIO_LCD_BL_P5V TEGRA_GPIO(I, 0) -#define GPIO_LCD_BL_N5V TEGRA_GPIO(I, 1) -#define GPIO_LCD_BL_PWM TEGRA_GPIO(V, 0) -#define GPIO_LCD_BL_EN TEGRA_GPIO(V, 1) -#define GPIO_LCD_BL_RST TEGRA_GPIO(V, 2) - -void gpio_configure_mode(uint32_t pin, uint32_t mode); -void gpio_configure_direction(uint32_t pin, uint32_t dir); -void gpio_write(uint32_t pin, uint32_t value); -uint32_t gpio_read(uint32_t pin); - -#endif diff --git a/sept/sept-secondary/src/hwinit.c b/sept/sept-secondary/src/hwinit.c deleted file mode 100644 index 242a35157..000000000 --- a/sept/sept-secondary/src/hwinit.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "hwinit.h" -#include "apb_misc.h" -#include "car.h" -#include "di.h" -#include "fuse.h" -#include "gpio.h" -#include "i2c.h" -#include "max77620.h" -#include "mc.h" -#include "pinmux.h" -#include "pmc.h" -#include "se.h" -#include "sdram.h" -#include "sysctr0.h" -#include "sysreg.h" -#include "timers.h" -#include "uart.h" - -/* Determine the current SoC for Mariko specific code. */ -static bool is_soc_mariko() { - return (fuse_get_soc_type() == 1); -} - -static void config_oscillators(void) { - volatile tegra_car_t *car = car_get_regs(); - volatile tegra_pmc_t *pmc = pmc_get_regs(); - - car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4); - - SYSCTR0_CNTFID0_0 = 19200000; - TIMERUS_USEC_CFG_0 = 0x45F; - - car->osc_ctrl = 0x50000071; - pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE); - pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFBFFFFF) | 0x400000); - pmc->cntrl2 = ((pmc->cntrl2 & 0xFFFFEFFF) | 0x1000); - pmc->scratch188 = ((pmc->scratch188 & 0xFCFFFFFF) | 0x2000000); - car->clk_sys_rate = 0x10; - car->pllmb_base &= 0xBFFFFFFF; - pmc->tsc_mult = ((pmc->tsc_mult & 0xFFFF0000) | 0x249F); /* 0x249F = 19200000 * (16 / 32.768 kHz) */ - car->sclk_brst_pol = 0x20004444; - car->super_sclk_div = 0x80000000; - car->clk_sys_rate = 2; -} - -static void config_gpios(void) { - volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); - bool is_mariko = is_soc_mariko(); - - if (is_mariko) { - uint32_t hardware_type = fuse_get_hardware_type(); - - /* Only for HardwareType_Iowa and HardwareType_Five. */ - if ((hardware_type == 3) || (hardware_type == 5)) { - pinmux->uart2_tx = 0; - pinmux->uart3_tx = 0; - gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO); - gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO); - gpio_configure_direction(TEGRA_GPIO(G, 0), GPIO_DIRECTION_INPUT); - gpio_configure_direction(TEGRA_GPIO(D, 1), GPIO_DIRECTION_INPUT); - } - } else { - pinmux->uart2_tx = 0; - pinmux->uart3_tx = 0; - } - - pinmux->pe6 = PINMUX_INPUT; - pinmux->ph6 = PINMUX_INPUT; - if (!is_mariko) { - gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO); - gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO); - } - gpio_configure_mode(TEGRA_GPIO(E, 6), GPIO_MODE_GPIO); - gpio_configure_mode(TEGRA_GPIO(H, 6), GPIO_MODE_GPIO); - if (!is_mariko) { - gpio_configure_direction(TEGRA_GPIO(G, 0), GPIO_DIRECTION_INPUT); - gpio_configure_direction(TEGRA_GPIO(D, 1), GPIO_DIRECTION_INPUT); - } - gpio_configure_direction(TEGRA_GPIO(E, 6), GPIO_DIRECTION_INPUT); - gpio_configure_direction(TEGRA_GPIO(H, 6), GPIO_DIRECTION_INPUT); - - i2c_config(I2C_1); - i2c_config(I2C_5); - uart_config(UART_A); - - /* Configure volume up/down buttons as inputs. */ - gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO); - gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO); - gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT); - gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT); - - if (is_mariko) { - /* Configure home button as input. */ - gpio_configure_mode(TEGRA_GPIO(Y, 1), GPIO_MODE_GPIO); - gpio_configure_direction(TEGRA_GPIO(Y, 1), GPIO_DIRECTION_INPUT); - } -} - -static void mbist_workaround(void) { - volatile tegra_car_t *car = car_get_regs(); - - car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF); - car->plld_base |= 0x40800000u; - car->rst_dev_y_clr = 0x40; - car->rst_dev_x_clr = 0x40000; - car->rst_dev_l_clr = 0x18000000; - udelay(2); - - /* Setup I2S. */ - MAKE_I2S_REG(0x0A0) |= 0x400; - MAKE_I2S_REG(0x088) &= 0xFFFFFFFE; - MAKE_I2S_REG(0x1A0) |= 0x400; - MAKE_I2S_REG(0x188) &= 0xFFFFFFFE; - MAKE_I2S_REG(0x2A0) |= 0x400; - MAKE_I2S_REG(0x288) &= 0xFFFFFFFE; - MAKE_I2S_REG(0x3A0) |= 0x400; - MAKE_I2S_REG(0x388) &= 0xFFFFFFFE; - MAKE_I2S_REG(0x4A0) |= 0x400; - MAKE_I2S_REG(0x488) &= 0xFFFFFFFE; - - MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4; - MAKE_VIC_REG(0x8C) = 0xFFFFFFFF; - udelay(2); - - /* Set devices in reset. */ - car->rst_dev_y_set = 0x40; - car->rst_dev_l_set = 0x18000000; - car->rst_dev_x_set = 0x40000; - - /* Clock out enables. */ - car->clk_out_enb_h = 0xC0; - car->clk_out_enb_l = 0x80000130; - car->clk_out_enb_u = 0x1F00200; - car->clk_out_enb_v = 0x80400808; - car->clk_out_enb_w = 0x402000FC; - car->clk_out_enb_x = 0x23000780; - car->clk_out_enb_y = 0x300; - - /* LVL2 clock gate overrides. */ - car->lvl2_clk_gate_ovra = 0; - car->lvl2_clk_gate_ovrb = 0; - car->lvl2_clk_gate_ovrc = 0; - car->lvl2_clk_gate_ovrd = 0; - car->lvl2_clk_gate_ovre = 0; - - /* Configure clock sources. */ - car->plld_base &= 0x1F7FFFFF; - car->clk_source_sor1 &= 0xFFFF3FFF; - car->clk_source_vi = ((car->clk_source_vi & 0x1FFFFFFF) | 0x80000000); - car->clk_source_host1x = ((car->clk_source_host1x & 0x1FFFFFFF) | 0x80000000); - car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000); -} - -static void config_se_brom(void) { - volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs(); - volatile tegra_se_t *se = se_get_regs(); - volatile tegra_pmc_t *pmc = pmc_get_regs(); - - /* Bootrom part we skipped. */ - uint32_t sbk[4] = {fuse_chip->FUSE_PRIVATE_KEY[0], fuse_chip->FUSE_PRIVATE_KEY[1], fuse_chip->FUSE_PRIVATE_KEY[2], fuse_chip->FUSE_PRIVATE_KEY[3]}; - set_aes_keyslot(0xE, sbk, 0x10); - - /* Lock SBK from being read. */ - se->SE_CRYPTO_KEYTABLE_ACCESS[0xE] = 0x7E; - - /* This memset needs to happen here, else TZRAM will behave weirdly later on. */ - memset((void *)0x7C010000, 0, 0x10000); - - pmc->crypto_op = 0; - se->SE_INT_STATUS = 0x1F; - - /* Lock SSK (although it's not set and unused anyways). */ - se->SE_CRYPTO_KEYTABLE_ACCESS[0xF] = 0x7E; - - /* Clear the boot reason to avoid problems later */ - pmc->scratch200 = 0; - pmc->rst_status = 0; -} - -void nx_hwinit(bool enable_log) { - volatile tegra_pmc_t *pmc = pmc_get_regs(); - volatile tegra_car_t *car = car_get_regs(); - bool is_mariko = is_soc_mariko(); - - if (!is_mariko) { - /* Bootrom stuff we skipped by going through RCM. */ - config_se_brom(); - - AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F; - pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD); - - /* Apply the memory built-in self test workaround. */ - mbist_workaround(); - } - - /* Enable SE clock. */ - clkrst_reboot(CARDEVICE_SE); - if (is_mariko) { - /* Lock the SE clock. */ - car->clk_source_se |= 0x100; - } - - /* Initialize the fuse driver. */ - fuse_init(); - - if (!is_mariko) { - /* Initialize the memory controller. */ - mc_enable(); - } - - /* Configure oscillators. */ - config_oscillators(); - - /* Disable pinmux tristate input clamping. */ - APB_MISC_PP_PINMUX_GLOBAL_0 = 0; - - /* Configure GPIOs. */ - config_gpios(); - - /* UART debugging. */ - if (enable_log) { - clkrst_reboot(CARDEVICE_UARTA); - uart_init(UART_A, 115200); - } - - /* Enable CL-DVFS clock. */ - clkrst_reboot(CARDEVICE_CL_DVFS); - - /* Enable I2C1 clock. */ - clkrst_reboot(CARDEVICE_I2C1); - - /* Enable I2C5 clock. */ - clkrst_reboot(CARDEVICE_I2C5); - - /* Enable TZRAM clock. */ - clkrst_reboot(CARDEVICE_TZRAM); - - /* Initialize I2C5. */ - i2c_init(I2C_5); - - /* Configure the PMIC. */ - if (is_mariko) { - uint8_t val = 0x40; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1); - val = 0x78; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1); - } else { - uint8_t val = 0x40; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1); - val = 0x60; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1); - val = 0x38; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG0, &val, 1); - val = 0x3A; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG1, &val, 1); - val = 0x38; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG2, &val, 1); - val = 0xF; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO4, &val, 1); - val = 0xC7; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO8, &val, 1); - val = 0x4F; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD0, &val, 1); - val = 0x29; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD1, &val, 1); - val = 0x1B; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1); - - /* NOTE: [3.0.0+] This was added. */ - val = 0x22; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_GPIO3, &val, 1); - - /* TODO: In 3.x+, if the unit is SDEV, the MBLPD bit is set. */ - /* - i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1); - val |= 0x40; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1); - */ - } - - /* Configure SD0 voltage. */ - uint8_t val = 0x24; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1); - - /* Enable LDO8 in HardwareType_Hoag only. */ - if (is_mariko && (fuse_get_hardware_type() == 2)) { - val = 0xE8; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO8_CFG, &val, 1); - } - - /* Initialize I2C1. */ - i2c_init(I2C_1); - - /* Set super clock burst policy. */ - car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333); - - if (is_mariko) { - /* Mariko only PMC configuration for TZRAM. */ - pmc->tzram_pwr_cntrl &= 0xFFFFFFFE; - pmc->tzram_non_sec_disable = 0x3; - pmc->tzram_sec_disable = 0x3; - } - - /* Save SDRAM parameters to scratch. */ - sdram_save_params(sdram_get_params(fuse_get_dram_id())); - - /* Initialize SDRAM. */ - sdram_init(); -} diff --git a/sept/sept-secondary/src/hwinit.h b/sept/sept-secondary/src/hwinit.h deleted file mode 100644 index b01a34c0b..000000000 --- a/sept/sept-secondary/src/hwinit.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_HWINIT_H_ -#define FUSEE_HWINIT_H_ - -#include - -#define I2S_BASE 0x702D1000 -#define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n) - -void nx_hwinit(bool enable_log); - -#endif diff --git a/sept/sept-secondary/src/i2c.c b/sept/sept-secondary/src/i2c.c deleted file mode 100644 index e8a9d3e1b..000000000 --- a/sept/sept-secondary/src/i2c.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "i2c.h" -#include "utils.h" -#include "timers.h" -#include "pinmux.h" - -/* Prototypes for internal commands. */ -volatile tegra_i2c_t *i2c_get_registers_from_id(I2CDevice id); -void i2c_load_config(volatile tegra_i2c_t *regs); - -bool i2c_query(I2CDevice id, uint8_t device, uint8_t r, void *dst, size_t dst_size); -bool i2c_send(I2CDevice id, uint8_t device, uint8_t r, void *src, size_t src_size); - -bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size); -bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size); - -/* Configure I2C pinmux. */ -void i2c_config(I2CDevice id) { - volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); - - switch (id) { - case I2C_1: - pinmux->gen1_i2c_scl = PINMUX_INPUT; - pinmux->gen1_i2c_sda = PINMUX_INPUT; - break; - case I2C_2: - pinmux->gen2_i2c_scl = PINMUX_INPUT; - pinmux->gen2_i2c_sda = PINMUX_INPUT; - break; - case I2C_3: - pinmux->gen3_i2c_scl = PINMUX_INPUT; - pinmux->gen3_i2c_sda = PINMUX_INPUT; - break; - case I2C_4: - pinmux->cam_i2c_scl = PINMUX_INPUT; - pinmux->cam_i2c_sda = PINMUX_INPUT; - break; - case I2C_5: - pinmux->pwr_i2c_scl = PINMUX_INPUT; - pinmux->pwr_i2c_sda = PINMUX_INPUT; - break; - case I2C_6: - /* Unused. */ - break; - default: break; - } -} - -/* Initialize I2C based on registers. */ -void i2c_init(I2CDevice id) { - volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id); - - /* Setup divisor, and clear the bus. */ - regs->I2C_I2C_CLK_DIVISOR_REGISTER_0 = 0x50001; - regs->I2C_I2C_BUS_CLEAR_CONFIG_0 = 0x90003; - - /* Load hardware configuration. */ - i2c_load_config(regs); - - /* Wait a while until BUS_CLEAR_DONE is set. */ - for (unsigned int i = 0; i < 10; i++) { - udelay(20000); - if (regs->I2C_INTERRUPT_STATUS_REGISTER_0 & 0x800) { - break; - } - } - - /* Read the BUS_CLEAR_STATUS. Result doesn't matter. */ - regs->I2C_I2C_BUS_CLEAR_STATUS_0; - - /* Read and set the Interrupt Status. */ - uint32_t int_status = regs->I2C_INTERRUPT_STATUS_REGISTER_0; - regs->I2C_INTERRUPT_STATUS_REGISTER_0 = int_status; -} - -/* Sets a bit in a PMIC register over I2C during CPU shutdown. */ -void i2c_send_pmic_cpu_shutdown_cmd(void) { - uint32_t val = 0; - /* PMIC == Device 4:3C. */ - i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, 0x41, &val, 1); - val |= 4; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, 0x41, &val, 1); -} - -/* Queries the value of TI charger bit over I2C. */ -bool i2c_query_ti_charger_bit_7(void) { - uint32_t val = 0; - /* TI Charger = Device 0:6B. */ - i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1); - return (val & 0x80) != 0; -} - -/* Clears TI charger bit over I2C. */ -void i2c_clear_ti_charger_bit_7(void) { - uint32_t val = 0; - /* TI Charger = Device 0:6B. */ - i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1); - val &= 0x7F; - i2c_send(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1); -} - -/* Sets TI charger bit over I2C. */ -void i2c_set_ti_charger_bit_7(void) { - uint32_t val = 0; - /* TI Charger = Device 0:6B. */ - i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1); - val |= 0x80; - i2c_send(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1); -} - -/* Get registers pointer based on I2C ID. */ -volatile tegra_i2c_t *i2c_get_registers_from_id(I2CDevice id) { - switch (id) { - case I2C_1: - return I2C1_REGS; - case I2C_2: - return I2C2_REGS; - case I2C_3: - return I2C3_REGS; - case I2C_4: - return I2C4_REGS; - case I2C_5: - return I2C5_REGS; - case I2C_6: - return I2C6_REGS; - default: - generic_panic(); - } - return NULL; -} - -/* Load hardware config for I2C4. */ -void i2c_load_config(volatile tegra_i2c_t *regs) { - /* Set MSTR_CONFIG_LOAD, TIMEOUT_CONFIG_LOAD, undocumented bit. */ - regs->I2C_I2C_CONFIG_LOAD_0 = 0x25; - - /* Wait a bit for master config to be loaded. */ - for (unsigned int i = 0; i < 20; i++) { - udelay(1); - if (!(regs->I2C_I2C_CONFIG_LOAD_0 & 1)) { - break; - } - } -} - -/* Reads a register from a device over I2C, writes result to output. */ -bool i2c_query(I2CDevice id, uint8_t device, uint8_t r, void *dst, size_t dst_size) { - volatile tegra_i2c_t *regs = i2c_get_registers_from_id(id); - uint32_t val = r; - - /* Write single byte register ID to device. */ - if (!i2c_write(regs, device, &val, 1)) { - return false; - } - /* Limit output size to 32-bits. */ - if (dst_size > 4) { - return false; - } - - return i2c_read(regs, device, dst, dst_size); -} - -/* Writes a value to a register over I2C. */ -bool i2c_send(I2CDevice id, uint8_t device, uint8_t r, void *src, size_t src_size) { - uint32_t val = r; - if (src_size == 0) { - return true; - } else if (src_size <= 3) { - memcpy(((uint8_t *)&val) + 1, src, src_size); - return i2c_write(i2c_get_registers_from_id(id), device, &val, src_size + 1); - } else { - return false; - } -} - -/* Writes bytes to device over I2C. */ -bool i2c_write(volatile tegra_i2c_t *regs, uint8_t device, void *src, size_t src_size) { - if (src_size > 4) { - return false; - } else if (src_size == 0) { - return true; - } - - /* Set device for 7-bit write mode. */ - regs->I2C_I2C_CMD_ADDR0_0 = device << 1; - - /* Load in data to write. */ - regs->I2C_I2C_CMD_DATA1_0 = read32le(src, 0); - - /* Set config with LENGTH = src_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */ - regs->I2C_I2C_CNFG_0 = ((src_size << 1) - 2) | 0x2800; - - i2c_load_config(regs); - - /* Config |= SEND; */ - regs->I2C_I2C_CNFG_0 = ((regs->I2C_I2C_CNFG_0 & 0xFFFFFDFF) | 0x200); - - while (regs->I2C_I2C_STATUS_0 & 0x100) { - /* Wait until not busy. */ - } - - /* Return CMD1_STAT == SL1_XFER_SUCCESSFUL. */ - return (regs->I2C_I2C_STATUS_0 & 0xF) == 0; -} - -/* Reads bytes from device over I2C. */ -bool i2c_read(volatile tegra_i2c_t *regs, uint8_t device, void *dst, size_t dst_size) { - if (dst_size > 4) { - return false; - } else if (dst_size == 0) { - return true; - } - - /* Set device for 7-bit read mode. */ - regs->I2C_I2C_CMD_ADDR0_0 = (device << 1) | 1; - - /* Set config with LENGTH = dst_size, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */ - regs->I2C_I2C_CNFG_0 = ((dst_size << 1) - 2) | 0x2840; - - i2c_load_config(regs); - - /* Config |= SEND; */ - regs->I2C_I2C_CNFG_0 = ((regs->I2C_I2C_CNFG_0 & 0xFFFFFDFF) | 0x200); - - while (regs->I2C_I2C_STATUS_0 & 0x100) { - /* Wait until not busy. */ - } - - /* Ensure success. */ - if ((regs->I2C_I2C_STATUS_0 & 0xF) != 0) { - return false; - } - - uint32_t val = regs->I2C_I2C_CMD_DATA1_0; - memcpy(dst, &val, dst_size); - return true; -} diff --git a/sept/sept-secondary/src/i2c.h b/sept/sept-secondary/src/i2c.h deleted file mode 100644 index 4d3254333..000000000 --- a/sept/sept-secondary/src/i2c.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_I2C_H -#define FUSEE_I2C_H - -#include -#include -#include - -#define I2C1234_BASE 0x7000C000 -#define I2C56_BASE 0x7000D000 - -#define MAX77621_CPU_I2C_ADDR 0x1B -#define MAX77621_GPU_I2C_ADDR 0x1C -#define MAX77812_PHASE31_CPU_I2C_ADDR 0x31 -#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 -#define MAX17050_I2C_ADDR 0x36 -#define MAX77620_PWR_I2C_ADDR 0x3C -#define MAX77620_RTC_I2C_ADDR 0x68 -#define BQ24193_I2C_ADDR 0x6B - -typedef enum { - I2C_1 = 0, - I2C_2 = 1, - I2C_3 = 2, - I2C_4 = 3, - I2C_5 = 4, - I2C_6 = 5, -} I2CDevice; - -typedef struct { - uint32_t I2C_I2C_CNFG_0; - uint32_t I2C_I2C_CMD_ADDR0_0; - uint32_t I2C_I2C_CMD_ADDR1_0; - uint32_t I2C_I2C_CMD_DATA1_0; - uint32_t I2C_I2C_CMD_DATA2_0; - uint32_t _0x14; - uint32_t _0x18; - uint32_t I2C_I2C_STATUS_0; - uint32_t I2C_I2C_SL_CNFG_0; - uint32_t I2C_I2C_SL_RCVD_0; - uint32_t I2C_I2C_SL_STATUS_0; - uint32_t I2C_I2C_SL_ADDR1_0; - uint32_t I2C_I2C_SL_ADDR2_0; - uint32_t I2C_I2C_TLOW_SEXT_0; - uint32_t _0x38; - uint32_t I2C_I2C_SL_DELAY_COUNT_0; - uint32_t I2C_I2C_SL_INT_MASK_0; - uint32_t I2C_I2C_SL_INT_SOURCE_0; - uint32_t I2C_I2C_SL_INT_SET_0; - uint32_t _0x4C; - uint32_t I2C_I2C_TX_PACKET_FIFO_0; - uint32_t I2C_I2C_RX_FIFO_0; - uint32_t I2C_PACKET_TRANSFER_STATUS_0; - uint32_t I2C_FIFO_CONTROL_0; - uint32_t I2C_FIFO_STATUS_0; - uint32_t I2C_INTERRUPT_MASK_REGISTER_0; - uint32_t I2C_INTERRUPT_STATUS_REGISTER_0; - uint32_t I2C_I2C_CLK_DIVISOR_REGISTER_0; - uint32_t I2C_I2C_INTERRUPT_SOURCE_REGISTER_0; - uint32_t I2C_I2C_INTERRUPT_SET_REGISTER_0; - uint32_t I2C_I2C_SLV_TX_PACKET_FIFO_0; - uint32_t I2C_I2C_SLV_RX_FIFO_0; - uint32_t I2C_I2C_SLV_PACKET_STATUS_0; - uint32_t I2C_I2C_BUS_CLEAR_CONFIG_0; - uint32_t I2C_I2C_BUS_CLEAR_STATUS_0; - uint32_t I2C_I2C_CONFIG_LOAD_0; - uint32_t _0x90; - uint32_t I2C_I2C_INTERFACE_TIMING_0_0; - uint32_t I2C_I2C_INTERFACE_TIMING_1_0; - uint32_t I2C_I2C_HS_INTERFACE_TIMING_0_0; - uint32_t I2C_I2C_HS_INTERFACE_TIMING_1_0; -} tegra_i2c_t; - -#define I2C1_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x000)) -#define I2C2_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x400)) -#define I2C3_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x500)) -#define I2C4_REGS ((volatile tegra_i2c_t *)(I2C1234_BASE + 0x700)) -#define I2C5_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x000)) -#define I2C6_REGS ((volatile tegra_i2c_t *)(I2C56_BASE + 0x100)) - -void i2c_config(I2CDevice id); - -void i2c_init(I2CDevice id); -bool i2c_query(I2CDevice id, uint8_t device, uint8_t r, void *dst, size_t dst_size); -bool i2c_send(I2CDevice id, uint8_t device, uint8_t r, void *src, size_t src_size); - -void i2c_send_pmic_cpu_shutdown_cmd(void); -bool i2c_query_ti_charger_bit_7(void); -void i2c_clear_ti_charger_bit_7(void); -void i2c_set_ti_charger_bit_7(void); - -#endif diff --git a/sept/sept-secondary/src/init.c b/sept/sept-secondary/src/init.c deleted file mode 100644 index 1f1ed4cdd..000000000 --- a/sept/sept-secondary/src/init.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include "utils.h" - -void __libc_init_array(void); -void __libc_fini_array(void); - -extern uint8_t __bss_start__[], __bss_end__[]; -extern uint8_t __heap_start__[], __heap_end__[]; - -extern char *fake_heap_start; -extern char *fake_heap_end; - -int __program_argc; -void **__program_argv; - -void __attribute__((noreturn)) __program_exit(int rc); -void __attribute__((noreturn)) (*__program_exit_callback)(int rc) = NULL; - -static void __program_parse_argc_argv(int argc, char *argdata); -static void __program_cleanup_argv(void); - -static void __program_init_heap(void) { - fake_heap_start = (char*)__heap_start__; - fake_heap_end = (char*)__heap_end__; -} - -static void __program_init_newlib_hooks(void) { - __syscalls.exit = __program_exit; /* For exit, etc. */ -} - -static void __program_move_additional_sections(void) { -#if defined(SEPT_STAGE1_SRC) || defined(SEPT_STAGE2_SRC) - extern uint8_t __chainloader_lma__[], __chainloader_start__[], __chainloader_bss_start__[], __chainloader_end__[]; - memcpy(__chainloader_start__, __chainloader_lma__, __chainloader_bss_start__ - __chainloader_start__); - memset(__chainloader_bss_start__, 0, __chainloader_end__ - __chainloader_bss_start__); -#endif -} - -void __program_init(int argc, char *argdata) { - /* Zero-fill the .bss section */ - memset(__bss_start__, 0, __bss_end__ - __bss_start__); - - __program_init_heap(); - __program_init_newlib_hooks(); - __program_parse_argc_argv(argc, argdata); - - /* Once argv is parsed, we can discard the low IRAM region */ - __program_move_additional_sections(); - __libc_init_array(); -} - -void __program_exit(int rc) { - __libc_fini_array(); - __program_cleanup_argv(); - if (__program_exit_callback == NULL) { - /* Default callback */ - generic_panic(); - } else { - __program_exit_callback(rc); - } - for (;;); -} - - -static void __program_parse_argc_argv(int argc, char *argdata) { - __program_argc = 0; - __program_argv = NULL; -} -static void __program_cleanup_argv(void) { - /* ... */ -} diff --git a/sept/sept-secondary/src/key_derivation.c b/sept/sept-secondary/src/key_derivation.c deleted file mode 100644 index eef98aa50..000000000 --- a/sept/sept-secondary/src/key_derivation.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include "key_derivation.h" -#include "se.h" -#include "cluster.h" -#include "timers.h" -#include "fuse.h" -#include "uart.h" -#include "utils.h" - -#define u8 uint8_t -#define u32 uint32_t -#include "key_derivation_bin.h" -#undef u8 -#undef u32 - - -void derive_keys(uint32_t version) { - /* Clear mailbox. */ - volatile uint32_t *mailbox = (volatile uint32_t *)0x4003FF00; - while (*mailbox != 0) { - *mailbox = 0; - } - - /* Set derivation id. */ - *((volatile uint32_t *)0x4003E800) = version; - - /* Copy key derivation stub into IRAM high. */ - for (size_t i = 0; i < key_derivation_bin_size; i += sizeof(uint32_t)) { - write32le((void *)0x4003D000, i, read32le(key_derivation_bin, i)); - } - - cluster_boot_cpu0(0x4003D000); - - while (*mailbox != 7) { - /* Wait until keys have been derived. */ - } -} - -void load_keys(const uint8_t *se_state) { - /* Clear keyslots up to 0xA. */ - for (size_t i = 0; i < 0xA; i++) { - clear_aes_keyslot(i); - } - - /* Copy device keygen key out of state keyslot 0xA into keyslot 0xA. */ - set_aes_keyslot(0xA, se_state + 0x30 + (0xA * 0x20), 0x10); - - /* Clear keyslot 0xB. */ - clear_aes_keyslot(0xB); - - /* Copy firmware device key out of state keyslot 0xE into keyslot 0xC. */ - set_aes_keyslot(0xC, se_state + 0x30 + (0xE * 0x20), 0x10); - - /* Copy master key out of state keyslot 0xC into keyslot 0xD. */ - set_aes_keyslot(0xD, se_state + 0x30 + (0xC * 0x20), 0x10); - - /* Clear keyslot 0xE. */ - clear_aes_keyslot(0xE); - - /* Copy device key out of state keyslot 0xF into keyslot 0xF. */ - set_aes_keyslot(0xF, se_state + 0x30 + (0xF * 0x20), 0x10); - - /* Set keyslot flags properly in preparation for secmon. */ - set_aes_keyslot_flags(0xE, 0x15); - set_aes_keyslot_flags(0xC, 0x15); -} diff --git a/sept/sept-secondary/src/key_derivation.h b/sept/sept-secondary/src/key_derivation.h deleted file mode 100644 index 210872a45..000000000 --- a/sept/sept-secondary/src/key_derivation.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef SEPT_KEYDERIVATION_H -#define SEPT_KEYDERIVATION_H - -#include -#include -#include - -void derive_keys(uint32_t version); -void load_keys(const uint8_t *se_state); - -#endif diff --git a/sept/sept-secondary/src/main.c b/sept/sept-secondary/src/main.c deleted file mode 100644 index 79530406c..000000000 --- a/sept/sept-secondary/src/main.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "utils.h" -#include "exception_handlers.h" -#include "panic.h" -#include "hwinit.h" -#include "car.h" -#include "di.h" -#include "se.h" -#include "pmc.h" -#include "emc.h" -#include "sysreg.h" -#include "key_derivation.h" -#include "timers.h" -#include "fs_utils.h" -#include "stage2.h" -#include "splash.h" -#include "chainloader.h" -#include "../../../fusee/common/sdmmc/sdmmc.h" -#include "../../../fusee/common/fatfs/ff.h" -#include "../../../fusee/common/log.h" -#include "../../../fusee/common/vsprintf.h" -#include "../../../fusee/common/ini.h" -#include "../../../fusee/common/display/video_fb.h" - -extern void (*__program_exit_callback)(int rc); - -static void *g_framebuffer; - -static bool has_rebooted(void) { - return MAKE_REG32(0x4003FFFC) == 0xFAFAFAFA; -} - -static void set_has_rebooted(bool rebooted) { - MAKE_REG32(0x4003FFFC) = rebooted ? 0xFAFAFAFA : 0x00000000; -} - -static void exfiltrate_keys_and_reboot_if_needed(uint32_t version) { - volatile tegra_pmc_t *pmc = pmc_get_regs(); - uint8_t *enc_se_state = (uint8_t *)0x4003E000; - uint8_t *dec_se_state = (uint8_t *)0x4003F000; - - if (!has_rebooted()) { - /* Prepare for a reboot before doing anything else. */ - prepare_for_reboot_to_self(); - set_has_rebooted(true); - - /* Derive keys. */ - derive_keys(version); - - reboot_to_self(); - } else { - /* Decrypt the security engine state. */ - uint32_t ALIGN(16) context_key[4]; - context_key[0] = pmc->secure_scratch4; - context_key[1] = pmc->secure_scratch5; - context_key[2] = pmc->secure_scratch6; - context_key[3] = pmc->secure_scratch7; - set_aes_keyslot(0xC, context_key, sizeof(context_key)); - se_aes_128_cbc_decrypt(0xC, dec_se_state, 0x840, enc_se_state, 0x840); - - /* Load keys in from decrypted state. */ - load_keys(dec_se_state); - - /* Clear the security engine state. */ - for (size_t i = 0; i < 0x840; i += 4) { - MAKE_REG32((uintptr_t)(enc_se_state) + i) = 0xCCCCCCCC; - MAKE_REG32((uintptr_t)(dec_se_state) + i) = 0xCCCCCCCC; - } - for (size_t i = 0; i < 4; i++) { - context_key[i] = 0xCCCCCCCC; - } - pmc->secure_scratch4 = 0xCCCCCCCC; - pmc->secure_scratch5 = 0xCCCCCCCC; - pmc->secure_scratch6 = 0xCCCCCCCC; - pmc->secure_scratch7 = 0xCCCCCCCC; - } -} - -static void display_splash_screen(void) { - /* Draw splash. */ - draw_splash((volatile uint32_t *)g_framebuffer); - - /* Turn on the backlight. */ - display_backlight(true); - - /* Ensure the splash screen is displayed for at least one second. */ - mdelay(1000); - - /* Turn off the backlight. */ - display_backlight(false); -} - -static void setup_env(void) { - g_framebuffer = (void *)0xC0000000; - - /* Initialize hardware. */ - nx_hwinit(false); - - /* Zero-fill the framebuffer and register it as printk provider. */ - video_init(g_framebuffer); - - /* Initialize the display. */ - display_init(); - - /* Set the framebuffer. */ - display_init_framebuffer(g_framebuffer); - - /* Set up the exception handlers. */ - setup_exception_handlers(); - - /* Mount the SD card. */ - mount_sd(); -} - -static void cleanup_env(void) { - /* Unmount the SD card. */ - unmount_sd(); - - /* Terminate the display. */ - display_end(); -} - -static void exit_callback(int rc) { - (void)rc; - relocate_and_chainload(); -} - -int sept_main(uint32_t version) { - const char *stage2_path; - stage2_args_t *stage2_args; - uint32_t stage2_version = 0; - ScreenLogLevel log_level = SCREEN_LOG_LEVEL_NONE; - - /* Validate that we can safely boot the CCPLEX. */ - if (SB_CSR_0 & 2) { - generic_panic(); - } - - /* Extract keys from the security engine, which TSEC FW locked down. */ - exfiltrate_keys_and_reboot_if_needed(version); - - /* Override the global logging level. */ - log_set_log_level(log_level); - - /* Initialize the boot environment. */ - setup_env(); - - /* Mark EMC scratch to say that sept has run. */ - MAKE_EMC_REG(EMC_SCRATCH0) |= 0x80000000; - - /* Load the loader payload into DRAM. */ - load_stage2(); - - /* Display the splash screen. */ - display_splash_screen(); - - /* Setup argument data. */ - stage2_path = stage2_get_program_path(); - strcpy(g_chainloader_arg_data, stage2_path); - stage2_args = (stage2_args_t *)(g_chainloader_arg_data + strlen(stage2_path) + 1); /* May be unaligned. */ - memcpy(&stage2_args->version, &stage2_version, 4); - memcpy(&stage2_args->log_level, &log_level, sizeof(log_level)); - strcpy(stage2_args->bct0, ""); - g_chainloader_argc = 2; - - /* Terminate the boot environment. */ - cleanup_env(); - - /* Finally, after the cleanup routines (__libc_fini_array, etc.) are called, jump to Stage2. */ - __program_exit_callback = exit_callback; - return 0; -} diff --git a/sept/sept-secondary/src/max77620.h b/sept/sept-secondary/src/max77620.h deleted file mode 100644 index 7c8e95556..000000000 --- a/sept/sept-secondary/src/max77620.h +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Defining registers address and its bit definitions of MAX77620 and MAX20024 - * - * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - */ - -#ifndef _MFD_MAX77620_H_ -#define _MFD_MAX77620_H_ - -/* RTC Registers */ -#define MAX77620_REG_RTCINT 0x00 -#define MAX77620_REG_RTCINTM 0x01 -#define MAX77620_REG_RTCCNTLM 0x02 -#define MAX77620_REG_RTCCNTL 0x03 -#define MAX77620_REG_RTCUPDATE0 0x04 -#define MAX77620_REG_RTCUPDATE1 0x05 -#define MAX77620_REG_RTCSMPL 0x06 -#define MAX77620_REG_RTCSEC 0x07 -#define MAX77620_REG_RTCMIN 0x08 -#define MAX77620_REG_RTCHOUR 0x09 -#define MAX77620_REG_RTCDOW 0x0A -#define MAX77620_REG_RTCMONTH 0x0B -#define MAX77620_REG_RTCYEAR 0x0C -#define MAX77620_REG_RTCDOM 0x0D -#define MAX77620_REG_RTCSECA1 0x0E -#define MAX77620_REG_RTCMINA1 0x0F -#define MAX77620_REG_RTCHOURA1 0x10 -#define MAX77620_REG_RTCDOWA1 0x11 -#define MAX77620_REG_RTCMONTHA1 0x12 -#define MAX77620_REG_RTCYEARA1 0x13 -#define MAX77620_REG_RTCDOMA1 0x14 -#define MAX77620_REG_RTCSECA2 0x15 -#define MAX77620_REG_RTCMINA2 0x16 -#define MAX77620_REG_RTCHOURA2 0x17 -#define MAX77620_REG_RTCDOWA2 0x18 -#define MAX77620_REG_RTCMONTHA2 0x19 -#define MAX77620_REG_RTCYEARA2 0x1A -#define MAX77620_REG_RTCDOMA2 0x1B - -/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */ -#define MAX77620_REG_CNFGGLBL1 0x00 -#define MAX77620_REG_CNFGGLBL2 0x01 -#define MAX77620_REG_CNFGGLBL3 0x02 -#define MAX77620_REG_CNFG1_32K 0x03 -#define MAX77620_REG_CNFGBBC 0x04 -#define MAX77620_REG_IRQTOP 0x05 -#define MAX77620_REG_INTLBT 0x06 -#define MAX77620_REG_IRQSD 0x07 -#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 -#define MAX77620_REG_IRQ_LVL2_L8 0x09 -#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A -#define MAX77620_REG_ONOFFIRQ 0x0B -#define MAX77620_REG_NVERC 0x0C -#define MAX77620_REG_IRQTOPM 0x0D -#define MAX77620_REG_INTENLBT 0x0E -#define MAX77620_REG_IRQMASKSD 0x0F -#define MAX77620_REG_IRQ_MSK_L0_7 0x10 -#define MAX77620_REG_IRQ_MSK_L8 0x11 -#define MAX77620_REG_ONOFFIRQM 0x12 -#define MAX77620_REG_STATLBT 0x13 -#define MAX77620_REG_STATSD 0x14 -#define MAX77620_REG_ONOFFSTAT 0x15 - -/* SD and LDO Registers */ -#define MAX77620_REG_SD0 0x16 -#define MAX77620_REG_SD1 0x17 -#define MAX77620_REG_SD2 0x18 -#define MAX77620_REG_SD3 0x19 -#define MAX77620_REG_SD4 0x1A -#define MAX77620_REG_DVSSD0 0x1B -#define MAX77620_REG_DVSSD1 0x1C -#define MAX77620_REG_SD0_CFG 0x1D -#define MAX77620_REG_SD1_CFG 0x1E -#define MAX77620_REG_SD2_CFG 0x1F -#define MAX77620_REG_SD3_CFG 0x20 -#define MAX77620_REG_SD4_CFG 0x21 -#define MAX77620_REG_SD_CFG2 0x22 -#define MAX77620_REG_LDO0_CFG 0x23 -#define MAX77620_REG_LDO0_CFG2 0x24 -#define MAX77620_REG_LDO1_CFG 0x25 -#define MAX77620_REG_LDO1_CFG2 0x26 -#define MAX77620_REG_LDO2_CFG 0x27 -#define MAX77620_REG_LDO2_CFG2 0x28 -#define MAX77620_REG_LDO3_CFG 0x29 -#define MAX77620_REG_LDO3_CFG2 0x2A -#define MAX77620_REG_LDO4_CFG 0x2B -#define MAX77620_REG_LDO4_CFG2 0x2C -#define MAX77620_REG_LDO5_CFG 0x2D -#define MAX77620_REG_LDO5_CFG2 0x2E -#define MAX77620_REG_LDO6_CFG 0x2F -#define MAX77620_REG_LDO6_CFG2 0x30 -#define MAX77620_REG_LDO7_CFG 0x31 -#define MAX77620_REG_LDO7_CFG2 0x32 -#define MAX77620_REG_LDO8_CFG 0x33 -#define MAX77620_REG_LDO8_CFG2 0x34 -#define MAX77620_REG_LDO_CFG3 0x35 - -#define MAX77620_LDO_SLEW_RATE_MASK 0x1 - -/* LDO Configuration 3 */ -#define MAX77620_TRACK4_MASK (1 << 5) -#define MAX77620_TRACK4_SHIFT 5 - -/* Voltage */ -#define MAX77620_SDX_VOLT_MASK 0xFF -#define MAX77620_SD0_VOLT_MASK 0x3F -#define MAX77620_SD1_VOLT_MASK 0x7F -#define MAX77620_LDO_VOLT_MASK 0x3F - -#define MAX77620_REG_GPIO0 0x36 -#define MAX77620_REG_GPIO1 0x37 -#define MAX77620_REG_GPIO2 0x38 -#define MAX77620_REG_GPIO3 0x39 -#define MAX77620_REG_GPIO4 0x3A -#define MAX77620_REG_GPIO5 0x3B -#define MAX77620_REG_GPIO6 0x3C -#define MAX77620_REG_GPIO7 0x3D -#define MAX77620_REG_PUE_GPIO 0x3E -#define MAX77620_REG_PDE_GPIO 0x3F -#define MAX77620_REG_AME_GPIO 0x40 -#define MAX77620_REG_ONOFFCNFG1 0x41 -#define MAX77620_REG_ONOFFCNFG2 0x42 - -/* FPS Registers */ -#define MAX77620_REG_FPS_CFG0 0x43 -#define MAX77620_REG_FPS_CFG1 0x44 -#define MAX77620_REG_FPS_CFG2 0x45 -#define MAX77620_REG_FPS_LDO0 0x46 -#define MAX77620_REG_FPS_LDO1 0x47 -#define MAX77620_REG_FPS_LDO2 0x48 -#define MAX77620_REG_FPS_LDO3 0x49 -#define MAX77620_REG_FPS_LDO4 0x4A -#define MAX77620_REG_FPS_LDO5 0x4B -#define MAX77620_REG_FPS_LDO6 0x4C -#define MAX77620_REG_FPS_LDO7 0x4D -#define MAX77620_REG_FPS_LDO8 0x4E -#define MAX77620_REG_FPS_SD0 0x4F -#define MAX77620_REG_FPS_SD1 0x50 -#define MAX77620_REG_FPS_SD2 0x51 -#define MAX77620_REG_FPS_SD3 0x52 -#define MAX77620_REG_FPS_SD4 0x53 -#define MAX77620_REG_FPS_NONE 0 - -#define MAX77620_FPS_SRC_MASK 0xC0 -#define MAX77620_FPS_SRC_SHIFT 6 -#define MAX77620_FPS_PU_PERIOD_MASK 0x38 -#define MAX77620_FPS_PU_PERIOD_SHIFT 3 -#define MAX77620_FPS_PD_PERIOD_MASK 0x07 -#define MAX77620_FPS_PD_PERIOD_SHIFT 0 -#define MAX77620_FPS_TIME_PERIOD_MASK 0x38 -#define MAX77620_FPS_TIME_PERIOD_SHIFT 3 -#define MAX77620_FPS_EN_SRC_MASK 0x06 -#define MAX77620_FPS_EN_SRC_SHIFT 1 -#define MAX77620_FPS_ENFPS_SW_MASK 0x01 -#define MAX77620_FPS_ENFPS_SW 0x01 - -/* Minimum and maximum FPS period time (in microseconds) are - * different for MAX77620 and Max20024. - */ -#define MAX77620_FPS_PERIOD_MIN_US 40 -#define MAX20024_FPS_PERIOD_MIN_US 20 - -#define MAX77620_FPS_PERIOD_MAX_US 2560 -#define MAX20024_FPS_PERIOD_MAX_US 5120 - -#define MAX77620_REG_FPS_GPIO1 0x54 -#define MAX77620_REG_FPS_GPIO2 0x55 -#define MAX77620_REG_FPS_GPIO3 0x56 -#define MAX77620_REG_FPS_RSO 0x57 -#define MAX77620_REG_CID0 0x58 -#define MAX77620_REG_CID1 0x59 -#define MAX77620_REG_CID2 0x5A -#define MAX77620_REG_CID3 0x5B -#define MAX77620_REG_CID4 0x5C -#define MAX77620_REG_CID5 0x5D - -#define MAX77620_REG_DVSSD4 0x5E -#define MAX20024_REG_MAX_ADD 0x70 - -#define MAX77620_CID_DIDM_MASK 0xF0 -#define MAX77620_CID_DIDM_SHIFT 4 - -/* CNCG2SD */ -#define MAX77620_SD_CNF2_ROVS_EN_SD1 (1 << 1) -#define MAX77620_SD_CNF2_ROVS_EN_SD0 (1 << 2) - -/* Device Identification Metal */ -#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF) -/* Device Indentification OTP */ -#define MAX77620_CID5_DIDO(n) ((n) & 0xF) - -/* SD CNFG1 */ -#define MAX77620_SD_SR_MASK 0xC0 -#define MAX77620_SD_SR_SHIFT 6 -#define MAX77620_SD_POWER_MODE_MASK 0x30 -#define MAX77620_SD_POWER_MODE_SHIFT 4 -#define MAX77620_SD_CFG1_ADE_MASK (1 << 3) -#define MAX77620_SD_CFG1_ADE_DISABLE 0 -#define MAX77620_SD_CFG1_ADE_ENABLE (1 << 3) -#define MAX77620_SD_FPWM_MASK 0x04 -#define MAX77620_SD_FPWM_SHIFT 2 -#define MAX77620_SD_FSRADE_MASK 0x01 -#define MAX77620_SD_FSRADE_SHIFT 0 -#define MAX77620_SD_CFG1_FPWM_SD_MASK (1 << 2) -#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0 -#define MAX77620_SD_CFG1_FPWM_SD_FPWM (1 << 2) -#define MAX20024_SD_CFG1_MPOK_MASK (1 << 1) -#define MAX77620_SD_CFG1_FSRADE_SD_MASK (1 << 0) -#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0 -#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0) - -/* LDO_CNFG2 */ -#define MAX77620_LDO_POWER_MODE_MASK 0xC0 -#define MAX77620_LDO_POWER_MODE_SHIFT 6 -#define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2) -#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1) -#define MAX77620_LDO_CFG2_ADE_DISABLE 0 -#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1) -#define MAX77620_LDO_CFG2_SS_MASK (1 << 0) -#define MAX77620_LDO_CFG2_SS_FAST (1 << 0) -#define MAX77620_LDO_CFG2_SS_SLOW 0 - -#define MAX77620_IRQ_TOP_GLBL_MASK (1 << 7) -#define MAX77620_IRQ_TOP_SD_MASK (1 << 6) -#define MAX77620_IRQ_TOP_LDO_MASK (1 << 5) -#define MAX77620_IRQ_TOP_GPIO_MASK (1 << 4) -#define MAX77620_IRQ_TOP_RTC_MASK (1 << 3) -#define MAX77620_IRQ_TOP_32K_MASK (1 << 2) -#define MAX77620_IRQ_TOP_ONOFF_MASK (1 << 1) - -#define MAX77620_IRQ_LBM_MASK (1 << 3) -#define MAX77620_IRQ_TJALRM1_MASK (1 << 2) -#define MAX77620_IRQ_TJALRM2_MASK (1 << 1) - -#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0) -#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0 -#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1) -#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1) -#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0 -#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3) -#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0 -#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4) -#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4) -#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5) -#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6) -#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6) -#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6) -#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6) -#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6) - -#define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0) -#define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1) -#define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2) -#define MAX77620_IRQ_LVL2_GPIO_EDGE3 (1 << 3) -#define MAX77620_IRQ_LVL2_GPIO_EDGE4 (1 << 4) -#define MAX77620_IRQ_LVL2_GPIO_EDGE5 (1 << 5) -#define MAX77620_IRQ_LVL2_GPIO_EDGE6 (1 << 6) -#define MAX77620_IRQ_LVL2_GPIO_EDGE7 (1 << 7) - -#define MAX77620_CNFG1_32K_OUT0_EN (1 << 2) - -#define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7) -#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38 -#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3 -#define MAX77620_ONOFFCNFG1_SLPEN (1 << 2) -#define MAX77620_ONOFFCNFG1_PWR_OFF (1 << 1) -#define MAX20024_ONOFFCNFG1_CLRSE 0x18 - -#define MAX77620_ONOFFCNFG2_SFT_RST_WK (1 << 7) -#define MAX77620_ONOFFCNFG2_WD_RST_WK (1 << 6) -#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK (1 << 5) -#define MAX77620_ONOFFCNFG2_WK_ALARM1 (1 << 2) -#define MAX77620_ONOFFCNFG2_WK_EN0 (1 << 0) - -#define MAX77620_GLBLM_MASK (1 << 0) - -#define MAX77620_WDTC_MASK 0x3 -#define MAX77620_WDTOFFC (1 << 4) -#define MAX77620_WDTSLPC (1 << 3) -#define MAX77620_WDTEN (1 << 2) - -#define MAX77620_TWD_MASK 0x3 -#define MAX77620_TWD_2s 0x0 -#define MAX77620_TWD_16s 0x1 -#define MAX77620_TWD_64s 0x2 -#define MAX77620_TWD_128s 0x3 - -#define MAX77620_CNFGGLBL1_LBDAC_EN (1 << 7) -#define MAX77620_CNFGGLBL1_MPPLD (1 << 6) -#define MAX77620_CNFGGLBL1_LBHYST ((1 << 5) | (1 << 4)) -#define MAX77620_CNFGGLBL1_LBHYST_N (1 << 4) -#define MAX77620_CNFGGLBL1_LBDAC 0x0E -#define MAX77620_CNFGGLBL1_LBDAC_N (1 << 1) -#define MAX77620_CNFGGLBL1_LBRSTEN (1 << 0) - -/* CNFG BBC registers */ -#define MAX77620_CNFGBBC_ENABLE (1 << 0) -#define MAX77620_CNFGBBC_CURRENT_MASK 0x06 -#define MAX77620_CNFGBBC_CURRENT_SHIFT 1 -#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18 -#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3 -#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5) -#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0 -#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6 - -#define MAX77620_FPS_COUNT 3 - -/* Interrupts */ -enum { - MAX77620_IRQ_TOP_GLBL, /* Low-Battery */ - MAX77620_IRQ_TOP_SD, /* SD power fail */ - MAX77620_IRQ_TOP_LDO, /* LDO power fail */ - MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */ - MAX77620_IRQ_TOP_RTC, /* RTC */ - MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */ - MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */ - MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */ - MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */ - MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */ -}; - -/* GPIOs */ -enum { - MAX77620_GPIO0, - MAX77620_GPIO1, - MAX77620_GPIO2, - MAX77620_GPIO3, - MAX77620_GPIO4, - MAX77620_GPIO5, - MAX77620_GPIO6, - MAX77620_GPIO7, - MAX77620_GPIO_NR, -}; - -/* FPS Source */ -enum max77620_fps_src { - MAX77620_FPS_SRC_0, - MAX77620_FPS_SRC_1, - MAX77620_FPS_SRC_2, - MAX77620_FPS_SRC_NONE, - MAX77620_FPS_SRC_DEF, -}; - -enum max77620_chip_id { - MAX77620, - MAX20024, -}; - -#endif /* _MFD_MAX77620_H_ */ diff --git a/sept/sept-secondary/src/max7762x.c b/sept/sept-secondary/src/max7762x.c deleted file mode 100644 index 54530499d..000000000 --- a/sept/sept-secondary/src/max7762x.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "max7762x.h" -#include "max77620.h" -#include "i2c.h" -#include "timers.h" - -#define REGULATOR_SD 0 -#define REGULATOR_LDO 1 - -typedef struct _max77620_regulator_t -{ - uint8_t type; - const char *name; - uint8_t reg_sd; - uint32_t mv_step; - uint32_t mv_min; - uint32_t mv_default; - uint32_t mv_max; - uint8_t volt_addr; - uint8_t cfg_addr; - uint8_t volt_mask; - uint8_t enable_mask; - uint8_t enable_shift; - uint8_t status_mask; - - uint8_t fps_addr; - uint8_t fps_src; - uint8_t pd_period; - uint8_t pu_period; -} max77620_regulator_t; - -static const max77620_regulator_t _pmic_regulators[] = { - { REGULATOR_SD, "sd0", 0x16, 12500, 600000, 625000, 1400000, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, 0x3F, 0x30, 4, 0x80, 0x4F, 1, 7, 1 }, - { REGULATOR_SD, "sd1", 0x17, 12500, 600000, 1125000, 1125000, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, 0x3F, 0x30, 4, 0x40, 0x50, 0, 1, 5 }, - { REGULATOR_SD, "sd2", 0x18, 12500, 600000, 1325000, 1350000, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, 0xFF, 0x30, 4, 0x20, 0x51, 1, 5, 2 }, - { REGULATOR_SD, "sd3", 0x19, 12500, 600000, 1800000, 1800000, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, 0xFF, 0x30, 4, 0x10, 0x52, 0, 3, 3 }, - { REGULATOR_LDO, "ldo0", 0x00, 25000, 800000, 1200000, 1200000, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, 0x3F, 0xC0, 6, 0x00, 0x46, 3, 7, 0 }, - { REGULATOR_LDO, "ldo1", 0x00, 25000, 800000, 1050000, 1050000, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, 0x3F, 0xC0, 6, 0x00, 0x47, 3, 7, 0 }, - { REGULATOR_LDO, "ldo2", 0x00, 50000, 800000, 1800000, 3300000, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, 0x3F, 0xC0, 6, 0x00, 0x48, 3, 7, 0 }, - { REGULATOR_LDO, "ldo3", 0x00, 50000, 800000, 3100000, 3100000, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, 0x3F, 0xC0, 6, 0x00, 0x49, 3, 7, 0 }, - { REGULATOR_LDO, "ldo4", 0x00, 12500, 800000, 850000, 850000, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4A, 0, 7, 1 }, - { REGULATOR_LDO, "ldo5", 0x00, 50000, 800000, 1800000, 1800000, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4B, 3, 7, 0 }, - { REGULATOR_LDO, "ldo6", 0x00, 50000, 800000, 2900000, 2900000, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4C, 3, 7, 0 }, - { REGULATOR_LDO, "ldo7", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4D, 1, 4, 3 }, - { REGULATOR_LDO, "ldo8", 0x00, 50000, 800000, 1050000, 1050000, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, 0x3F, 0xC0, 6, 0x00, 0x4E, 3, 7, 0 } -}; - -int max77620_regulator_get_status(uint32_t id) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - uint8_t val = 0; - - if (reg->type == REGULATOR_SD) { - if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_STATSD, &val, 1)) - return (val & reg->status_mask) ? 0 : 1; - } - - if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->cfg_addr, &val, 1)) - return (val & 8) ? 1 : 0; - - return 0; -} - -int max77620_regulator_config_fps(uint32_t id) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - uint8_t val = ((reg->fps_src << 6) | (reg->pu_period << 3) | (reg->pd_period)); - - if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, reg->fps_addr, &val, 1)) { - return 1; - } - - return 0; -} - -int max77620_regulator_set_voltage(uint32_t id, uint32_t mv) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - - if ((mv < reg->mv_default) || (mv > reg->mv_max)) - return 0; - - uint32_t mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step; - uint8_t val = 0; - - if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->volt_addr, &val, 1)) - { - val = ((val & ~reg->volt_mask) | (mult & reg->volt_mask)); - - if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, reg->volt_addr, &val, 1)) - { - udelay(1000); - return 1; - } - } - - return 0; -} - -int max77620_regulator_enable(uint32_t id, int enable) -{ - if (id > REGULATOR_MAX) - return 0; - - const max77620_regulator_t *reg = &_pmic_regulators[id]; - - uint32_t addr = (reg->type == REGULATOR_SD) ? reg->cfg_addr : reg->volt_addr; - uint8_t val = 0; - - if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, addr, &val, 1)) - { - if (enable) - val = ((val & ~reg->enable_mask) | ((3 << reg->enable_shift) & reg->enable_mask)); - else - val &= ~reg->enable_mask; - - if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, addr, &val, 1)) - { - udelay(1000); - return 1; - } - } - - return 0; -} - -void max77620_config_default() -{ - for (uint32_t i = 1; i <= REGULATOR_MAX; i++) - { - uint8_t val = 0; - if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CID4, &val, 1)) - { - max77620_regulator_config_fps(i); - max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default); - - if (_pmic_regulators[i].fps_src != MAX77620_FPS_SRC_NONE) { - max77620_regulator_enable(i, 1); - } - } - } - - uint8_t val = 4; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1); -} - -void max77620_low_battery_monitor_config() -{ - uint8_t val = (MAX77620_CNFGGLBL1_LBDAC_EN | MAX77620_CNFGGLBL1_LBHYST_N | MAX77620_CNFGGLBL1_LBDAC_N); - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1); -} diff --git a/sept/sept-secondary/src/max7762x.h b/sept/sept-secondary/src/max7762x.h deleted file mode 100644 index 3e6d4a1e3..000000000 --- a/sept/sept-secondary/src/max7762x.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_MAX7762X_H_ -#define FUSEE_MAX7762X_H_ - -/* -* Switch Power domains (max77620): -* Name | Usage | uV step | uV min | uV default | uV max | Init -*-------+---------------+---------+--------+------------+---------+------------------ -* sd0 | core | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1) -* sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1) -* sd2 | ldo{0-1, 7-8} | 12500 | 600000 | 1325000 | 1350000 | 1.325V (pcv) -* sd3 | 1.8V general | 12500 | 600000 | 1800000 | 1800000 | -* ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1) -* ldo1 | XUSB, PCIE | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv) -* ldo2 | SDMMC1 | 50000 | 800000 | 1800000 | 3300000 | -* ldo3 | | 50000 | 800000 | 3100000 | 3100000 | -* ldo4 | RTC | 12500 | 800000 | 850000 | 850000 | -* ldo5 | | 50000 | 800000 | 1800000 | 1800000 | -* ldo6 | | 50000 | 800000 | 2900000 | 2900000 | -* ldo7 | XUSB | 50000 | 800000 | 1050000 | 1050000 | -* ldo8 | XUSB, DC | 50000 | 800000 | 1050000 | 1050000 | -*/ - -/* -* MAX77620_AME_GPIO: control GPIO modes (bits 0 - 7 correspond to GPIO0 - GPIO7); 0 -> GPIO, 1 -> alt-mode -* MAX77620_REG_GPIOx: 0x9 sets output and enable -*/ - -/*! MAX77620 partitions. */ -#define REGULATOR_SD0 0 -#define REGULATOR_SD1 1 -#define REGULATOR_SD2 2 -#define REGULATOR_SD3 3 -#define REGULATOR_LDO0 4 -#define REGULATOR_LDO1 5 -#define REGULATOR_LDO2 6 -#define REGULATOR_LDO3 7 -#define REGULATOR_LDO4 8 -#define REGULATOR_LDO5 9 -#define REGULATOR_LDO6 10 -#define REGULATOR_LDO7 11 -#define REGULATOR_LDO8 12 -#define REGULATOR_MAX 12 - -int max77620_regulator_get_status(uint32_t id); -int max77620_regulator_config_fps(uint32_t id); -int max77620_regulator_set_voltage(uint32_t id, uint32_t mv); -int max77620_regulator_enable(uint32_t id, int enable); -void max77620_config_default(); -void max77620_low_battery_monitor_config(); - -#endif diff --git a/sept/sept-secondary/src/max77812.h b/sept/sept-secondary/src/max77812.h deleted file mode 100644 index bf329ff6b..000000000 --- a/sept/sept-secondary/src/max77812.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_MAX77812_H_ -#define FUSEE_MAX77812_H_ - -#define MAX77812_REG_RESET 0x00 -#define MAX77812_REG_INT_SRC 0x01 -#define MAX77812_REG_INT_SRC_M 0x02 -#define MAX77812_REG_TOPSYS_INT 0x03 -#define MAX77812_REG_TOPSYS_INT_M 0x04 -#define MAX77812_REG_TOPSYS_STAT 0x05 -#define MAX77812_REG_EN_CTRL 0x06 -#define MAX77812_REG_STUP_DLY1 0x07 -#define MAX77812_REG_STUP_DLY2 0x08 -#define MAX77812_REG_STUP_DLY3 0x09 -#define MAX77812_REG_SHDN_DLY1 0x0A -#define MAX77812_REG_SHDN_DLY2 0x0B -#define MAX77812_REG_SHDN_DLY3 0x0C -#define MAX77812_REG_SHDN_DLY4 0x0D -#define MAX77812_REG_WDTRSTB_DEB 0x0E -#define MAX77812_REG_GPI_FUNC 0x0F -#define MAX77812_REG_GPI_DEB1 0x10 -#define MAX77812_REG_GPI_DEB2 0x11 -#define MAX77812_REG_GPI_PD_CTRL 0x12 -#define MAX77812_REG_PROT_CFG 0x13 -#define MAX77812_REG_I2C_CFG 0x15 -#define MAX77812_REG_BUCK_INT 0x20 -#define MAX77812_REG_BUCK_INT_M 0x21 -#define MAX77812_REG_BUCK_STAT 0x22 -#define MAX77812_REG_M1_VOUT 0x23 -#define MAX77812_REG_M2_VOUT 0x24 -#define MAX77812_REG_M3_VOUT 0x25 -#define MAX77812_REG_M4_VOUT 0x26 -#define MAX77812_REG_M1_VOUT_D 0x27 -#define MAX77812_REG_M2_VOUT_D 0x28 -#define MAX77812_REG_M3_VOUT_D 0x29 -#define MAX77812_REG_M4_VOUT_D 0x2A -#define MAX77812_REG_M1_VOUT_S 0x2B -#define MAX77812_REG_M2_VOUT_S 0x2C -#define MAX77812_REG_M3_VOUT_S 0x2D -#define MAX77812_REG_M4_VOUT_S 0x2E -#define MAX77812_REG_M1_CGF 0x2F -#define MAX77812_REG_M2_CGF 0x30 -#define MAX77812_REG_M3_CGF 0x31 -#define MAX77812_REG_M4_CGF 0x32 -#define MAX77812_REG_GLB_CFG1 0x33 -#define MAX77812_REG_GLB_CFG2 0x34 -#define MAX77812_REG_GLB_CFG3 0x35 - -#define MAX77812_REG_EN_CTRL_MASK(n) BIT(n) -#define MAX77812_START_SLEW_RATE_MASK 0x07 -#define MAX77812_SHDN_SLEW_RATE_MASK 0x70 -#define MAX77812_RAMPDOWN_SLEW_RATE_MASK 0x07 -#define MAX77812_RAMPUP_SLEW_RATE_MASK 0x70 - -#define MAX77812_VOUT_MASK 0xFF -#define MAX77812_VOUT_N_VOLTAGE 0xFF -#define MAX77812_VOUT_VMIN 250000 -#define MAX77812_VOUT_VMAX 1525000 -#define MAX77812_VOUT_STEP 5000 - -#define MAX77812_REGULATOR_ID_M1 0 -#define MAX77812_REGULATOR_ID_M2 1 -#define MAX77812_REGULATOR_ID_M3 2 -#define MAX77812_REGULATOR_ID_M4 3 - -#endif diff --git a/sept/sept-secondary/src/mc.c b/sept/sept-secondary/src/mc.c deleted file mode 100644 index 35048d98e..000000000 --- a/sept/sept-secondary/src/mc.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "mc.h" -#include "car.h" -#include "timers.h" - -void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock) -{ - MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = bom; - MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = size1mb; - - if (lock) - MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = 1; -} - -void mc_config_carveout() -{ - *(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC; - - MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1; - MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0; - MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0; - MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0; - MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1; - - mc_config_tsec_carveout(0, 0, true); - - MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0; - MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0; - MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0; - MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1; - - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006; - - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM_HI) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR)); - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2)); - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E; - - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F; - - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F; -} - -void mc_config_carveout_finalize() -{ - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM_HI) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR)); - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2)); - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; - MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E; -} - -void mc_enable_ahb_redirect() -{ - volatile tegra_car_t *car = car_get_regs(); - car->lvl2_clk_gate_ovrd = ((car->lvl2_clk_gate_ovrd & 0xFFF7FFFF) | 0x80000); - - MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000; - MAKE_MC_REG(MC_IRAM_TOM) = 0x4003F000; -} - -void mc_disable_ahb_redirect() -{ - volatile tegra_car_t *car = car_get_regs(); - - MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000; - MAKE_MC_REG(MC_IRAM_TOM) = 0; - - car->lvl2_clk_gate_ovrd &= 0xFFF7FFFF; -} - -void mc_enable() -{ - volatile tegra_car_t *car = car_get_regs(); - - /* Set EMC clock source. */ - car->clk_source_emc = ((car->clk_source_emc & 0x1FFFFFFF) | 0x40000000); - - /* Enable MIPI CAL clock. */ - car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFDFFFFFF) | 0x2000000); - - /* Enable MC clock. */ - car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFFFFFFFE) | 1); - - /* Enable EMC DLL clock. */ - car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000); - - /* Clear EMC and MC reset. */ - /* NOTE: [4.0.0+] This was changed to use the right register. */ - /* car->rst_dev_h_set = 0x2000001; */ - car->rst_dev_h_clr = 0x2000001; - udelay(5); - - mc_disable_ahb_redirect(); -} \ No newline at end of file diff --git a/sept/sept-secondary/src/mc.h b/sept/sept-secondary/src/mc.h deleted file mode 100644 index c414f907a..000000000 --- a/sept/sept-secondary/src/mc.h +++ /dev/null @@ -1,606 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA Corporation. All rights reserved. - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_MC_H_ -#define FUSEE_MC_H_ - -#include -#include - -#define MC_BASE 0x70019000 -#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n) - -#define MC_INTSTATUS 0x0 -#define MC_INTMASK 0x4 -#define MC_ERR_STATUS 0x8 -#define MC_ERR_ADR 0xc -#define MC_SMMU_CONFIG 0x10 -#define MC_SMMU_TLB_CONFIG 0x14 -#define MC_SMMU_PTC_CONFIG 0x18 -#define MC_SMMU_PTB_ASID 0x1c -#define MC_SMMU_PTB_DATA 0x20 -#define MC_SMMU_TLB_FLUSH 0x30 -#define MC_SMMU_PTC_FLUSH 0x34 -#define MC_SMMU_ASID_SECURITY 0x38 -#define MC_SMMU_ASID_SECURITY_1 0x3c -#define MC_SMMU_ASID_SECURITY_2 0x9e0 -#define MC_SMMU_ASID_SECURITY_3 0x9e4 -#define MC_SMMU_ASID_SECURITY_4 0x9e8 -#define MC_SMMU_ASID_SECURITY_5 0x9ec -#define MC_SMMU_ASID_SECURITY_6 0x9f0 -#define MC_SMMU_ASID_SECURITY_7 0x9f4 -#define MC_SMMU_AFI_ASID 0x238 -#define MC_SMMU_AVPC_ASID 0x23c -#define MC_SMMU_TSEC_ASID 0x294 -#define MC_SMMU_PPCS1_ASID 0x298 -#define MC_SMMU_TRANSLATION_ENABLE_0 0x228 -#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c -#define MC_SMMU_TRANSLATION_ENABLE_2 0x230 -#define MC_SMMU_TRANSLATION_ENABLE_3 0x234 -#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98 -#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0 -#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 -#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8 -#define MC_PCFIFO_CLIENT_CONFIG3 0xddc -#define MC_PCFIFO_CLIENT_CONFIG4 0xde0 -#define MC_EMEM_CFG 0x50 -#define MC_EMEM_ADR_CFG 0x54 -#define MC_EMEM_ADR_CFG_DEV0 0x58 -#define MC_EMEM_ADR_CFG_DEV1 0x5c -#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60 -#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64 -#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68 -#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c -#define MC_SECURITY_CFG0 0x70 -#define MC_SECURITY_CFG1 0x74 -#define MC_SECURITY_CFG3 0x9bc -#define MC_SECURITY_RSV 0x7c -#define MC_EMEM_ARB_CFG 0x90 -#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 -#define MC_EMEM_ARB_TIMING_RCD 0x98 -#define MC_EMEM_ARB_TIMING_RP 0x9c -#define MC_EMEM_ARB_TIMING_RC 0xa0 -#define MC_EMEM_ARB_TIMING_RAS 0xa4 -#define MC_EMEM_ARB_TIMING_FAW 0xa8 -#define MC_EMEM_ARB_TIMING_RRD 0xac -#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 -#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 -#define MC_EMEM_ARB_TIMING_R2R 0xb8 -#define MC_EMEM_ARB_TIMING_W2W 0xbc -#define MC_EMEM_ARB_TIMING_R2W 0xc0 -#define MC_EMEM_ARB_TIMING_W2R 0xc4 -#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0 -#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4 -#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0 -#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4 -#define MC_EMEM_ARB_DA_TURNS 0xd0 -#define MC_EMEM_ARB_DA_COVERS 0xd4 -#define MC_EMEM_ARB_MISC0 0xd8 -#define MC_EMEM_ARB_MISC1 0xdc -#define MC_EMEM_ARB_MISC2 0xc8 -#define MC_EMEM_ARB_RING1_THROTTLE 0xe0 -#define MC_EMEM_ARB_RING3_THROTTLE 0xe4 -#define MC_EMEM_ARB_NISO_THROTTLE 0x6b0 -#define MC_EMEM_ARB_OVERRIDE 0xe8 -#define MC_EMEM_ARB_RSV 0xec -#define MC_CLKEN_OVERRIDE 0xf4 -#define MC_TIMING_CONTROL_DBG 0xf8 -#define MC_TIMING_CONTROL 0xfc -#define MC_STAT_CONTROL 0x100 -#define MC_STAT_STATUS 0x104 -#define MC_STAT_EMC_CLOCK_LIMIT 0x108 -#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c -#define MC_STAT_EMC_CLOCKS 0x110 -#define MC_STAT_EMC_CLOCKS_MSBS 0x114 -#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118 -#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158 -#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c -#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c -#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20 -#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24 -#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198 -#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8 -#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c -#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac -#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28 -#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c -#define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0 -#define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0 -#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120 -#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160 -#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128 -#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168 -#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c -#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c -#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130 -#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170 -#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134 -#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88 -#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174 -#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c -#define MC_STAT_EMC_SET0_COUNT 0x138 -#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c -#define MC_STAT_EMC_SET1_COUNT 0x178 -#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c -#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140 -#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144 -#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180 -#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184 -#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148 -#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c -#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188 -#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c -#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150 -#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190 -#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8 -#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc -#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8 -#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc -#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0 -#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0 -#define MC_CLIENT_HOTRESET_CTRL 0x200 -#define MC_CLIENT_HOTRESET_CTRL_1 0x970 -#define MC_CLIENT_HOTRESET_STATUS 0x204 -#define MC_CLIENT_HOTRESET_STATUS_1 0x974 -#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208 -#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c -#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210 -#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214 -#define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94 -#define MC_EMEM_ARB_HYSTERESIS_0 0x218 -#define MC_EMEM_ARB_HYSTERESIS_1 0x21c -#define MC_EMEM_ARB_HYSTERESIS_2 0x220 -#define MC_EMEM_ARB_HYSTERESIS_3 0x224 -#define MC_EMEM_ARB_HYSTERESIS_4 0xb84 -#define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0 -#define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4 -#define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8 -#define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc -#define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0 -#define MC_EMEM_ARB_DHYST_CTRL 0xbcc -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8 -#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec -#define MC_RESERVED_RSV 0x3fc -#define MC_DISB_EXTRA_SNAP_LEVELS 0x408 -#define MC_APB_EXTRA_SNAP_LEVELS 0x2a4 -#define MC_AHB_EXTRA_SNAP_LEVELS 0x2a0 -#define MC_USBD_EXTRA_SNAP_LEVELS 0xa18 -#define MC_ISP_EXTRA_SNAP_LEVELS 0xa08 -#define MC_AUD_EXTRA_SNAP_LEVELS 0xa10 -#define MC_MSE_EXTRA_SNAP_LEVELS 0x40c -#define MC_GK2_EXTRA_SNAP_LEVELS 0xa40 -#define MC_A9AVPPC_EXTRA_SNAP_LEVELS 0x414 -#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc -#define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c -#define MC_HOST_EXTRA_SNAP_LEVELS 0xa14 -#define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0 -#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac -#define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c -#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48 -#define MC_AVP_EXTRA_SNAP_LEVELS 0x2a8 -#define MC_USBX_EXTRA_SNAP_LEVELS 0x404 -#define MC_PCX_EXTRA_SNAP_LEVELS 0x2b8 -#define MC_SD_EXTRA_SNAP_LEVELS 0xa04 -#define MC_DFD_EXTRA_SNAP_LEVELS 0xa4c -#define MC_VE_EXTRA_SNAP_LEVELS 0x2d8 -#define MC_GK_EXTRA_SNAP_LEVELS 0xa00 -#define MC_VE2_EXTRA_SNAP_LEVELS 0x410 -#define MC_SDM_EXTRA_SNAP_LEVELS 0xa44 -#define MC_VIDEO_PROTECT_BOM 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c -#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978 -#define MC_VIDEO_PROTECT_REG_CTRL 0x650 -#define MC_ERR_VPR_STATUS 0x654 -#define MC_ERR_VPR_ADR 0x658 -#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418 -#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590 -#define MC_IRAM_BOM 0x65c -#define MC_IRAM_TOM 0x660 -#define MC_IRAM_ADR_HI 0x980 -#define MC_IRAM_REG_CTRL 0x964 -#define MC_EMEM_CFG_ACCESS_CTRL 0x664 -#define MC_TZ_SECURITY_CTRL 0x668 -#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c -#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4 -#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc -#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8 -#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80 -#define MC_SEC_CARVEOUT_BOM 0x670 -#define MC_SEC_CARVEOUT_SIZE_MB 0x674 -#define MC_SEC_CARVEOUT_ADR_HI 0x9d4 -#define MC_SEC_CARVEOUT_REG_CTRL 0x678 -#define MC_ERR_SEC_STATUS 0x67c -#define MC_ERR_SEC_ADR 0x680 -#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684 -#define MC_STUTTER_CONTROL 0x688 -#define MC_RESERVED_RSV_1 0x958 -#define MC_DVFS_PIPE_SELECT 0x95c -#define MC_AHB_PTSA_MIN 0x4e0 -#define MC_AUD_PTSA_MIN 0x54c -#define MC_MLL_MPCORER_PTSA_RATE 0x44c -#define MC_RING2_PTSA_RATE 0x440 -#define MC_USBD_PTSA_RATE 0x530 -#define MC_USBX_PTSA_MIN 0x528 -#define MC_USBD_PTSA_MIN 0x534 -#define MC_APB_PTSA_MAX 0x4f0 -#define MC_JPG_PTSA_RATE 0x584 -#define MC_DIS_PTSA_MIN 0x420 -#define MC_AVP_PTSA_MAX 0x4fc -#define MC_AVP_PTSA_RATE 0x4f4 -#define MC_RING1_PTSA_MIN 0x480 -#define MC_DIS_PTSA_MAX 0x424 -#define MC_SD_PTSA_MAX 0x4d8 -#define MC_MSE_PTSA_RATE 0x4c4 -#define MC_VICPC_PTSA_MIN 0x558 -#define MC_PCX_PTSA_MAX 0x4b4 -#define MC_ISP_PTSA_RATE 0x4a0 -#define MC_A9AVPPC_PTSA_MIN 0x48c -#define MC_RING2_PTSA_MAX 0x448 -#define MC_AUD_PTSA_RATE 0x548 -#define MC_HOST_PTSA_MIN 0x51c -#define MC_MLL_MPCORER_PTSA_MAX 0x454 -#define MC_SD_PTSA_MIN 0x4d4 -#define MC_RING1_PTSA_RATE 0x47c -#define MC_JPG_PTSA_MIN 0x588 -#define MC_HDAPC_PTSA_MIN 0x62c -#define MC_AVP_PTSA_MIN 0x4f8 -#define MC_JPG_PTSA_MAX 0x58c -#define MC_VE_PTSA_MAX 0x43c -#define MC_DFD_PTSA_MAX 0x63c -#define MC_VICPC_PTSA_RATE 0x554 -#define MC_GK_PTSA_MAX 0x544 -#define MC_VICPC_PTSA_MAX 0x55c -#define MC_SDM_PTSA_MAX 0x624 -#define MC_SAX_PTSA_RATE 0x4b8 -#define MC_PCX_PTSA_MIN 0x4b0 -#define MC_APB_PTSA_MIN 0x4ec -#define MC_GK2_PTSA_MIN 0x614 -#define MC_PCX_PTSA_RATE 0x4ac -#define MC_RING1_PTSA_MAX 0x484 -#define MC_HDAPC_PTSA_RATE 0x628 -#define MC_MLL_MPCORER_PTSA_MIN 0x450 -#define MC_GK2_PTSA_MAX 0x618 -#define MC_AUD_PTSA_MAX 0x550 -#define MC_GK2_PTSA_RATE 0x610 -#define MC_ISP_PTSA_MAX 0x4a8 -#define MC_DISB_PTSA_RATE 0x428 -#define MC_VE2_PTSA_MAX 0x49c -#define MC_DFD_PTSA_MIN 0x638 -#define MC_FTOP_PTSA_RATE 0x50c -#define MC_A9AVPPC_PTSA_RATE 0x488 -#define MC_VE2_PTSA_MIN 0x498 -#define MC_USBX_PTSA_MAX 0x52c -#define MC_DIS_PTSA_RATE 0x41c -#define MC_USBD_PTSA_MAX 0x538 -#define MC_A9AVPPC_PTSA_MAX 0x490 -#define MC_USBX_PTSA_RATE 0x524 -#define MC_FTOP_PTSA_MAX 0x514 -#define MC_HDAPC_PTSA_MAX 0x630 -#define MC_SD_PTSA_RATE 0x4d0 -#define MC_DFD_PTSA_RATE 0x634 -#define MC_FTOP_PTSA_MIN 0x510 -#define MC_SDM_PTSA_RATE 0x61c -#define MC_AHB_PTSA_RATE 0x4dc -#define MC_SMMU_SMMU_PTSA_MAX 0x460 -#define MC_RING2_PTSA_MIN 0x444 -#define MC_SDM_PTSA_MIN 0x620 -#define MC_APB_PTSA_RATE 0x4e8 -#define MC_MSE_PTSA_MIN 0x4c8 -#define MC_HOST_PTSA_RATE 0x518 -#define MC_VE_PTSA_RATE 0x434 -#define MC_AHB_PTSA_MAX 0x4e4 -#define MC_SAX_PTSA_MIN 0x4bc -#define MC_SMMU_SMMU_PTSA_MIN 0x45c -#define MC_ISP_PTSA_MIN 0x4a4 -#define MC_HOST_PTSA_MAX 0x520 -#define MC_SAX_PTSA_MAX 0x4c0 -#define MC_VE_PTSA_MIN 0x438 -#define MC_GK_PTSA_MIN 0x540 -#define MC_MSE_PTSA_MAX 0x4cc -#define MC_DISB_PTSA_MAX 0x430 -#define MC_DISB_PTSA_MIN 0x42c -#define MC_SMMU_SMMU_PTSA_RATE 0x458 -#define MC_VE2_PTSA_RATE 0x494 -#define MC_GK_PTSA_RATE 0x53c -#define MC_PTSA_GRANT_DECREMENT 0x960 -#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4 -#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0 -#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380 -#define MC_LATENCY_ALLOWANCE_ISP2B_0 0x384 -#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc -#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8 -#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370 -#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0 -#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374 -#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8 -#define MC_LATENCY_ALLOWANCE_VIC_0 0x394 -#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8 -#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8 -#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc -#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390 -#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0 -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694 -#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 -#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c -#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 -#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0 -#define MC_LATENCY_ALLOWANCE_AFI_0 0x2e0 -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698 -#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec -#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0 -#define MC_LATENCY_ALLOWANCE_A9AVP_0 0x3a4 -#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e8 -#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4 -#define MC_LATENCY_ALLOWANCE_HC_1 0x314 -#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0 -#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4 -#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c -#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec -#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 -#define MC_LATENCY_ALLOWANCE_VI2_0 0x398 -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4 -#define MC_LATENCY_ALLOWANCE_SATA_0 0x350 -#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690 -#define MC_LATENCY_ALLOWANCE_HC_0 0x310 -#define MC_LATENCY_ALLOWANCE_DC_3 0x3c8 -#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac -#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4 -#define MC_LATENCY_ALLOWANCE_ISP2B_1 0x388 -#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328 -#define MC_LATENCY_ALLOWANCE_HDA_0 0x318 -#define MC_MIN_LENGTH_APE_0 0xb34 -#define MC_MIN_LENGTH_DCB_2 0x8a8 -#define MC_MIN_LENGTH_A9AVP_0 0x950 -#define MC_MIN_LENGTH_TSEC_0 0x93c -#define MC_MIN_LENGTH_DC_1 0x898 -#define MC_MIN_LENGTH_AXIAP_0 0x94c -#define MC_MIN_LENGTH_ISP2B_0 0x930 -#define MC_MIN_LENGTH_VI2_0 0x944 -#define MC_MIN_LENGTH_DCB_0 0x8a0 -#define MC_MIN_LENGTH_DCB_1 0x8a4 -#define MC_MIN_LENGTH_PPCS_1 0x8f4 -#define MC_MIN_LENGTH_NVJPG_0 0xb3c -#define MC_MIN_LENGTH_HDA_0 0x8c4 -#define MC_MIN_LENGTH_NVENC_0 0x8d4 -#define MC_MIN_LENGTH_SDMMC_0 0xb18 -#define MC_MIN_LENGTH_ISP2B_1 0x934 -#define MC_MIN_LENGTH_HC_1 0x8c0 -#define MC_MIN_LENGTH_DC_3 0xb20 -#define MC_MIN_LENGTH_AVPC_0 0x890 -#define MC_MIN_LENGTH_VIC_0 0x940 -#define MC_MIN_LENGTH_ISP2_0 0x91c -#define MC_MIN_LENGTH_HC_0 0x8bc -#define MC_MIN_LENGTH_SE_0 0xb38 -#define MC_MIN_LENGTH_NVDEC_0 0xb30 -#define MC_MIN_LENGTH_SATA_0 0x8fc -#define MC_MIN_LENGTH_DC_0 0x894 -#define MC_MIN_LENGTH_XUSB_1 0x92c -#define MC_MIN_LENGTH_DC_2 0x89c -#define MC_MIN_LENGTH_SDMMCAA_0 0xb14 -#define MC_MIN_LENGTH_GPU_0 0xb04 -#define MC_MIN_LENGTH_ETR_0 0xb44 -#define MC_MIN_LENGTH_AFI_0 0x88c -#define MC_MIN_LENGTH_PPCS_0 0x8f0 -#define MC_MIN_LENGTH_ISP2_1 0x920 -#define MC_MIN_LENGTH_XUSB_0 0x928 -#define MC_MIN_LENGTH_MPCORE_0 0x8cc -#define MC_MIN_LENGTH_TSECB_0 0xb48 -#define MC_MIN_LENGTH_SDMMCA_0 0xb10 -#define MC_MIN_LENGTH_GPU2_0 0xb40 -#define MC_MIN_LENGTH_SDMMCAB_0 0xb1c -#define MC_MIN_LENGTH_PTC_0 0x8f8 -#define MC_EMEM_ARB_OVERRIDE_1 0x968 -#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984 -#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988 -#define MC_EMEM_ARB_STATS_0 0x990 -#define MC_EMEM_ARB_STATS_1 0x994 -#define MC_MTS_CARVEOUT_BOM 0x9a0 -#define MC_MTS_CARVEOUT_SIZE_MB 0x9a4 -#define MC_MTS_CARVEOUT_ADR_HI 0x9a8 -#define MC_MTS_CARVEOUT_REG_CTRL 0x9ac -#define MC_ERR_MTS_STATUS 0x9b0 -#define MC_ERR_MTS_ADR 0x9b4 -#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 -#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 -#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd74 -#define MC_SECURITY_CARVEOUT4_CFG0 0xcf8 -#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10 -#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04 -#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28 -#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc30 -#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc8c -#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd1c -#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd70 -#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc2c -#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd7c -#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4 -#define MC_SECURITY_CARVEOUT2_CFG0 0xc58 -#define MC_SECURITY_CARVEOUT1_CFG0 0xc08 -#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc84 -#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68 -#define MC_SECURITY_CARVEOUT3_BOM 0xcac -#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70 -#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd78 -#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc7c -#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18 -#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc -#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc38 -#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc34 -#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0 -#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60 -#define MC_SECURITY_CARVEOUT3_CFG0 0xca8 -#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8 -#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc88 -#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64 -#define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50 -#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14 -#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14 -#define MC_SECURITY_CARVEOUT1_BOM 0xc0c -#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd2c -#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68 -#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8 -#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58 -#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd24 -#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4 -#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78 -#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c -#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18 -#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd28 -#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c -#define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0 -#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcd8 -#define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60 -#define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00 -#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64 -#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xcdc -#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc80 -#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54 -#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd20 -#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd4 -#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c -#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74 -#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xccc -#define MC_SECURITY_CARVEOUT4_BOM 0xcfc -#define MC_SECURITY_CARVEOUT5_CFG0 0xd48 -#define MC_SECURITY_CARVEOUT2_BOM 0xc5c -#define MC_SECURITY_CARVEOUT5_BOM 0xd4c -#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24 -#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd6c -#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd0 -#define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10 -#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20 -#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc3c -#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c -#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 -#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 -#define MC_DA_CONFIG0 0x9dc -#define MC_UNTRANSLATED_REGION_CHECK 0x948 - -/* Memory Controller clients */ -#define CLIENT_ACCESS_NUM_CLIENTS 32 -typedef enum { - /* _ACCESS0 */ - CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)), - - /* _ACCESS1 */ - CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)), - - /* _ACCESS2 */ - CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)), - - /* _ACCESS3 */ - CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)), - - /* _ACCESS4 */ - CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)), - CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4)) -} McClient; - -void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock); -void mc_config_carveout(); -void mc_config_carveout_finalize(); -void mc_enable_ahb_redirect(); -void mc_disable_ahb_redirect(); -void mc_enable(); - -#endif \ No newline at end of file diff --git a/sept/sept-secondary/src/panic.c b/sept/sept-secondary/src/panic.c deleted file mode 100644 index 52bc52e6a..000000000 --- a/sept/sept-secondary/src/panic.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include -#include -#include "panic.h" -#include "di.h" -#include "pmc.h" -#include "se.h" -#include "fuse.h" -#include "utils.h" -#include "uart.h" - -static uint32_t g_panic_code = 0; - -__attribute__ ((noreturn)) void panic(uint32_t code) { - /* Set panic code. */ - if (g_panic_code == 0) { - g_panic_code = code; - APBDEV_PMC_SCRATCH200_0 = code; - } - - /* Clear all keyslots. */ - for (size_t i = 0; i < 0x10; i++) { - clear_aes_keyslot(i); - } - - fuse_disable_programming(); - APBDEV_PMC_CRYPTO_OP_0 = 1; /* Disable all SE operations. */ - - while(true); -} diff --git a/sept/sept-secondary/src/panic.h b/sept/sept-secondary/src/panic.h deleted file mode 100644 index 50ec7a1bd..000000000 --- a/sept/sept-secondary/src/panic.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_PANIC_H -#define FUSEE_PANIC_H - -#include - -#define PANIC_COLOR_KERNEL 0x0000FF -#define PANIC_COLOR_SECMON_EXCEPTION 0xFF7700 -#define PANIC_COLOR_SECMON_GENERIC 0x00FFFF -#define PANIC_COLOR_SECMON_DEEPSLEEP 0xFF77FF /* 4.0+ color */ -#define PANIC_COLOR_BOOTLOADER_GENERIC 0xAA00FF -#define PANIC_COLOR_BOOTLOADER_SAFEMODE 0xFFFFAA /* Removed */ - -#define PANIC_CODE_SAFEMODE 0x00000020 - -__attribute__ ((noreturn)) void panic(uint32_t code); - -#endif diff --git a/sept/sept-secondary/src/panic_color.h b/sept/sept-secondary/src/panic_color.h deleted file mode 100644 index 8d90c7ffa..000000000 --- a/sept/sept-secondary/src/panic_color.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_PANIC_COLOR_H -#define FUSEE_PANIC_COLOR_H - -#define COLOR_0 0x00F00003 -#define COLOR_1 0x0F000003 -#define COLOR_2 0xF0000003 -#define COLOR_3 0x0FF00003 -#define COLOR_4 0xF0F00003 -#define COLOR_5 0xFF000003 -#define COLOR_6 0xFFF00003 -#define COLOR_7 0xAAF00003 -#define COLOR_8 0xAFA00003 -#define COLOR_9 0xFAA00003 -#define COLOR_A 0x33300003 -#define COLOR_B 0x06F00003 -#define COLOR_C 0x14800003 -#define COLOR_D 0x00300003 -#define COLOR_E 0x03000003 -#define COLOR_F 0xB6000003 - -#define PANIC_REBOOT 0x20 - -#endif \ No newline at end of file diff --git a/sept/sept-secondary/src/pinmux.h b/sept/sept-secondary/src/pinmux.h deleted file mode 100644 index 616e90262..000000000 --- a/sept/sept-secondary/src/pinmux.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_PINMUX_H -#define FUSEE_PINMUX_H - -#define PINMUX_BASE 0x70003000 -#define MAKE_PINMUX_REG(n) MAKE_REG32(PINMUX_BASE + n) - -#define PINMUX_TRISTATE (1 << 4) -#define PINMUX_PARKED (1 << 5) -#define PINMUX_INPUT (1 << 6) -#define PINMUX_PULL_NONE (0 << 2) -#define PINMUX_PULL_DOWN (1 << 2) -#define PINMUX_PULL_UP (2 << 2) -#define PINMUX_SELECT_FUNCTION0 0 -#define PINMUX_SELECT_FUNCTION1 1 -#define PINMUX_SELECT_FUNCTION2 2 -#define PINMUX_SELECT_FUNCTION3 3 -#define PINMUX_DRIVE_1X (0 << 13) -#define PINMUX_DRIVE_2X (1 << 13) -#define PINMUX_DRIVE_3X (2 << 13) -#define PINMUX_DRIVE_4X (3 << 13) - -typedef struct { - uint32_t sdmmc1_clk; - uint32_t sdmmc1_cmd; - uint32_t sdmmc1_dat3; - uint32_t sdmmc1_dat2; - uint32_t sdmmc1_dat1; - uint32_t sdmmc1_dat0; - uint32_t _r18; - uint32_t sdmmc3_clk; - uint32_t sdmmc3_cmd; - uint32_t sdmmc3_dat0; - uint32_t sdmmc3_dat1; - uint32_t sdmmc3_dat2; - uint32_t sdmmc3_dat3; - uint32_t _r34; - uint32_t pex_l0_rst_n; - uint32_t pex_l0_clkreq_n; - uint32_t pex_wake_n; - uint32_t pex_l1_rst_n; - uint32_t pex_l1_clkreq_n; - uint32_t sata_led_active; - uint32_t spi1_mosi; - uint32_t spi1_miso; - uint32_t spi1_sck; - uint32_t spi1_cs0; - uint32_t spi1_cs1; - uint32_t spi2_mosi; - uint32_t spi2_miso; - uint32_t spi2_sck; - uint32_t spi2_cs0; - uint32_t spi2_cs1; - uint32_t spi4_mosi; - uint32_t spi4_miso; - uint32_t spi4_sck; - uint32_t spi4_cs0; - uint32_t qspi_sck; - uint32_t qspi_cs_n; - uint32_t qspi_io0; - uint32_t qspi_io1; - uint32_t qspi_io2; - uint32_t qspi_io3; - uint32_t _ra0; - uint32_t dmic1_clk; - uint32_t dmic1_dat; - uint32_t dmic2_clk; - uint32_t dmic2_dat; - uint32_t dmic3_clk; - uint32_t dmic3_dat; - uint32_t gen1_i2c_scl; - uint32_t gen1_i2c_sda; - uint32_t gen2_i2c_scl; - uint32_t gen2_i2c_sda; - uint32_t gen3_i2c_scl; - uint32_t gen3_i2c_sda; - uint32_t cam_i2c_scl; - uint32_t cam_i2c_sda; - uint32_t pwr_i2c_scl; - uint32_t pwr_i2c_sda; - uint32_t uart1_tx; - uint32_t uart1_rx; - uint32_t uart1_rts; - uint32_t uart1_cts; - uint32_t uart2_tx; - uint32_t uart2_rx; - uint32_t uart2_rts; - uint32_t uart2_cts; - uint32_t uart3_tx; - uint32_t uart3_rx; - uint32_t uart3_rts; - uint32_t uart3_cts; - uint32_t uart4_tx; - uint32_t uart4_rx; - uint32_t uart4_rts; - uint32_t uart4_cts; - uint32_t dap1_fs; - uint32_t dap1_din; - uint32_t dap1_dout; - uint32_t dap1_sclk; - uint32_t dap2_fs; - uint32_t dap2_din; - uint32_t dap2_dout; - uint32_t dap2_sclk; - uint32_t dap4_fs; - uint32_t dap4_din; - uint32_t dap4_dout; - uint32_t dap4_sclk; - uint32_t cam1_mclk; - uint32_t cam2_mclk; - uint32_t jtag_rtck; - uint32_t clk_32k_in; - uint32_t clk_32k_out; - uint32_t batt_bcl; - uint32_t clk_req; - uint32_t cpu_pwr_req; - uint32_t pwr_int_n; - uint32_t shutdown; - uint32_t core_pwr_req; - uint32_t aud_mclk; - uint32_t dvfs_pwm; - uint32_t dvfs_clk; - uint32_t gpio_x1_aud; - uint32_t gpio_x3_aud; - uint32_t pcc7; - uint32_t hdmi_cec; - uint32_t hdmi_int_dp_hpd; - uint32_t spdif_out; - uint32_t spdif_in; - uint32_t usb_vbus_en0; - uint32_t usb_vbus_en1; - uint32_t dp_hpd0; - uint32_t wifi_en; - uint32_t wifi_rst; - uint32_t wifi_wake_ap; - uint32_t ap_wake_bt; - uint32_t bt_rst; - uint32_t bt_wake_ap; - uint32_t ap_wake_nfc; - uint32_t nfc_en; - uint32_t nfc_int; - uint32_t gps_en; - uint32_t gps_rst; - uint32_t cam_rst; - uint32_t cam_af_en; - uint32_t cam_flash_en; - uint32_t cam1_pwdn; - uint32_t cam2_pwdn; - uint32_t cam1_strobe; - uint32_t lcd_te; - uint32_t lcd_bl_pwm; - uint32_t lcd_bl_en; - uint32_t lcd_rst; - uint32_t lcd_gpio1; - uint32_t lcd_gpio2; - uint32_t ap_ready; - uint32_t touch_rst; - uint32_t touch_clk; - uint32_t modem_wake_ap; - uint32_t touch_int; - uint32_t motion_int; - uint32_t als_prox_int; - uint32_t temp_alert; - uint32_t button_power_on; - uint32_t button_vol_up; - uint32_t button_vol_down; - uint32_t button_slide_sw; - uint32_t button_home; - uint32_t pa6; - uint32_t pe6; - uint32_t pe7; - uint32_t ph6; - uint32_t pk0; - uint32_t pk1; - uint32_t pk2; - uint32_t pk3; - uint32_t pk4; - uint32_t pk5; - uint32_t pk6; - uint32_t pk7; - uint32_t pl0; - uint32_t pl1; - uint32_t pz0; - uint32_t pz1; - uint32_t pz2; - uint32_t pz3; - uint32_t pz4; - uint32_t pz5; -} tegra_pinmux_t; - -static inline volatile tegra_pinmux_t *pinmux_get_regs(void) -{ - return (volatile tegra_pinmux_t *)PINMUX_BASE; -} - -#endif diff --git a/sept/sept-secondary/src/pmc.h b/sept/sept-secondary/src/pmc.h deleted file mode 100644 index a287d85e7..000000000 --- a/sept/sept-secondary/src/pmc.h +++ /dev/null @@ -1,713 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_PMC_H -#define FUSEE_PMC_H - -#include - -#define PMC_BASE 0x7000E400 -#define MAKE_PMC_REG(n) MAKE_REG32(PMC_BASE + n) - -#define PMC_CONTROL_SDMMC1 (1 << 12) -#define PMC_CONTROL_SDMMC3 (1 << 13) -#define PMC_CONTROL_SDMMC4 (1 << 14) - -#define APBDEV_PMC_CONTROL MAKE_PMC_REG(0x00) -#define APBDEV_PM_0 MAKE_PMC_REG(0x14) -#define APBDEV_PMC_DPD_ENABLE_0 MAKE_PMC_REG(0x24) -#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x30) -#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x38) -#define APBDEV_PMC_NO_IOPOWER_0 MAKE_PMC_REG(0x44) -#define APBDEV_PMC_SCRATCH0_0 MAKE_PMC_REG(0x50) -#define APBDEV_PMC_SCRATCH1_0 MAKE_PMC_REG(0x54) -#define APBDEV_PMC_SCRATCH20_0 MAKE_PMC_REG(0xA0) -#define APBDEV_PMC_PWR_DET_VAL_0 MAKE_PMC_REG(0xE4) -#define APBDEV_PMC_DDR_PWR_0 MAKE_PMC_REG(0xE8) -#define APBDEV_PMC_CRYPTO_OP_0 MAKE_PMC_REG(0xF4) -#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_PMC_REG(0x168) -#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4) -#define APBDEV_PMC_RST_STATUS_0 MAKE_PMC_REG(0x1B4) -#define APBDEV_PMC_IO_DPD_REQ_0 MAKE_PMC_REG(0x1B8) -#define APBDEV_PMC_IO_DPD2_REQ_0 MAKE_PMC_REG(0x1C0) -#define APBDEV_PMC_VDDP_SEL_0 MAKE_PMC_REG(0x1CC) -#define APBDEV_PMC_SCRATCH49_0 MAKE_PMC_REG(0x244) -#define APBDEV_PMC_TSC_MULT_0 MAKE_PMC_REG(0x2B4) -#define APBDEV_PMC_REG_SHORT_0 MAKE_PMC_REG(0x2CC) -#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8) -#define APBDEV_PMC_SECURE_SCRATCH21_0 MAKE_PMC_REG(0x334) -#define APBDEV_PMC_SECURE_SCRATCH32_0 MAKE_PMC_REG(0x360) -#define APBDEV_PMC_SECURE_SCRATCH49_0 MAKE_PMC_REG(0x3A4) -#define APBDEV_PMC_CNTRL2_0 MAKE_PMC_REG(0x440) -#define APBDEV_PMC_IO_DPD4_REQ_0 MAKE_PMC_REG(0x464) -#define APBDEV_PMC_UTMIP_PAD_CFG1_0 MAKE_PMC_REG(0x4C4) -#define APBDEV_PMC_UTMIP_PAD_CFG3_0 MAKE_PMC_REG(0x4CC) -#define APBDEV_PMC_DDR_CNTRL_0 MAKE_PMC_REG(0x4E4) -#define APBDEV_PMC_SCRATCH43_0 MAKE_PMC_REG(0x22C) -#define APBDEV_PMC_SCRATCH188_0 MAKE_PMC_REG(0x810) -#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818) -#define APBDEV_PMC_SCRATCH200_0 MAKE_PMC_REG(0x840) - -#define APBDEV_PMC_SCRATCH45_0 MAKE_PMC_REG(0x234) -#define APBDEV_PMC_SCRATCH46_0 MAKE_PMC_REG(0x238) -#define APBDEV_PMC_SCRATCH33_0 MAKE_PMC_REG(0x120) -#define APBDEV_PMC_SCRATCH40_0 MAKE_PMC_REG(0x13C) - -/* Power Management Controller (APBDEV_PMC_) regs */ -typedef struct { - uint32_t cntrl; /* _CNTRL_0, 0x00 */ - uint32_t sec_disable; /* _SEC_DISABLE_0, 0x04 */ - uint32_t pmc_swrst; /* _PMC_SWRST_0, 0x08 */ - uint32_t wake_mask; /* _WAKE_MASK_0, 0x0c */ - uint32_t wake_lvl; /* _WAKE_LVL_0, 0x10 */ - uint32_t wake_status; /* _WAKE_STATUS_0, 0x14 */ - uint32_t sw_wake_status; /* _SW_WAKE_STATUS_0, 0x18 */ - uint32_t dpd_pads_oride; /* _DPD_PADS_ORIDE_0, 0x1c */ - uint32_t dpd_sample; /* _DPD_SAMPLE_0, 0x20 */ - uint32_t dpd_enable; /* _DPD_ENABLE_0, 0x24 */ - uint32_t pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, 0x28 */ - uint32_t clamp_status; /* _CLAMP_STATUS_0, 0x2c */ - uint32_t pwrgate_toggle; /* _PWRGATE_TOGGLE_0, 0x30 */ - uint32_t remove_clamping; /* _REMOVE_CLAMPING_0, 0x34 */ - uint32_t pwrgate_status; /* _PWRGATE_STATUS_0, 0x38 */ - uint32_t pwrgood_timer; /* _PWRGOOD_TIMER_0, 0x3c */ - uint32_t blink_timer; /* _BLINK_TIMER_0, 0x40 */ - uint32_t no_iopower; /* _NO_IOPOWER_0, 0x44 */ - uint32_t pwr_det; /* _PWR_DET_0, 0x48 */ - uint32_t pwr_det_latch; /* _PWR_DET_LATCH_0, 0x4c */ - uint32_t scratch0; /* _SCRATCH0_0, 0x50 */ - uint32_t scratch1; /* _SCRATCH1_0, 0x54 */ - uint32_t scratch2; /* _SCRATCH2_0, 0x58 */ - uint32_t scratch3; /* _SCRATCH3_0, 0x5c */ - uint32_t scratch4; /* _SCRATCH4_0, 0x60 */ - uint32_t scratch5; /* _SCRATCH5_0, 0x64 */ - uint32_t scratch6; /* _SCRATCH6_0, 0x68 */ - uint32_t scratch7; /* _SCRATCH7_0, 0x6c */ - uint32_t scratch8; /* _SCRATCH8_0, 0x70 */ - uint32_t scratch9; /* _SCRATCH9_0, 0x74 */ - uint32_t scratch10; /* _SCRATCH10_0, 0x78 */ - uint32_t scratch11; /* _SCRATCH11_0, 0x7c */ - uint32_t scratch12; /* _SCRATCH12_0, 0x80 */ - uint32_t scratch13; /* _SCRATCH13_0, 0x84 */ - uint32_t scratch14; /* _SCRATCH14_0, 0x88 */ - uint32_t scratch15; /* _SCRATCH15_0, 0x8c */ - uint32_t scratch16; /* _SCRATCH16_0, 0x90 */ - uint32_t scratch17; /* _SCRATCH17_0, 0x94 */ - uint32_t scratch18; /* _SCRATCH18_0, 0x98 */ - uint32_t scratch19; /* _SCRATCH19_0, 0x9c */ - uint32_t scratch20; /* _SCRATCH20_0, 0xa0 */ - uint32_t scratch21; /* _SCRATCH21_0, 0xa4 */ - uint32_t scratch22; /* _SCRATCH22_0, 0xa8 */ - uint32_t scratch23; /* _SCRATCH23_0, 0xac */ - uint32_t secure_scratch0; /* _SECURE_SCRATCH0_0, 0xb0 */ - uint32_t secure_scratch1; /* _SECURE_SCRATCH1_0, 0xb4 */ - uint32_t secure_scratch2; /* _SECURE_SCRATCH2_0, 0xb8 */ - uint32_t secure_scratch3; /* _SECURE_SCRATCH3_0, 0xbc */ - uint32_t secure_scratch4; /* _SECURE_SCRATCH4_0, 0xc0 */ - uint32_t secure_scratch5; /* _SECURE_SCRATCH5_0, 0xc4 */ - uint32_t cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, 0xc8 */ - uint32_t cpupwroff_timer; /* _CPUPWROFF_TIMER_0, 0xcc */ - uint32_t pg_mask; /* _PG_MASK_0, 0xd0 */ - uint32_t pg_mask_1; /* _PG_MASK_1_0, 0xd4 */ - uint32_t auto_wake_lvl; /* _AUTO_WAKE_LVL_0, 0xd8 */ - uint32_t auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, 0xdc */ - uint32_t wake_delay; /* _WAKE_DELAY_0, 0xe0 */ - uint32_t pwr_det_val; /* _PWR_DET_VAL_0, 0xe4 */ - uint32_t ddr_pwr; /* _DDR_PWR_0, 0xe8 */ - uint32_t usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, 0xec */ - uint32_t usb_ao; /* _USB_AO_0, 0xf0 */ - uint32_t crypto_op; /* _CRYPTO_OP_0, 0xf4 */ - uint32_t pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, 0xf8 */ - uint32_t scratch24; /* _SCRATCH24_0, 0xfc */ - uint32_t scratch25; /* _SCRATCH25_0, 0x100 */ - uint32_t scratch26; /* _SCRATCH26_0, 0x104 */ - uint32_t scratch27; /* _SCRATCH27_0, 0x108 */ - uint32_t scratch28; /* _SCRATCH28_0, 0x10c */ - uint32_t scratch29; /* _SCRATCH29_0, 0x110 */ - uint32_t scratch30; /* _SCRATCH30_0, 0x114 */ - uint32_t scratch31; /* _SCRATCH31_0, 0x118 */ - uint32_t scratch32; /* _SCRATCH32_0, 0x11c */ - uint32_t scratch33; /* _SCRATCH33_0, 0x120 */ - uint32_t scratch34; /* _SCRATCH34_0, 0x124 */ - uint32_t scratch35; /* _SCRATCH35_0, 0x128 */ - uint32_t scratch36; /* _SCRATCH36_0, 0x12c */ - uint32_t scratch37; /* _SCRATCH37_0, 0x130 */ - uint32_t scratch38; /* _SCRATCH38_0, 0x134 */ - uint32_t scratch39; /* _SCRATCH39_0, 0x138 */ - uint32_t scratch40; /* _SCRATCH40_0, 0x13c */ - uint32_t scratch41; /* _SCRATCH41_0, 0x140 */ - uint32_t scratch42; /* _SCRATCH42_0, 0x144 */ - uint32_t bondout_mirror0; /* _BONDOUT_MIRROR0_0, 0x148 */ - uint32_t bondout_mirror1; /* _BONDOUT_MIRROR1_0, 0x14c */ - uint32_t bondout_mirror2; /* _BONDOUT_MIRROR2_0, 0x150 */ - uint32_t sys_33v_en; /* _SYS_33V_EN_0, 0x154 */ - uint32_t bondout_mirror_access; /* _BONDOUT_MIRROR_ACCESS_0, 0x158 */ - uint32_t gate; /* _GATE_0, 0x15c */ - uint32_t wake2_mask; /* _WAKE2_MASK_0, 0x160 */ - uint32_t wake2_lvl; /* _WAKE2_LVL_0, 0x164 */ - uint32_t wake2_status; /* _WAKE2_STATUS_0, 0x168 */ - uint32_t sw_wake2_status; /* _SW_WAKE2_STATUS_0, 0x16c */ - uint32_t auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, 0x170 */ - uint32_t pg_mask_2; /* _PG_MASK_2_0, 0x174 */ - uint32_t pg_mask_ce1; /* _PG_MASK_CE1_0, 0x178 */ - uint32_t pg_mask_ce2; /* _PG_MASK_CE2_0, 0x17c */ - uint32_t pg_mask_ce3; /* _PG_MASK_CE3_0, 0x180 */ - uint32_t pwrgate_timer_ce_0; /* _PWRGATE_TIMER_CE_0_0, 0x184 */ - uint32_t pwrgate_timer_ce_1; /* _PWRGATE_TIMER_CE_1_0, 0x188 */ - uint32_t pwrgate_timer_ce_2; /* _PWRGATE_TIMER_CE_2_0, 0x18c */ - uint32_t pwrgate_timer_ce_3; /* _PWRGATE_TIMER_CE_3_0, 0x190 */ - uint32_t pwrgate_timer_ce_4; /* _PWRGATE_TIMER_CE_4_0, 0x194 */ - uint32_t pwrgate_timer_ce_5; /* _PWRGATE_TIMER_CE_5_0, 0x198 */ - uint32_t pwrgate_timer_ce_6; /* _PWRGATE_TIMER_CE_6_0, 0x19c */ - uint32_t pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, 0x1a0 */ - uint32_t osc_edpd_over; /* _OSC_EDPD_OVER_0, 0x1a4 */ - uint32_t clk_out_cntrl; /* _CLK_OUT_CNTRL_0, 0x1a8 */ - uint32_t sata_pwrgt; /* _SATA_PWRGT_0, 0x1ac */ - uint32_t sensor_ctrl; /* _SENSOR_CTRL_0, 0x1b0 */ - uint32_t rst_status; /* _RST_STATUS_0, 0x1b4 */ - uint32_t io_dpd_req; /* _IO_DPD_REQ_0, 0x1b8 */ - uint32_t io_dpd_status; /* _IO_DPD_STATUS_0, 0x1bc */ - uint32_t io_dpd2_req; /* _IO_DPD2_REQ_0, 0x1c0 */ - uint32_t io_dpd2_status; /* _IO_DPD2_STATUS_0, 0x1c4 */ - uint32_t sel_dpd_tim; /* _SEL_DPD_TIM_0, 0x1c8 */ - uint32_t vddp_sel; /* _VDDP_SEL_0, 0x1cc */ - uint32_t ddr_cfg; /* _DDR_CFG_0, 0x1d0 */ - uint32_t _0x1d4[2]; - uint32_t pllm_wb0_override_freq; /* _PLLM_WB0_OVERRIDE_FREQ_0, 0x1dc */ - uint32_t _0x1e0; - uint32_t pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, 0x1e4 */ - uint32_t dsi_sel_dpd; /* _DSI_SEL_DPD_0, 0x1e8 */ - uint32_t utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, 0x1ec */ - uint32_t utmip_uhsic_saved_state; /* _UTMIP_UHSIC_SAVED_STATE_0, 0x1f0 */ - uint32_t _0x1f4; - uint32_t utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, 0x1f8 */ - uint32_t utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, 0x1fc */ - uint32_t utmip_uhsic_sleepwalk_cfg; /* _UTMIP_UHSIC_SLEEPWALK_CFG_0, 0x200 */ - uint32_t utmip_sleepwalk_p0; /* _UTMIP_SLEEPWALK_P0_0, 0x204 */ - uint32_t utmip_sleepwalk_p1; /* _UTMIP_SLEEPWALK_P1_0, 0x208 */ - uint32_t utmip_sleepwalk_p2; /* _UTMIP_SLEEPWALK_P2_0, 0x20c */ - uint32_t uhsic_sleepwalk_p0; /* _UHSIC_SLEEPWALK_P0_0, 0x210 */ - uint32_t utmip_uhsic_status; /* _UTMIP_UHSIC_STATUS_0, 0x214 */ - uint32_t utmip_uhsic_fake; /* _UTMIP_UHSIC_FAKE_0, 0x218 */ - uint32_t bondout_mirror3; /* _BONDOUT_MIRROR3_0, 0x21c */ - uint32_t bondout_mirror4; /* _BONDOUT_MIRROR4_0, 0x220 */ - uint32_t secure_scratch6; /* _SECURE_SCRATCH6_0, 0x224 */ - uint32_t secure_scratch7; /* _SECURE_SCRATCH7_0, 0x228 */ - uint32_t scratch43; /* _SCRATCH43_0, 0x22c */ - uint32_t scratch44; /* _SCRATCH44_0, 0x230 */ - uint32_t scratch45; /* _SCRATCH45_0, 0x234 */ - uint32_t scratch46; /* _SCRATCH46_0, 0x238 */ - uint32_t scratch47; /* _SCRATCH47_0, 0x23c */ - uint32_t scratch48; /* _SCRATCH48_0, 0x240 */ - uint32_t scratch49; /* _SCRATCH49_0, 0x244 */ - uint32_t scratch50; /* _SCRATCH50_0, 0x248 */ - uint32_t scratch51; /* _SCRATCH51_0, 0x24c */ - uint32_t scratch52; /* _SCRATCH52_0, 0x250 */ - uint32_t scratch53; /* _SCRATCH53_0, 0x254 */ - uint32_t scratch54; /* _SCRATCH54_0, 0x258 */ - uint32_t scratch55; /* _SCRATCH55_0, 0x25c */ - uint32_t scratch0_eco; /* _SCRATCH0_ECO_0, 0x260 */ - uint32_t por_dpd_ctrl; /* _POR_DPD_CTRL_0, 0x264 */ - uint32_t scratch2_eco; /* _SCRATCH2_ECO_0, 0x268 */ - uint32_t utmip_uhsic_line_wakeup; /* _UTMIP_UHSIC_LINE_WAKEUP_0, 0x26c */ - uint32_t utmip_bias_master_cntrl; /* _UTMIP_BIAS_MASTER_CNTRL_0, 0x270 */ - uint32_t utmip_master_config; /* _UTMIP_MASTER_CONFIG_0, 0x274 */ - uint32_t td_pwrgate_inter_part_timer; /* _TD_PWRGATE_INTER_PART_TIMER_0, 0x278 */ - uint32_t utmip_uhsic2_triggers; /* _UTMIP_UHSIC2_TRIGGERS_0, 0x27c */ - uint32_t utmip_uhsic2_saved_state; /* _UTMIP_UHSIC2_SAVED_STATE_0, 0x280 */ - uint32_t utmip_uhsic2_sleep_cfg; /* _UTMIP_UHSIC2_SLEEP_CFG_0, 0x284 */ - uint32_t utmip_uhsic2_sleepwalk_cfg; /* _UTMIP_UHSIC2_SLEEPWALK_CFG_0, 0x288 */ - uint32_t uhsic2_sleepwalk_p1; /* _UHSIC2_SLEEPWALK_P1_0, 0x28c */ - uint32_t utmip_uhsic2_status; /* _UTMIP_UHSIC2_STATUS_0, 0x290 */ - uint32_t utmip_uhsic2_fake; /* _UTMIP_UHSIC2_FAKE_0, 0x294 */ - uint32_t utmip_uhsic2_line_wakeup; /* _UTMIP_UHSIC2_LINE_WAKEUP_0, 0x298 */ - uint32_t utmip_master2_config; /* _UTMIP_MASTER2_CONFIG_0, 0x29c */ - uint32_t utmip_uhsic_rpd_cfg; /* _UTMIP_UHSIC_RPD_CFG_0, 0x2a0 */ - uint32_t pg_mask_ce0; /* _PG_MASK_CE0_0, 0x2a4 */ - uint32_t pg_mask_3; /* _PG_MASK_3_0, 0x2a8 */ - uint32_t pg_mask_4; /* _PG_MASK_4_0, 0x2ac */ - uint32_t pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2_0, 0x2b0 */ - uint32_t tsc_mult; /* _TSC_MULT_0, 0x2b4 */ - uint32_t cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, 0x2b8 */ - uint32_t glb_amap_cfg; /* _GLB_AMAP_CFG_0, 0x2bc */ - uint32_t sticky_bits; /* _STICKY_BITS_0, 0x2c0 */ - uint32_t sec_disable2; /* _SEC_DISABLE2_0, 0x2c4 */ - uint32_t weak_bias; /* _WEAK_BIAS_0, 0x2c8 */ - uint32_t reg_short; /* _REG_SHORT_0, 0x2cc */ - uint32_t pg_mask_andor; /* _PG_MASK_ANDOR_0, 0x2d0 */ - uint32_t gpu_rg_cntrl; /* _GPU_RG_CNTRL_0, 0x2d4 */ - uint32_t sec_disable3; /* _SEC_DISABLE3_0, 0x2d8 */ - uint32_t pg_mask_5; /* _PG_MASK_5_0, 0x2dc */ - uint32_t pg_mask_6; /* _PG_MASK_6_0, 0x2e0 */ - uint32_t _0x2e4[7]; - uint32_t secure_scratch8; /* _SECURE_SCRATCH8_0, 0x300 */ - uint32_t secure_scratch9; /* _SECURE_SCRATCH9_0, 0x304 */ - uint32_t secure_scratch10; /* _SECURE_SCRATCH10_0, 0x308 */ - uint32_t secure_scratch11; /* _SECURE_SCRATCH11_0, 0x30c */ - uint32_t secure_scratch12; /* _SECURE_SCRATCH12_0, 0x310 */ - uint32_t secure_scratch13; /* _SECURE_SCRATCH13_0, 0x314 */ - uint32_t secure_scratch14; /* _SECURE_SCRATCH14_0, 0x318 */ - uint32_t secure_scratch15; /* _SECURE_SCRATCH15_0, 0x31c */ - uint32_t secure_scratch16; /* _SECURE_SCRATCH16_0, 0x320 */ - uint32_t secure_scratch17; /* _SECURE_SCRATCH17_0, 0x324 */ - uint32_t secure_scratch18; /* _SECURE_SCRATCH18_0, 0x328 */ - uint32_t secure_scratch19; /* _SECURE_SCRATCH19_0, 0x32c */ - uint32_t secure_scratch20; /* _SECURE_SCRATCH20_0, 0x330 */ - uint32_t secure_scratch21; /* _SECURE_SCRATCH21_0, 0x334 */ - uint32_t secure_scratch22; /* _SECURE_SCRATCH22_0, 0x338 */ - uint32_t secure_scratch23; /* _SECURE_SCRATCH23_0, 0x33c */ - uint32_t secure_scratch24; /* _SECURE_SCRATCH24_0, 0x340 */ - uint32_t secure_scratch25; /* _SECURE_SCRATCH25_0, 0x344 */ - uint32_t secure_scratch26; /* _SECURE_SCRATCH26_0, 0x348 */ - uint32_t secure_scratch27; /* _SECURE_SCRATCH27_0, 0x34c */ - uint32_t secure_scratch28; /* _SECURE_SCRATCH28_0, 0x350 */ - uint32_t secure_scratch29; /* _SECURE_SCRATCH29_0, 0x354 */ - uint32_t secure_scratch30; /* _SECURE_SCRATCH30_0, 0x358 */ - uint32_t secure_scratch31; /* _SECURE_SCRATCH31_0, 0x35c */ - uint32_t secure_scratch32; /* _SECURE_SCRATCH32_0, 0x360 */ - uint32_t secure_scratch33; /* _SECURE_SCRATCH33_0, 0x364 */ - uint32_t secure_scratch34; /* _SECURE_SCRATCH34_0, 0x368 */ - uint32_t secure_scratch35; /* _SECURE_SCRATCH35_0, 0x36c */ - uint32_t secure_scratch36; /* _SECURE_SCRATCH36_0, 0x370 */ - uint32_t secure_scratch37; /* _SECURE_SCRATCH37_0, 0x374 */ - uint32_t secure_scratch38; /* _SECURE_SCRATCH38_0, 0x378 */ - uint32_t secure_scratch39; /* _SECURE_SCRATCH39_0, 0x37c */ - uint32_t secure_scratch40; /* _SECURE_SCRATCH40_0, 0x380 */ - uint32_t secure_scratch41; /* _SECURE_SCRATCH41_0, 0x384 */ - uint32_t secure_scratch42; /* _SECURE_SCRATCH42_0, 0x388 */ - uint32_t secure_scratch43; /* _SECURE_SCRATCH43_0, 0x38c */ - uint32_t secure_scratch44; /* _SECURE_SCRATCH44_0, 0x390 */ - uint32_t secure_scratch45; /* _SECURE_SCRATCH45_0, 0x394 */ - uint32_t secure_scratch46; /* _SECURE_SCRATCH46_0, 0x398 */ - uint32_t secure_scratch47; /* _SECURE_SCRATCH47_0, 0x39c */ - uint32_t secure_scratch48; /* _SECURE_SCRATCH48_0, 0x3a0 */ - uint32_t secure_scratch49; /* _SECURE_SCRATCH49_0, 0x3a4 */ - uint32_t secure_scratch50; /* _SECURE_SCRATCH50_0, 0x3a8 */ - uint32_t secure_scratch51; /* _SECURE_SCRATCH51_0, 0x3ac */ - uint32_t secure_scratch52; /* _SECURE_SCRATCH52_0, 0x3b0 */ - uint32_t secure_scratch53; /* _SECURE_SCRATCH53_0, 0x3b4 */ - uint32_t secure_scratch54; /* _SECURE_SCRATCH54_0, 0x3b8 */ - uint32_t secure_scratch55; /* _SECURE_SCRATCH55_0, 0x3bc */ - uint32_t secure_scratch56; /* _SECURE_SCRATCH56_0, 0x3c0 */ - uint32_t secure_scratch57; /* _SECURE_SCRATCH57_0, 0x3c4 */ - uint32_t secure_scratch58; /* _SECURE_SCRATCH58_0, 0x3c8 */ - uint32_t secure_scratch59; /* _SECURE_SCRATCH59_0, 0x3cc */ - uint32_t secure_scratch60; /* _SECURE_SCRATCH60_0, 0x3d0 */ - uint32_t secure_scratch61; /* _SECURE_SCRATCH61_0, 0x3d4 */ - uint32_t secure_scratch62; /* _SECURE_SCRATCH62_0, 0x3d8 */ - uint32_t secure_scratch63; /* _SECURE_SCRATCH63_0, 0x3dc */ - uint32_t secure_scratch64; /* _SECURE_SCRATCH64_0, 0x3e0 */ - uint32_t secure_scratch65; /* _SECURE_SCRATCH65_0, 0x3e4 */ - uint32_t secure_scratch66; /* _SECURE_SCRATCH66_0, 0x3e8 */ - uint32_t secure_scratch67; /* _SECURE_SCRATCH67_0, 0x3ec */ - uint32_t secure_scratch68; /* _SECURE_SCRATCH68_0, 0x3f0 */ - uint32_t secure_scratch69; /* _SECURE_SCRATCH69_0, 0x3f4 */ - uint32_t secure_scratch70; /* _SECURE_SCRATCH70_0, 0x3f8 */ - uint32_t secure_scratch71; /* _SECURE_SCRATCH71_0, 0x3fc */ - uint32_t secure_scratch72; /* _SECURE_SCRATCH72_0, 0x400 */ - uint32_t secure_scratch73; /* _SECURE_SCRATCH73_0, 0x404 */ - uint32_t secure_scratch74; /* _SECURE_SCRATCH74_0, 0x408 */ - uint32_t secure_scratch75; /* _SECURE_SCRATCH75_0, 0x40c */ - uint32_t secure_scratch76; /* _SECURE_SCRATCH76_0, 0x410 */ - uint32_t secure_scratch77; /* _SECURE_SCRATCH77_0, 0x414 */ - uint32_t secure_scratch78; /* _SECURE_SCRATCH78_0, 0x418 */ - uint32_t secure_scratch79; /* _SECURE_SCRATCH79_0, 0x41c */ - uint32_t _0x420[8]; - uint32_t cntrl2; /* _CNTRL2_0, 0x440 */ - uint32_t io_dpd_off_mask; /* _IO_DPD_OFF_MASK_0, 0x444 */ - uint32_t io_dpd2_off_mask; /* _IO_DPD2_OFF_MASK_0, 0x448 */ - uint32_t event_counter; /* _EVENT_COUNTER_0, 0x44c */ - uint32_t fuse_control; /* _FUSE_CONTROL_0, 0x450 */ - uint32_t scratch1_eco; /* _SCRATCH1_ECO_0, 0x454 */ - uint32_t _0x458; - uint32_t io_dpd3_req; /* _IO_DPD3_REQ_0, 0x45c */ - uint32_t io_dpd3_status; /* _IO_DPD3_STATUS_0, 0x460 */ - uint32_t io_dpd4_req; /* _IO_DPD4_REQ_0, 0x464 */ - uint32_t io_dpd4_status; /* _IO_DPD4_STATUS_0, 0x468 */ - uint32_t _0x46c[2]; - uint32_t direct_thermtrip_cfg; /* _DIRECT_THERMTRIP_CFG_0, 0x474 */ - uint32_t tsosc_delay; /* _TSOSC_DELAY_0, 0x478 */ - uint32_t set_sw_clamp; /* _SET_SW_CLAMP_0, 0x47c */ - uint32_t debug_authentication; /* _DEBUG_AUTHENTICATION_0, 0x480 */ - uint32_t aotag_cfg; /* _AOTAG_CFG_0, 0x484 */ - uint32_t aotag_thresh1_cfg; /* _AOTAG_THRESH1_CFG_0, 0x488 */ - uint32_t aotag_thresh2_cfg; /* _AOTAG_THRESH2_CFG_0, 0x48c */ - uint32_t aotag_thresh3_cfg; /* _AOTAG_THRESH3_CFG_0, 0x490 */ - uint32_t aotag_status; /* _AOTAG_STATUS_0, 0x494 */ - uint32_t aotag_security; /* _AOTAG_SECURITY_0, 0x498 */ - uint32_t tsensor_config0; /* _TSENSOR_CONFIG0_0, 0x49c */ - uint32_t tsensor_config1; /* _TSENSOR_CONFIG1_0, 0x4a0 */ - uint32_t tsensor_config2; /* _TSENSOR_CONFIG2_0, 0x4a4 */ - uint32_t tsensor_status0; /* _TSENSOR_STATUS0_0, 0x4a8 */ - uint32_t tsensor_status1; /* _TSENSOR_STATUS1_0, 0x4ac */ - uint32_t tsensor_status2; /* _TSENSOR_STATUS2_0, 0x4b0 */ - uint32_t tsensor_pdiv; /* _TSENSOR_PDIV_0, 0x4b4 */ - uint32_t aotag_intr_en; /* _AOTAG_INTR_EN_0, 0x4b8 */ - uint32_t aotag_intr_dis; /* _AOTAG_INTR_DIS_0, 0x4bc */ - uint32_t utmip_pad_cfg0; /* _UTMIP_PAD_CFG0_0, 0x4c0 */ - uint32_t utmip_pad_cfg1; /* _UTMIP_PAD_CFG1_0, 0x4c4 */ - uint32_t utmip_pad_cfg2; /* _UTMIP_PAD_CFG2_0, 0x4c8 */ - uint32_t utmip_pad_cfg3; /* _UTMIP_PAD_CFG3_0, 0x4cc */ - uint32_t utmip_uhsic_sleep_cfg1; /* _UTMIP_UHSIC_SLEEP_CFG1_0, 0x4d0 */ - uint32_t cc4_hvc_control; /* _CC4_HVC_CONTROL_0, 0x4d4 */ - uint32_t wake_debounce_en; /* _WAKE_DEBOUNCE_EN_0, 0x4d8 */ - uint32_t ramdump_ctl_status; /* _RAMDUMP_CTL_STATUS_0, 0x4dc */ - uint32_t utmip_sleepwalk_p3; /* _UTMIP_SLEEPWALK_P3_0, 0x4e0 */ - uint32_t ddr_cntrl; /* _DDR_CNTRL_0, 0x4e4 */ - uint32_t _0x4e8[50]; - uint32_t sec_disable4; /* _SEC_DISABLE4_0, 0x5b0 */ - uint32_t sec_disable5; /* _SEC_DISABLE5_0, 0x5b4 */ - uint32_t sec_disable6; /* _SEC_DISABLE6_0, 0x5b8 */ - uint32_t sec_disable7; /* _SEC_DISABLE7_0, 0x5bc */ - uint32_t sec_disable8; /* _SEC_DISABLE8_0, 0x5c0 */ - uint32_t sec_disable9; /* _SEC_DISABLE9_0, 0x5c4 */ - uint32_t sec_disable10; /* _SEC_DISABLE10_0, 0x5c8 */ - uint32_t _0x5cc[13]; - uint32_t scratch56; /* _SCRATCH56_0, 0x600 */ - uint32_t scratch57; /* _SCRATCH57_0, 0x604 */ - uint32_t scratch58; /* _SCRATCH58_0, 0x608 */ - uint32_t scratch59; /* _SCRATCH59_0, 0x60c */ - uint32_t scratch60; /* _SCRATCH60_0, 0x610 */ - uint32_t scratch61; /* _SCRATCH61_0, 0x614 */ - uint32_t scratch62; /* _SCRATCH62_0, 0x618 */ - uint32_t scratch63; /* _SCRATCH63_0, 0x61c */ - uint32_t scratch64; /* _SCRATCH64_0, 0x620 */ - uint32_t scratch65; /* _SCRATCH65_0, 0x624 */ - uint32_t scratch66; /* _SCRATCH66_0, 0x628 */ - uint32_t scratch67; /* _SCRATCH67_0, 0x62c */ - uint32_t scratch68; /* _SCRATCH68_0, 0x630 */ - uint32_t scratch69; /* _SCRATCH69_0, 0x634 */ - uint32_t scratch70; /* _SCRATCH70_0, 0x638 */ - uint32_t scratch71; /* _SCRATCH71_0, 0x63c */ - uint32_t scratch72; /* _SCRATCH72_0, 0x640 */ - uint32_t scratch73; /* _SCRATCH73_0, 0x644 */ - uint32_t scratch74; /* _SCRATCH74_0, 0x648 */ - uint32_t scratch75; /* _SCRATCH75_0, 0x64c */ - uint32_t scratch76; /* _SCRATCH76_0, 0x650 */ - uint32_t scratch77; /* _SCRATCH77_0, 0x654 */ - uint32_t scratch78; /* _SCRATCH78_0, 0x658 */ - uint32_t scratch79; /* _SCRATCH79_0, 0x65c */ - uint32_t scratch80; /* _SCRATCH80_0, 0x660 */ - uint32_t scratch81; /* _SCRATCH81_0, 0x664 */ - uint32_t scratch82; /* _SCRATCH82_0, 0x668 */ - uint32_t scratch83; /* _SCRATCH83_0, 0x66c */ - uint32_t scratch84; /* _SCRATCH84_0, 0x670 */ - uint32_t scratch85; /* _SCRATCH85_0, 0x674 */ - uint32_t scratch86; /* _SCRATCH86_0, 0x678 */ - uint32_t scratch87; /* _SCRATCH87_0, 0x67c */ - uint32_t scratch88; /* _SCRATCH88_0, 0x680 */ - uint32_t scratch89; /* _SCRATCH89_0, 0x684 */ - uint32_t scratch90; /* _SCRATCH90_0, 0x688 */ - uint32_t scratch91; /* _SCRATCH91_0, 0x68c */ - uint32_t scratch92; /* _SCRATCH92_0, 0x690 */ - uint32_t scratch93; /* _SCRATCH93_0, 0x694 */ - uint32_t scratch94; /* _SCRATCH94_0, 0x698 */ - uint32_t scratch95; /* _SCRATCH95_0, 0x69c */ - uint32_t scratch96; /* _SCRATCH96_0, 0x6a0 */ - uint32_t scratch97; /* _SCRATCH97_0, 0x6a4 */ - uint32_t scratch98; /* _SCRATCH98_0, 0x6a8 */ - uint32_t scratch99; /* _SCRATCH99_0, 0x6ac */ - uint32_t scratch100; /* _SCRATCH100_0, 0x6b0 */ - uint32_t scratch101; /* _SCRATCH101_0, 0x6b4 */ - uint32_t scratch102; /* _SCRATCH102_0, 0x6b8 */ - uint32_t scratch103; /* _SCRATCH103_0, 0x6bc */ - uint32_t scratch104; /* _SCRATCH104_0, 0x6c0 */ - uint32_t scratch105; /* _SCRATCH105_0, 0x6c4 */ - uint32_t scratch106; /* _SCRATCH106_0, 0x6c8 */ - uint32_t scratch107; /* _SCRATCH107_0, 0x6cc */ - uint32_t scratch108; /* _SCRATCH108_0, 0x6d0 */ - uint32_t scratch109; /* _SCRATCH109_0, 0x6d4 */ - uint32_t scratch110; /* _SCRATCH110_0, 0x6d8 */ - uint32_t scratch111; /* _SCRATCH111_0, 0x6dc */ - uint32_t scratch112; /* _SCRATCH112_0, 0x6e0 */ - uint32_t scratch113; /* _SCRATCH113_0, 0x6e4 */ - uint32_t scratch114; /* _SCRATCH114_0, 0x6e8 */ - uint32_t scratch115; /* _SCRATCH115_0, 0x6ec */ - uint32_t scratch116; /* _SCRATCH116_0, 0x6f0 */ - uint32_t scratch117; /* _SCRATCH117_0, 0x6f4 */ - uint32_t scratch118; /* _SCRATCH118_0, 0x6f8 */ - uint32_t scratch119; /* _SCRATCH119_0, 0x6fc */ - uint32_t scratch120; /* _SCRATCH120_0, 0x700 */ - uint32_t scratch121; /* _SCRATCH121_0, 0x704 */ - uint32_t scratch122; /* _SCRATCH122_0, 0x708 */ - uint32_t scratch123; /* _SCRATCH123_0, 0x70c */ - uint32_t scratch124; /* _SCRATCH124_0, 0x710 */ - uint32_t scratch125; /* _SCRATCH125_0, 0x714 */ - uint32_t scratch126; /* _SCRATCH126_0, 0x718 */ - uint32_t scratch127; /* _SCRATCH127_0, 0x71c */ - uint32_t scratch128; /* _SCRATCH128_0, 0x720 */ - uint32_t scratch129; /* _SCRATCH129_0, 0x724 */ - uint32_t scratch130; /* _SCRATCH130_0, 0x728 */ - uint32_t scratch131; /* _SCRATCH131_0, 0x72c */ - uint32_t scratch132; /* _SCRATCH132_0, 0x730 */ - uint32_t scratch133; /* _SCRATCH133_0, 0x734 */ - uint32_t scratch134; /* _SCRATCH134_0, 0x738 */ - uint32_t scratch135; /* _SCRATCH135_0, 0x73c */ - uint32_t scratch136; /* _SCRATCH136_0, 0x740 */ - uint32_t scratch137; /* _SCRATCH137_0, 0x744 */ - uint32_t scratch138; /* _SCRATCH138_0, 0x748 */ - uint32_t scratch139; /* _SCRATCH139_0, 0x74c */ - uint32_t scratch140; /* _SCRATCH140_0, 0x750 */ - uint32_t scratch141; /* _SCRATCH141_0, 0x754 */ - uint32_t scratch142; /* _SCRATCH142_0, 0x758 */ - uint32_t scratch143; /* _SCRATCH143_0, 0x75c */ - uint32_t scratch144; /* _SCRATCH144_0, 0x760 */ - uint32_t scratch145; /* _SCRATCH145_0, 0x764 */ - uint32_t scratch146; /* _SCRATCH146_0, 0x768 */ - uint32_t scratch147; /* _SCRATCH147_0, 0x76c */ - uint32_t scratch148; /* _SCRATCH148_0, 0x770 */ - uint32_t scratch149; /* _SCRATCH149_0, 0x774 */ - uint32_t scratch150; /* _SCRATCH150_0, 0x778 */ - uint32_t scratch151; /* _SCRATCH151_0, 0x77c */ - uint32_t scratch152; /* _SCRATCH152_0, 0x780 */ - uint32_t scratch153; /* _SCRATCH153_0, 0x784 */ - uint32_t scratch154; /* _SCRATCH154_0, 0x788 */ - uint32_t scratch155; /* _SCRATCH155_0, 0x78c */ - uint32_t scratch156; /* _SCRATCH156_0, 0x790 */ - uint32_t scratch157; /* _SCRATCH157_0, 0x794 */ - uint32_t scratch158; /* _SCRATCH158_0, 0x798 */ - uint32_t scratch159; /* _SCRATCH159_0, 0x79c */ - uint32_t scratch160; /* _SCRATCH160_0, 0x7a0 */ - uint32_t scratch161; /* _SCRATCH161_0, 0x7a4 */ - uint32_t scratch162; /* _SCRATCH162_0, 0x7a8 */ - uint32_t scratch163; /* _SCRATCH163_0, 0x7ac */ - uint32_t scratch164; /* _SCRATCH164_0, 0x7b0 */ - uint32_t scratch165; /* _SCRATCH165_0, 0x7b4 */ - uint32_t scratch166; /* _SCRATCH166_0, 0x7b8 */ - uint32_t scratch167; /* _SCRATCH167_0, 0x7bc */ - uint32_t scratch168; /* _SCRATCH168_0, 0x7c0 */ - uint32_t scratch169; /* _SCRATCH169_0, 0x7c4 */ - uint32_t scratch170; /* _SCRATCH170_0, 0x7c8 */ - uint32_t scratch171; /* _SCRATCH171_0, 0x7cc */ - uint32_t scratch172; /* _SCRATCH172_0, 0x7d0 */ - uint32_t scratch173; /* _SCRATCH173_0, 0x7d4 */ - uint32_t scratch174; /* _SCRATCH174_0, 0x7d8 */ - uint32_t scratch175; /* _SCRATCH175_0, 0x7dc */ - uint32_t scratch176; /* _SCRATCH176_0, 0x7e0 */ - uint32_t scratch177; /* _SCRATCH177_0, 0x7e4 */ - uint32_t scratch178; /* _SCRATCH178_0, 0x7e8 */ - uint32_t scratch179; /* _SCRATCH179_0, 0x7ec */ - uint32_t scratch180; /* _SCRATCH180_0, 0x7f0 */ - uint32_t scratch181; /* _SCRATCH181_0, 0x7f4 */ - uint32_t scratch182; /* _SCRATCH182_0, 0x7f8 */ - uint32_t scratch183; /* _SCRATCH183_0, 0x7fc */ - uint32_t scratch184; /* _SCRATCH184_0, 0x800 */ - uint32_t scratch185; /* _SCRATCH185_0, 0x804 */ - uint32_t scratch186; /* _SCRATCH186_0, 0x808 */ - uint32_t scratch187; /* _SCRATCH187_0, 0x80c */ - uint32_t scratch188; /* _SCRATCH188_0, 0x810 */ - uint32_t scratch189; /* _SCRATCH189_0, 0x814 */ - uint32_t scratch190; /* _SCRATCH190_0, 0x818 */ - uint32_t scratch191; /* _SCRATCH191_0, 0x81c */ - uint32_t scratch192; /* _SCRATCH192_0, 0x820 */ - uint32_t scratch193; /* _SCRATCH193_0, 0x824 */ - uint32_t scratch194; /* _SCRATCH194_0, 0x828 */ - uint32_t scratch195; /* _SCRATCH195_0, 0x82c */ - uint32_t scratch196; /* _SCRATCH196_0, 0x830 */ - uint32_t scratch197; /* _SCRATCH197_0, 0x834 */ - uint32_t scratch198; /* _SCRATCH198_0, 0x838 */ - uint32_t scratch199; /* _SCRATCH199_0, 0x83c */ - uint32_t scratch200; /* _SCRATCH200_0, 0x840 */ - uint32_t scratch201; /* _SCRATCH201_0, 0x844 */ - uint32_t scratch202; /* _SCRATCH202_0, 0x848 */ - uint32_t scratch203; /* _SCRATCH203_0, 0x84c */ - uint32_t scratch204; /* _SCRATCH204_0, 0x850 */ - uint32_t scratch205; /* _SCRATCH205_0, 0x854 */ - uint32_t scratch206; /* _SCRATCH206_0, 0x858 */ - uint32_t scratch207; /* _SCRATCH207_0, 0x85c */ - uint32_t scratch208; /* _SCRATCH208_0, 0x860 */ - uint32_t scratch209; /* _SCRATCH209_0, 0x864 */ - uint32_t scratch210; /* _SCRATCH210_0, 0x868 */ - uint32_t scratch211; /* _SCRATCH211_0, 0x86c */ - uint32_t scratch212; /* _SCRATCH212_0, 0x870 */ - uint32_t scratch213; /* _SCRATCH213_0, 0x874 */ - uint32_t scratch214; /* _SCRATCH214_0, 0x878 */ - uint32_t scratch215; /* _SCRATCH215_0, 0x87c */ - uint32_t scratch216; /* _SCRATCH216_0, 0x880 */ - uint32_t scratch217; /* _SCRATCH217_0, 0x884 */ - uint32_t scratch218; /* _SCRATCH218_0, 0x888 */ - uint32_t scratch219; /* _SCRATCH219_0, 0x88c */ - uint32_t scratch220; /* _SCRATCH220_0, 0x890 */ - uint32_t scratch221; /* _SCRATCH221_0, 0x894 */ - uint32_t scratch222; /* _SCRATCH222_0, 0x898 */ - uint32_t scratch223; /* _SCRATCH223_0, 0x89c */ - uint32_t scratch224; /* _SCRATCH224_0, 0x8a0 */ - uint32_t scratch225; /* _SCRATCH225_0, 0x8a4 */ - uint32_t scratch226; /* _SCRATCH226_0, 0x8a8 */ - uint32_t scratch227; /* _SCRATCH227_0, 0x8ac */ - uint32_t scratch228; /* _SCRATCH228_0, 0x8b0 */ - uint32_t scratch229; /* _SCRATCH229_0, 0x8b4 */ - uint32_t scratch230; /* _SCRATCH230_0, 0x8b8 */ - uint32_t scratch231; /* _SCRATCH231_0, 0x8bc */ - uint32_t scratch232; /* _SCRATCH232_0, 0x8c0 */ - uint32_t scratch233; /* _SCRATCH233_0, 0x8c4 */ - uint32_t scratch234; /* _SCRATCH234_0, 0x8c8 */ - uint32_t scratch235; /* _SCRATCH235_0, 0x8cc */ - uint32_t scratch236; /* _SCRATCH236_0, 0x8d0 */ - uint32_t scratch237; /* _SCRATCH237_0, 0x8d4 */ - uint32_t scratch238; /* _SCRATCH238_0, 0x8d8 */ - uint32_t scratch239; /* _SCRATCH239_0, 0x8dc */ - uint32_t scratch240; /* _SCRATCH240_0, 0x8e0 */ - uint32_t scratch241; /* _SCRATCH241_0, 0x8e4 */ - uint32_t scratch242; /* _SCRATCH242_0, 0x8e8 */ - uint32_t scratch243; /* _SCRATCH243_0, 0x8ec */ - uint32_t scratch244; /* _SCRATCH244_0, 0x8f0 */ - uint32_t scratch245; /* _SCRATCH245_0, 0x8f4 */ - uint32_t scratch246; /* _SCRATCH246_0, 0x8f8 */ - uint32_t scratch247; /* _SCRATCH247_0, 0x8fc */ - uint32_t scratch248; /* _SCRATCH248_0, 0x900 */ - uint32_t scratch249; /* _SCRATCH249_0, 0x904 */ - uint32_t scratch250; /* _SCRATCH250_0, 0x908 */ - uint32_t scratch251; /* _SCRATCH251_0, 0x90c */ - uint32_t scratch252; /* _SCRATCH252_0, 0x910 */ - uint32_t scratch253; /* _SCRATCH253_0, 0x914 */ - uint32_t scratch254; /* _SCRATCH254_0, 0x918 */ - uint32_t scratch255; /* _SCRATCH255_0, 0x91c */ - uint32_t scratch256; /* _SCRATCH256_0, 0x920 */ - uint32_t scratch257; /* _SCRATCH257_0, 0x924 */ - uint32_t scratch258; /* _SCRATCH258_0, 0x928 */ - uint32_t scratch259; /* _SCRATCH259_0, 0x92c */ - uint32_t scratch260; /* _SCRATCH260_0, 0x930 */ - uint32_t scratch261; /* _SCRATCH261_0, 0x934 */ - uint32_t scratch262; /* _SCRATCH262_0, 0x938 */ - uint32_t scratch263; /* _SCRATCH263_0, 0x93c */ - uint32_t scratch264; /* _SCRATCH264_0, 0x940 */ - uint32_t scratch265; /* _SCRATCH265_0, 0x944 */ - uint32_t scratch266; /* _SCRATCH266_0, 0x948 */ - uint32_t scratch267; /* _SCRATCH267_0, 0x94c */ - uint32_t scratch268; /* _SCRATCH268_0, 0x950 */ - uint32_t scratch269; /* _SCRATCH269_0, 0x954 */ - uint32_t scratch270; /* _SCRATCH270_0, 0x958 */ - uint32_t scratch271; /* _SCRATCH271_0, 0x95c */ - uint32_t scratch272; /* _SCRATCH272_0, 0x960 */ - uint32_t scratch273; /* _SCRATCH273_0, 0x964 */ - uint32_t scratch274; /* _SCRATCH274_0, 0x968 */ - uint32_t scratch275; /* _SCRATCH275_0, 0x96c */ - uint32_t scratch276; /* _SCRATCH276_0, 0x970 */ - uint32_t scratch277; /* _SCRATCH277_0, 0x974 */ - uint32_t scratch278; /* _SCRATCH278_0, 0x978 */ - uint32_t scratch279; /* _SCRATCH279_0, 0x97c */ - uint32_t scratch280; /* _SCRATCH280_0, 0x980 */ - uint32_t scratch281; /* _SCRATCH281_0, 0x984 */ - uint32_t scratch282; /* _SCRATCH282_0, 0x988 */ - uint32_t scratch283; /* _SCRATCH283_0, 0x98c */ - uint32_t scratch284; /* _SCRATCH284_0, 0x990 */ - uint32_t scratch285; /* _SCRATCH285_0, 0x994 */ - uint32_t scratch286; /* _SCRATCH286_0, 0x998 */ - uint32_t scratch287; /* _SCRATCH287_0, 0x99c */ - uint32_t scratch288; /* _SCRATCH288_0, 0x9a0 */ - uint32_t scratch289; /* _SCRATCH289_0, 0x9a4 */ - uint32_t scratch290; /* _SCRATCH290_0, 0x9a8 */ - uint32_t scratch291; /* _SCRATCH291_0, 0x9ac */ - uint32_t scratch292; /* _SCRATCH292_0, 0x9b0 */ - uint32_t scratch293; /* _SCRATCH293_0, 0x9b4 */ - uint32_t scratch294; /* _SCRATCH294_0, 0x9b8 */ - uint32_t scratch295; /* _SCRATCH295_0, 0x9bc */ - uint32_t scratch296; /* _SCRATCH296_0, 0x9c0 */ - uint32_t scratch297; /* _SCRATCH297_0, 0x9c4 */ - uint32_t scratch298; /* _SCRATCH298_0, 0x9c8 */ - uint32_t scratch299; /* _SCRATCH299_0, 0x9cc */ - uint32_t _0x9d0[50]; - uint32_t secure_scratch80; /* _SECURE_SCRATCH80_0, 0xa98 */ - uint32_t secure_scratch81; /* _SECURE_SCRATCH81_0, 0xa9c */ - uint32_t secure_scratch82; /* _SECURE_SCRATCH82_0, 0xaa0 */ - uint32_t secure_scratch83; /* _SECURE_SCRATCH83_0, 0xaa4 */ - uint32_t secure_scratch84; /* _SECURE_SCRATCH84_0, 0xaa8 */ - uint32_t secure_scratch85; /* _SECURE_SCRATCH85_0, 0xaac */ - uint32_t secure_scratch86; /* _SECURE_SCRATCH86_0, 0xab0 */ - uint32_t secure_scratch87; /* _SECURE_SCRATCH87_0, 0xab4 */ - uint32_t secure_scratch88; /* _SECURE_SCRATCH88_0, 0xab8 */ - uint32_t secure_scratch89; /* _SECURE_SCRATCH89_0, 0xabc */ - uint32_t secure_scratch90; /* _SECURE_SCRATCH90_0, 0xac0 */ - uint32_t secure_scratch91; /* _SECURE_SCRATCH91_0, 0xac4 */ - uint32_t secure_scratch92; /* _SECURE_SCRATCH92_0, 0xac8 */ - uint32_t secure_scratch93; /* _SECURE_SCRATCH93_0, 0xacc */ - uint32_t secure_scratch94; /* _SECURE_SCRATCH94_0, 0xad0 */ - uint32_t secure_scratch95; /* _SECURE_SCRATCH95_0, 0xad4 */ - uint32_t secure_scratch96; /* _SECURE_SCRATCH96_0, 0xad8 */ - uint32_t secure_scratch97; /* _SECURE_SCRATCH97_0, 0xadc */ - uint32_t secure_scratch98; /* _SECURE_SCRATCH98_0, 0xae0 */ - uint32_t secure_scratch99; /* _SECURE_SCRATCH99_0, 0xae4 */ - uint32_t secure_scratch100; /* _SECURE_SCRATCH100_0, 0xae8 */ - uint32_t secure_scratch101; /* _SECURE_SCRATCH101_0, 0xaec */ - uint32_t secure_scratch102; /* _SECURE_SCRATCH102_0, 0xaf0 */ - uint32_t secure_scratch103; /* _SECURE_SCRATCH103_0, 0xaf4 */ - uint32_t secure_scratch104; /* _SECURE_SCRATCH104_0, 0xaf8 */ - uint32_t secure_scratch105; /* _SECURE_SCRATCH105_0, 0xafc */ - uint32_t secure_scratch106; /* _SECURE_SCRATCH106_0, 0xb00 */ - uint32_t secure_scratch107; /* _SECURE_SCRATCH107_0, 0xb04 */ - uint32_t secure_scratch108; /* _SECURE_SCRATCH108_0, 0xb08 */ - uint32_t secure_scratch109; /* _SECURE_SCRATCH109_0, 0xb0c */ - uint32_t secure_scratch110; /* _SECURE_SCRATCH110_0, 0xb10 */ - uint32_t secure_scratch111; /* _SECURE_SCRATCH111_0, 0xb14 */ - uint32_t secure_scratch112; /* _SECURE_SCRATCH112_0, 0xb18 */ - uint32_t secure_scratch113; /* _SECURE_SCRATCH113_0, 0xb1c */ - uint32_t secure_scratch114; /* _SECURE_SCRATCH114_0, 0xb20 */ - uint32_t secure_scratch115; /* _SECURE_SCRATCH115_0, 0xb24 */ - uint32_t secure_scratch116; /* _SECURE_SCRATCH116_0, 0xb28 */ - uint32_t secure_scratch117; /* _SECURE_SCRATCH117_0, 0xb2c */ - uint32_t secure_scratch118; /* _SECURE_SCRATCH118_0, 0xb30 */ - uint32_t secure_scratch119; /* _SECURE_SCRATCH119_0, 0xb34 */ - uint32_t secure_scratch120; /* _SECURE_SCRATCH120_0, 0xb38 */ - uint32_t secure_scratch121; /* _SECURE_SCRATCH121_0, 0xb3c */ - uint32_t secure_scratch122; /* _SECURE_SCRATCH122_0, 0xb40 */ - uint32_t secure_scratch123; /* _SECURE_SCRATCH123_0, 0xb44 */ - uint32_t led_breathing_ctrl; /* _LED_BREATHING_CTRL_0, 0xb48 */ - uint32_t led_breathing_counter0; /* _LED_BREATHING_COUNTER0_0, 0xb4c */ - uint32_t led_breathing_counter1; /* _LED_BREATHING_COUNTER1_0, 0xb50 */ - uint32_t led_breathing_counter2; /* _LED_BREATHING_COUNTER2_0, 0xb54 */ - uint32_t led_breathing_counter3; /* _LED_BREATHING_COUNTER3_0, 0xb58 */ - uint32_t led_breathing_status; /* _LED_BREATHING_STATUS_0, 0xb5c */ - uint32_t _0xb60[2]; - uint32_t secure_scratch124; /* _SECURE_SCRATCH124_0, 0xb68 */ - uint32_t secure_scratch125; /* _SECURE_SCRATCH125_0, 0xb6c */ - uint32_t secure_scratch126; /* _SECURE_SCRATCH126_0, 0xb70 */ - uint32_t secure_scratch127; /* _SECURE_SCRATCH127_0, 0xb74 */ - uint32_t secure_scratch128; /* _SECURE_SCRATCH128_0, 0xb78 */ - uint32_t secure_scratch129; /* _SECURE_SCRATCH129_0, 0xb7c */ - uint32_t secure_scratch130; /* _SECURE_SCRATCH130_0, 0xb80 */ - uint32_t secure_scratch131; /* _SECURE_SCRATCH131_0, 0xb84 */ - uint32_t secure_scratch132; /* _SECURE_SCRATCH132_0, 0xb88 */ - uint32_t secure_scratch133; /* _SECURE_SCRATCH133_0, 0xb8c */ - uint32_t secure_scratch134; /* _SECURE_SCRATCH134_0, 0xb90 */ - uint32_t secure_scratch135; /* _SECURE_SCRATCH135_0, 0xb94 */ - uint32_t secure_scratch136; /* _SECURE_SCRATCH136_0, 0xb98 */ - uint32_t secure_scratch137; /* _SECURE_SCRATCH137_0, 0xb9c */ - uint32_t secure_scratch138; /* _SECURE_SCRATCH138_0, 0xba0 */ - uint32_t secure_scratch139; /* _SECURE_SCRATCH139_0, 0xba4 */ - uint32_t _0xba8[2]; - uint32_t sec_disable_ns; /* _SEC_DISABLE_NS_0, 0xbb0 */ - uint32_t sec_disable2_ns; /* _SEC_DISABLE2_NS_0, 0xbb4 */ - uint32_t sec_disable3_ns; /* _SEC_DISABLE3_NS_0, 0xbb8 */ - uint32_t sec_disable4_ns; /* _SEC_DISABLE4_NS_0, 0xbbc */ - uint32_t sec_disable5_ns; /* _SEC_DISABLE5_NS_0, 0xbc0 */ - uint32_t sec_disable6_ns; /* _SEC_DISABLE6_NS_0, 0xbc4 */ - uint32_t sec_disable7_ns; /* _SEC_DISABLE7_NS_0, 0xbc8 */ - uint32_t sec_disable8_ns; /* _SEC_DISABLE8_NS_0, 0xbcc */ - uint32_t sec_disable9_ns; /* _SEC_DISABLE9_NS_0, 0xbd0 */ - uint32_t sec_disable10_ns; /* _SEC_DISABLE10_NS_0, 0xbd4 */ - uint32_t _0xbd8[4]; - uint32_t tzram_pwr_cntrl; /* _TZRAM_PWR_CNTRL_0, 0xbe8 */ - uint32_t tzram_sec_disable; /* _TZRAM_SEC_DISABLE_0, 0xbec */ - uint32_t tzram_non_sec_disable; /* _TZRAM_NON_SEC_DISABLE_0, 0xbf0 */ -} tegra_pmc_t; - -static inline volatile tegra_pmc_t *pmc_get_regs(void) -{ - return (volatile tegra_pmc_t *)PMC_BASE; -} - -#endif diff --git a/sept/sept-secondary/src/preprocessor.h b/sept/sept-secondary/src/preprocessor.h deleted file mode 100644 index 2560cf456..000000000 --- a/sept/sept-secondary/src/preprocessor.h +++ /dev/null @@ -1,207 +0,0 @@ -/* TuxSH: I added INC/DEC_10 to INC/DEC_32; tuples */ - -#ifndef FUSEE_PREPROCESSOR_H -#define FUSEE_PREPROCESSOR_H - -/*============================================================================= - Copyright (c) 2015 Paul Fultz II - cloak.h - Distributed under the Boost Software License, Version 1.0. (See accompanying - file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt) -==============================================================================*/ - -/*#ifndef CLOAK_GUARD_H -#define CLOAK_GUARD_H*/ - -#define CAT(a, ...) PRIMITIVE_CAT(a, __VA_ARGS__) -#define PRIMITIVE_CAT(a, ...) a ## __VA_ARGS__ - -#define COMPL(b) PRIMITIVE_CAT(COMPL_, b) -#define COMPL_0 1 -#define COMPL_1 0 - -#define BITAND(x) PRIMITIVE_CAT(BITAND_, x) -#define BITAND_0(y) 0 -#define BITAND_1(y) y - -#define INC(x) PRIMITIVE_CAT(INC_, x) -#define INC_0 1 -#define INC_1 2 -#define INC_2 3 -#define INC_3 4 -#define INC_4 5 -#define INC_5 6 -#define INC_6 7 -#define INC_7 8 -#define INC_8 9 -#define INC_9 10 -#define INC_10 11 -#define INC_11 12 -#define INC_12 13 -#define INC_13 14 -#define INC_14 15 -#define INC_15 16 -#define INC_16 17 -#define INC_17 18 -#define INC_18 19 -#define INC_19 20 -#define INC_20 21 -#define INC_21 22 -#define INC_22 23 -#define INC_23 24 -#define INC_24 25 -#define INC_25 26 -#define INC_26 27 -#define INC_27 28 -#define INC_28 29 -#define INC_29 30 -#define INC_30 31 -#define INC_31 32 -#define INC_32 32 -#define INC_33 33 - -#define DEC(x) PRIMITIVE_CAT(DEC_, x) -#define DEC_0 0 -#define DEC_1 0 -#define DEC_2 1 -#define DEC_3 2 -#define DEC_4 3 -#define DEC_5 4 -#define DEC_6 5 -#define DEC_7 6 -#define DEC_8 7 -#define DEC_9 8 -#define DEC_10 9 -#define DEC_11 10 -#define DEC_12 11 -#define DEC_13 12 -#define DEC_14 13 -#define DEC_15 14 -#define DEC_16 15 -#define DEC_17 16 -#define DEC_18 17 -#define DEC_19 18 -#define DEC_20 19 -#define DEC_21 20 -#define DEC_22 21 -#define DEC_23 22 -#define DEC_24 23 -#define DEC_25 24 -#define DEC_26 25 -#define DEC_27 26 -#define DEC_28 27 -#define DEC_29 28 -#define DEC_30 29 -#define DEC_31 30 -#define DEC_32 31 -#define DEC_33 32 - -#define CHECK_N(x, n, ...) n -#define CHECK(...) CHECK_N(__VA_ARGS__, 0,) -#define PROBE(x) x, 1, - -#define IS_PAREN(x) CHECK(IS_PAREN_PROBE x) -#define IS_PAREN_PROBE(...) PROBE(~) - -#define NOT(x) CHECK(PRIMITIVE_CAT(NOT_, x)) -#define NOT_0 PROBE(~) - -#define COMPL(b) PRIMITIVE_CAT(COMPL_, b) -#define COMPL_0 1 -#define COMPL_1 0 - -#define BOOL(x) COMPL(NOT(x)) - -#define IIF(c) PRIMITIVE_CAT(IIF_, c) -#define IIF_0(t, ...) __VA_ARGS__ -#define IIF_1(t, ...) t - -#define IF(c) IIF(BOOL(c)) - -#define EAT(...) -#define EXPAND(...) __VA_ARGS__ -#define WHEN(c) IF(c)(EXPAND, EAT) - -#define EMPTY() -#define DEFER(id) id EMPTY() -#define OBSTRUCT(id) id DEFER(EMPTY)() - -#define EVAL(...) EVAL1(EVAL1(EVAL1(__VA_ARGS__))) -#define EVAL1(...) EVAL2(EVAL2(EVAL2(__VA_ARGS__))) -#define EVAL2(...) EVAL3(EVAL3(EVAL3(__VA_ARGS__))) -#define EVAL3(...) EVAL4(EVAL4(EVAL4(__VA_ARGS__))) -#define EVAL4(...) EVAL5(EVAL5(EVAL5(__VA_ARGS__))) -#define EVAL5(...) __VA_ARGS__ - -#define REPEAT(count, macro, ...) \ - WHEN(count) \ - ( \ - OBSTRUCT(REPEAT_INDIRECT) () \ - ( \ - DEC(count), macro, __VA_ARGS__ \ - ) \ - OBSTRUCT(macro) \ - ( \ - DEC(count), __VA_ARGS__ \ - ) \ - ) -#define REPEAT_INDIRECT() REPEAT - -#define WHILE(pred, op, ...) \ - IF(pred(__VA_ARGS__)) \ - ( \ - OBSTRUCT(WHILE_INDIRECT) () \ - ( \ - pred, op, op(__VA_ARGS__) \ - ), \ - __VA_ARGS__ \ - ) -#define WHILE_INDIRECT() WHILE - -#define PRIMITIVE_COMPARE(x, y) IS_PAREN \ -( \ - COMPARE_ ## x ( COMPARE_ ## y) (()) \ -) - -#define IS_COMPARABLE(x) IS_PAREN( CAT(COMPARE_, x) (()) ) - -#define NOT_EQUAL(x, y) \ -IIF(BITAND(IS_COMPARABLE(x))(IS_COMPARABLE(y)) ) \ -( \ - PRIMITIVE_COMPARE, \ - 1 EAT \ -)(x, y) - -#define EQUAL(x, y) COMPL(NOT_EQUAL(x, y)) - -#define COMMA() , - -#define COMMA_IF(n) IF(n)(COMMA, EAT)() - -#define PLUS() + - -#define _TUPLE_ELEM_0(a, ...) a -#define _TUPLE_ELEM_1(a, b, ...) b -#define _TUPLE_ELEM_2(a, b, c, ...) c -#define _TUPLE_ELEM_3(a, b, c, d, ...) d -#define _TUPLE_ELEM_4(a, b, c, d, e, ...) e - -#define TUPLE_ELEM_0(T) EVAL(_TUPLE_ELEM_0 T) -#define TUPLE_ELEM_1(T) EVAL(_TUPLE_ELEM_1 T) -#define TUPLE_ELEM_2(T) EVAL(_TUPLE_ELEM_2 T) -#define TUPLE_ELEM_3(T) EVAL(_TUPLE_ELEM_3 T) -#define TUPLE_ELEM_4(T) EVAL(_TUPLE_ELEM_4 T) - -#define _TUPLE_FOLD_LEFT_0(i, T, op) (_TUPLE_ELEM_0 CAT(T,i)) op() -#define _TUPLE_FOLD_LEFT_1(i, T, op) (_TUPLE_ELEM_1 CAT(T,i)) op() -#define _TUPLE_FOLD_LEFT_2(i, T, op) (_TUPLE_ELEM_2 CAT(T,i)) op() -#define _TUPLE_FOLD_LEFT_3(i, T, op) (_TUPLE_ELEM_3 CAT(T,i)) op() -#define _TUPLE_FOLD_LEFT_4(i, T, op) (_TUPLE_ELEM_4 CAT(T,i)) op() - -#define TUPLE_FOLD_LEFT_0(len, T, op) EVAL(REPEAT(len, _TUPLE_FOLD_LEFT_0, T, op)) -#define TUPLE_FOLD_LEFT_1(len, T, op) EVAL(REPEAT(len, _TUPLE_FOLD_LEFT_1, T, op)) -#define TUPLE_FOLD_LEFT_2(len, T, op) EVAL(REPEAT(len, _TUPLE_FOLD_LEFT_2, T, op)) -#define TUPLE_FOLD_LEFT_3(len, T, op) EVAL(REPEAT(len, _TUPLE_FOLD_LEFT_3, T, op)) -#define TUPLE_FOLD_LEFT_4(len, T, op) EVAL(REPEAT(len, _TUPLE_FOLD_LEFT_4, T, op)) - -#endif diff --git a/sept/sept-secondary/src/sdram.c b/sept/sept-secondary/src/sdram.c deleted file mode 100644 index a4e494e15..000000000 --- a/sept/sept-secondary/src/sdram.c +++ /dev/null @@ -1,1673 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "i2c.h" -#include "mc.h" -#include "emc.h" -#include "pmc.h" -#include "timers.h" -#include "sysreg.h" -#include "fuse.h" -#include "max77620.h" -#include "sdram_params.h" -#include "car.h" - -#define CONFIG_SDRAM_COMPRESS - -#ifdef CONFIG_SDRAM_COMPRESS -#include "../../../fusee/common/lz.h" -#include "sdram_lz.inl" -#else -#include "sdram.inl" -#endif - -static void sdram_config_erista(const sdram_params_erista_t *params) { - volatile tegra_car_t *car = car_get_regs(); - volatile tegra_pmc_t *pmc = pmc_get_regs(); - - pmc->io_dpd3_req = (((4 * params->EmcPmcScratch1 >> 2) + 0x80000000) ^ 0xFFFF) & 0xC000FFFF; - udelay(params->PmcIoDpd3ReqWait); - uint32_t req = (4 * params->EmcPmcScratch2 >> 2) + 0x80000000; - pmc->io_dpd4_req = (req >> 16 << 16) ^ 0x3FFF0000; - udelay(params->PmcIoDpd4ReqWait); - pmc->io_dpd4_req = (req ^ 0xFFFF) & 0xC000FFFF; - udelay(params->PmcIoDpd4ReqWait); - pmc->weak_bias = 0; - udelay(1); - - car->pllm_misc1 = params->PllMSetupControl; - car->pllm_misc2 = 0; - car->pllm_base = ((params->PllMFeedbackDivider << 8) | params->PllMInputDivider | 0x40000000 | ((params->PllMPostDivider & 0xFFFF) << 20)); - - bool timeout = false; - uint32_t wait_end = get_time_us() + 300; - - while (!(car->pllm_base & 0x8000000) && !timeout) { - if (get_time_us() >= wait_end) - timeout = true; - } - - if (!timeout) { - udelay(10); - } - - car->clk_source_emc = (((params->McEmemArbMisc0 >> 11) & 0x10000) | (params->EmcClockSource & 0xFFFEFFFF)); - - if (params->EmcClockSourceDll) { - car->clk_source_emc_dll = params->EmcClockSourceDll; - } - if (params->ClearClk2Mc1) { - car->clk_enb_w_clr = 0x40000000; - } - - car->clk_enb_h_set = 0x2000001; - car->clk_enb_x_set = 0x4000; - car->rst_dev_h_clr = 0x2000001; - - MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_0) = params->EmcPmacroVttgenCtrl0; - MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_1) = params->EmcPmacroVttgenCtrl1; - MAKE_EMC_REG(EMC_PMACRO_VTTGEN_CTRL_2) = params->EmcPmacroVttgenCtrl2; - MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - udelay(1); - - MAKE_EMC_REG(EMC_DBG) = (params->EmcDbgWriteMux << 1) | params->EmcDbg; - - if (params->EmcBctSpare2) { - *(volatile uint32_t *)params->EmcBctSpare2 = params->EmcBctSpare3; - } - - MAKE_EMC_REG(EMC_FBIO_CFG7) = params->EmcFbioCfg7; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_0) = params->EmcCmdMappingCmd0_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_1) = params->EmcCmdMappingCmd0_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD0_2) = params->EmcCmdMappingCmd0_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_0) = params->EmcCmdMappingCmd1_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_1) = params->EmcCmdMappingCmd1_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD1_2) = params->EmcCmdMappingCmd1_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_0) = params->EmcCmdMappingCmd2_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_1) = params->EmcCmdMappingCmd2_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD2_2) = params->EmcCmdMappingCmd2_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_0) = params->EmcCmdMappingCmd3_0; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_1) = params->EmcCmdMappingCmd3_1; - MAKE_EMC_REG(EMC_CMD_MAPPING_CMD3_2) = params->EmcCmdMappingCmd3_2; - MAKE_EMC_REG(EMC_CMD_MAPPING_BYTE) = params->EmcCmdMappingByte; - MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_0) = params->EmcPmacroBrickMapping0; - MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_1) = params->EmcPmacroBrickMapping1; - MAKE_EMC_REG(EMC_PMACRO_BRICK_MAPPING_2) = params->EmcPmacroBrickMapping2; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->EmcPmacroBrickCtrlRfu1 & 0x1120112) | 0x1EED1EED); - MAKE_EMC_REG(EMC_CONFIG_SAMPLE_DELAY) = params->EmcConfigSampleDelay; - MAKE_EMC_REG(EMC_FBIO_CFG8) = params->EmcFbioCfg8; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE0) = params->EmcSwizzleRank0Byte0; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE1) = params->EmcSwizzleRank0Byte1; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE2) = params->EmcSwizzleRank0Byte2; - MAKE_EMC_REG(EMC_SWIZZLE_RANK0_BYTE3) = params->EmcSwizzleRank0Byte3; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE0) = params->EmcSwizzleRank1Byte0; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE1) = params->EmcSwizzleRank1Byte1; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE2) = params->EmcSwizzleRank1Byte2; - MAKE_EMC_REG(EMC_SWIZZLE_RANK1_BYTE3) = params->EmcSwizzleRank1Byte3; - - if (params->EmcBctSpare6) { - *(volatile uint32_t *)params->EmcBctSpare6 = params->EmcBctSpare7; - } - - MAKE_EMC_REG(EMC_XM2COMPPADCTRL) = params->EmcXm2CompPadCtrl; - MAKE_EMC_REG(EMC_XM2COMPPADCTRL2) = params->EmcXm2CompPadCtrl2; - MAKE_EMC_REG(EMC_XM2COMPPADCTRL3) = params->EmcXm2CompPadCtrl3; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG2) = params->EmcAutoCalConfig2; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG3) = params->EmcAutoCalConfig3; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG4) = params->EmcAutoCalConfig4; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG5) = params->EmcAutoCalConfig5; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG6) = params->EmcAutoCalConfig6; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG7) = params->EmcAutoCalConfig7; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG8) = params->EmcAutoCalConfig8; - MAKE_EMC_REG(EMC_PMACRO_RX_TERM) = params->EmcPmacroRxTerm; - MAKE_EMC_REG(EMC_PMACRO_DQ_TX_DRV) = params->EmcPmacroDqTxDrv; - MAKE_EMC_REG(EMC_PMACRO_CA_TX_DRV) = params->EmcPmacroCaTxDrv; - MAKE_EMC_REG(EMC_PMACRO_CMD_TX_DRV) = params->EmcPmacroCmdTxDrv; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->EmcPmacroAutocalCfgCommon; - MAKE_EMC_REG(EMC_AUTO_CAL_CHANNEL) = params->EmcAutoCalChannel; - MAKE_EMC_REG(EMC_PMACRO_ZCTRL) = params->EmcPmacroZctrl; - MAKE_EMC_REG(EMC_DLL_CFG_0) = params->EmcDllCfg0; - MAKE_EMC_REG(EMC_DLL_CFG_1) = params->EmcDllCfg1; - MAKE_EMC_REG(EMC_CFG_DIG_DLL_1) = params->EmcCfgDigDll_1; - MAKE_EMC_REG(EMC_DATA_BRLSHFT_0) = params->EmcDataBrlshft0; - MAKE_EMC_REG(EMC_DATA_BRLSHFT_1) = params->EmcDataBrlshft1; - MAKE_EMC_REG(EMC_DQS_BRLSHFT_0) = params->EmcDqsBrlshft0; - MAKE_EMC_REG(EMC_DQS_BRLSHFT_1) = params->EmcDqsBrlshft1; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_0) = params->EmcCmdBrlshft0; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_1) = params->EmcCmdBrlshft1; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_2) = params->EmcCmdBrlshft2; - MAKE_EMC_REG(EMC_CMD_BRLSHFT_3) = params->EmcCmdBrlshft3; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_0) = params->EmcQuseBrlshft0; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_1) = params->EmcQuseBrlshft1; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_2) = params->EmcQuseBrlshft2; - MAKE_EMC_REG(EMC_QUSE_BRLSHFT_3) = params->EmcQuseBrlshft3; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = ((params->EmcPmacroBrickCtrlRfu1 & 0x1BF01BF) | 0x1E401E40); - MAKE_EMC_REG(EMC_PMACRO_PAD_CFG_CTRL) = params->EmcPmacroPadCfgCtrl; - MAKE_EMC_REG(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->EmcPmacroCmdBrickCtrlFdpd; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = (params->EmcPmacroBrickCtrlRfu2 & 0xFF7FFF7F); - MAKE_EMC_REG(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->EmcPmacroDataBrickCtrlFdpd; - MAKE_EMC_REG(EMC_PMACRO_BG_BIAS_CTRL_0) = params->EmcPmacroBgBiasCtrl0; - MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->EmcPmacroDataPadRxCtrl; - MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->EmcPmacroCmdPadRxCtrl; - MAKE_EMC_REG(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->EmcPmacroDataPadTxCtrl; - MAKE_EMC_REG(EMC_PMACRO_DATA_RX_TERM_MODE) = params->EmcPmacroDataRxTermMode; - MAKE_EMC_REG(EMC_PMACRO_CMD_RX_TERM_MODE) = params->EmcPmacroCmdRxTermMode; - MAKE_EMC_REG(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->EmcPmacroCmdPadTxCtrl; - MAKE_EMC_REG(EMC_CFG_3) = params->EmcCfg3; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_0) = params->EmcPmacroTxPwrd0; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_1) = params->EmcPmacroTxPwrd1; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_2) = params->EmcPmacroTxPwrd2; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_3) = params->EmcPmacroTxPwrd3; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_4) = params->EmcPmacroTxPwrd4; - MAKE_EMC_REG(EMC_PMACRO_TX_PWRD_5) = params->EmcPmacroTxPwrd5; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->EmcPmacroTxSelClkSrc0; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->EmcPmacroTxSelClkSrc1; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->EmcPmacroTxSelClkSrc2; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->EmcPmacroTxSelClkSrc3; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->EmcPmacroTxSelClkSrc4; - MAKE_EMC_REG(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->EmcPmacroTxSelClkSrc5; - MAKE_EMC_REG(EMC_PMACRO_DDLL_BYPASS) = params->EmcPmacroDdllBypass; - MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_0) = params->EmcPmacroDdllPwrd0; - MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_1) = params->EmcPmacroDdllPwrd1; - MAKE_EMC_REG(EMC_PMACRO_DDLL_PWRD_2) = params->EmcPmacroDdllPwrd2; - MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_0) = params->EmcPmacroCmdCtrl0; - MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_1) = params->EmcPmacroCmdCtrl1; - MAKE_EMC_REG(EMC_PMACRO_CMD_CTRL_2) = params->EmcPmacroCmdCtrl2; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_0) = params->EmcPmacroIbVrefDq_0; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQ_1) = params->EmcPmacroIbVrefDq_1; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_0) = params->EmcPmacroIbVrefDqs_0; - MAKE_EMC_REG(EMC_PMACRO_IB_VREF_DQS_1) = params->EmcPmacroIbVrefDqs_1; - MAKE_EMC_REG(EMC_PMACRO_IB_RXRT) = params->EmcPmacroIbRxrt; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->EmcPmacroQuseDdllRank0_0; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->EmcPmacroQuseDdllRank0_1; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->EmcPmacroQuseDdllRank0_2; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_3) = params->EmcPmacroQuseDdllRank0_3; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_4) = params->EmcPmacroQuseDdllRank0_4; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK0_5) = params->EmcPmacroQuseDdllRank0_5; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_0) = params->EmcPmacroQuseDdllRank1_0; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_1) = params->EmcPmacroQuseDdllRank1_1; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_2) = params->EmcPmacroQuseDdllRank1_2; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->EmcPmacroQuseDdllRank1_3; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->EmcPmacroQuseDdllRank1_4; - MAKE_EMC_REG(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->EmcPmacroQuseDdllRank1_5; - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU1) = params->EmcPmacroBrickCtrlRfu1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->EmcPmacroObDdllLongDqRank0_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->EmcPmacroObDdllLongDqRank0_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->EmcPmacroObDdllLongDqRank0_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) = params->EmcPmacroObDdllLongDqRank0_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4) = params->EmcPmacroObDdllLongDqRank0_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) = params->EmcPmacroObDdllLongDqRank0_5; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0) = params->EmcPmacroObDdllLongDqRank1_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1) = params->EmcPmacroObDdllLongDqRank1_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) = params->EmcPmacroObDdllLongDqRank1_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) = params->EmcPmacroObDdllLongDqRank1_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4) = params->EmcPmacroObDdllLongDqRank1_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5) = params->EmcPmacroObDdllLongDqRank1_5; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0) = params->EmcPmacroObDdllLongDqsRank0_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1) = params->EmcPmacroObDdllLongDqsRank0_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2) = params->EmcPmacroObDdllLongDqsRank0_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3) = params->EmcPmacroObDdllLongDqsRank0_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4) = params->EmcPmacroObDdllLongDqsRank0_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5) = params->EmcPmacroObDdllLongDqsRank0_5; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0) = params->EmcPmacroObDdllLongDqsRank1_0; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1) = params->EmcPmacroObDdllLongDqsRank1_1; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2) = params->EmcPmacroObDdllLongDqsRank1_2; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3) = params->EmcPmacroObDdllLongDqsRank1_3; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4) = params->EmcPmacroObDdllLongDqsRank1_4; - MAKE_EMC_REG(EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5) = params->EmcPmacroObDdllLongDqsRank1_5; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0) = params->EmcPmacroIbDdllLongDqsRank0_0; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1) = params->EmcPmacroIbDdllLongDqsRank0_1; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) = params->EmcPmacroIbDdllLongDqsRank0_2; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) = params->EmcPmacroIbDdllLongDqsRank0_3; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0) = params->EmcPmacroIbDdllLongDqsRank1_0; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1) = params->EmcPmacroIbDdllLongDqsRank1_1; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->EmcPmacroIbDdllLongDqsRank1_2; - MAKE_EMC_REG(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->EmcPmacroIbDdllLongDqsRank1_3; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_0) = params->EmcPmacroDdllLongCmd_0; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_1) = params->EmcPmacroDdllLongCmd_1; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_2) = params->EmcPmacroDdllLongCmd_2; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_3) = params->EmcPmacroDdllLongCmd_3; - MAKE_EMC_REG(EMC_PMACRO_DDLL_LONG_CMD_4) = params->EmcPmacroDdllLongCmd_4; - MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->EmcPmacroDdllShortCmd_0; - MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->EmcPmacroDdllShortCmd_1; - MAKE_EMC_REG(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->EmcPmacroDdllShortCmd_2; - MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = ((params->EmcPmacroCommonPadTxCtrl & 1) | 0xE); - - if (params->EmcBctSpare4) { - *(volatile uint32_t *)params->EmcBctSpare4 = params->EmcBctSpare5; - } - - MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - - MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = params->McVideoProtectBom; - MAKE_MC_REG(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->McVideoProtectBomAdrHi; - MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = params->McVideoProtectSizeMb; - MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->McVideoProtectVprOverride; - MAKE_MC_REG(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->McVideoProtectVprOverride1; - MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->McVideoProtectGpuOverride0; - MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->McVideoProtectGpuOverride1; - MAKE_MC_REG(MC_EMEM_ADR_CFG) = params->McEmemAdrCfg; - MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV0) = params->McEmemAdrCfgDev0; - MAKE_MC_REG(MC_EMEM_ADR_CFG_DEV1) = params->McEmemAdrCfgDev1; - MAKE_MC_REG(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->McEmemAdrCfgChannelMask; - MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_0) = params->McEmemAdrCfgBankMask0; - MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_1) = params->McEmemAdrCfgBankMask1; - MAKE_MC_REG(MC_EMEM_ADR_CFG_BANK_MASK_2) = params->McEmemAdrCfgBankMask2; - MAKE_MC_REG(MC_EMEM_CFG) = params->McEmemCfg; - MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = params->McSecCarveoutBom; - MAKE_MC_REG(MC_SEC_CARVEOUT_ADR_HI) = params->McSecCarveoutAdrHi; - MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = params->McSecCarveoutSizeMb; - MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = params->McMtsCarveoutBom; - MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = params->McMtsCarveoutAdrHi; - MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = params->McMtsCarveoutSizeMb; - MAKE_MC_REG(MC_EMEM_ARB_CFG) = params->McEmemArbCfg; - MAKE_MC_REG(MC_EMEM_ARB_OUTSTANDING_REQ) = params->McEmemArbOutstandingReq; - MAKE_MC_REG(MC_EMEM_ARB_REFPB_HP_CTRL) = params->McEmemArbRefpbHpCtrl; - MAKE_MC_REG(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->McEmemArbRefpbBankCtrl; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RCD) = params->McEmemArbTimingRcd; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RP) = params->McEmemArbTimingRp; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RC) = params->McEmemArbTimingRc; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAS) = params->McEmemArbTimingRas; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_FAW) = params->McEmemArbTimingFaw; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RRD) = params->McEmemArbTimingRrd; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RAP2PRE) = params->McEmemArbTimingRap2Pre; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_WAP2PRE) = params->McEmemArbTimingWap2Pre; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2R) = params->McEmemArbTimingR2R; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2W) = params->McEmemArbTimingW2W; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_CCDMW) = params->McEmemArbTimingCcdmw; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_R2W) = params->McEmemArbTimingR2W; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_W2R) = params->McEmemArbTimingW2R; - MAKE_MC_REG(MC_EMEM_ARB_TIMING_RFCPB) = params->McEmemArbTimingRFCPB; - MAKE_MC_REG(MC_EMEM_ARB_DA_TURNS) = params->McEmemArbDaTurns; - MAKE_MC_REG(MC_EMEM_ARB_DA_COVERS) = params->McEmemArbDaCovers; - MAKE_MC_REG(MC_EMEM_ARB_MISC0) = params->McEmemArbMisc0; - MAKE_MC_REG(MC_EMEM_ARB_MISC1) = params->McEmemArbMisc1; - MAKE_MC_REG(MC_EMEM_ARB_MISC2) = params->McEmemArbMisc2; - MAKE_MC_REG(MC_EMEM_ARB_RING1_THROTTLE) = params->McEmemArbRing1Throttle; - MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE) = params->McEmemArbOverride; - MAKE_MC_REG(MC_EMEM_ARB_OVERRIDE_1) = params->McEmemArbOverride1; - MAKE_MC_REG(MC_EMEM_ARB_RSV) = params->McEmemArbRsv; - MAKE_MC_REG(MC_DA_CONFIG0) = params->McDaCfg0; - MAKE_MC_REG(MC_TIMING_CONTROL) = 1; - MAKE_MC_REG(MC_CLKEN_OVERRIDE) = params->McClkenOverride; - MAKE_MC_REG(MC_STAT_CONTROL) = params->McStatControl; - - MAKE_EMC_REG(EMC_ADR_CFG) = params->EmcAdrCfg; - MAKE_EMC_REG(EMC_CLKEN_OVERRIDE) = params->EmcClkenOverride; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_0) = params->EmcPmacroAutocalCfg0; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_1) = params->EmcPmacroAutocalCfg1; - MAKE_EMC_REG(EMC_PMACRO_AUTOCAL_CFG_2) = params->EmcPmacroAutocalCfg2; - MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_0) = params->EmcAutoCalVrefSel0; - MAKE_EMC_REG(EMC_AUTO_CAL_VREF_SEL_1) = params->EmcAutoCalVrefSel1; - MAKE_EMC_REG(EMC_AUTO_CAL_INTERVAL) = params->EmcAutoCalInterval; - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = params->EmcAutoCalConfig; - udelay(params->EmcAutoCalWait); - - if (params->EmcBctSpare8) { - *(volatile uint32_t *)params->EmcBctSpare8 = params->EmcBctSpare9; - } - - MAKE_EMC_REG(EMC_CFG_2) = params->EmcCfg2; - MAKE_EMC_REG(EMC_CFG_PIPE) = params->EmcCfgPipe; - MAKE_EMC_REG(EMC_CFG_PIPE_1) = params->EmcCfgPipe1; - MAKE_EMC_REG(EMC_CFG_PIPE_2) = params->EmcCfgPipe2; - MAKE_EMC_REG(EMC_CMDQ) = params->EmcCmdQ; - MAKE_EMC_REG(EMC_MC2EMCQ) = params->EmcMc2EmcQ; - MAKE_EMC_REG(EMC_MRS_WAIT_CNT) = params->EmcMrsWaitCnt; - MAKE_EMC_REG(EMC_MRS_WAIT_CNT2) = params->EmcMrsWaitCnt2; - MAKE_EMC_REG(EMC_FBIO_CFG5) = params->EmcFbioCfg5; - MAKE_EMC_REG(EMC_RC) = params->EmcRc; - MAKE_EMC_REG(EMC_RFC) = params->EmcRfc; - MAKE_EMC_REG(EMC_RFCPB) = params->EmcRfcPb; - MAKE_EMC_REG(EMC_REFCTRL2) = params->EmcRefctrl2; - MAKE_EMC_REG(EMC_RFC_SLR) = params->EmcRfcSlr; - MAKE_EMC_REG(EMC_RAS) = params->EmcRas; - MAKE_EMC_REG(EMC_RP) = params->EmcRp; - MAKE_EMC_REG(EMC_TPPD) = params->EmcTppd; - MAKE_EMC_REG(EMC_R2R) = params->EmcR2r; - MAKE_EMC_REG(EMC_W2W) = params->EmcW2w; - MAKE_EMC_REG(EMC_R2W) = params->EmcR2w; - MAKE_EMC_REG(EMC_W2R) = params->EmcW2r; - MAKE_EMC_REG(EMC_R2P) = params->EmcR2p; - MAKE_EMC_REG(EMC_W2P) = params->EmcW2p; - MAKE_EMC_REG(EMC_CCDMW) = params->EmcCcdmw; - MAKE_EMC_REG(EMC_RD_RCD) = params->EmcRdRcd; - MAKE_EMC_REG(EMC_WR_RCD) = params->EmcWrRcd; - MAKE_EMC_REG(EMC_RRD) = params->EmcRrd; - MAKE_EMC_REG(EMC_REXT) = params->EmcRext; - MAKE_EMC_REG(EMC_WEXT) = params->EmcWext; - MAKE_EMC_REG(EMC_WDV) = params->EmcWdv; - MAKE_EMC_REG(EMC_WDV_CHK) = params->EmcWdvChk; - MAKE_EMC_REG(EMC_WSV) = params->EmcWsv; - MAKE_EMC_REG(EMC_WEV) = params->EmcWev; - MAKE_EMC_REG(EMC_WDV_MASK) = params->EmcWdvMask; - MAKE_EMC_REG(EMC_WS_DURATION) = params->EmcWsDuration; - MAKE_EMC_REG(EMC_WE_DURATION) = params->EmcWeDuration; - MAKE_EMC_REG(EMC_QUSE) = params->EmcQUse; - MAKE_EMC_REG(EMC_QUSE_WIDTH) = params->EmcQuseWidth; - MAKE_EMC_REG(EMC_IBDLY) = params->EmcIbdly; - MAKE_EMC_REG(EMC_OBDLY) = params->EmcObdly; - MAKE_EMC_REG(EMC_EINPUT) = params->EmcEInput; - MAKE_EMC_REG(EMC_EINPUT_DURATION) = params->EmcEInputDuration; - MAKE_EMC_REG(EMC_PUTERM_EXTRA) = params->EmcPutermExtra; - MAKE_EMC_REG(EMC_PUTERM_WIDTH) = params->EmcPutermWidth; - MAKE_EMC_REG(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->EmcPmacroCommonPadTxCtrl; - MAKE_EMC_REG(EMC_DBG) = params->EmcDbg; - MAKE_EMC_REG(EMC_QRST) = params->EmcQRst; - MAKE_EMC_REG(EMC_ISSUE_QRST) = 0; - MAKE_EMC_REG(EMC_QSAFE) = params->EmcQSafe; - MAKE_EMC_REG(EMC_RDV) = params->EmcRdv; - MAKE_EMC_REG(EMC_RDV_MASK) = params->EmcRdvMask; - MAKE_EMC_REG(EMC_RDV_EARLY) = params->EmcRdvEarly; - MAKE_EMC_REG(EMC_RDV_EARLY_MASK) = params->EmcRdvEarlyMask; - MAKE_EMC_REG(EMC_QPOP) = params->EmcQpop; - MAKE_EMC_REG(EMC_REFRESH) = params->EmcRefresh; - MAKE_EMC_REG(EMC_BURST_REFRESH_NUM) = params->EmcBurstRefreshNum; - MAKE_EMC_REG(EMC_PRE_REFRESH_REQ_CNT) = params->EmcPreRefreshReqCnt; - MAKE_EMC_REG(EMC_PDEX2WR) = params->EmcPdEx2Wr; - MAKE_EMC_REG(EMC_PDEX2RD) = params->EmcPdEx2Rd; - MAKE_EMC_REG(EMC_PCHG2PDEN) = params->EmcPChg2Pden; - MAKE_EMC_REG(EMC_ACT2PDEN) = params->EmcAct2Pden; - MAKE_EMC_REG(EMC_AR2PDEN) = params->EmcAr2Pden; - MAKE_EMC_REG(EMC_RW2PDEN) = params->EmcRw2Pden; - MAKE_EMC_REG(EMC_CKE2PDEN) = params->EmcCke2Pden; - MAKE_EMC_REG(EMC_PDEX2CKE) = params->EmcPdex2Cke; - MAKE_EMC_REG(EMC_PDEX2MRR) = params->EmcPdex2Mrr; - MAKE_EMC_REG(EMC_TXSR) = params->EmcTxsr; - MAKE_EMC_REG(EMC_TXSRDLL) = params->EmcTxsrDll; - MAKE_EMC_REG(EMC_TCKE) = params->EmcTcke; - MAKE_EMC_REG(EMC_TCKESR) = params->EmcTckesr; - MAKE_EMC_REG(EMC_TPD) = params->EmcTpd; - MAKE_EMC_REG(EMC_TFAW) = params->EmcTfaw; - MAKE_EMC_REG(EMC_TRPAB) = params->EmcTrpab; - MAKE_EMC_REG(EMC_TCLKSTABLE) = params->EmcTClkStable; - MAKE_EMC_REG(EMC_TCLKSTOP) = params->EmcTClkStop; - MAKE_EMC_REG(EMC_TREFBW) = params->EmcTRefBw; - MAKE_EMC_REG(EMC_ODT_WRITE) = params->EmcOdtWrite; - MAKE_EMC_REG(EMC_CFG_DIG_DLL) = params->EmcCfgDigDll; - MAKE_EMC_REG(EMC_CFG_DIG_DLL_PERIOD) = params->EmcCfgDigDllPeriod; - MAKE_EMC_REG(EMC_FBIO_SPARE) = params->EmcFbioSpare & 0xFFFFFFFD; - MAKE_EMC_REG(EMC_CFG_RSV) = params->EmcCfgRsv; - MAKE_EMC_REG(EMC_PMC_SCRATCH1) = params->EmcPmcScratch1; - MAKE_EMC_REG(EMC_PMC_SCRATCH2) = params->EmcPmcScratch2; - MAKE_EMC_REG(EMC_PMC_SCRATCH3) = params->EmcPmcScratch3; - MAKE_EMC_REG(EMC_ACPD_CONTROL) = params->EmcAcpdControl; - MAKE_EMC_REG(EMC_TXDSRVTTGEN) = params->EmcTxdsrvttgen; - MAKE_EMC_REG(EMC_CFG) = (params->EmcCfg & 0xE) | 0x3C00000; - - if (params->BootRomPatchControl & 0x80000000) { - *(volatile uint32_t *)(4 * (params->BootRomPatchControl + 0x1C000000)) = params->BootRomPatchData; - MAKE_MC_REG(MC_TIMING_CONTROL) = 1; - } - - pmc->io_dpd3_req = (((4 * params->EmcPmcScratch1 >> 2) + 0x40000000) & 0xCFFF0000); - udelay(params->PmcIoDpd3ReqWait); - - if (!params->EmcAutoCalInterval) { - MAKE_EMC_REG(EMC_AUTO_CAL_CONFIG) = (params->EmcAutoCalConfig | 0x200); - } - - MAKE_EMC_REG(EMC_PMACRO_BRICK_CTRL_RFU2) = params->EmcPmacroBrickCtrlRfu2; - - if (params->EmcZcalWarmColdBootEnables & 1) { - if (params->MemoryType == NvBootMemoryType_Ddr3) { - MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = (8 * params->EmcZcalWaitCnt); - } else if (params->MemoryType == NvBootMemoryType_LpDdr4) { - MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->EmcZcalWaitCnt; - MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->EmcZcalMrwCmd; - } - } - - MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - udelay(params->EmcTimingControlWait); - - pmc->ddr_cntrl &= 0xFFF8007F; - udelay(params->PmcDdrCntrlWait); - - MAKE_EMC_REG(EMC_PIN) = (params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12); - udelay(params->EmcPinExtraWait + 200); - MAKE_EMC_REG(EMC_PIN) = ((params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12)) + 256; - - if (params->MemoryType == NvBootMemoryType_Ddr3) { - udelay(params->EmcPinExtraWait + 500); - } else if (params->MemoryType == NvBootMemoryType_LpDdr4) { - udelay(params->EmcPinExtraWait + 2000); - } - - MAKE_EMC_REG(EMC_PIN) = (((params->EmcPinGpioEn << 16) | (params->EmcPinGpio << 12)) + 0x101); - udelay(params->EmcPinProgramWait); - - if (params->MemoryType != NvBootMemoryType_LpDdr4) { - MAKE_EMC_REG(EMC_NOP) = (params->EmcDevSelect << 30) + 1; - if (params->MemoryType == NvBootMemoryType_LpDdr2) { - udelay(params->EmcPinExtraWait + 200); - } - } else { - if (params->EmcBctSpare10) { - *(volatile uint32_t *)params->EmcBctSpare10 = params->EmcBctSpare11; - } - - MAKE_EMC_REG(EMC_MRW2) = params->EmcMrw2; - MAKE_EMC_REG(EMC_MRW) = params->EmcMrw1; - MAKE_EMC_REG(EMC_MRW3) = params->EmcMrw3; - MAKE_EMC_REG(EMC_MRW4) = params->EmcMrw4; - MAKE_EMC_REG(EMC_MRW6) = params->EmcMrw6; - MAKE_EMC_REG(EMC_MRW14) = params->EmcMrw14; - MAKE_EMC_REG(EMC_MRW8) = params->EmcMrw8; - MAKE_EMC_REG(EMC_MRW12) = params->EmcMrw12; - MAKE_EMC_REG(EMC_MRW9) = params->EmcMrw9; - MAKE_EMC_REG(EMC_MRW13) = params->EmcMrw13; - - if (params->EmcZcalWarmColdBootEnables & 1) { - MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev0; - udelay(params->EmcZcalInitWait); - MAKE_EMC_REG(EMC_ZQ_CAL) = (params->EmcZcalInitDev0 ^ 3); - - if (!(params->EmcDevSelect & 2)) { - MAKE_EMC_REG(EMC_ZQ_CAL) = params->EmcZcalInitDev1; - udelay(params->EmcZcalInitWait); - MAKE_EMC_REG(EMC_ZQ_CAL) = (params->EmcZcalInitDev1 ^ 3); - } - } - } - - pmc->ddr_cfg = params->PmcDdrCfg; - if ((params->MemoryType == NvBootMemoryType_LpDdr2) - || (params->MemoryType == NvBootMemoryType_Ddr3) - || (params->MemoryType == NvBootMemoryType_LpDdr4)) { - MAKE_EMC_REG(EMC_ZCAL_INTERVAL) = params->EmcZcalInterval; - MAKE_EMC_REG(EMC_ZCAL_WAIT_CNT) = params->EmcZcalWaitCnt; - MAKE_EMC_REG(EMC_ZCAL_MRW_CMD) = params->EmcZcalMrwCmd; - } - - if (params->EmcBctSpare12) { - *(volatile uint32_t *)params->EmcBctSpare12 = params->EmcBctSpare13; - } - - MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - - if (params->EmcExtraRefreshNum) { - MAKE_EMC_REG(EMC_REF) = (((1 << params->EmcExtraRefreshNum << 8) - 0xFD) | (params->EmcPinGpio << 30)); - } - - MAKE_EMC_REG(EMC_REFCTRL) = (params->EmcDevSelect | 0x80000000); - MAKE_EMC_REG(EMC_DYN_SELF_REF_CONTROL) = params->EmcDynSelfRefControl; - MAKE_EMC_REG(EMC_CFG_UPDATE) = params->EmcCfgUpdate; - MAKE_EMC_REG(EMC_CFG) = params->EmcCfg; - MAKE_EMC_REG(EMC_FDPD_CTRL_DQ) = params->EmcFdpdCtrlDq; - MAKE_EMC_REG(EMC_FDPD_CTRL_CMD) = params->EmcFdpdCtrlCmd; - MAKE_EMC_REG(EMC_SEL_DPD_CTRL) = params->EmcSelDpdCtrl; - MAKE_EMC_REG(EMC_FBIO_SPARE) = (params->EmcFbioSpare | 2); - MAKE_EMC_REG(EMC_TIMING_CONTROL) = 1; - MAKE_EMC_REG(EMC_CFG_PIPE_CLK) = params->EmcCfgPipeClk; - MAKE_EMC_REG(EMC_FDPD_CTRL_CMD_NO_RAMP) = params->EmcFdpdCtrlCmdNoRamp; - - AHB_ARBITRATION_XBAR_CTRL_0 = ((AHB_ARBITRATION_XBAR_CTRL_0 & 0xFFFEFFFF) | ((params->AhbArbitrationXbarCtrlMemInitDone & 0xFFFF) << 16)); - - MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = params->McVideoProtectWriteAccess; - MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = params->McSecCarveoutProtectWriteAccess; - MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = params->McMtsCarveoutRegCtrl; - MAKE_MC_REG(MC_EMEM_CFG_ACCESS_CTRL) = 1; -} - -static const void *sdram_get_params_erista(uint32_t dram_id) { - uint32_t sdram_params_index = sdram_params_index_table_erista[dram_id]; -#ifdef CONFIG_SDRAM_COMPRESS - uint8_t *buf = (uint8_t *)0x40030000; - LZ_Uncompress(sdram_params_erista_lz, buf, sizeof(sdram_params_erista_lz)); - return (const void *)&buf[sizeof(sdram_params_erista_t) * sdram_params_index]; -#else - return sdram_params_erista[sdram_params_index]; -#endif -} - -static void sdram_init_erista(void) { - volatile tegra_pmc_t *pmc = pmc_get_regs(); - const sdram_params_erista_t *params = (const sdram_params_erista_t *)sdram_get_params_erista(fuse_get_dram_id()); - - /* Enable VddMemory. */ - uint8_t val = 5; - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1); - val = 40; /* 40 = (1000 * 1100 - 600000) / 12500 -> 1.1V */ - i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD1, &val, 1); - - pmc->vddp_sel = params->PmcVddpSel; - udelay(params->PmcVddpSelWait); - pmc->ddr_pwr = pmc->ddr_pwr; - pmc->no_iopower = params->PmcNoIoPower; - pmc->reg_short = params->PmcRegShort; - pmc->ddr_cntrl = params->PmcDdrCntrl; - - if (params->EmcBctSpare0) { - *(volatile uint32_t *)params->EmcBctSpare0 = params->EmcBctSpare1; - } - - sdram_config_erista(params); -} - -static void sdram_save_params_erista(const void *save_params) { - const sdram_params_erista_t *params = (const sdram_params_erista_t *)save_params; - volatile tegra_pmc_t *pmc = pmc_get_regs(); - -#define pack(src, src_bits, dst, dst_bits) { \ - uint32_t mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ - dst &= ~(mask << (0 ? dst_bits)); \ - dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ -} - -#define s(param, src_bits, pmcreg, dst_bits) \ - pack(params->param, src_bits, pmc->pmcreg, dst_bits) - -#define c(value, pmcreg, dst_bits) \ - pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) - -/* 32 bits version of s macro */ -#define s32(param, pmcreg) pmc->pmcreg = params->param - -/* 32 bits version c macro */ -#define c32(value, pmcreg) pmc->pmcreg = value - - /* [1.0.0-3.0.2] Patch carveout parameters. */ - /* - *(volatile uint32_t *)params->McGeneralizedCarveout1Bom = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1BomHi = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1Size128kb = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1Access0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1Access1 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1Access2 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1Access3 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1Access4 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1ForceInternalAccess0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1ForceInternalAccess1 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1ForceInternalAccess2 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1ForceInternalAccess3 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1ForceInternalAccess4 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout1Cfg0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout2Bom = 0x80020000; - *(volatile uint32_t *)params->McGeneralizedCarveout2BomHi = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout2Size128kb = 2; - *(volatile uint32_t *)params->McGeneralizedCarveout2Access0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout2Access1 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout2Access2 = 0x3000000; - *(volatile uint32_t *)params->McGeneralizedCarveout2Access3 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout2Access4 = 0x300; - *(volatile uint32_t *)params->McGeneralizedCarveout2ForceInternalAccess0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout2ForceInternalAccess1 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout2ForceInternalAccess2 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout2ForceInternalAccess3 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout2ForceInternalAccess4 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout2Cfg0 = 0x440167E; - *(volatile uint32_t *)params->McGeneralizedCarveout3Bom = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3BomHi = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3Size128kb = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3Access0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3Access1 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3Access2 = 0x3000000; - *(volatile uint32_t *)params->McGeneralizedCarveout3Access3 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3Access4 = 0x300; - *(volatile uint32_t *)params->McGeneralizedCarveout3ForceInternalAccess0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3ForceInternalAccess1 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3ForceInternalAccess2 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3ForceInternalAccess3 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3ForceInternalAccess4 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout3Cfg0 = 0x4401E7E; - *(volatile uint32_t *)params->McGeneralizedCarveout4Bom = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4BomHi = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4Size128kb = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4Access0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4Access1 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4Access2 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4Access3 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4Access4 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4ForceInternalAccess0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4ForceInternalAccess1 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4ForceInternalAccess2 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4ForceInternalAccess3 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4ForceInternalAccess4 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout4Cfg0 = 0x8F; - *(volatile uint32_t *)params->McGeneralizedCarveout5Bom = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5BomHi = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5Size128kb = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5Access0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5Access1 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5Access2 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5Access3 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5Access4 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5ForceInternalAccess0 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5ForceInternalAccess1 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5ForceInternalAccess2 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5ForceInternalAccess3 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5ForceInternalAccess4 = 0; - *(volatile uint32_t *)params->McGeneralizedCarveout5Cfg0 = 0x8F; - */ - - /* [4.0.0+] Patch carveout parameters. */ - *(volatile uint32_t *)¶ms->McGeneralizedCarveout1Cfg0 = 0; - *(volatile uint32_t *)¶ms->McGeneralizedCarveout2Cfg0 = 0; - *(volatile uint32_t *)¶ms->McGeneralizedCarveout3Cfg0 = 0; - *(volatile uint32_t *)¶ms->McGeneralizedCarveout4Cfg0 = 0; - *(volatile uint32_t *)¶ms->McGeneralizedCarveout5Cfg0 = 0; - - /* Patch SDRAM parameters. */ - uint32_t t0 = params->EmcSwizzleRank0Byte0 << 5 >> 29 > params->EmcSwizzleRank0Byte0 << 1 >> 29; - uint32_t t1 = (t0 & 0xFFFFFFEF) | ((params->EmcSwizzleRank1Byte0 << 5 >> 29 > params->EmcSwizzleRank1Byte0 << 1 >> 29) << 4); - uint32_t t2 = (t1 & 0xFFFFFFFD) | ((params->EmcSwizzleRank0Byte1 << 5 >> 29 > params->EmcSwizzleRank0Byte1 << 1 >> 29) << 1); - uint32_t t3 = (t2 & 0xFFFFFFDF) | ((params->EmcSwizzleRank1Byte1 << 5 >> 29 > params->EmcSwizzleRank1Byte1 << 1 >> 29) << 5); - uint32_t t4 = (t3 & 0xFFFFFFFB) | ((params->EmcSwizzleRank0Byte2 << 5 >> 29 > params->EmcSwizzleRank0Byte2 << 1 >> 29) << 2); - uint32_t t5 = (t4 & 0xFFFFFFBF) | ((params->EmcSwizzleRank1Byte2 << 5 >> 29 > params->EmcSwizzleRank1Byte2 << 1 >> 29) << 6); - uint32_t t6 = (t5 & 0xFFFFFFF7) | ((params->EmcSwizzleRank0Byte3 << 5 >> 29 > params->EmcSwizzleRank0Byte3 << 1 >> 29) << 3); - uint32_t t7 = (t6 & 0xFFFFFF7F) | ((params->EmcSwizzleRank1Byte3 << 5 >> 29 > params->EmcSwizzleRank1Byte3 << 1 >> 29) << 7); - *(volatile uint32_t *)¶ms->SwizzleRankByteEncode = t7; - *(volatile uint32_t *)¶ms->EmcBctSpare2 = 0x40000DD8; - *(volatile uint32_t *)¶ms->EmcBctSpare3 = t7; - - s(EmcClockSource, 7:0, scratch6, 15:8); - s(EmcClockSourceDll, 7:0, scratch6, 23:16); - s(EmcClockSource, 31:29, scratch6, 26:24); - s(EmcClockSourceDll, 31:29, scratch6, 29:27); - s(EmcClockSourceDll, 11:10, scratch6, 31:30); - s(ClkRstControllerPllmMisc2Override, 9:8, scratch7, 1:0); - s(ClkRstControllerPllmMisc2Override, 2:1, scratch7, 3:2); - s(EmcZqCalLpDdr4WarmBoot, 31:30, scratch7, 5:4); - s(EmcClockSource, 15:15, scratch7, 6:6); - s(EmcClockSource, 26:26, scratch7, 7:7); - s(EmcClockSource, 20:20, scratch7, 8:8); - s(EmcClockSource, 19:19, scratch7, 9:9); - s(ClkRstControllerPllmMisc2Override, 13:13, scratch7, 10:10); - s(ClkRstControllerPllmMisc2Override, 12:12, scratch7, 11:11); - s(ClkRstControllerPllmMisc2Override, 11:11, scratch7, 12:12); - s(ClkRstControllerPllmMisc2Override, 10:10, scratch7, 13:13); - s(ClkRstControllerPllmMisc2Override, 5:5, scratch7, 14:14); - s(ClkRstControllerPllmMisc2Override, 4:4, scratch7, 15:15); - s(ClkRstControllerPllmMisc2Override, 3:3, scratch7, 16:16); - s(ClkRstControllerPllmMisc2Override, 0:0, scratch7, 17:17); - s(EmcZqCalLpDdr4WarmBoot, 1:0, scratch7, 19:18); - s(EmcZqCalLpDdr4WarmBoot, 4:4, scratch7, 20:20); - s(EmcOdtWrite, 5:0, scratch7, 26:21); - s(EmcOdtWrite, 11:8, scratch7, 30:27); - s(EmcOdtWrite, 31:31, scratch7, 31:31); - s(EmcFdpdCtrlCmdNoRamp, 0:0, scratch13, 30:30); - s(EmcCfgPipeClk, 0:0, scratch13, 31:31); - s(McEmemArbMisc2, 0:0, scratch14, 30:30); - s(McDaCfg0, 0:0, scratch14, 31:31); - s(EmcQRst, 6:0, scratch15, 26:20); - s(EmcQRst, 20:16, scratch15, 31:27); - s(EmcPmacroCmdTxDrv, 5:0, scratch16, 25:20); - s(EmcPmacroCmdTxDrv, 13:8, scratch16, 31:26); - s(EmcPmacroAutocalCfg0, 2:0, scratch17, 22:20); - s(EmcPmacroAutocalCfg0, 10:8, scratch17, 25:23); - s(EmcPmacroAutocalCfg0, 18:16, scratch17, 28:26); - s(EmcPmacroAutocalCfg0, 26:24, scratch17, 31:29); - s(EmcPmacroAutocalCfg1, 2:0, scratch18, 22:20); - s(EmcPmacroAutocalCfg1, 10:8, scratch18, 25:23); - s(EmcPmacroAutocalCfg1, 18:16, scratch18, 28:26); - s(EmcPmacroAutocalCfg1, 26:24, scratch18, 31:29); - s(EmcPmacroAutocalCfg2, 2:0, scratch19, 22:20); - s(EmcPmacroAutocalCfg2, 10:8, scratch19, 25:23); - s(EmcPmacroAutocalCfg2, 18:16, scratch19, 28:26); - s(EmcPmacroAutocalCfg2, 26:24, scratch19, 31:29); - s32(EmcCfgRsv,scratch22); - s32(EmcAutoCalConfig, scratch23); - s32(EmcAutoCalVrefSel0, scratch24); - s32(EmcPmacroBrickCtrlRfu1, scratch25); - s32(EmcPmacroBrickCtrlRfu2, scratch26); - s32(EmcPmcScratch1, scratch27); - s32(EmcPmcScratch2, scratch28); - s32(EmcPmcScratch3, scratch29); - s32(McEmemArbDaTurns, scratch30); - s(EmcFbioSpare, 31:24, scratch58, 7:0); - s(EmcFbioSpare, 23:16, scratch58, 15:8); - s(EmcFbioSpare, 15:8, scratch58, 23:16); - s(EmcFbioSpare, 7:2, scratch58, 29:24); - s(EmcFbioSpare, 0:0, scratch58, 30:30); - s(EmcDllCfg0, 29:0, scratch59, 29:0); - s(EmcPmacroDdllBypass, 11:0, scratch60, 11:0); - s(EmcPmacroDdllBypass, 27:13, scratch60, 26:12); - s(EmcPmacroDdllBypass, 31:29, scratch60, 29:27); - s(McEmemArbMisc0, 14:0, scratch61, 14:0); - s(McEmemArbMisc0, 30:16, scratch61, 29:15); - s(EmcFdpdCtrlCmd, 16:0, scratch62, 16:0); - s(EmcFdpdCtrlCmd, 31:20, scratch62, 28:17); - s(EmcAutoCalConfig2, 27:0, scratch63, 27:0); - s(EmcBurstRefreshNum, 3:0, scratch63, 31:28); - s(EmcPmacroZctrl, 27:0, scratch64, 27:0); - s(EmcTppd, 3:0, scratch64, 31:28); - s(EmcCfgDigDll, 10:0, scratch65, 10:0); - s(EmcCfgDigDll, 25:12, scratch65, 24:11); - s(EmcCfgDigDll, 27:27, scratch65, 25:25); - s(EmcCfgDigDll, 31:30, scratch65, 27:26); - s(EmcR2r, 3:0, scratch65, 31:28); - s(EmcFdpdCtrlDq, 16:0, scratch66, 16:0); - s(EmcFdpdCtrlDq, 28:20, scratch66, 25:17); - s(EmcFdpdCtrlDq, 31:30, scratch66, 27:26); - s(EmcW2w, 3:0, scratch66, 31:28); - s(EmcPmacroTxPwrd4, 13:0, scratch67, 13:0); - s(EmcPmacroTxPwrd4, 29:16, scratch67, 27:14); - s(EmcPmacroCommonPadTxCtrl, 3:0, scratch67, 31:28); - s(EmcPmacroTxPwrd5, 13:0, scratch68, 13:0); - s(EmcPmacroTxPwrd5, 29:16, scratch68, 27:14); - s(EmcPmacroDdllPwrd0, 4:0, scratch69, 4:0); - s(EmcPmacroDdllPwrd0, 12:6, scratch69, 11:5); - s(EmcPmacroDdllPwrd0, 20:14, scratch69, 18:12); - s(EmcPmacroDdllPwrd0, 28:22, scratch69, 25:19); - s(EmcPmacroDdllPwrd0, 31:30, scratch69, 27:26); - s(EmcCfg, 4:4, scratch69, 31:31); - s(EmcPmacroDdllPwrd1, 4:0, scratch70, 4:0); - s(EmcPmacroDdllPwrd1, 12:6, scratch70, 11:5); - s(EmcPmacroDdllPwrd1, 20:14, scratch70, 18:12); - s(EmcPmacroDdllPwrd1, 28:22, scratch70, 25:19); - s(EmcPmacroDdllPwrd1, 31:30, scratch70, 27:26); - s(EmcCfg, 5:5, scratch70, 31:31); - s(EmcPmacroDdllPwrd2, 4:0, scratch71, 4:0); - s(EmcPmacroDdllPwrd2, 12:6, scratch71, 11:5); - s(EmcPmacroDdllPwrd2, 20:14, scratch71, 18:12); - s(EmcPmacroDdllPwrd2, 28:22, scratch71, 25:19); - s(EmcPmacroDdllPwrd2, 31:30, scratch71, 27:26); - s(EmcFbioCfg5, 23:20, scratch71, 31:28); - s(EmcPmacroIbVrefDq_0, 6:0, scratch72, 6:0); - s(EmcPmacroIbVrefDq_0, 14:8, scratch72, 13:7); - s(EmcPmacroIbVrefDq_0, 22:16, scratch72, 20:14); - s(EmcPmacroIbVrefDq_0, 30:24, scratch72, 27:21); - s(EmcFbioCfg5, 15:13, scratch72, 30:28); - s(EmcCfg, 6:6, scratch72, 31:31); - s(EmcPmacroIbVrefDq_1, 6:0, scratch73, 6:0); - s(EmcPmacroIbVrefDq_1, 14:8, scratch73, 13:7); - s(EmcPmacroIbVrefDq_1, 22:16, scratch73, 20:14); - s(EmcPmacroIbVrefDq_1, 30:24, scratch73, 27:21); - s(EmcCfg2, 5:3, scratch73, 30:28); - s(EmcCfg, 7:7, scratch73, 31:31); - s(EmcPmacroIbVrefDqs_0, 6:0, scratch74, 6:0); - s(EmcPmacroIbVrefDqs_0, 14:8, scratch74, 13:7); - s(EmcPmacroIbVrefDqs_0, 22:16, scratch74, 20:14); - s(EmcPmacroIbVrefDqs_0, 30:24, scratch74, 27:21); - s(EmcCfg, 17:16, scratch74, 29:28); - s(EmcFbioCfg5, 1:0, scratch74, 31:30); - s(EmcPmacroIbVrefDqs_1, 6:0, scratch75, 6:0); - s(EmcPmacroIbVrefDqs_1, 14:8, scratch75, 13:7); - s(EmcPmacroIbVrefDqs_1, 22:16, scratch75, 20:14); - s(EmcPmacroIbVrefDqs_1, 30:24, scratch75, 27:21); - s(EmcFbioCfg5, 3:2, scratch75, 29:28); - s(EmcCfg2, 27:26, scratch75, 31:30); - s(EmcPmacroDdllShortCmd_0, 6:0, scratch76, 6:0); - s(EmcPmacroDdllShortCmd_0, 14:8, scratch76, 13:7); - s(EmcPmacroDdllShortCmd_0, 22:16, scratch76, 20:14); - s(EmcPmacroDdllShortCmd_0, 30:24, scratch76, 27:21); - s(EmcPmacroCmdPadTxCtrl, 3:2, scratch76, 29:28); - s(EmcPmacroCmdPadTxCtrl, 7:6, scratch76, 31:30); - s(EmcPmacroDdllShortCmd_1, 6:0, scratch77, 6:0); - s(EmcPmacroDdllShortCmd_1, 14:8, scratch77, 13:7); - s(EmcPmacroDdllShortCmd_1, 22:16, scratch77, 20:14); - s(EmcPmacroDdllShortCmd_1, 30:24, scratch77, 27:21); - s(EmcPmacroCmdPadTxCtrl, 11:10, scratch77, 29:28); - s(EmcPmacroCmdPadTxCtrl, 15:14, scratch77, 31:30); - s(EmcAutoCalChannel, 5:0, scratch78, 5:0); - s(EmcAutoCalChannel, 11:8, scratch78, 9:6); - s(EmcAutoCalChannel, 27:16, scratch78, 21:10); - s(EmcAutoCalChannel, 31:29, scratch78, 24:22); - s(EmcConfigSampleDelay, 6:0, scratch78, 31:25); - s(EmcPmacroRxTerm, 5:0, scratch79, 5:0); - s(EmcPmacroRxTerm, 13:8, scratch79, 11:6); - s(EmcPmacroRxTerm, 21:16, scratch79, 17:12); - s(EmcPmacroRxTerm, 29:24, scratch79, 23:18); - s(EmcRc, 7:0, scratch79, 31:24); - s(EmcPmacroDqTxDrv, 5:0, scratch80, 5:0); - s(EmcPmacroDqTxDrv, 13:8, scratch80, 11:6); - s(EmcPmacroDqTxDrv, 21:16, scratch80, 17:12); - s(EmcPmacroDqTxDrv, 29:24, scratch80, 23:18); - s(EmcSelDpdCtrl, 5:2, scratch80, 27:24); - s(EmcSelDpdCtrl, 8:8, scratch80, 28:28); - s(EmcSelDpdCtrl, 18:16, scratch80, 31:29); - s(EmcPmacroCaTxDrv, 5:0, scratch81, 5:0); - s(EmcPmacroCaTxDrv, 13:8, scratch81, 11:6); - s(EmcPmacroCaTxDrv, 21:16, scratch81, 17:12); - s(EmcPmacroCaTxDrv, 29:24, scratch81, 23:18); - s(EmcObdly, 5:0, scratch81, 29:24); - s(EmcObdly, 29:28, scratch81, 31:30); - s(EmcZcalInterval, 23:10, scratch82, 13:0); - s(EmcZcalInterval, 9:0, scratch82, 23:14); - s(EmcPmacroCmdRxTermMode, 1:0, scratch82, 25:24); - s(EmcPmacroCmdRxTermMode, 5:4, scratch82, 27:26); - s(EmcPmacroCmdRxTermMode, 9:8, scratch82, 29:28); - s(EmcPmacroCmdRxTermMode, 13:12, scratch82, 31:30); - s(EmcDataBrlshft0, 23:0, scratch83, 23:0); - s(EmcPmacroDataRxTermMode, 1:0, scratch83, 25:24); - s(EmcPmacroDataRxTermMode, 5:4, scratch83, 27:26); - s(EmcPmacroDataRxTermMode, 9:8, scratch83, 29:28); - s(EmcPmacroDataRxTermMode, 13:12, scratch83, 31:30); - s(EmcDataBrlshft1, 23:0, scratch84, 23:0); - s(McEmemArbTimingRc, 7:0, scratch84, 31:24); - s(EmcDqsBrlshft0, 23:0, scratch85, 23:0); - s(McEmemArbRsv, 7:0, scratch85, 31:24); - s(EmcDqsBrlshft1, 23:0, scratch86, 23:0); - s(EmcCfgPipe2, 11:0, scratch87, 11:0); - s(EmcCfgPipe2, 27:16, scratch87, 23:12); - s(EmcCfgPipe1, 11:0, scratch88, 11:0); - s(EmcCfgPipe1, 27:16, scratch88, 23:12); - s(EmcPmacroCmdCtrl0, 5:0, scratch89, 5:0); - s(EmcPmacroCmdCtrl0, 13:8, scratch89, 11:6); - s(EmcPmacroCmdCtrl0, 21:16, scratch89, 17:12); - s(EmcPmacroCmdCtrl0, 29:24, scratch89, 23:18); - s(EmcPmacroCmdCtrl1, 5:0, scratch90, 5:0); - s(EmcPmacroCmdCtrl1, 13:8, scratch90, 11:6); - s(EmcPmacroCmdCtrl1, 21:16, scratch90, 17:12); - s(EmcPmacroCmdCtrl1, 29:24, scratch90, 23:18); - s(EmcRas, 6:0, scratch90, 30:24); - s(EmcCfg, 8:8, scratch90, 31:31); - s(EmcPmacroVttgenCtrl2, 23:0, scratch91, 23:0); - s(EmcW2p, 6:0, scratch91, 30:24); - s(EmcCfg, 9:9, scratch91, 31:31); - s(EmcPmacroCmdPadRxCtrl, 2:0, scratch92, 2:0); - s(EmcPmacroCmdPadRxCtrl, 5:4, scratch92, 4:3); - s(EmcPmacroCmdPadRxCtrl, 10:8, scratch92, 7:5); - s(EmcPmacroCmdPadRxCtrl, 22:12, scratch92, 18:8); - s(EmcPmacroCmdPadRxCtrl, 28:24, scratch92, 23:19); - s(EmcQSafe, 6:0, scratch92, 30:24); - s(EmcCfg, 18:18, scratch92, 31:31); - s(EmcPmacroDataPadRxCtrl, 2:0, scratch93, 2:0); - s(EmcPmacroDataPadRxCtrl, 5:4, scratch93, 4:3); - s(EmcPmacroDataPadRxCtrl, 10:8, scratch93, 7:5); - s(EmcPmacroDataPadRxCtrl, 22:12, scratch93, 18:8); - s(EmcPmacroDataPadRxCtrl, 28:24, scratch93, 23:19); - s(EmcRdv, 6:0, scratch93, 30:24); - s(EmcCfg, 21:21, scratch93, 31:31); - s(McEmemArbDaCovers, 23:0, scratch94, 23:0); - s(EmcRw2Pden, 6:0, scratch94, 30:24); - s(EmcCfg, 22:22, scratch94, 31:31); - s(EmcPmacroCmdCtrl2, 5:0, scratch95, 5:0); - s(EmcPmacroCmdCtrl2, 13:9, scratch95, 10:6); - s(EmcPmacroCmdCtrl2, 21:16, scratch95, 16:11); - s(EmcPmacroCmdCtrl2, 29:24, scratch95, 22:17); - s(EmcRfcPb, 8:0, scratch95, 31:23); - s(EmcPmacroQuseDdllRank0_0, 10:0, scratch96, 10:0); - s(EmcPmacroQuseDdllRank0_0, 26:16, scratch96, 21:11); - s(EmcCfgUpdate, 2:0, scratch96, 24:22); - s(EmcCfgUpdate, 10:8, scratch96, 27:25); - s(EmcCfgUpdate, 31:28, scratch96, 31:28); - s(EmcPmacroQuseDdllRank0_1, 10:0, scratch97, 10:0); - s(EmcPmacroQuseDdllRank0_1, 26:16, scratch97, 21:11); - s(EmcRfc, 9:0, scratch97, 31:22); - s(EmcPmacroQuseDdllRank0_2, 10:0, scratch98, 10:0); - s(EmcPmacroQuseDdllRank0_2, 26:16, scratch98, 21:11); - s(EmcTxsr, 9:0, scratch98, 31:22); - s(EmcPmacroQuseDdllRank0_3, 10:0, scratch99, 10:0); - s(EmcPmacroQuseDdllRank0_3, 26:16, scratch99, 21:11); - s(EmcMc2EmcQ, 2:0, scratch99, 24:22); - s(EmcMc2EmcQ, 10:8, scratch99, 27:25); - s(EmcMc2EmcQ, 27:24, scratch99, 31:28); - s(EmcPmacroQuseDdllRank0_4, 10:0, scratch100, 10:0); - s(EmcPmacroQuseDdllRank0_4, 26:16, scratch100, 21:11); - s(McEmemArbRing1Throttle, 4:0, scratch100, 26:22); - s(McEmemArbRing1Throttle, 20:16, scratch100, 31:27); - s(EmcPmacroQuseDdllRank0_5, 10:0, scratch101, 10:0); - s(EmcPmacroQuseDdllRank0_5, 26:16, scratch101, 21:11); - s(EmcPmacroQuseDdllRank1_0, 10:0, scratch102, 10:0); - s(EmcPmacroQuseDdllRank1_0, 26:16, scratch102, 21:11); - s(EmcAr2Pden, 8:0, scratch102, 30:22); - s(EmcCfg, 23:23, scratch102, 31:31); - s(EmcPmacroQuseDdllRank1_1, 10:0, scratch103, 10:0); - s(EmcPmacroQuseDdllRank1_1, 26:16, scratch103, 21:11); - s(EmcRfcSlr, 8:0, scratch103, 30:22); - s(EmcCfg, 24:24, scratch103, 31:31); - s(EmcPmacroQuseDdllRank1_2, 10:0, scratch104, 10:0); - s(EmcPmacroQuseDdllRank1_2, 26:16, scratch104, 21:11); - s(EmcIbdly, 6:0, scratch104, 28:22); - s(EmcIbdly, 29:28, scratch104, 30:29); - s(EmcCfg, 25:25, scratch104, 31:31); - s(EmcPmacroQuseDdllRank1_3, 10:0, scratch105, 10:0); - s(EmcPmacroQuseDdllRank1_3, 26:16, scratch105, 21:11); - s(McEmemArbTimingRFCPB, 8:0, scratch105, 30:22); - s(EmcCfg, 26:26, scratch105, 31:31); - s(EmcPmacroQuseDdllRank1_4, 10:0, scratch106, 10:0); - s(EmcPmacroQuseDdllRank1_4, 26:16, scratch106, 21:11); - s(EmcTfaw, 6:0, scratch106, 28:22); - s(EmcPmacroDataPadTxCtrl, 3:2, scratch106, 30:29); - s(EmcCfg, 28:28, scratch106, 31:31); - s(EmcPmacroQuseDdllRank1_5, 10:0, scratch107, 10:0); - s(EmcPmacroQuseDdllRank1_5, 26:16, scratch107, 21:11); - s(EmcTClkStable, 6:0, scratch107, 28:22); - s(EmcPmacroDataPadTxCtrl, 7:6, scratch107, 30:29); - s(EmcCfg, 29:29, scratch107, 31:31); - s(EmcPmacroObDdllLongDqRank0_0, 10:0, scratch108, 10:0); - s(EmcPmacroObDdllLongDqRank0_0, 26:16, scratch108, 21:11); - s(EmcPdex2Mrr, 6:0, scratch108, 28:22); - s(EmcPmacroDataPadTxCtrl, 11:10, scratch108, 30:29); - s(EmcCfg, 30:30, scratch108, 31:31); - s(EmcPmacroObDdllLongDqRank0_1, 10:0, scratch109, 10:0); - s(EmcPmacroObDdllLongDqRank0_1, 26:16, scratch109, 21:11); - s(EmcRdvMask, 6:0, scratch109, 28:22); - s(EmcPmacroDataPadTxCtrl, 15:14, scratch109, 30:29); - s(EmcCfg, 31:31, scratch109, 31:31); - s(EmcPmacroObDdllLongDqRank0_2, 10:0, scratch110, 10:0); - s(EmcPmacroObDdllLongDqRank0_2, 26:16, scratch110, 21:11); - s(EmcRdvEarlyMask, 6:0, scratch110, 28:22); - s(EmcFbioCfg5, 4:4, scratch110, 29:29); - s(EmcFbioCfg5, 8:8, scratch110, 30:30); - s(EmcFbioCfg5, 10:10, scratch110, 31:31); - s(EmcPmacroObDdllLongDqRank0_3, 10:0, scratch111, 10:0); - s(EmcPmacroObDdllLongDqRank0_3, 26:16, scratch111, 21:11); - s(EmcRdvEarly, 6:0, scratch111, 28:22); - s(EmcFbioCfg5, 12:12, scratch111, 29:29); - s(EmcFbioCfg5, 25:24, scratch111, 31:30); - s(EmcPmacroObDdllLongDqRank0_4, 10:0, scratch112, 10:0); - s(EmcPmacroObDdllLongDqRank0_4, 26:16, scratch112, 21:11); - s(EmcPmacroDdllShortCmd_2, 6:0, scratch112, 28:22); - s(EmcFbioCfg5, 28:26, scratch112, 31:29); - s(EmcPmacroObDdllLongDqRank0_5, 10:0, scratch113, 10:0); - s(EmcPmacroObDdllLongDqRank0_5, 26:16, scratch113, 21:11); - s(McEmemArbTimingRp, 6:0, scratch113, 28:22); - s(EmcFbioCfg5, 31:30, scratch113, 30:29); - s(EmcCfg2, 0:0, scratch113, 31:31); - s(EmcPmacroObDdllLongDqRank1_0, 10:0, scratch114, 10:0); - s(EmcPmacroObDdllLongDqRank1_0, 26:16, scratch114, 21:11); - s(McEmemArbTimingRas, 6:0, scratch114, 28:22); - s(EmcCfg2, 2:1, scratch114, 30:29); - s(EmcCfg2, 7:7, scratch114, 31:31); - s(EmcPmacroObDdllLongDqRank1_1, 10:0, scratch115, 10:0); - s(EmcPmacroObDdllLongDqRank1_1, 26:16, scratch115, 21:11); - s(McEmemArbTimingFaw, 6:0, scratch115, 28:22); - s(EmcCfg2, 11:10, scratch115, 30:29); - s(EmcCfg2, 14:14, scratch115, 31:31); - s(EmcPmacroObDdllLongDqRank1_2, 10:0, scratch123, 10:0); - s(EmcPmacroObDdllLongDqRank1_2, 26:16, scratch123, 21:11); - s(McEmemArbTimingRap2Pre, 6:0, scratch123, 28:22); - s(EmcCfg2, 16:15, scratch123, 30:29); - s(EmcCfg2, 20:20, scratch123, 31:31); - s(EmcPmacroObDdllLongDqRank1_3, 10:0, scratch124, 10:0); - s(EmcPmacroObDdllLongDqRank1_3, 26:16, scratch124, 21:11); - s(McEmemArbTimingWap2Pre, 6:0, scratch124, 28:22); - s(EmcCfg2, 24:22, scratch124, 31:29); - s(EmcPmacroObDdllLongDqRank1_4, 10:0, scratch125, 10:0); - s(EmcPmacroObDdllLongDqRank1_4, 26:16, scratch125, 21:11); - s(McEmemArbTimingR2W, 6:0, scratch125, 28:22); - s(EmcCfg2, 25:25, scratch125, 29:29); - s(EmcCfg2, 29:28, scratch125, 31:30); - s(EmcPmacroObDdllLongDqRank1_5, 10:0, scratch126, 10:0); - s(EmcPmacroObDdllLongDqRank1_5, 26:16, scratch126, 21:11); - s(McEmemArbTimingW2R, 6:0, scratch126, 28:22); - s(EmcCfg2, 31:30, scratch126, 30:29); - s(EmcCfgPipe, 0:0, scratch126, 31:31); - s(EmcPmacroObDdllLongDqsRank0_0, 10:0, scratch127, 10:0); - s(EmcPmacroObDdllLongDqsRank0_0, 26:16, scratch127, 21:11); - s(EmcRp, 5:0, scratch127, 27:22); - s(EmcCfgPipe, 4:1, scratch127, 31:28); - s(EmcPmacroObDdllLongDqsRank0_1, 10:0, scratch128, 10:0); - s(EmcPmacroObDdllLongDqsRank0_1, 26:16, scratch128, 21:11); - s(EmcR2w, 5:0, scratch128, 27:22); - s(EmcCfgPipe, 8:5, scratch128, 31:28); - s(EmcPmacroObDdllLongDqsRank0_2, 10:0, scratch129, 10:0); - s(EmcPmacroObDdllLongDqsRank0_2, 26:16, scratch129, 21:11); - s(EmcW2r, 5:0, scratch129, 27:22); - s(EmcCfgPipe, 11:9, scratch129, 30:28); - s(EmcCfgPipe, 16:16, scratch129, 31:31); - s(EmcPmacroObDdllLongDqsRank0_3, 10:0, scratch130, 10:0); - s(EmcPmacroObDdllLongDqsRank0_3, 26:16, scratch130, 21:11); - s(EmcR2p, 5:0, scratch130, 27:22); - s(EmcCfgPipe, 20:17, scratch130, 31:28); - s(EmcPmacroObDdllLongDqsRank0_4, 10:0, scratch131, 10:0); - s(EmcPmacroObDdllLongDqsRank0_4, 26:16, scratch131, 21:11); - s(EmcCcdmw, 5:0, scratch131, 27:22); - s(EmcCfgPipe, 24:21, scratch131, 31:28); - s(EmcPmacroObDdllLongDqsRank0_5, 10:0, scratch132, 10:0); - s(EmcPmacroObDdllLongDqsRank0_5, 26:16, scratch132, 21:11); - s(EmcRdRcd, 5:0, scratch132, 27:22); - s(EmcCfgPipe, 27:25, scratch132, 30:28); - s(EmcPmacroTxPwrd0, 0:0, scratch132, 31:31); - s(EmcPmacroObDdllLongDqsRank1_0, 10:0, scratch133, 10:0); - s(EmcPmacroObDdllLongDqsRank1_0, 26:16, scratch133, 21:11); - s(EmcWrRcd, 5:0, scratch133, 27:22); - s(EmcPmacroTxPwrd0, 4:1, scratch133, 31:28); - s(EmcPmacroObDdllLongDqsRank1_1, 10:0, scratch134, 10:0); - s(EmcPmacroObDdllLongDqsRank1_1, 26:16, scratch134, 21:11); - s(EmcWdv, 5:0, scratch134, 27:22); - s(EmcPmacroTxPwrd0, 8:5, scratch134, 31:28); - s(EmcPmacroObDdllLongDqsRank1_2, 10:0, scratch135, 10:0); - s(EmcPmacroObDdllLongDqsRank1_2, 26:16, scratch135, 21:11); - s(EmcQUse, 5:0, scratch135, 27:22); - s(EmcPmacroTxPwrd0, 12:9, scratch135, 31:28); - s(EmcPmacroObDdllLongDqsRank1_3, 10:0, scratch136, 10:0); - s(EmcPmacroObDdllLongDqsRank1_3, 26:16, scratch136, 21:11); - s(EmcPdEx2Wr, 5:0, scratch136, 27:22); - s(EmcPmacroTxPwrd0, 13:13, scratch136, 28:28); - s(EmcPmacroTxPwrd0, 18:16, scratch136, 31:29); - s(EmcPmacroObDdllLongDqsRank1_4, 10:0, scratch137, 10:0); - s(EmcPmacroObDdllLongDqsRank1_4, 26:16, scratch137, 21:11); - s(EmcPdEx2Rd, 5:0, scratch137, 27:22); - s(EmcPmacroTxPwrd0, 22:19, scratch137, 31:28); - s(EmcPmacroObDdllLongDqsRank1_5, 10:0, scratch138, 10:0); - s(EmcPmacroObDdllLongDqsRank1_5, 26:16, scratch138, 21:11); - s(EmcPdex2Cke, 5:0, scratch138, 27:22); - s(EmcPmacroTxPwrd0, 26:23, scratch138, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_0, 10:0, scratch139, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_0, 26:16, scratch139, 21:11); - s(EmcPChg2Pden, 5:0, scratch139, 27:22); - s(EmcPmacroTxPwrd0, 29:27, scratch139, 30:28); - s(EmcPmacroTxPwrd1, 0:0, scratch139, 31:31); - s(EmcPmacroIbDdllLongDqsRank0_1, 10:0, scratch140, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_1, 26:16, scratch140, 21:11); - s(EmcAct2Pden, 5:0, scratch140, 27:22); - s(EmcPmacroTxPwrd1, 4:1, scratch140, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_2, 10:0, scratch141, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_2, 26:16, scratch141, 21:11); - s(EmcCke2Pden, 5:0, scratch141, 27:22); - s(EmcPmacroTxPwrd1, 8:5, scratch141, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_3, 10:0, scratch142, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_3, 26:16, scratch142, 21:11); - s(EmcTcke, 5:0, scratch142, 27:22); - s(EmcPmacroTxPwrd1, 12:9, scratch142, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_0, 10:0, scratch143, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_0, 26:16, scratch143, 21:11); - s(EmcTrpab, 5:0, scratch143, 27:22); - s(EmcPmacroTxPwrd1, 13:13, scratch143, 28:28); - s(EmcPmacroTxPwrd1, 18:16, scratch143, 31:29); - s(EmcPmacroIbDdllLongDqsRank1_1, 10:0, scratch144, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_1, 26:16, scratch144, 21:11); - s(EmcClkenOverride, 3:1, scratch144, 24:22); - s(EmcClkenOverride, 8:6, scratch144, 27:25); - s(EmcPmacroTxPwrd1, 22:19, scratch144, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_2, 10:0, scratch145, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_2, 26:16, scratch145, 21:11); - s(EmcEInput, 5:0, scratch145, 27:22); - s(EmcPmacroTxPwrd1, 26:23, scratch145, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_3, 10:0, scratch146, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_3, 26:16, scratch146, 21:11); - s(EmcEInputDuration, 5:0, scratch146, 27:22); - s(EmcPmacroTxPwrd1, 29:27, scratch146, 30:28); - s(EmcPmacroTxPwrd2, 0:0, scratch146, 31:31); - s(EmcPmacroDdllLongCmd_0, 10:0, scratch147, 10:0); - s(EmcPmacroDdllLongCmd_0, 26:16, scratch147, 21:11); - s(EmcPutermExtra, 5:0, scratch147, 27:22); - s(EmcPmacroTxPwrd2, 4:1, scratch147, 31:28); - s(EmcPmacroDdllLongCmd_1, 10:0, scratch148, 10:0); - s(EmcPmacroDdllLongCmd_1, 26:16, scratch148, 21:11); - s(EmcTckesr, 5:0, scratch148, 27:22); - s(EmcPmacroTxPwrd2, 8:5, scratch148, 31:28); - s(EmcPmacroDdllLongCmd_2, 10:0, scratch149, 10:0); - s(EmcPmacroDdllLongCmd_2, 26:16, scratch149, 21:11); - s(EmcTpd, 5:0, scratch149, 27:22); - s(EmcPmacroTxPwrd2, 12:9, scratch149, 31:28); - s(EmcPmacroDdllLongCmd_3, 10:0, scratch150, 10:0); - s(EmcPmacroDdllLongCmd_3, 26:16, scratch150, 21:11); - s(EmcWdvMask, 5:0, scratch150, 27:22); - s(EmcPmacroTxPwrd2, 13:13, scratch150, 28:28); - s(EmcPmacroTxPwrd2, 18:16, scratch150, 31:29); - s(McEmemArbCfg, 8:0, scratch151, 8:0); - s(McEmemArbCfg, 20:16, scratch151, 13:9); - s(McEmemArbCfg, 31:24, scratch151, 21:14); - s(EmcWdvChk, 5:0, scratch151, 27:22); - s(EmcPmacroTxPwrd2, 22:19, scratch151, 31:28); - s(McEmemArbMisc1, 12:0, scratch152, 12:0); - s(McEmemArbMisc1, 25:21, scratch152, 17:13); - s(McEmemArbMisc1, 31:28, scratch152, 21:18); - s(EmcCmdBrlshft0, 5:0, scratch152, 27:22); - s(EmcPmacroTxPwrd2, 26:23, scratch152, 31:28); - s(EmcMrsWaitCnt2, 9:0, scratch153, 9:0); - s(EmcMrsWaitCnt2, 26:16, scratch153, 20:10); - s(EmcPmacroIbRxrt, 10:0, scratch153, 31:21); - s(EmcMrsWaitCnt, 9:0, scratch154, 9:0); - s(EmcMrsWaitCnt, 26:16, scratch154, 20:10); - s(EmcPmacroDdllLongCmd_4, 10:0, scratch154, 31:21); - s(EmcAutoCalInterval, 20:0, scratch155, 20:0); - s(McEmemArbOutstandingReq, 8:0, scratch155, 29:21); - s(McEmemArbOutstandingReq, 31:30, scratch155, 31:30); - s(McEmemArbRefpbHpCtrl, 6:0, scratch156, 6:0); - s(McEmemArbRefpbHpCtrl, 14:8, scratch156, 13:7); - s(McEmemArbRefpbHpCtrl, 22:16, scratch156, 20:14); - s(EmcCmdBrlshft1, 5:0, scratch156, 26:21); - s(EmcRrd, 4:0, scratch156, 31:27); - s(EmcQuseBrlshft0, 19:0, scratch157, 19:0); - s(EmcFbioCfg8, 27:16, scratch157, 31:20); - s(EmcQuseBrlshft1, 19:0, scratch158, 19:0); - s(EmcTxsrDll, 11:0, scratch158, 31:20); - s(EmcQuseBrlshft2, 19:0, scratch159, 19:0); - s(EmcTxdsrvttgen, 11:0, scratch159, 31:20); - s(EmcQuseBrlshft3, 19:0, scratch160, 19:0); - s(EmcPmacroVttgenCtrl0, 3:0, scratch160, 23:20); - s(EmcPmacroVttgenCtrl0, 11:8, scratch160, 27:24); - s(EmcPmacroVttgenCtrl0, 19:16, scratch160, 31:28); - s(EmcPmacroVttgenCtrl1, 19:0, scratch161, 19:0); - s(EmcCmdBrlshft2, 5:0, scratch161, 25:20); - s(EmcCmdBrlshft3, 5:0, scratch161, 31:26); - s(EmcAutoCalConfig3, 5:0, scratch162, 5:0); - s(EmcAutoCalConfig3, 13:8, scratch162, 11:6); - s(EmcAutoCalConfig3, 18:16, scratch162, 14:12); - s(EmcAutoCalConfig3, 22:20, scratch162, 17:15); - s(EmcTRefBw, 13:0, scratch162, 31:18); - s(EmcAutoCalConfig4, 5:0, scratch163, 5:0); - s(EmcAutoCalConfig4, 13:8, scratch163, 11:6); - s(EmcAutoCalConfig4, 18:16, scratch163, 14:12); - s(EmcAutoCalConfig4, 22:20, scratch163, 17:15); - s(EmcQpop, 6:0, scratch163, 24:18); - s(EmcQpop, 22:16, scratch163, 31:25); - s(EmcAutoCalConfig5, 5:0, scratch164, 5:0); - s(EmcAutoCalConfig5, 13:8, scratch164, 11:6); - s(EmcAutoCalConfig5, 18:16, scratch164, 14:12); - s(EmcAutoCalConfig5, 22:20, scratch164, 17:15); - s(EmcPmacroAutocalCfgCommon, 5:0, scratch164, 23:18); - s(EmcPmacroAutocalCfgCommon, 13:8, scratch164, 29:24); - s(EmcPmacroAutocalCfgCommon, 16:16, scratch164, 30:30); - s(EmcPmacroTxPwrd2, 27:27, scratch164, 31:31); - s(EmcAutoCalConfig6, 5:0, scratch165, 5:0); - s(EmcAutoCalConfig6, 13:8, scratch165, 11:6); - s(EmcAutoCalConfig6, 18:16, scratch165, 14:12); - s(EmcAutoCalConfig6, 22:20, scratch165, 17:15); - s(EmcWev, 5:0, scratch165, 23:18); - s(EmcWsv, 5:0, scratch165, 29:24); - s(EmcPmacroTxPwrd2, 29:28, scratch165, 31:30); - s(EmcAutoCalConfig7, 5:0, scratch166, 5:0); - s(EmcAutoCalConfig7, 13:8, scratch166, 11:6); - s(EmcAutoCalConfig7, 18:16, scratch166, 14:12); - s(EmcAutoCalConfig7, 22:20, scratch166, 17:15); - s(EmcCfg3, 2:0, scratch166, 20:18); - s(EmcCfg3, 6:4, scratch166, 23:21); - s(EmcQuseWidth, 3:0, scratch166, 27:24); - s(EmcQuseWidth, 29:28, scratch166, 29:28); - s(EmcPmacroTxPwrd3, 1:0, scratch166, 31:30); - s(EmcAutoCalConfig8, 5:0, scratch167, 5:0); - s(EmcAutoCalConfig8, 13:8, scratch167, 11:6); - s(EmcAutoCalConfig8, 18:16, scratch167, 14:12); - s(EmcAutoCalConfig8, 22:20, scratch167, 17:15); - s(EmcPmacroBgBiasCtrl0, 2:0, scratch167, 20:18); - s(EmcPmacroBgBiasCtrl0, 6:4, scratch167, 23:21); - s(McEmemArbTimingRcd, 5:0, scratch167, 29:24); - s(EmcPmacroTxPwrd3, 3:2, scratch167, 31:30); - s(EmcXm2CompPadCtrl2, 17:0, scratch168, 17:0); - s(McEmemArbTimingCcdmw, 5:0, scratch168, 23:18); - s(McEmemArbOverride, 27:27, scratch168, 24:24); - s(McEmemArbOverride, 26:26, scratch168, 25:25); - s(McEmemArbOverride, 16:16, scratch168, 26:26); - s(McEmemArbOverride, 10:10, scratch168, 27:27); - s(McEmemArbOverride, 4:4, scratch168, 28:28); - s(McEmemArbOverride, 3:3, scratch168, 29:29); - s(EmcPmacroTxPwrd3, 5:4, scratch168, 31:30); - s(EmcXm2CompPadCtrl3, 17:0, scratch169, 17:0); - s(EmcRext, 4:0, scratch169, 22:18); - s(EmcTClkStop, 4:0, scratch169, 27:23); - s(EmcPmacroTxPwrd3, 9:6, scratch169, 31:28); - s(EmcZcalWaitCnt, 10:0, scratch170, 10:0); - s(EmcZcalWaitCnt, 21:16, scratch170, 16:11); - s(EmcZcalWaitCnt, 31:31, scratch170, 17:17); - s(EmcWext, 4:0, scratch170, 22:18); - s(EmcRefctrl2, 0:0, scratch170, 23:23); - s(EmcRefctrl2, 26:24, scratch170, 26:24); - s(EmcRefctrl2, 31:31, scratch170, 27:27); - s(EmcPmacroTxPwrd3, 13:10, scratch170, 31:28); - s(EmcZcalMrwCmd, 7:0, scratch171, 7:0); - s(EmcZcalMrwCmd, 23:16, scratch171, 15:8); - s(EmcZcalMrwCmd, 31:30, scratch171, 17:16); - s(EmcWeDuration, 4:0, scratch171, 22:18); - s(EmcWsDuration, 4:0, scratch171, 27:23); - s(EmcPmacroTxPwrd3, 19:16, scratch171, 31:28); - s(EmcSwizzleRank0Byte0, 2:0, scratch172, 2:0); - s(EmcSwizzleRank0Byte0, 6:4, scratch172, 5:3); - s(EmcSwizzleRank0Byte0, 10:8, scratch172, 8:6); - s(EmcSwizzleRank0Byte0, 14:12, scratch172, 11:9); - s(EmcSwizzleRank0Byte0, 18:16, scratch172, 14:12); - s(EmcSwizzleRank0Byte0, 22:20, scratch172, 17:15); - s(EmcPutermWidth, 31:31, scratch172, 18:18); - s(EmcPutermWidth, 3:0, scratch172, 22:19); - s(McEmemArbTimingRrd, 4:0, scratch172, 27:23); - s(EmcPmacroTxPwrd3, 23:20, scratch172, 31:28); - s(EmcSwizzleRank0Byte1, 2:0, scratch173, 2:0); - s(EmcSwizzleRank0Byte1, 6:4, scratch173, 5:3); - s(EmcSwizzleRank0Byte1, 10:8, scratch173, 8:6); - s(EmcSwizzleRank0Byte1, 14:12, scratch173, 11:9); - s(EmcSwizzleRank0Byte1, 18:16, scratch173, 14:12); - s(EmcSwizzleRank0Byte1, 22:20, scratch173, 17:15); - s(McEmemArbTimingR2R, 4:0, scratch173, 22:18); - s(McEmemArbTimingW2W, 4:0, scratch173, 27:23); - s(EmcPmacroTxPwrd3, 27:24, scratch173, 31:28); - s(EmcSwizzleRank0Byte2, 2:0, scratch174, 2:0); - s(EmcSwizzleRank0Byte2, 6:4, scratch174, 5:3); - s(EmcSwizzleRank0Byte2, 10:8, scratch174, 8:6); - s(EmcSwizzleRank0Byte2, 14:12, scratch174, 11:9); - s(EmcSwizzleRank0Byte2, 18:16, scratch174, 14:12); - s(EmcSwizzleRank0Byte2, 22:20, scratch174, 17:15); - s(EmcPmacroTxPwrd3, 29:28, scratch174, 19:18); - s(EmcPmacroTxSelClkSrc0, 11:0, scratch174, 31:20); - s(EmcSwizzleRank0Byte3, 2:0, scratch175, 2:0); - s(EmcSwizzleRank0Byte3, 6:4, scratch175, 5:3); - s(EmcSwizzleRank0Byte3, 10:8, scratch175, 8:6); - s(EmcSwizzleRank0Byte3, 14:12, scratch175, 11:9); - s(EmcSwizzleRank0Byte3, 18:16, scratch175, 14:12); - s(EmcSwizzleRank0Byte3, 22:20, scratch175, 17:15); - s(EmcPmacroTxSelClkSrc0, 27:16, scratch175, 29:18); - s(EmcPmacroTxSelClkSrc1, 1:0, scratch175, 31:30); - s(EmcSwizzleRank1Byte0, 2:0, scratch176, 2:0); - s(EmcSwizzleRank1Byte0, 6:4, scratch176, 5:3); - s(EmcSwizzleRank1Byte0, 10:8, scratch176, 8:6); - s(EmcSwizzleRank1Byte0, 14:12, scratch176, 11:9); - s(EmcSwizzleRank1Byte0, 18:16, scratch176, 14:12); - s(EmcSwizzleRank1Byte0, 22:20, scratch176, 17:15); - s(EmcPmacroTxSelClkSrc1, 11:2, scratch176, 27:18); - s(EmcPmacroTxSelClkSrc1, 19:16, scratch176, 31:28); - s(EmcSwizzleRank1Byte1, 2:0, scratch177, 2:0); - s(EmcSwizzleRank1Byte1, 6:4, scratch177, 5:3); - s(EmcSwizzleRank1Byte1, 10:8, scratch177, 8:6); - s(EmcSwizzleRank1Byte1, 14:12, scratch177, 11:9); - s(EmcSwizzleRank1Byte1, 18:16, scratch177, 14:12); - s(EmcSwizzleRank1Byte1, 22:20, scratch177, 17:15); - s(EmcPmacroTxSelClkSrc1, 27:20, scratch177, 25:18); - s(EmcPmacroTxSelClkSrc3, 5:0, scratch177, 31:26); - s(EmcSwizzleRank1Byte2, 2:0, scratch178, 2:0); - s(EmcSwizzleRank1Byte2, 6:4, scratch178, 5:3); - s(EmcSwizzleRank1Byte2, 10:8, scratch178, 8:6); - s(EmcSwizzleRank1Byte2, 14:12, scratch178, 11:9); - s(EmcSwizzleRank1Byte2, 18:16, scratch178, 14:12); - s(EmcSwizzleRank1Byte2, 22:20, scratch178, 17:15); - s(EmcPmacroTxSelClkSrc3, 11:6, scratch178, 23:18); - s(EmcPmacroTxSelClkSrc3, 23:16, scratch178, 31:24); - s(EmcSwizzleRank1Byte3, 2:0, scratch179, 2:0); - s(EmcSwizzleRank1Byte3, 6:4, scratch179, 5:3); - s(EmcSwizzleRank1Byte3, 10:8, scratch179, 8:6); - s(EmcSwizzleRank1Byte3, 14:12, scratch179, 11:9); - s(EmcSwizzleRank1Byte3, 18:16, scratch179, 14:12); - s(EmcSwizzleRank1Byte3, 22:20, scratch179, 17:15); - s(EmcPmacroTxSelClkSrc3, 27:24, scratch179, 21:18); - s(EmcPmacroTxSelClkSrc2, 9:0, scratch179, 31:22); - s(EmcPmacroCmdBrickCtrlFdpd, 17:0, scratch180, 17:0); - s(EmcPmacroTxSelClkSrc2, 11:10, scratch180, 19:18); - s(EmcPmacroTxSelClkSrc2, 27:16, scratch180, 31:20); - s(EmcPmacroDataBrickCtrlFdpd, 17:0, scratch181, 17:0); - s(EmcPmacroTxSelClkSrc4, 11:0, scratch181, 29:18); - s(EmcPmacroTxSelClkSrc4, 17:16, scratch181, 31:30); - s(EmcFbioCfg7, 16:0, scratch182, 16:0); - s(McEmemArbRefpbBankCtrl, 6:0, scratch182, 23:17); - s(McEmemArbRefpbBankCtrl, 14:8, scratch182, 30:24); - s(McEmemArbRefpbBankCtrl, 31:31, scratch182, 31:31); - s(EmcDynSelfRefControl, 15:0, scratch183, 15:0); - s(EmcDynSelfRefControl, 31:31, scratch183, 16:16); - s(EmcPmacroTxSelClkSrc4, 27:18, scratch183, 26:17); - s(EmcPmacroTxSelClkSrc5, 4:0, scratch183, 31:27); - s(EmcDllCfg1, 16:0, scratch184, 16:0); - s(EmcPmacroTxSelClkSrc5, 11:5, scratch184, 23:17); - s(EmcPmacroTxSelClkSrc5, 23:16, scratch184, 31:24); - s(EmcPmacroPadCfgCtrl, 1:0, scratch185, 1:0); - s(EmcPmacroPadCfgCtrl, 6:5, scratch185, 3:2); - s(EmcPmacroPadCfgCtrl, 11:9, scratch185, 6:4); - s(EmcPmacroPadCfgCtrl, 13:13, scratch185, 7:7); - s(EmcPmacroPadCfgCtrl, 17:16, scratch185, 9:8); - s(EmcPmacroPadCfgCtrl, 21:20, scratch185, 11:10); - s(EmcPmacroPadCfgCtrl, 25:24, scratch185, 13:12); - s(EmcPmacroPadCfgCtrl, 30:28, scratch185, 16:14); - s(EmcPmacroTxSelClkSrc5, 27:24, scratch185, 20:17); - s(EmcPmacroCmdPadTxCtrl, 1:0, scratch185, 22:21); - s(EmcPmacroCmdPadTxCtrl, 5:4, scratch185, 24:23); - s(EmcPmacroCmdPadTxCtrl, 9:8, scratch185, 26:25); - s(EmcPmacroCmdPadTxCtrl, 13:12, scratch185, 28:27); - s(EmcPmacroCmdPadTxCtrl, 16:16, scratch185, 29:29); - s(EmcPmacroCmdPadTxCtrl, 21:20, scratch185, 31:30); - s(EmcRefresh, 15:0, scratch186, 15:0); - s(EmcCmdQ, 4:0, scratch186, 20:16); - s(EmcCmdQ, 10:8, scratch186, 23:21); - s(EmcCmdQ, 14:12, scratch186, 26:24); - s(EmcCmdQ, 28:24, scratch186, 31:27); - s(EmcAcpdControl, 15:0, scratch187, 15:0); - s(EmcAutoCalVrefSel1, 15:0, scratch187, 31:16); - s(EmcXm2CompPadCtrl, 1:0, scratch188, 1:0); - s(EmcXm2CompPadCtrl, 6:3, scratch188, 5:2); - s(EmcXm2CompPadCtrl, 9:9, scratch188, 6:6); - s(EmcXm2CompPadCtrl, 19:11, scratch188, 15:7); - s(EmcCfgDigDllPeriod, 15:0, scratch188, 31:16); - s(EmcCfgDigDll_1, 15:0, scratch189, 15:0); - s(EmcPreRefreshReqCnt, 15:0, scratch189, 31:16); - s(EmcPmacroCmdPadTxCtrl, 27:24, scratch190, 19:16); - s(EmcPmacroDataPadTxCtrl, 1:0, scratch190, 21:20); - s(EmcPmacroDataPadTxCtrl, 5:4, scratch190, 23:22); - s(EmcPmacroDataPadTxCtrl, 9:8, scratch190, 25:24); - s(EmcPmacroDataPadTxCtrl, 13:12, scratch190, 27:26); - s(EmcPmacroDataPadTxCtrl, 16:16, scratch190, 28:28); - s(EmcPmacroDataPadTxCtrl, 21:20, scratch190, 30:29); - s(EmcPmacroDataPadTxCtrl, 24:24, scratch190, 31:31); - s(EmcPmacroDataPadTxCtrl, 27:25, scratch191, 2:0); - - s(EmcPinGpio, 1:0, scratch8, 31:30); - s(EmcPinGpioEn, 1:0, scratch9, 31:30); - s(EmcDevSelect, 1:0, scratch10, 31:30); - s(EmcZcalWarmColdBootEnables, 1:0, scratch11, 31:30); - s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch12, 31:30); - s32(EmcBctSpare13, scratch31); - s32(EmcBctSpare12, scratch32); - s32(EmcBctSpare7, scratch33); - s32(EmcBctSpare6, scratch40); - s32(EmcBctSpare5, scratch42); - s32(EmcBctSpare4, scratch44); - s32(EmcBctSpare3, scratch45); - s32(EmcBctSpare2, scratch46); - s32(EmcBctSpare1, scratch47); - s32(EmcBctSpare0, scratch48); - s32(EmcBctSpare9, scratch50); - s32(EmcBctSpare8, scratch51); - s32(BootRomPatchData, scratch56); - s32(BootRomPatchControl, scratch57); - s(McClkenOverrideAllWarmBoot, 0:0, scratch58, 31:31); - s(EmcClkenOverrideAllWarmBoot, 0:0, scratch59, 30:30); - s(EmcMrsWarmBootEnable, 0:0, scratch59, 31:31); - s(ClearClk2Mc1, 0:0, scratch60, 30:30); - s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch60, 31:31); - s(ClkRstControllerPllmMisc2OverrideEnable, 0:0, scratch61, 30:30); - s(EmcDbgWriteMux, 0:0, scratch61, 31:31); - s(EmcExtraRefreshNum, 2:0, scratch62, 31:29); - s(PmcIoDpd3ReqWait, 2:0, scratch68, 30:28); - s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch68, 31:31); - s(MemoryType, 2:0, scratch69, 30:28); - s(PmcIoDpd4ReqWait, 2:0, scratch70, 30:28); - s(EmcTimingControlWait, 7:0, scratch86, 31:24); - s(EmcZcalWarmBootWait, 7:0, scratch87, 31:24); - s(WarmBootWait, 7:0, scratch88, 31:24); - s(EmcPinProgramWait, 7:0, scratch89, 31:24); - s(EmcAutoCalWait, 9:0, scratch101, 31:22); - s(SwizzleRankByteEncode, 15:0, scratch190, 15:0); - - switch (params->MemoryType) { - case NvBootMemoryType_LpDdr2: - case NvBootMemoryType_LpDdr4: - s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); - s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); - s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); - s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24); - s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0); - s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); - s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); - s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); - s(EmcMrw6, 27:0, scratch8, 27:0); - s(EmcMrw6, 31:30, scratch8, 29:28); - s(EmcMrw8, 27:0, scratch9, 27:0); - s(EmcMrw8, 31:30, scratch9, 29:28); - s(EmcMrw9, 27:0, scratch10, 27:0); - s(EmcMrw9, 31:30, scratch10, 29:28); - s(EmcMrw10, 27:0, scratch11, 27:0); - s(EmcMrw10, 31:30, scratch11, 29:28); - s(EmcMrw12, 27:0, scratch12, 27:0); - s(EmcMrw12, 31:30, scratch12, 29:28); - s(EmcMrw13, 27:0, scratch13, 27:0); - s(EmcMrw13, 31:30, scratch13, 29:28); - s(EmcMrw14, 27:0, scratch14, 27:0); - s(EmcMrw14, 31:30, scratch14, 29:28); - s(EmcMrw1, 7:0, scratch15, 7:0); - s(EmcMrw1, 23:16, scratch15, 15:8); - s(EmcMrw1, 27:26, scratch15, 17:16); - s(EmcMrw1, 31:30, scratch15, 19:18); - s(EmcWarmBootMrwExtra, 7:0, scratch16, 7:0); - s(EmcWarmBootMrwExtra, 23:16, scratch16, 15:8); - s(EmcWarmBootMrwExtra, 27:26, scratch16, 17:16); - s(EmcWarmBootMrwExtra, 31:30, scratch16, 19:18); - s(EmcMrw2, 7:0, scratch17, 7:0); - s(EmcMrw2, 23:16, scratch17, 15:8); - s(EmcMrw2, 27:26, scratch17, 17:16); - s(EmcMrw2, 31:30, scratch17, 19:18); - s(EmcMrw3, 7:0, scratch18, 7:0); - s(EmcMrw3, 23:16, scratch18, 15:8); - s(EmcMrw3, 27:26, scratch18, 17:16); - s(EmcMrw3, 31:30, scratch18, 19:18); - s(EmcMrw4, 7:0, scratch19, 7:0); - s(EmcMrw4, 23:16, scratch19, 15:8); - s(EmcMrw4, 27:26, scratch19, 17:16); - s(EmcMrw4, 31:30, scratch19, 19:18); - break; - case NvBootMemoryType_Ddr3: - s(EmcMrs, 13:0, scratch5, 13:0); - s(EmcEmrs, 13:0, scratch5, 27:14); - s(EmcMrs, 21:20, scratch5, 29:28); - s(EmcMrs, 31:30, scratch5, 31:30); - s(EmcEmrs2, 13:0, scratch8, 13:0); - s(EmcEmrs3, 13:0, scratch8, 27:14); - s(EmcEmrs, 21:20, scratch8, 29:28); - s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); - s(EmcEmrs, 31:30, scratch9, 15:14); - s(EmcEmrs2, 21:20, scratch9, 17:16); - s(EmcEmrs2, 31:30, scratch9, 19:18); - s(EmcEmrs3, 21:20, scratch9, 21:20); - s(EmcEmrs3, 31:30, scratch9, 23:22); - s(EmcWarmBootMrsExtra, 31:30, scratch9, 25:24); - s(EmcWarmBootMrsExtra, 21:20, scratch9, 27:26); - s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 29:28); - s(EmcMrs, 27:26, scratch10, 1:0); - s(EmcEmrs, 27:26, scratch10, 3:2); - s(EmcEmrs2, 27:26, scratch10, 5:4); - s(EmcEmrs3, 27:26, scratch10, 7:6); - s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8); - s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); - s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); - s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); - break; - default: break; - } - - s32(EmcCmdMappingByte, secure_scratch8); - s32(EmcPmacroBrickMapping0, secure_scratch9); - s32(EmcPmacroBrickMapping1, secure_scratch10); - s32(EmcPmacroBrickMapping2, secure_scratch11); - s32(McVideoProtectGpuOverride0, secure_scratch12); - s(EmcCmdMappingCmd0_0, 6:0, secure_scratch13, 6:0); - s(EmcCmdMappingCmd0_0, 14:8, secure_scratch13, 13:7); - s(EmcCmdMappingCmd0_0, 22:16, secure_scratch13, 20:14); - s(EmcCmdMappingCmd0_0, 30:24, secure_scratch13, 27:21); - s(McVideoProtectBomAdrHi, 1:0, secure_scratch13, 29:28); - s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 31:30); - s(EmcCmdMappingCmd0_1, 6:0, secure_scratch14, 6:0); - s(EmcCmdMappingCmd0_1, 14:8, secure_scratch14, 13:7); - s(EmcCmdMappingCmd0_1, 22:16, secure_scratch14, 20:14); - s(EmcCmdMappingCmd0_1, 30:24, secure_scratch14, 27:21); - s(McSecCarveoutAdrHi, 1:0, secure_scratch14, 29:28); - s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 31:30); - s(EmcCmdMappingCmd1_0, 6:0, secure_scratch15, 6:0); - s(EmcCmdMappingCmd1_0, 14:8, secure_scratch15, 13:7); - s(EmcCmdMappingCmd1_0, 22:16, secure_scratch15, 20:14); - s(EmcCmdMappingCmd1_0, 30:24, secure_scratch15, 27:21); - s(McGeneralizedCarveout5BomHi, 1:0, secure_scratch15, 29:28); - s(McGeneralizedCarveout3BomHi, 1:0, secure_scratch15, 31:30); - s(EmcCmdMappingCmd1_1, 6:0, secure_scratch16, 6:0); - s(EmcCmdMappingCmd1_1, 14:8, secure_scratch16, 13:7); - s(EmcCmdMappingCmd1_1, 22:16, secure_scratch16, 20:14); - s(EmcCmdMappingCmd1_1, 30:24, secure_scratch16, 27:21); - s(McGeneralizedCarveout2BomHi, 1:0, secure_scratch16, 29:28); - s(McGeneralizedCarveout4BomHi, 1:0, secure_scratch16, 31:30); - s(EmcCmdMappingCmd2_0, 6:0, secure_scratch17, 6:0); - s(EmcCmdMappingCmd2_0, 14:8, secure_scratch17, 13:7); - s(EmcCmdMappingCmd2_0, 22:16, secure_scratch17, 20:14); - s(EmcCmdMappingCmd2_0, 30:24, secure_scratch17, 27:21); - s(McGeneralizedCarveout1BomHi, 1:0, secure_scratch17, 29:28); - s(EmcAdrCfg, 0:0, secure_scratch17, 30:30); - s(EmcFbioSpare, 1:1, secure_scratch17, 31:31); - s(EmcCmdMappingCmd2_1, 6:0, secure_scratch18, 6:0); - s(EmcCmdMappingCmd2_1, 14:8, secure_scratch18, 13:7); - s(EmcCmdMappingCmd2_1, 22:16, secure_scratch18, 20:14); - s(EmcCmdMappingCmd2_1, 30:24, secure_scratch18, 27:21); - s(EmcFbioCfg8, 15:15, secure_scratch18, 28:28); - s(McEmemAdrCfg, 0:0, secure_scratch18, 29:29); - s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch18, 30:30); - s(McMtsCarveoutRegCtrl, 0:0, secure_scratch18, 31:31); - s(EmcCmdMappingCmd3_0, 6:0, secure_scratch19, 6:0); - s(EmcCmdMappingCmd3_0, 14:8, secure_scratch19, 13:7); - s(EmcCmdMappingCmd3_0, 22:16, secure_scratch19, 20:14); - s(EmcCmdMappingCmd3_0, 30:24, secure_scratch19, 27:21); - s(McGeneralizedCarveout2Cfg0, 6:3, secure_scratch19, 31:28); - s(EmcCmdMappingCmd3_1, 6:0, secure_scratch20, 6:0); - s(EmcCmdMappingCmd3_1, 14:8, secure_scratch20, 13:7); - s(EmcCmdMappingCmd3_1, 22:16, secure_scratch20, 20:14); - s(EmcCmdMappingCmd3_1, 30:24, secure_scratch20, 27:21); - s(McGeneralizedCarveout2Cfg0, 10:7, secure_scratch20, 31:28); - s(McGeneralizedCarveout4Cfg0, 26:0, secure_scratch39, 26:0); - s(McGeneralizedCarveout2Cfg0, 17:14, secure_scratch39, 30:27); - s(McVideoProtectVprOverride, 0:0, secure_scratch39, 31:31); - s(McGeneralizedCarveout5Cfg0, 26:0, secure_scratch40, 26:0); - s(McGeneralizedCarveout2Cfg0, 21:18, secure_scratch40, 30:27); - s(McVideoProtectVprOverride, 1:1, secure_scratch40, 31:31); - s(EmcCmdMappingCmd0_2, 6:0, secure_scratch41, 6:0); - s(EmcCmdMappingCmd0_2, 14:8, secure_scratch41, 13:7); - s(EmcCmdMappingCmd0_2, 22:16, secure_scratch41, 20:14); - s(EmcCmdMappingCmd0_2, 27:24, secure_scratch41, 24:21); - s(McGeneralizedCarveout1Cfg0, 6:3, secure_scratch41, 28:25); - s(McGeneralizedCarveout2Cfg0, 13:11, secure_scratch41, 31:29); - s(EmcCmdMappingCmd1_2, 6:0, secure_scratch42, 6:0); - s(EmcCmdMappingCmd1_2, 14:8, secure_scratch42, 13:7); - s(EmcCmdMappingCmd1_2, 22:16, secure_scratch42, 20:14); - s(EmcCmdMappingCmd1_2, 27:24, secure_scratch42, 24:21); - s(McGeneralizedCarveout1Cfg0, 13:7, secure_scratch42, 31:25); - s(EmcCmdMappingCmd2_2, 6:0, secure_scratch43, 6:0); - s(EmcCmdMappingCmd2_2, 14:8, secure_scratch43, 13:7); - s(EmcCmdMappingCmd2_2, 22:16, secure_scratch43, 20:14); - s(EmcCmdMappingCmd2_2, 27:24, secure_scratch43, 24:21); - s(McGeneralizedCarveout1Cfg0, 17:14, secure_scratch43, 28:25); - s(McGeneralizedCarveout3Cfg0, 13:11, secure_scratch43, 31:29); - s(EmcCmdMappingCmd3_2, 6:0, secure_scratch44, 6:0); - s(EmcCmdMappingCmd3_2, 14:8, secure_scratch44, 13:7); - s(EmcCmdMappingCmd3_2, 22:16, secure_scratch44, 20:14); - s(EmcCmdMappingCmd3_2, 27:24, secure_scratch44, 24:21); - s(McGeneralizedCarveout1Cfg0, 21:18, secure_scratch44, 28:25); - s(McVideoProtectVprOverride, 3:2, secure_scratch44, 30:29); - s(McVideoProtectVprOverride, 6:6, secure_scratch44, 31:31); - s(McEmemAdrCfgChannelMask, 31:9, secure_scratch45, 22:0); - s(McEmemAdrCfgDev0, 2:0, secure_scratch45, 25:23); - s(McEmemAdrCfgDev0, 9:8, secure_scratch45, 27:26); - s(McEmemAdrCfgDev0, 19:16, secure_scratch45, 31:28); - s(McEmemAdrCfgBankMask0, 31:10, secure_scratch46, 21:0); - s(McEmemAdrCfgDev1, 2:0, secure_scratch46, 24:22); - s(McEmemAdrCfgDev1, 9:8, secure_scratch46, 26:25); - s(McEmemAdrCfgDev1, 19:16, secure_scratch46, 30:27); - s(McVideoProtectVprOverride, 7:7, secure_scratch46, 31:31); - s(McEmemAdrCfgBankMask1, 31:10, secure_scratch47, 21:0); - s(McGeneralizedCarveout3Cfg0, 10:3, secure_scratch47, 29:22); - s(McVideoProtectVprOverride, 9:8, secure_scratch47, 31:30); - s(McEmemAdrCfgBankMask2, 31:10, secure_scratch48, 21:0); - s(McGeneralizedCarveout3Cfg0, 21:14, secure_scratch48, 29:22); - s(McVideoProtectVprOverride, 11:11, secure_scratch48, 30:30); - s(McVideoProtectVprOverride, 14:14, secure_scratch48, 31:31); - s(McVideoProtectGpuOverride1, 15:0, secure_scratch49, 15:0); - s(McEmemCfg, 13:0, secure_scratch49, 29:16); - s(McEmemCfg, 31:31, secure_scratch49, 30:30); - s(McVideoProtectVprOverride, 15:15, secure_scratch49, 31:31); - s(McGeneralizedCarveout3Bom, 31:17, secure_scratch50, 14:0); - s(McGeneralizedCarveout1Bom, 31:17, secure_scratch50, 29:15); - s(McVideoProtectVprOverride, 18:17, secure_scratch50, 31:30); - s(McGeneralizedCarveout4Bom, 31:17, secure_scratch51, 14:0); - s(McGeneralizedCarveout2Bom, 31:17, secure_scratch51, 29:15); - s(McVideoProtectVprOverride, 20:19, secure_scratch51, 31:30); - s(McGeneralizedCarveout5Bom, 31:17, secure_scratch52, 14:0); - s(McVideoProtectBom, 31:20, secure_scratch52, 26:15); - s(McVideoProtectVprOverride, 23:21, secure_scratch52, 29:27); - s(McVideoProtectVprOverride, 26:26, secure_scratch52, 30:30); - s(McVideoProtectVprOverride, 29:29, secure_scratch52, 31:31); - s(McVideoProtectSizeMb, 11:0, secure_scratch53, 11:0); - s(McSecCarveoutBom, 31:20, secure_scratch53, 23:12); - s(McVideoProtectVprOverride, 31:30, secure_scratch53, 25:24); - s(McVideoProtectVprOverride1, 1:0, secure_scratch53, 27:26); - s(McVideoProtectVprOverride1, 7:4, secure_scratch53, 31:28); - s(McSecCarveoutSizeMb, 11:0, secure_scratch54, 11:0); - s(McMtsCarveoutBom, 31:20, secure_scratch54, 23:12); - s(McVideoProtectVprOverride1, 15:8, secure_scratch54, 31:24); - s(McMtsCarveoutSizeMb, 11:0, secure_scratch55, 11:0); - s(McGeneralizedCarveout4Size128kb, 11:0, secure_scratch55, 23:12); - s(McVideoProtectVprOverride1, 16:16, secure_scratch55, 24:24); - s(McGeneralizedCarveout2Cfg0, 2:0, secure_scratch55, 27:25); - s(McGeneralizedCarveout2Cfg0, 25:22, secure_scratch55, 31:28); - s(McGeneralizedCarveout3Size128kb, 11:0, secure_scratch56, 11:0); - s(McGeneralizedCarveout2Size128kb, 11:0, secure_scratch56, 23:12); - s(McGeneralizedCarveout2Cfg0, 26:26, secure_scratch56, 24:24); - s(McGeneralizedCarveout1Cfg0, 2:0, secure_scratch56, 27:25); - s(McGeneralizedCarveout1Cfg0, 25:22, secure_scratch56, 31:28); - s(McGeneralizedCarveout1Size128kb, 11:0, secure_scratch57, 11:0); - s(McGeneralizedCarveout5Size128kb, 11:0, secure_scratch57, 23:12); - s(McGeneralizedCarveout1Cfg0, 26:26, secure_scratch57, 24:24); - s(McGeneralizedCarveout3Cfg0, 2:0, secure_scratch57, 27:25); - s(McGeneralizedCarveout3Cfg0, 25:22, secure_scratch57, 31:28); - s(McGeneralizedCarveout3Cfg0, 26:26, secure_scratch58, 0:0); - - s32(McGeneralizedCarveout1Access0, secure_scratch59); - s32(McGeneralizedCarveout1Access1, secure_scratch60); - s32(McGeneralizedCarveout1Access2, secure_scratch61); - s32(McGeneralizedCarveout1Access3, secure_scratch62); - s32(McGeneralizedCarveout1Access4, secure_scratch63); - s32(McGeneralizedCarveout2Access0, secure_scratch64); - s32(McGeneralizedCarveout2Access1, secure_scratch65); - s32(McGeneralizedCarveout2Access2, secure_scratch66); - s32(McGeneralizedCarveout2Access3, secure_scratch67); - s32(McGeneralizedCarveout2Access4, secure_scratch68); - s32(McGeneralizedCarveout3Access0, secure_scratch69); - s32(McGeneralizedCarveout3Access1, secure_scratch70); - s32(McGeneralizedCarveout3Access2, secure_scratch71); - s32(McGeneralizedCarveout3Access3, secure_scratch72); - s32(McGeneralizedCarveout3Access4, secure_scratch73); - s32(McGeneralizedCarveout4Access0, secure_scratch74); - s32(McGeneralizedCarveout4Access1, secure_scratch75); - s32(McGeneralizedCarveout4Access2, secure_scratch76); - s32(McGeneralizedCarveout4Access3, secure_scratch77); - s32(McGeneralizedCarveout4Access4, secure_scratch78); - s32(McGeneralizedCarveout5Access0, secure_scratch79); - s32(McGeneralizedCarveout5Access1, secure_scratch80); - s32(McGeneralizedCarveout5Access2, secure_scratch81); - s32(McGeneralizedCarveout5Access3, secure_scratch82); - s32(McGeneralizedCarveout1ForceInternalAccess0, secure_scratch84); - s32(McGeneralizedCarveout1ForceInternalAccess1, secure_scratch85); - s32(McGeneralizedCarveout1ForceInternalAccess2, secure_scratch86); - s32(McGeneralizedCarveout1ForceInternalAccess3, secure_scratch87); - s32(McGeneralizedCarveout1ForceInternalAccess4, secure_scratch88); - s32(McGeneralizedCarveout2ForceInternalAccess0, secure_scratch89); - s32(McGeneralizedCarveout2ForceInternalAccess1, secure_scratch90); - s32(McGeneralizedCarveout2ForceInternalAccess2, secure_scratch91); - s32(McGeneralizedCarveout2ForceInternalAccess3, secure_scratch92); - s32(McGeneralizedCarveout2ForceInternalAccess4, secure_scratch93); - s32(McGeneralizedCarveout3ForceInternalAccess0, secure_scratch94); - s32(McGeneralizedCarveout3ForceInternalAccess1, secure_scratch95); - s32(McGeneralizedCarveout3ForceInternalAccess2, secure_scratch96); - s32(McGeneralizedCarveout3ForceInternalAccess3, secure_scratch97); - s32(McGeneralizedCarveout3ForceInternalAccess4, secure_scratch98); - s32(McGeneralizedCarveout4ForceInternalAccess0, secure_scratch99); - s32(McGeneralizedCarveout4ForceInternalAccess1, secure_scratch100); - s32(McGeneralizedCarveout4ForceInternalAccess2, secure_scratch101); - s32(McGeneralizedCarveout4ForceInternalAccess3, secure_scratch102); - s32(McGeneralizedCarveout4ForceInternalAccess4, secure_scratch103); - s32(McGeneralizedCarveout5ForceInternalAccess0, secure_scratch104); - s32(McGeneralizedCarveout5ForceInternalAccess1, secure_scratch105); - s32(McGeneralizedCarveout5ForceInternalAccess2, secure_scratch106); - s32(McGeneralizedCarveout5ForceInternalAccess3, secure_scratch107); - - c32(0, scratch2); - s(PllMInputDivider, 7:0, scratch2, 7:0); - s(PllMFeedbackDivider, 7:0, scratch2, 15:8); - s(PllMPostDivider, 4:0, scratch2, 20:16); - s(PllMKVCO, 0:0, scratch2, 21:21); - s(PllMKCP, 1:0, scratch2, 23:22); - - c32(0, scratch35); - s(PllMSetupControl, 15:0, scratch35, 15:0); - - c32(0, scratch3); - s(PllMInputDivider, 7:0, scratch3, 7:0); - c(0x3e, scratch3, 15:8); - c(0, scratch3, 20:16); - s(PllMKVCO, 0:0, scratch3, 21:21); - s(PllMKCP, 1:0, scratch3, 23:22); - - c32(0, scratch36); - s(PllMSetupControl, 23:0, scratch36, 23:0); - - c32(0, scratch4); - s(PllMStableTime, 9:0, scratch4, 9:0); -} - -void sdram_init(void) { - sdram_init_erista(); -} - -const void *sdram_get_params(uint32_t dram_id) { - return sdram_get_params_erista(dram_id); -} - -void sdram_save_params(const void *save_params) { - sdram_save_params_erista(save_params); -} \ No newline at end of file diff --git a/sept/sept-secondary/src/sdram.h b/sept/sept-secondary/src/sdram.h deleted file mode 100644 index 38f725579..000000000 --- a/sept/sept-secondary/src/sdram.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_SDRAM_H_ -#define FUSEE_SDRAM_H_ - -void sdram_init(void); -const void *sdram_get_params(uint32_t dram_id); -void sdram_save_params(const void *save_params); - -#endif diff --git a/sept/sept-secondary/src/sdram.inl b/sept/sept-secondary/src/sdram.inl deleted file mode 100644 index dd68f6bf0..000000000 --- a/sept/sept-secondary/src/sdram.inl +++ /dev/null @@ -1,3560 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -static const uint8_t sdram_params_erista_0[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, - 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, - 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, - 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, - 0xA6, 0xA6, 0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - 0x1F, 0x1F, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, - 0xA1, 0x01, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, - 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x16, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, - 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, - 0xBF, 0x3B, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, - 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, - 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, - 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, - 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, - 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, 0x00, 0x0D, 0x08, - 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00, 0x00, 0x0B, 0x08, - 0x72, 0x72, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x0D, 0x0C, - 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x04, 0x00, 0x01, 0x08, - 0x00, 0x00, 0x11, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0xCC, 0x00, - 0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, - 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x00, 0x80, - 0x01, 0x00, 0x00, 0x00, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x00, 0x00, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, - 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28, 0x28, 0x28, - 0x28, 0x28, 0x28, 0x28, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, - 0xBE, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x12, 0x00, 0x10, 0x00, 0x14, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x12, 0x00, 0x10, 0x00, 0x14, 0x00, - 0x30, 0x00, 0x2E, 0x00, 0x33, 0x00, 0x30, 0x00, 0x33, 0x00, 0x35, 0x00, - 0x30, 0x00, 0x32, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x30, 0x00, 0x2E, 0x00, 0x33, 0x00, 0x30, 0x00, 0x33, 0x00, 0x35, 0x00, - 0x30, 0x00, 0x32, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, - 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, - 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x14, 0x00, 0x14, 0x00, - 0x12, 0x00, 0x12, 0x00, 0x10, 0x00, 0x10, 0x00, 0x14, 0x00, 0x14, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, 0x00, 0x51, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x40, - 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0xAB, 0x00, 0x0A, 0x04, - 0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x22, 0x04, 0xFF, 0xFF, 0xAF, 0x4F, - 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0xFF, 0x07, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x54, 0x76, 0x10, 0x47, 0x32, 0x65, - 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75, 0x64, 0x32, - 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45, 0x32, 0x67, - 0x00, 0x00, 0x00, 0x00, 0x49, 0x92, 0x24, 0x00, 0x49, 0x92, 0x24, 0x00, - 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0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x7E, 0x16, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_erista_1[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, - 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, - 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0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_erista_2[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_erista_3[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, - 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, - 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, - 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, - 0xA6, 0xA6, 0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - 0x1F, 0x1F, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, - 0xA1, 0x01, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, - 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x16, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x12, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, - 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, - 0xBF, 0x3B, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, - 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, - 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, - 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, - 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, - 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, 0x00, 0x0D, 0x08, - 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00, 0x00, 0x0B, 0x08, - 0x72, 0x72, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x0D, 0x0C, - 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x04, 0x00, 0x01, 0x08, - 0x00, 0x00, 0x11, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0xCC, 0x00, - 0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, - 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, - 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x00, 0x80, - 0x01, 0x00, 0x00, 0x00, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x00, 0x00, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, - 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28, 0x28, 0x28, - 0x28, 0x28, 0x28, 0x28, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, - 0xBE, 0x00, 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x40, - 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0xAB, 0x00, 0x0A, 0x04, - 0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x22, 0x04, 0xFF, 0xFF, 0xAF, 0x4F, - 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0xFF, 0x07, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x54, 0x76, 0x10, 0x47, 0x32, 0x65, - 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75, 0x64, 0x32, - 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45, 0x32, 0x67, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x7E, 0x16, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_erista_4[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, - 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, - 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, - 0xBF, 0x3B, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, - 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, - 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, - 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, - 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, - 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, 0x00, 0x0D, 0x08, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_erista_5[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_erista_6[1896] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, 0x00, 0x04, 0xB4, 0x01, 0x70, - 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, - 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x46, 0x2C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_mariko_0[2104] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_mariko_1[2104] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_mariko_3[2104] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, - 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_mariko_5[2104] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x3A, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, - 0x17, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x0E, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, - 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, - 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_mariko_8[2104] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, - 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, - 0x17, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x0E, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, - 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, - 0x1A, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, - 0x0A, 0x00, 0x00, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xC1, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x0D, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, - 0x05, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, - 0x3F, 0x3A, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, - 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, - 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, - 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0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_mariko_10[2104] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, - 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static const uint8_t sdram_params_mariko_12[2104] = { - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x2C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x09, 0x00, 0x00, 0x00, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, - 0x3F, 0x3A, 0x00, 0x00, 0x00, 0x00, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, - 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, - 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, - 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, - 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, - 0x12, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x01, 0x88, 0x00, 0x00, 0x02, 0x88, 0x00, 0x00, 0x0D, 0x88, - 0x00, 0x00, 0x00, 0xC0, 0x31, 0x31, 0x03, 0x88, 0x00, 0x00, 0x0B, 0x88, - 0x5D, 0x5D, 0x0E, 0x8C, 0x5D, 0x5D, 0x0C, 0x88, 0x08, 0x08, 0x0D, 0x8C, - 0x00, 0x00, 0x0D, 0x8C, 0x14, 0x14, 0x16, 0x88, 0x04, 0x00, 0x01, 0x88, - 0x00, 0x00, 0x11, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0xCC, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x76, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x16, 0x40, 0x04, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x7E, 0x1E, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x46, 0x24, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x2C, 0x00, 0x04, - 0x00, 0x00, 0x00, 0x00, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static const uint32_t sdram_params_index_table_erista[29] = { - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, -}; - -static const uint32_t *sdram_params_erista[7] = { - (const uint32_t *)sdram_params_erista_0, - (const uint32_t *)sdram_params_erista_1, - (const uint32_t *)sdram_params_erista_2, - (const uint32_t *)sdram_params_erista_3, - (const uint32_t *)sdram_params_erista_4, - (const uint32_t *)sdram_params_erista_5, - (const uint32_t *)sdram_params_erista_6, -}; - -static const uint32_t sdram_params_index_table_mariko[29] = { - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xC, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0, - 1, - 2, - 3, - 4, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 6, - 8, - 9, - 0xA, - 7, - 6, - 0xB, - 0xB, - 0xB, - 7, -}; - -static const uint32_t *sdram_params_mariko[12] = { - (const uint32_t *)sdram_params_mariko_0, - (const uint32_t *)sdram_params_mariko_1, - (const uint32_t *)sdram_params_mariko_2, - (const uint32_t *)sdram_params_mariko_3, - (const uint32_t *)sdram_params_mariko_4, - (const uint32_t *)sdram_params_mariko_5, - (const uint32_t *)sdram_params_mariko_6, - (const uint32_t *)sdram_params_mariko_7, - (const uint32_t *)sdram_params_mariko_8, - (const uint32_t *)sdram_params_mariko_9, - (const uint32_t *)sdram_params_mariko_10, - (const uint32_t *)sdram_params_mariko_11, - (const uint32_t *)sdram_params_mariko_12, -}; diff --git a/sept/sept-secondary/src/sdram_lz.inl b/sept/sept-secondary/src/sdram_lz.inl deleted file mode 100644 index 4e29d890f..000000000 --- a/sept/sept-secondary/src/sdram_lz.inl +++ /dev/null @@ -1,338 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -static const uint8_t sdram_params_erista_lz[1262] = { - 0x17, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, - 0x00, 0x2C, 0x17, 0x04, 0x09, 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, - 0x17, 0x10, 0x10, 0x00, 0x00, 0x68, 0xBC, 0x01, 0x70, 0x0A, 0x00, 0x00, - 0x00, 0x04, 0xB4, 0x01, 0x70, 0x01, 0x32, 0x54, 0x76, 0xC8, 0xE6, 0x00, - 0x70, 0x17, 0x10, 0x24, 0x34, 0x00, 0x00, 0x00, 0x02, 0x80, 0x18, 0x40, - 0x00, 0x00, 0x00, 0x17, 0x04, 0x04, 0x17, 0x09, 0x18, 0xFF, 0xFF, 0x1F, - 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x00, 0x00, 0x50, 0x05, 0x00, 0x00, 0x77, - 0x00, 0x17, 0x04, 0x04, 0x17, 0x08, 0x08, 0x17, 0x08, 0x08, 0xA6, 0xA6, - 0xAF, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x03, 0x03, 0xE0, 0xC1, 0x04, 0x04, - 0x04, 0x04, 0x17, 0x04, 0x04, 0x17, 0x04, 0x3C, 0x1F, 0x1F, 0x1F, 0x1F, - 0x17, 0x04, 0x04, 0x17, 0x06, 0x06, 0x00, 0x00, 0x04, 0x08, 0x17, 0x06, - 0x46, 0xA1, 0x01, 0x00, 0x00, 0x32, 0x17, 0x0B, 0x64, 0x01, 0x17, 0x04, - 0x7C, 0x17, 0x07, 0x0C, 0x03, 0x17, 0x04, 0x04, 0x00, 0x00, 0x00, 0x1E, - 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x13, - 0x17, 0x0B, 0x2C, 0x09, 0x00, 0x00, 0x00, 0x17, 0x05, 0x5D, 0x17, 0x07, - 0x10, 0x0B, 0x17, 0x07, 0x28, 0x08, 0x17, 0x07, 0x0C, 0x17, 0x04, 0x1C, - 0x20, 0x00, 0x00, 0x00, 0x06, 0x17, 0x04, 0x04, 0x17, 0x07, 0x08, 0x17, - 0x04, 0x50, 0x17, 0x04, 0x2C, 0x17, 0x04, 0x1C, 0x17, 0x04, 0x10, 0x17, - 0x08, 0x6C, 0x17, 0x04, 0x10, 0x17, 0x04, 0x38, 0x17, 0x04, 0x40, 0x05, - 0x17, 0x07, 0x1C, 0x17, 0x08, 0x58, 0x17, 0x04, 0x24, 0x17, 0x04, 0x18, - 0x17, 0x08, 0x64, 0x00, 0x00, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x14, - 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x17, 0x09, 0x0C, 0x17, 0x05, 0x82, - 0x58, 0x17, 0x07, 0x61, 0xC1, 0x17, 0x07, 0x50, 0x17, 0x04, 0x04, 0x17, - 0x08, 0x81, 0x48, 0x17, 0x04, 0x04, 0x17, 0x04, 0x28, 0x17, 0x04, 0x60, - 0x17, 0x08, 0x54, 0x27, 0x17, 0x04, 0x04, 0x17, 0x07, 0x14, 0x17, 0x04, - 0x04, 0x04, 0x17, 0x07, 0x81, 0x58, 0x17, 0x0C, 0x0C, 0x1C, 0x03, 0x00, - 0x00, 0x0D, 0xA0, 0x60, 0x91, 0xBF, 0x3B, 0x17, 0x04, 0x5A, 0xF3, 0x0C, - 0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07, 0x1C, 0x23, 0x25, 0x25, 0x05, - 0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E, 0x0D, 0x0C, 0x26, 0x26, 0x03, - 0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07, 0x05, 0x06, 0x25, 0x25, 0x02, - 0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09, 0x1E, 0x24, 0x26, 0x26, 0x08, - 0x24, 0x06, 0x07, 0x9A, 0x12, 0x17, 0x05, 0x83, 0x41, 0x00, 0xFF, 0x17, - 0x10, 0x83, 0x6C, 0x04, 0x00, 0x01, 0x08, 0x00, 0x00, 0x02, 0x08, 0x00, - 0x00, 0x0D, 0x08, 0x00, 0x00, 0x00, 0xC0, 0x71, 0x71, 0x03, 0x08, 0x00, - 0x00, 0x0B, 0x08, 0x72, 0x72, 0x0E, 0x0C, 0x17, 0x04, 0x20, 0x08, 0x08, - 0x0D, 0x0C, 0x00, 0x00, 0x0D, 0x0C, 0x14, 0x14, 0x16, 0x08, 0x17, 0x06, - 0x2C, 0x11, 0x08, 0x17, 0x10, 0x84, 0x67, 0x15, 0x00, 0xCC, 0x00, 0x0A, - 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, 0xF3, 0x05, 0x08, 0x11, 0x00, 0xFF, - 0x0F, 0xFF, 0x0F, 0x17, 0x08, 0x83, 0x4C, 0x01, 0x03, 0x00, 0x70, 0x00, - 0x0C, 0x00, 0x01, 0x17, 0x04, 0x0C, 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, - 0x00, 0x06, 0x13, 0x07, 0x00, 0x80, 0x17, 0x04, 0x10, 0xA0, 0x00, 0x2C, - 0x00, 0x01, 0x37, 0x00, 0x00, 0x00, 0x80, 0x17, 0x06, 0x48, 0x08, 0x00, - 0x04, 0x00, 0x1F, 0x22, 0x20, 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x28, 0x28, - 0x28, 0x28, 0x17, 0x04, 0x04, 0x11, 0x11, 0x11, 0x11, 0x17, 0x04, 0x04, - 0xBE, 0x00, 0x00, 0x17, 0x05, 0x58, 0x17, 0x08, 0x5C, 0x17, 0x22, 0x85, - 0x6A, 0x17, 0x1A, 0x1A, 0x14, 0x00, 0x12, 0x00, 0x10, 0x17, 0x05, 0x83, - 0x0A, 0x17, 0x16, 0x18, 0x30, 0x00, 0x2E, 0x00, 0x33, 0x00, 0x30, 0x00, - 0x33, 0x00, 0x35, 0x00, 0x30, 0x00, 0x32, 0x17, 0x05, 0x83, 0x0C, 0x17, - 0x04, 0x20, 0x17, 0x18, 0x18, 0x28, 0x00, 0x28, 0x17, 0x04, 0x04, 0x17, - 0x08, 0x08, 0x17, 0x10, 0x10, 0x00, 0x14, 0x17, 0x05, 0x5A, 0x17, 0x04, - 0x5C, 0x17, 0x04, 0x5E, 0x17, 0x04, 0x0E, 0x17, 0x0E, 0x78, 0x17, 0x09, - 0x82, 0x50, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, 0x00, 0x51, - 0x17, 0x08, 0x18, 0x80, 0x01, 0x00, 0x00, 0x40, 0x17, 0x04, 0x20, 0x03, - 0x00, 0x00, 0x00, 0xAB, 0x00, 0x0A, 0x04, 0x11, 0x17, 0x08, 0x82, 0x58, - 0x17, 0x0C, 0x38, 0x17, 0x1B, 0x81, 0x6C, 0x17, 0x08, 0x85, 0x60, 0x17, - 0x08, 0x86, 0x50, 0x17, 0x08, 0x86, 0x60, 0x17, 0x06, 0x83, 0x21, 0x22, - 0x04, 0xFF, 0xFF, 0xAF, 0x4F, 0x17, 0x0C, 0x86, 0x74, 0x17, 0x08, 0x2C, - 0x8B, 0xFF, 0x07, 0x17, 0x06, 0x81, 0x04, 0x32, 0x54, 0x76, 0x10, 0x47, - 0x32, 0x65, 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, 0x67, 0x25, 0x01, 0x75, - 0x64, 0x32, 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, 0x74, 0x56, 0x01, 0x45, - 0x32, 0x67, 0x17, 0x04, 0x24, 0x49, 0x92, 0x24, 0x17, 0x04, 0x04, 0x17, - 0x11, 0x7C, 0x1B, 0x17, 0x04, 0x04, 0x17, 0x13, 0x81, 0x14, 0x2F, 0x41, - 0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, 0x17, 0x04, 0x7C, 0xFF, 0xFF, 0xFF, - 0x7F, 0x0B, 0xD7, 0x06, 0x40, 0x00, 0x00, 0x02, 0x00, 0x08, 0x08, 0x03, - 0x00, 0x00, 0x5C, 0x01, 0x00, 0x10, 0x10, 0x10, 0x17, 0x06, 0x86, 0x59, - 0x17, 0x0F, 0x89, 0x14, 0x37, 0x17, 0x07, 0x82, 0x72, 0x10, 0x17, 0x06, - 0x83, 0x0D, 0x00, 0x11, 0x01, 0x17, 0x05, 0x85, 0x39, 0x17, 0x04, 0x0E, - 0x0A, 0x17, 0x07, 0x89, 0x29, 0x17, 0x04, 0x1B, 0x17, 0x08, 0x86, 0x77, - 0x17, 0x09, 0x12, 0x20, 0x00, 0x00, 0x00, 0x81, 0x10, 0x09, 0x28, 0x93, - 0x32, 0xA5, 0x44, 0x5B, 0x8A, 0x67, 0x76, 0x17, 0x18, 0x82, 0x2C, 0xFF, - 0xEF, 0xFF, 0xEF, 0xC0, 0xC0, 0xC0, 0xC0, 0x17, 0x04, 0x04, 0xDC, 0xDC, - 0xDC, 0xDC, 0x0A, 0x0A, 0x0A, 0x0A, 0x17, 0x04, 0x04, 0x17, 0x04, 0x04, - 0x17, 0x05, 0x82, 0x24, 0x03, 0x07, 0x17, 0x04, 0x04, 0x00, 0x00, 0x24, - 0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39, 0x00, 0x10, - 0x9C, 0x4B, 0x17, 0x04, 0x64, 0x01, 0x00, 0x00, 0x08, 0x4C, 0x00, 0x00, - 0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x17, 0x06, 0x85, 0x60, 0x17, - 0x10, 0x82, 0x74, 0x17, 0x08, 0x08, 0x17, 0x08, 0x88, 0x00, 0x17, 0x04, - 0x10, 0x04, 0x17, 0x0B, 0x87, 0x6C, 0x01, 0x00, 0x02, 0x02, 0x01, 0x02, - 0x03, 0x00, 0x04, 0x05, 0xC3, 0x71, 0x0F, 0x0F, 0x17, 0x08, 0x8B, 0x18, - 0x1F, 0x17, 0x09, 0x81, 0x73, 0x00, 0xFF, 0x00, 0xFF, 0x17, 0x05, 0x86, - 0x48, 0x17, 0x04, 0x0C, 0x17, 0x07, 0x86, 0x34, 0x00, 0x00, 0xF0, 0x17, - 0x09, 0x87, 0x54, 0x43, 0xC3, 0xBA, 0xE4, 0xD3, 0x1E, 0x17, 0x0C, 0x81, - 0x52, 0x17, 0x0A, 0x1C, 0x17, 0x10, 0x81, 0x6C, 0x17, 0x0A, 0x82, 0x21, - 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0x83, 0x04, 0x9D, 0x50, 0x15, 0x17, 0x05, 0x8D, 0x76, 0x17, 0x0F, 0x8B, - 0x49, 0x17, 0x0B, 0x18, 0x32, 0x00, 0x2F, 0x00, 0x32, 0x00, 0x31, 0x00, - 0x34, 0x00, 0x36, 0x00, 0x2F, 0x00, 0x33, 0x17, 0x09, 0x84, 0x0C, 0x17, - 0x18, 0x18, 0x17, 0x20, 0x8E, 0x68, 0x15, 0x17, 0x07, 0x5A, 0x17, 0x06, - 0x5E, 0x16, 0x00, 0x15, 0x17, 0x82, 0x40, 0x9D, 0x50, 0x17, 0x86, 0x5F, - 0xBB, 0x20, 0x3A, 0x00, 0x00, 0x00, 0x1D, 0x17, 0x81, 0x4F, 0xAC, 0x38, - 0x3B, 0x17, 0x04, 0x04, 0x17, 0x86, 0x30, 0x8E, 0x68, 0x17, 0x81, 0x53, - 0xAC, 0x38, 0x07, 0x17, 0x0D, 0x8E, 0x68, 0xA3, 0x72, 0x17, 0x83, 0x10, - 0x8E, 0x68 -}; - -static const uint8_t sdram_params_mariko_lz[1741] = { - 0x19, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, - 0x00, 0x2C, 0x19, 0x04, 0x09, 0x00, 0x19, 0x04, 0x04, 0x19, 0x08, 0x08, - 0x19, 0x10, 0x10, 0x19, 0x20, 0x20, 0x19, 0x40, 0x40, 0x19, 0x2A, 0x2A, - 0x02, 0x80, 0x18, 0x40, 0x00, 0x00, 0x00, 0x19, 0x04, 0x04, 0x19, 0x09, - 0x14, 0xFF, 0xFF, 0x1F, 0x00, 0xD8, 0x51, 0x1A, 0xA0, 0x19, 0x06, 0x0E, - 0x88, 0x19, 0x04, 0x04, 0x00, 0x20, 0x12, 0x19, 0x0A, 0x0C, 0x19, 0x06, - 0x08, 0x00, 0x00, 0xBC, 0xBC, 0xC5, 0xB3, 0x3C, 0x9E, 0x00, 0x00, 0x02, - 0x03, 0xE0, 0xC1, 0x04, 0x04, 0x04, 0x04, 0x19, 0x04, 0x04, 0x19, 0x04, - 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 0x19, 0x04, 0x04, 0x19, 0x04, 0x04, 0x19, - 0x04, 0x38, 0x04, 0x08, 0x00, 0x00, 0x50, 0x50, 0x50, 0x00, 0xA1, 0x01, - 0x00, 0x00, 0x30, 0x19, 0x04, 0x39, 0x10, 0x00, 0x16, 0x00, 0x10, 0x90, - 0x19, 0x06, 0x81, 0x00, 0x19, 0x07, 0x74, 0x03, 0x19, 0x04, 0x04, 0x00, - 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x3A, 0x00, - 0x00, 0x00, 0x1D, 0x19, 0x0B, 0x81, 0x14, 0x09, 0x00, 0x00, 0x00, 0x04, - 0x19, 0x0B, 0x10, 0x0B, 0x19, 0x07, 0x28, 0x08, 0x19, 0x07, 0x0C, 0x19, - 0x04, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x15, 0x19, 0x07, 0x08, 0x1B, 0x19, - 0x07, 0x28, 0x20, 0x00, 0x00, 0x00, 0x06, 0x19, 0x04, 0x04, 0x19, 0x07, - 0x08, 0x19, 0x04, 0x64, 0x19, 0x04, 0x18, 0x19, 0x04, 0x30, 0x19, 0x04, - 0x10, 0x19, 0x08, 0x81, 0x00, 0x19, 0x04, 0x10, 0x19, 0x04, 0x4C, 0x0E, - 0x00, 0x00, 0x00, 0x05, 0x19, 0x07, 0x1C, 0x19, 0x09, 0x82, 0x24, 0x19, - 0x07, 0x6C, 0x19, 0x07, 0x83, 0x57, 0x80, 0x19, 0x04, 0x0A, 0x12, 0x00, - 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x16, 0x19, - 0x07, 0x0C, 0x0A, 0x19, 0x04, 0x48, 0x19, 0x07, 0x61, 0xC1, 0x19, 0x07, - 0x50, 0x19, 0x04, 0x04, 0x19, 0x04, 0x13, 0x19, 0x04, 0x1C, 0x19, 0x04, - 0x08, 0x14, 0x19, 0x07, 0x60, 0x19, 0x08, 0x54, 0x3B, 0x19, 0x04, 0x04, - 0x19, 0x07, 0x14, 0x19, 0x04, 0x04, 0x04, 0x19, 0x07, 0x81, 0x6C, 0x19, - 0x0C, 0x0C, 0x1C, 0x03, 0x00, 0x00, 0x0D, 0xA0, 0x60, 0x91, 0x3F, 0x3A, - 0x19, 0x04, 0x5A, 0xF3, 0x0C, 0x04, 0x05, 0x1B, 0x06, 0x02, 0x03, 0x07, - 0x1C, 0x23, 0x25, 0x25, 0x05, 0x08, 0x1D, 0x09, 0x0A, 0x24, 0x0B, 0x1E, - 0x0D, 0x0C, 0x26, 0x26, 0x03, 0x02, 0x1B, 0x1C, 0x23, 0x03, 0x04, 0x07, - 0x05, 0x06, 0x25, 0x25, 0x02, 0x0A, 0x0B, 0x1D, 0x0D, 0x08, 0x0C, 0x09, - 0x1E, 0x24, 0x26, 0x26, 0x08, 0x24, 0x06, 0x07, 0x9A, 0x19, 0x05, 0x83, - 0x3F, 0xFF, 0x00, 0xFF, 0x19, 0x10, 0x84, 0x00, 0x04, 0x00, 0x01, 0x88, - 0x00, 0x00, 0x02, 0x88, 0x00, 0x00, 0x0D, 0x88, 0x00, 0x00, 0x00, 0xC0, - 0x31, 0x31, 0x03, 0x88, 0x00, 0x00, 0x0B, 0x88, 0x5D, 0x5D, 0x0E, 0x8C, - 0x5D, 0x5D, 0x0C, 0x88, 0x08, 0x08, 0x0D, 0x8C, 0x00, 0x00, 0x0D, 0x8C, - 0x16, 0x16, 0x16, 0x88, 0x19, 0x06, 0x2C, 0x11, 0x08, 0x19, 0x10, 0x85, - 0x5F, 0x10, 0x00, 0xCC, 0x00, 0x0A, 0x00, 0x33, 0x00, 0x00, 0x00, 0x20, - 0xF3, 0x25, 0x08, 0x11, 0x19, 0x04, 0x69, 0x0F, 0x19, 0x04, 0x18, 0x19, - 0x04, 0x28, 0x01, 0x03, 0x00, 0x70, 0x00, 0x0C, 0x00, 0x01, 0x19, 0x04, - 0x0C, 0x08, 0x44, 0x00, 0x10, 0x04, 0x04, 0x00, 0x06, 0x13, 0x07, 0x19, - 0x06, 0x1C, 0xA0, 0x00, 0x2C, 0x00, 0x01, 0x37, 0x0F, 0x19, 0x05, 0x82, - 0x52, 0x02, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x04, 0x00, 0x1F, 0x22, 0x20, - 0x80, 0x0F, 0xF4, 0x20, 0x02, 0x29, 0x29, 0x29, 0x29, 0x19, 0x04, 0x04, - 0x19, 0x08, 0x08, 0x78, 0x19, 0x06, 0x85, 0x1A, 0x19, 0x05, 0x58, 0x19, - 0x40, 0x85, 0x74, 0x22, 0x00, 0x0E, 0x00, 0x10, 0x19, 0x09, 0x84, 0x22, - 0x19, 0x12, 0x18, 0x43, 0x00, 0x49, 0x00, 0x45, 0x00, 0x42, 0x00, 0x47, - 0x00, 0x49, 0x00, 0x47, 0x00, 0x46, 0x19, 0x05, 0x83, 0x60, 0x00, 0x00, - 0x10, 0x19, 0x18, 0x18, 0x00, 0x28, 0x00, 0x28, 0x19, 0x04, 0x04, 0x19, - 0x08, 0x08, 0x19, 0x10, 0x10, 0x00, 0x22, 0x19, 0x05, 0x5A, 0x19, 0x04, - 0x5C, 0x19, 0x04, 0x5E, 0x1B, 0x19, 0x05, 0x88, 0x24, 0x19, 0x10, 0x7C, - 0x19, 0x09, 0x82, 0x54, 0x40, 0x06, 0x00, 0xCC, 0x00, 0x09, 0x00, 0x4F, - 0x00, 0x51, 0x80, 0x19, 0x07, 0x18, 0x19, 0x08, 0x08, 0x19, 0x05, 0x84, - 0x40, 0xAB, 0x00, 0x0A, 0x04, 0x11, 0x19, 0x08, 0x82, 0x5C, 0x19, 0x0C, - 0x38, 0x19, 0x1C, 0x87, 0x64, 0x19, 0x0B, 0x0C, 0x19, 0x08, 0x89, 0x28, - 0x19, 0x05, 0x14, 0x01, 0x22, 0x04, 0xFF, 0x9F, 0xAF, 0x4F, 0x19, 0x09, - 0x10, 0x19, 0x0B, 0x28, 0x9F, 0xFF, 0x37, 0x19, 0x06, 0x81, 0x18, 0x32, - 0x54, 0x76, 0x10, 0x47, 0x32, 0x65, 0x10, 0x34, 0x76, 0x25, 0x01, 0x34, - 0x67, 0x25, 0x01, 0x75, 0x64, 0x32, 0x01, 0x72, 0x56, 0x34, 0x10, 0x23, - 0x74, 0x56, 0x01, 0x45, 0x32, 0x67, 0x19, 0x04, 0x24, 0x49, 0x92, 0x24, - 0x19, 0x04, 0x04, 0x19, 0x11, 0x78, 0x12, 0x19, 0x04, 0x04, 0x19, 0x13, - 0x81, 0x10, 0x20, 0x41, 0x13, 0x1F, 0x14, 0x00, 0x01, 0x00, 0x19, 0x04, - 0x7C, 0xFF, 0xFF, 0xFF, 0x7F, 0x1F, 0xD7, 0x36, 0x19, 0x07, 0x89, 0x00, - 0x09, 0x00, 0x00, 0x34, 0x10, 0x19, 0x09, 0x87, 0x70, 0x19, 0x14, 0x81, - 0x4C, 0x03, 0x00, 0x05, 0x19, 0x05, 0x86, 0x2B, 0x10, 0x02, 0x19, 0x06, - 0x87, 0x5D, 0x21, 0x19, 0x07, 0x88, 0x15, 0x19, 0x07, 0x41, 0x19, 0x06, - 0x3D, 0x19, 0x07, 0x2C, 0x80, 0x00, 0x40, 0x00, 0x04, 0x10, 0x80, 0x19, - 0x05, 0x88, 0x04, 0x81, 0x10, 0x09, 0x28, 0x93, 0x32, 0xA5, 0x44, 0x5B, - 0x8A, 0x67, 0x76, 0x19, 0x60, 0x8A, 0x54, 0x10, 0x10, 0x19, 0x04, 0x04, - 0x00, 0x00, 0x00, 0xEF, 0x00, 0xEF, 0x19, 0x08, 0x14, 0x1C, 0x1C, 0x1C, - 0x1C, 0x19, 0x11, 0x83, 0x18, 0x03, 0x08, 0x19, 0x04, 0x04, 0x00, 0x00, - 0x24, 0xFF, 0xFF, 0x00, 0x44, 0x57, 0x6E, 0x00, 0x28, 0x72, 0x39, 0x00, - 0x10, 0x9C, 0x4B, 0x00, 0x10, 0x19, 0x05, 0x83, 0x24, 0x08, 0x4C, 0x00, - 0x00, 0x80, 0x20, 0x10, 0x0A, 0x00, 0x28, 0x10, 0x00, 0x80, 0x19, 0x08, - 0x83, 0x68, 0x19, 0x0C, 0x83, 0x40, 0x19, 0x08, 0x08, 0x05, 0x19, 0x0B, - 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0x38 -}; - -static const uint32_t sdram_params_index_table_erista[29] = { - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, -}; - -static const uint32_t sdram_params_index_table_mariko[29] = { - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xC, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0, - 1, - 2, - 3, - 4, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 6, - 8, - 9, - 0xA, - 7, - 6, - 0xB, - 0xB, - 0xB, - 7, -}; diff --git a/sept/sept-secondary/src/sdram_params.h b/sept/sept-secondary/src/sdram_params.h deleted file mode 100644 index 72e34d4bd..000000000 --- a/sept/sept-secondary/src/sdram_params.h +++ /dev/null @@ -1,1041 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_SDRAM_PARAMS_H_ -#define FUSEE_SDRAM_PARAMS_H_ - -#include - -typedef enum { - NvBootMemoryType_None = 0, - NvBootMemoryType_Ddr = 0, - NvBootMemoryType_LpDdr = 0, - NvBootMemoryType_Ddr2 = 0, - NvBootMemoryType_LpDdr2, - NvBootMemoryType_Ddr3, - NvBootMemoryType_LpDdr4, - NvBootMemoryType_Num, - NvBootMemoryType_Unused = 0X7FFFFFF, -} NvBootMemoryType; - -typedef struct { - NvBootMemoryType MemoryType; - uint32_t PllMInputDivider; - uint32_t PllMFeedbackDivider; - uint32_t PllMStableTime; - uint32_t PllMSetupControl; - uint32_t PllMPostDivider; - uint32_t PllMKCP; - uint32_t PllMKVCO; - uint32_t EmcBctSpare0; - uint32_t EmcBctSpare1; - uint32_t EmcBctSpare2; - uint32_t EmcBctSpare3; - uint32_t EmcBctSpare4; - uint32_t EmcBctSpare5; - uint32_t EmcBctSpare6; - uint32_t EmcBctSpare7; - uint32_t EmcBctSpare8; - uint32_t EmcBctSpare9; - uint32_t EmcBctSpare10; - uint32_t EmcBctSpare11; - uint32_t EmcBctSpare12; - uint32_t EmcBctSpare13; - uint32_t EmcClockSource; - uint32_t EmcClockSourceDll; - uint32_t ClkRstControllerPllmMisc2Override; - uint32_t ClkRstControllerPllmMisc2OverrideEnable; - uint32_t ClearClk2Mc1; - uint32_t EmcAutoCalInterval; - uint32_t EmcAutoCalConfig; - uint32_t EmcAutoCalConfig2; - uint32_t EmcAutoCalConfig3; - uint32_t EmcAutoCalConfig4; - uint32_t EmcAutoCalConfig5; - uint32_t EmcAutoCalConfig6; - uint32_t EmcAutoCalConfig7; - uint32_t EmcAutoCalConfig8; - uint32_t EmcAutoCalVrefSel0; - uint32_t EmcAutoCalVrefSel1; - uint32_t EmcAutoCalChannel; - uint32_t EmcPmacroAutocalCfg0; - uint32_t EmcPmacroAutocalCfg1; - uint32_t EmcPmacroAutocalCfg2; - uint32_t EmcPmacroRxTerm; - uint32_t EmcPmacroDqTxDrv; - uint32_t EmcPmacroCaTxDrv; - uint32_t EmcPmacroCmdTxDrv; - uint32_t EmcPmacroAutocalCfgCommon; - uint32_t EmcPmacroZctrl; - uint32_t EmcAutoCalWait; - uint32_t EmcXm2CompPadCtrl; - uint32_t EmcXm2CompPadCtrl2; - uint32_t EmcXm2CompPadCtrl3; - uint32_t EmcAdrCfg; - uint32_t EmcPinProgramWait; - uint32_t EmcPinExtraWait; - uint32_t EmcPinGpioEn; - uint32_t EmcPinGpio; - uint32_t EmcTimingControlWait; - uint32_t EmcRc; - uint32_t EmcRfc; - uint32_t EmcRfcPb; - uint32_t EmcRefctrl2; - uint32_t EmcRfcSlr; - uint32_t EmcRas; - uint32_t EmcRp; - uint32_t EmcR2r; - uint32_t EmcW2w; - uint32_t EmcR2w; - uint32_t EmcW2r; - uint32_t EmcR2p; - uint32_t EmcW2p; - uint32_t EmcTppd; - uint32_t EmcCcdmw; - uint32_t EmcRdRcd; - uint32_t EmcWrRcd; - uint32_t EmcRrd; - uint32_t EmcRext; - uint32_t EmcWext; - uint32_t EmcWdv; - uint32_t EmcWdvChk; - uint32_t EmcWsv; - uint32_t EmcWev; - uint32_t EmcWdvMask; - uint32_t EmcWsDuration; - uint32_t EmcWeDuration; - uint32_t EmcQUse; - uint32_t EmcQuseWidth; - uint32_t EmcIbdly; - uint32_t EmcObdly; - uint32_t EmcEInput; - uint32_t EmcEInputDuration; - uint32_t EmcPutermExtra; - uint32_t EmcPutermWidth; - uint32_t EmcQRst; - uint32_t EmcQSafe; - uint32_t EmcRdv; - uint32_t EmcRdvMask; - uint32_t EmcRdvEarly; - uint32_t EmcRdvEarlyMask; - uint32_t EmcQpop; - uint32_t EmcRefresh; - uint32_t EmcBurstRefreshNum; - uint32_t EmcPreRefreshReqCnt; - uint32_t EmcPdEx2Wr; - uint32_t EmcPdEx2Rd; - uint32_t EmcPChg2Pden; - uint32_t EmcAct2Pden; - uint32_t EmcAr2Pden; - uint32_t EmcRw2Pden; - uint32_t EmcCke2Pden; - uint32_t EmcPdex2Cke; - uint32_t EmcPdex2Mrr; - uint32_t EmcTxsr; - uint32_t EmcTxsrDll; - uint32_t EmcTcke; - uint32_t EmcTckesr; - uint32_t EmcTpd; - uint32_t EmcTfaw; - uint32_t EmcTrpab; - uint32_t EmcTClkStable; - uint32_t EmcTClkStop; - uint32_t EmcTRefBw; - uint32_t EmcFbioCfg5; - uint32_t EmcFbioCfg7; - uint32_t EmcFbioCfg8; - uint32_t EmcCmdMappingCmd0_0; - uint32_t EmcCmdMappingCmd0_1; - uint32_t EmcCmdMappingCmd0_2; - uint32_t EmcCmdMappingCmd1_0; - uint32_t EmcCmdMappingCmd1_1; - uint32_t EmcCmdMappingCmd1_2; - uint32_t EmcCmdMappingCmd2_0; - uint32_t EmcCmdMappingCmd2_1; - uint32_t EmcCmdMappingCmd2_2; - uint32_t EmcCmdMappingCmd3_0; - uint32_t EmcCmdMappingCmd3_1; - uint32_t EmcCmdMappingCmd3_2; - uint32_t EmcCmdMappingByte; - uint32_t EmcFbioSpare; - uint32_t EmcCfgRsv; - uint32_t EmcMrs; - uint32_t EmcEmrs; - uint32_t EmcEmrs2; - uint32_t EmcEmrs3; - uint32_t EmcMrw1; - uint32_t EmcMrw2; - uint32_t EmcMrw3; - uint32_t EmcMrw4; - uint32_t EmcMrw6; - uint32_t EmcMrw8; - uint32_t EmcMrw9; - uint32_t EmcMrw10; - uint32_t EmcMrw12; - uint32_t EmcMrw13; - uint32_t EmcMrw14; - uint32_t EmcMrwExtra; - uint32_t EmcWarmBootMrwExtra; - uint32_t EmcWarmBootExtraModeRegWriteEnable; - uint32_t EmcExtraModeRegWriteEnable; - uint32_t EmcMrwResetCommand; - uint32_t EmcMrwResetNInitWait; - uint32_t EmcMrsWaitCnt; - uint32_t EmcMrsWaitCnt2; - uint32_t EmcCfg; - uint32_t EmcCfg2; - uint32_t EmcCfgPipe; - uint32_t EmcCfgPipeClk; - uint32_t EmcFdpdCtrlCmdNoRamp; - uint32_t EmcCfgUpdate; - uint32_t EmcDbg; - uint32_t EmcDbgWriteMux; - uint32_t EmcCmdQ; - uint32_t EmcMc2EmcQ; - uint32_t EmcDynSelfRefControl; - uint32_t AhbArbitrationXbarCtrlMemInitDone; - uint32_t EmcCfgDigDll; - uint32_t EmcCfgDigDll_1; - uint32_t EmcCfgDigDllPeriod; - uint32_t EmcDevSelect; - uint32_t EmcSelDpdCtrl; - uint32_t EmcFdpdCtrlDq; - uint32_t EmcFdpdCtrlCmd; - uint32_t EmcPmacroIbVrefDq_0; - uint32_t EmcPmacroIbVrefDq_1; - uint32_t EmcPmacroIbVrefDqs_0; - uint32_t EmcPmacroIbVrefDqs_1; - uint32_t EmcPmacroIbRxrt; - uint32_t EmcCfgPipe1; - uint32_t EmcCfgPipe2; - uint32_t EmcPmacroQuseDdllRank0_0; - uint32_t EmcPmacroQuseDdllRank0_1; - uint32_t EmcPmacroQuseDdllRank0_2; - uint32_t EmcPmacroQuseDdllRank0_3; - uint32_t EmcPmacroQuseDdllRank0_4; - uint32_t EmcPmacroQuseDdllRank0_5; - uint32_t EmcPmacroQuseDdllRank1_0; - uint32_t EmcPmacroQuseDdllRank1_1; - uint32_t EmcPmacroQuseDdllRank1_2; - uint32_t EmcPmacroQuseDdllRank1_3; - uint32_t EmcPmacroQuseDdllRank1_4; - uint32_t EmcPmacroQuseDdllRank1_5; - uint32_t EmcPmacroObDdllLongDqRank0_0; - uint32_t EmcPmacroObDdllLongDqRank0_1; - uint32_t EmcPmacroObDdllLongDqRank0_2; - uint32_t EmcPmacroObDdllLongDqRank0_3; - uint32_t EmcPmacroObDdllLongDqRank0_4; - uint32_t EmcPmacroObDdllLongDqRank0_5; - uint32_t EmcPmacroObDdllLongDqRank1_0; - uint32_t EmcPmacroObDdllLongDqRank1_1; - uint32_t EmcPmacroObDdllLongDqRank1_2; - uint32_t EmcPmacroObDdllLongDqRank1_3; - uint32_t EmcPmacroObDdllLongDqRank1_4; - uint32_t EmcPmacroObDdllLongDqRank1_5; - uint32_t EmcPmacroObDdllLongDqsRank0_0; - uint32_t EmcPmacroObDdllLongDqsRank0_1; - uint32_t EmcPmacroObDdllLongDqsRank0_2; - uint32_t EmcPmacroObDdllLongDqsRank0_3; - uint32_t EmcPmacroObDdllLongDqsRank0_4; - uint32_t EmcPmacroObDdllLongDqsRank0_5; - uint32_t EmcPmacroObDdllLongDqsRank1_0; - uint32_t EmcPmacroObDdllLongDqsRank1_1; - uint32_t EmcPmacroObDdllLongDqsRank1_2; - uint32_t EmcPmacroObDdllLongDqsRank1_3; - uint32_t EmcPmacroObDdllLongDqsRank1_4; - uint32_t EmcPmacroObDdllLongDqsRank1_5; - uint32_t EmcPmacroIbDdllLongDqsRank0_0; - uint32_t EmcPmacroIbDdllLongDqsRank0_1; - uint32_t EmcPmacroIbDdllLongDqsRank0_2; - uint32_t EmcPmacroIbDdllLongDqsRank0_3; - uint32_t EmcPmacroIbDdllLongDqsRank1_0; - uint32_t EmcPmacroIbDdllLongDqsRank1_1; - uint32_t EmcPmacroIbDdllLongDqsRank1_2; - uint32_t EmcPmacroIbDdllLongDqsRank1_3; - uint32_t EmcPmacroDdllLongCmd_0; - uint32_t EmcPmacroDdllLongCmd_1; - uint32_t EmcPmacroDdllLongCmd_2; - uint32_t EmcPmacroDdllLongCmd_3; - uint32_t EmcPmacroDdllLongCmd_4; - uint32_t EmcPmacroDdllShortCmd_0; - uint32_t EmcPmacroDdllShortCmd_1; - uint32_t EmcPmacroDdllShortCmd_2; - uint32_t WarmBootWait; - uint32_t EmcOdtWrite; - uint32_t EmcZcalInterval; - uint32_t EmcZcalWaitCnt; - uint32_t EmcZcalMrwCmd; - uint32_t EmcMrsResetDll; - uint32_t EmcZcalInitDev0; - uint32_t EmcZcalInitDev1; - uint32_t EmcZcalInitWait; - uint32_t EmcZcalWarmColdBootEnables; - uint32_t EmcMrwLpddr2ZcalWarmBoot; - uint32_t EmcZqCalDdr3WarmBoot; - uint32_t EmcZqCalLpDdr4WarmBoot; - uint32_t EmcZcalWarmBootWait; - uint32_t EmcMrsWarmBootEnable; - uint32_t EmcMrsResetDllWait; - uint32_t EmcMrsExtra; - uint32_t EmcWarmBootMrsExtra; - uint32_t EmcEmrsDdr2DllEnable; - uint32_t EmcMrsDdr2DllReset; - uint32_t EmcEmrsDdr2OcdCalib; - uint32_t EmcDdr2Wait; - uint32_t EmcClkenOverride; - uint32_t EmcExtraRefreshNum; - uint32_t EmcClkenOverrideAllWarmBoot; - uint32_t McClkenOverrideAllWarmBoot; - uint32_t EmcCfgDigDllPeriodWarmBoot; - uint32_t PmcVddpSel; - uint32_t PmcVddpSelWait; - uint32_t PmcDdrPwr; - uint32_t PmcDdrCfg; - uint32_t PmcIoDpd3Req; - uint32_t PmcIoDpd3ReqWait; - uint32_t PmcIoDpd4ReqWait; - uint32_t PmcRegShort; - uint32_t PmcNoIoPower; - uint32_t PmcDdrCntrlWait; - uint32_t PmcDdrCntrl; - uint32_t EmcAcpdControl; - uint32_t EmcSwizzleRank0Byte0; - uint32_t EmcSwizzleRank0Byte1; - uint32_t EmcSwizzleRank0Byte2; - uint32_t EmcSwizzleRank0Byte3; - uint32_t EmcSwizzleRank1Byte0; - uint32_t EmcSwizzleRank1Byte1; - uint32_t EmcSwizzleRank1Byte2; - uint32_t EmcSwizzleRank1Byte3; - uint32_t EmcTxdsrvttgen; - uint32_t EmcDataBrlshft0; - uint32_t EmcDataBrlshft1; - uint32_t EmcDqsBrlshft0; - uint32_t EmcDqsBrlshft1; - uint32_t EmcCmdBrlshft0; - uint32_t EmcCmdBrlshft1; - uint32_t EmcCmdBrlshft2; - uint32_t EmcCmdBrlshft3; - uint32_t EmcQuseBrlshft0; - uint32_t EmcQuseBrlshft1; - uint32_t EmcQuseBrlshft2; - uint32_t EmcQuseBrlshft3; - uint32_t EmcDllCfg0; - uint32_t EmcDllCfg1; - uint32_t EmcPmcScratch1; - uint32_t EmcPmcScratch2; - uint32_t EmcPmcScratch3; - uint32_t EmcPmacroPadCfgCtrl; - uint32_t EmcPmacroVttgenCtrl0; - uint32_t EmcPmacroVttgenCtrl1; - uint32_t EmcPmacroVttgenCtrl2; - uint32_t EmcPmacroBrickCtrlRfu1; - uint32_t EmcPmacroCmdBrickCtrlFdpd; - uint32_t EmcPmacroBrickCtrlRfu2; - uint32_t EmcPmacroDataBrickCtrlFdpd; - uint32_t EmcPmacroBgBiasCtrl0; - uint32_t EmcPmacroDataPadRxCtrl; - uint32_t EmcPmacroCmdPadRxCtrl; - uint32_t EmcPmacroDataRxTermMode; - uint32_t EmcPmacroCmdRxTermMode; - uint32_t EmcPmacroDataPadTxCtrl; - uint32_t EmcPmacroCommonPadTxCtrl; - uint32_t EmcPmacroCmdPadTxCtrl; - uint32_t EmcCfg3; - uint32_t EmcPmacroTxPwrd0; - uint32_t EmcPmacroTxPwrd1; - uint32_t EmcPmacroTxPwrd2; - uint32_t EmcPmacroTxPwrd3; - uint32_t EmcPmacroTxPwrd4; - uint32_t EmcPmacroTxPwrd5; - uint32_t EmcConfigSampleDelay; - uint32_t EmcPmacroBrickMapping0; - uint32_t EmcPmacroBrickMapping1; - uint32_t EmcPmacroBrickMapping2; - uint32_t EmcPmacroTxSelClkSrc0; - uint32_t EmcPmacroTxSelClkSrc1; - uint32_t EmcPmacroTxSelClkSrc2; - uint32_t EmcPmacroTxSelClkSrc3; - uint32_t EmcPmacroTxSelClkSrc4; - uint32_t EmcPmacroTxSelClkSrc5; - uint32_t EmcPmacroDdllBypass; - uint32_t EmcPmacroDdllPwrd0; - uint32_t EmcPmacroDdllPwrd1; - uint32_t EmcPmacroDdllPwrd2; - uint32_t EmcPmacroCmdCtrl0; - uint32_t EmcPmacroCmdCtrl1; - uint32_t EmcPmacroCmdCtrl2; - uint32_t McEmemAdrCfg; - uint32_t McEmemAdrCfgDev0; - uint32_t McEmemAdrCfgDev1; - uint32_t McEmemAdrCfgChannelMask; - uint32_t McEmemAdrCfgBankMask0; - uint32_t McEmemAdrCfgBankMask1; - uint32_t McEmemAdrCfgBankMask2; - uint32_t McEmemCfg; - uint32_t McEmemArbCfg; - uint32_t McEmemArbOutstandingReq; - uint32_t McEmemArbRefpbHpCtrl; - uint32_t McEmemArbRefpbBankCtrl; - uint32_t McEmemArbTimingRcd; - uint32_t McEmemArbTimingRp; - uint32_t McEmemArbTimingRc; - uint32_t McEmemArbTimingRas; - uint32_t McEmemArbTimingFaw; - uint32_t McEmemArbTimingRrd; - uint32_t McEmemArbTimingRap2Pre; - uint32_t McEmemArbTimingWap2Pre; - uint32_t McEmemArbTimingR2R; - uint32_t McEmemArbTimingW2W; - uint32_t McEmemArbTimingR2W; - uint32_t McEmemArbTimingW2R; - uint32_t McEmemArbTimingRFCPB; - uint32_t McEmemArbDaTurns; - uint32_t McEmemArbDaCovers; - uint32_t McEmemArbMisc0; - uint32_t McEmemArbMisc1; - uint32_t McEmemArbMisc2; - uint32_t McEmemArbRing1Throttle; - uint32_t McEmemArbOverride; - uint32_t McEmemArbOverride1; - uint32_t McEmemArbRsv; - uint32_t McDaCfg0; - uint32_t McEmemArbTimingCcdmw; - uint32_t McClkenOverride; - uint32_t McStatControl; - uint32_t McVideoProtectBom; - uint32_t McVideoProtectBomAdrHi; - uint32_t McVideoProtectSizeMb; - uint32_t McVideoProtectVprOverride; - uint32_t McVideoProtectVprOverride1; - uint32_t McVideoProtectGpuOverride0; - uint32_t McVideoProtectGpuOverride1; - uint32_t McSecCarveoutBom; - uint32_t McSecCarveoutAdrHi; - uint32_t McSecCarveoutSizeMb; - uint32_t McVideoProtectWriteAccess; - uint32_t McSecCarveoutProtectWriteAccess; - uint32_t McGeneralizedCarveout1Bom; - uint32_t McGeneralizedCarveout1BomHi; - uint32_t McGeneralizedCarveout1Size128kb; - uint32_t McGeneralizedCarveout1Access0; - uint32_t McGeneralizedCarveout1Access1; - uint32_t McGeneralizedCarveout1Access2; - uint32_t McGeneralizedCarveout1Access3; - uint32_t McGeneralizedCarveout1Access4; - uint32_t McGeneralizedCarveout1ForceInternalAccess0; - uint32_t McGeneralizedCarveout1ForceInternalAccess1; - uint32_t McGeneralizedCarveout1ForceInternalAccess2; - uint32_t McGeneralizedCarveout1ForceInternalAccess3; - uint32_t McGeneralizedCarveout1ForceInternalAccess4; - uint32_t McGeneralizedCarveout1Cfg0; - uint32_t McGeneralizedCarveout2Bom; - uint32_t McGeneralizedCarveout2BomHi; - uint32_t McGeneralizedCarveout2Size128kb; - uint32_t McGeneralizedCarveout2Access0; - uint32_t McGeneralizedCarveout2Access1; - uint32_t McGeneralizedCarveout2Access2; - uint32_t McGeneralizedCarveout2Access3; - uint32_t McGeneralizedCarveout2Access4; - uint32_t McGeneralizedCarveout2ForceInternalAccess0; - uint32_t McGeneralizedCarveout2ForceInternalAccess1; - uint32_t McGeneralizedCarveout2ForceInternalAccess2; - uint32_t McGeneralizedCarveout2ForceInternalAccess3; - uint32_t McGeneralizedCarveout2ForceInternalAccess4; - uint32_t McGeneralizedCarveout2Cfg0; - uint32_t McGeneralizedCarveout3Bom; - uint32_t McGeneralizedCarveout3BomHi; - uint32_t McGeneralizedCarveout3Size128kb; - uint32_t McGeneralizedCarveout3Access0; - uint32_t McGeneralizedCarveout3Access1; - uint32_t McGeneralizedCarveout3Access2; - uint32_t McGeneralizedCarveout3Access3; - uint32_t McGeneralizedCarveout3Access4; - uint32_t McGeneralizedCarveout3ForceInternalAccess0; - uint32_t McGeneralizedCarveout3ForceInternalAccess1; - uint32_t McGeneralizedCarveout3ForceInternalAccess2; - uint32_t McGeneralizedCarveout3ForceInternalAccess3; - uint32_t McGeneralizedCarveout3ForceInternalAccess4; - uint32_t McGeneralizedCarveout3Cfg0; - uint32_t McGeneralizedCarveout4Bom; - uint32_t McGeneralizedCarveout4BomHi; - uint32_t McGeneralizedCarveout4Size128kb; - uint32_t McGeneralizedCarveout4Access0; - uint32_t McGeneralizedCarveout4Access1; - uint32_t McGeneralizedCarveout4Access2; - uint32_t McGeneralizedCarveout4Access3; - uint32_t McGeneralizedCarveout4Access4; - uint32_t McGeneralizedCarveout4ForceInternalAccess0; - uint32_t McGeneralizedCarveout4ForceInternalAccess1; - uint32_t McGeneralizedCarveout4ForceInternalAccess2; - uint32_t McGeneralizedCarveout4ForceInternalAccess3; - uint32_t McGeneralizedCarveout4ForceInternalAccess4; - uint32_t McGeneralizedCarveout4Cfg0; - uint32_t McGeneralizedCarveout5Bom; - uint32_t McGeneralizedCarveout5BomHi; - uint32_t McGeneralizedCarveout5Size128kb; - uint32_t McGeneralizedCarveout5Access0; - uint32_t McGeneralizedCarveout5Access1; - uint32_t McGeneralizedCarveout5Access2; - uint32_t McGeneralizedCarveout5Access3; - uint32_t McGeneralizedCarveout5Access4; - uint32_t McGeneralizedCarveout5ForceInternalAccess0; - uint32_t McGeneralizedCarveout5ForceInternalAccess1; - uint32_t McGeneralizedCarveout5ForceInternalAccess2; - uint32_t McGeneralizedCarveout5ForceInternalAccess3; - uint32_t McGeneralizedCarveout5ForceInternalAccess4; - uint32_t McGeneralizedCarveout5Cfg0; - uint32_t EmcCaTrainingEnable; - uint32_t SwizzleRankByteEncode; - uint32_t BootRomPatchControl; - uint32_t BootRomPatchData; - uint32_t McMtsCarveoutBom; - uint32_t McMtsCarveoutAdrHi; - uint32_t McMtsCarveoutSizeMb; - uint32_t McMtsCarveoutRegCtrl; -} sdram_params_erista_t; - -typedef struct { - NvBootMemoryType MemoryType; - uint32_t PllMInputDivider; - uint32_t PllMFeedbackDivider; - uint32_t PllMStableTime; - uint32_t PllMSetupControl; - uint32_t PllMPostDivider; - uint32_t PllMKCP; - uint32_t PllMKVCO; - uint32_t EmcBctSpare0; - uint32_t EmcBctSpare1; - uint32_t EmcBctSpare2; - uint32_t EmcBctSpare3; - uint32_t EmcBctSpare4; - uint32_t EmcBctSpare5; - uint32_t EmcBctSpare6; - uint32_t EmcBctSpare7; - uint32_t EmcBctSpare8; - uint32_t EmcBctSpare9; - uint32_t EmcBctSpare10; - uint32_t EmcBctSpare11; - uint32_t EmcBctSpare12; - uint32_t EmcBctSpare13; - uint32_t EmcBctSpareSecure0; - uint32_t EmcBctSpareSecure1; - uint32_t EmcBctSpareSecure2; - uint32_t EmcBctSpareSecure3; - uint32_t EmcBctSpareSecure4; - uint32_t EmcBctSpareSecure5; - uint32_t EmcBctSpareSecure6; - uint32_t EmcBctSpareSecure7; - uint32_t EmcBctSpareSecure8; - uint32_t EmcBctSpareSecure9; - uint32_t EmcBctSpareSecure10; - uint32_t EmcBctSpareSecure11; - uint32_t EmcBctSpareSecure12; - uint32_t EmcBctSpareSecure13; - uint32_t EmcBctSpareSecure14; - uint32_t EmcBctSpareSecure15; - uint32_t EmcBctSpareSecure16; - uint32_t EmcBctSpareSecure17; - uint32_t EmcBctSpareSecure18; - uint32_t EmcBctSpareSecure19; - uint32_t EmcBctSpareSecure20; - uint32_t EmcBctSpareSecure21; - uint32_t EmcBctSpareSecure22; - uint32_t EmcBctSpareSecure23; - uint32_t EmcClockSource; - uint32_t EmcClockSourceDll; - uint32_t ClkRstControllerPllmMisc2Override; - uint32_t ClkRstControllerPllmMisc2OverrideEnable; - uint32_t ClearClk2Mc1; - uint32_t EmcAutoCalInterval; - uint32_t EmcAutoCalConfig; - uint32_t EmcAutoCalConfig2; - uint32_t EmcAutoCalConfig3; - uint32_t EmcAutoCalConfig4; - uint32_t EmcAutoCalConfig5; - uint32_t EmcAutoCalConfig6; - uint32_t EmcAutoCalConfig7; - uint32_t EmcAutoCalConfig8; - uint32_t EmcAutoCalConfig9; - uint32_t EmcAutoCalVrefSel0; - uint32_t EmcAutoCalVrefSel1; - uint32_t EmcAutoCalChannel; - uint32_t EmcPmacroAutocalCfg0; - uint32_t EmcPmacroAutocalCfg1; - uint32_t EmcPmacroAutocalCfg2; - uint32_t EmcPmacroRxTerm; - uint32_t EmcPmacroDqTxDrv; - uint32_t EmcPmacroCaTxDrv; - uint32_t EmcPmacroCmdTxDrv; - uint32_t EmcPmacroAutocalCfgCommon; - uint32_t EmcPmacroZctrl; - uint32_t EmcAutoCalWait; - uint32_t EmcXm2CompPadCtrl; - uint32_t EmcXm2CompPadCtrl2; - uint32_t EmcXm2CompPadCtrl3; - uint32_t EmcAdrCfg; - uint32_t EmcPinProgramWait; - uint32_t EmcPinExtraWait; - uint32_t EmcPinGpioEn; - uint32_t EmcPinGpio; - uint32_t EmcTimingControlWait; - uint32_t EmcRc; - uint32_t EmcRfc; - uint32_t EmcRfcPb; - uint32_t EmcRefctrl2; - uint32_t EmcRfcSlr; - uint32_t EmcRas; - uint32_t EmcRp; - uint32_t EmcR2r; - uint32_t EmcW2w; - uint32_t EmcR2w; - uint32_t EmcW2r; - uint32_t EmcR2p; - uint32_t EmcW2p; - uint32_t EmcTppd; - uint32_t EmcTrtm; - uint32_t EmcTwtm; - uint32_t EmcTratm; - uint32_t EmcTwatm; - uint32_t EmcTr2ref; - uint32_t EmcCcdmw; - uint32_t EmcRdRcd; - uint32_t EmcWrRcd; - uint32_t EmcRrd; - uint32_t EmcRext; - uint32_t EmcWext; - uint32_t EmcWdv; - uint32_t EmcWdvChk; - uint32_t EmcWsv; - uint32_t EmcWev; - uint32_t EmcWdvMask; - uint32_t EmcWsDuration; - uint32_t EmcWeDuration; - uint32_t EmcQUse; - uint32_t EmcQuseWidth; - uint32_t EmcIbdly; - uint32_t EmcObdly; - uint32_t EmcEInput; - uint32_t EmcEInputDuration; - uint32_t EmcPutermExtra; - uint32_t EmcPutermWidth; - uint32_t EmcQRst; - uint32_t EmcQSafe; - uint32_t EmcRdv; - uint32_t EmcRdvMask; - uint32_t EmcRdvEarly; - uint32_t EmcRdvEarlyMask; - uint32_t EmcQpop; - uint32_t EmcRefresh; - uint32_t EmcBurstRefreshNum; - uint32_t EmcPreRefreshReqCnt; - uint32_t EmcPdEx2Wr; - uint32_t EmcPdEx2Rd; - uint32_t EmcPChg2Pden; - uint32_t EmcAct2Pden; - uint32_t EmcAr2Pden; - uint32_t EmcRw2Pden; - uint32_t EmcCke2Pden; - uint32_t EmcPdex2Cke; - uint32_t EmcPdex2Mrr; - uint32_t EmcTxsr; - uint32_t EmcTxsrDll; - uint32_t EmcTcke; - uint32_t EmcTckesr; - uint32_t EmcTpd; - uint32_t EmcTfaw; - uint32_t EmcTrpab; - uint32_t EmcTClkStable; - uint32_t EmcTClkStop; - uint32_t EmcTRefBw; - uint32_t EmcFbioCfg5; - uint32_t EmcFbioCfg7; - uint32_t EmcFbioCfg8; - uint32_t EmcCmdMappingCmd0_0; - uint32_t EmcCmdMappingCmd0_1; - uint32_t EmcCmdMappingCmd0_2; - uint32_t EmcCmdMappingCmd1_0; - uint32_t EmcCmdMappingCmd1_1; - uint32_t EmcCmdMappingCmd1_2; - uint32_t EmcCmdMappingCmd2_0; - uint32_t EmcCmdMappingCmd2_1; - uint32_t EmcCmdMappingCmd2_2; - uint32_t EmcCmdMappingCmd3_0; - uint32_t EmcCmdMappingCmd3_1; - uint32_t EmcCmdMappingCmd3_2; - uint32_t EmcCmdMappingByte; - uint32_t EmcFbioSpare; - uint32_t EmcCfgRsv; - uint32_t EmcMrs; - uint32_t EmcEmrs; - uint32_t EmcEmrs2; - uint32_t EmcEmrs3; - uint32_t EmcMrw1; - uint32_t EmcMrw2; - uint32_t EmcMrw3; - uint32_t EmcMrw4; - uint32_t EmcMrw6; - uint32_t EmcMrw8; - uint32_t EmcMrw9; - uint32_t EmcMrw10; - uint32_t EmcMrw12; - uint32_t EmcMrw13; - uint32_t EmcMrw14; - uint32_t EmcMrwExtra; - uint32_t EmcWarmBootMrwExtra; - uint32_t EmcWarmBootExtraModeRegWriteEnable; - uint32_t EmcExtraModeRegWriteEnable; - uint32_t EmcMrwResetCommand; - uint32_t EmcMrwResetNInitWait; - uint32_t EmcMrsWaitCnt; - uint32_t EmcMrsWaitCnt2; - uint32_t EmcCfg; - uint32_t EmcCfg2; - uint32_t EmcCfgPipe; - uint32_t EmcCfgPipeClk; - uint32_t EmcFdpdCtrlCmdNoRamp; - uint32_t EmcCfgUpdate; - uint32_t EmcDbg; - uint32_t EmcDbgWriteMux; - uint32_t EmcCmdQ; - uint32_t EmcMc2EmcQ; - uint32_t EmcDynSelfRefControl; - uint32_t AhbArbitrationXbarCtrlMemInitDone; - uint32_t EmcCfgDigDll; - uint32_t EmcCfgDigDll_1; - uint32_t EmcCfgDigDllPeriod; - uint32_t EmcDevSelect; - uint32_t EmcSelDpdCtrl; - uint32_t EmcFdpdCtrlDq; - uint32_t EmcFdpdCtrlCmd; - uint32_t EmcPmacroIbVrefDq_0; - uint32_t EmcPmacroIbVrefDq_1; - uint32_t EmcPmacroIbVrefDqs_0; - uint32_t EmcPmacroIbVrefDqs_1; - uint32_t EmcPmacroIbRxrt; - uint32_t EmcCfgPipe1; - uint32_t EmcCfgPipe2; - uint32_t EmcPmacroQuseDdllRank0_0; - uint32_t EmcPmacroQuseDdllRank0_1; - uint32_t EmcPmacroQuseDdllRank0_2; - uint32_t EmcPmacroQuseDdllRank0_3; - uint32_t EmcPmacroQuseDdllRank0_4; - uint32_t EmcPmacroQuseDdllRank0_5; - uint32_t EmcPmacroQuseDdllRank1_0; - uint32_t EmcPmacroQuseDdllRank1_1; - uint32_t EmcPmacroQuseDdllRank1_2; - uint32_t EmcPmacroQuseDdllRank1_3; - uint32_t EmcPmacroQuseDdllRank1_4; - uint32_t EmcPmacroQuseDdllRank1_5; - uint32_t EmcPmacroObDdllLongDqRank0_0; - uint32_t EmcPmacroObDdllLongDqRank0_1; - uint32_t EmcPmacroObDdllLongDqRank0_2; - uint32_t EmcPmacroObDdllLongDqRank0_3; - uint32_t EmcPmacroObDdllLongDqRank0_4; - uint32_t EmcPmacroObDdllLongDqRank0_5; - uint32_t EmcPmacroObDdllLongDqRank1_0; - uint32_t EmcPmacroObDdllLongDqRank1_1; - uint32_t EmcPmacroObDdllLongDqRank1_2; - uint32_t EmcPmacroObDdllLongDqRank1_3; - uint32_t EmcPmacroObDdllLongDqRank1_4; - uint32_t EmcPmacroObDdllLongDqRank1_5; - uint32_t EmcPmacroObDdllLongDqsRank0_0; - uint32_t EmcPmacroObDdllLongDqsRank0_1; - uint32_t EmcPmacroObDdllLongDqsRank0_2; - uint32_t EmcPmacroObDdllLongDqsRank0_3; - uint32_t EmcPmacroObDdllLongDqsRank0_4; - uint32_t EmcPmacroObDdllLongDqsRank0_5; - uint32_t EmcPmacroObDdllLongDqsRank1_0; - uint32_t EmcPmacroObDdllLongDqsRank1_1; - uint32_t EmcPmacroObDdllLongDqsRank1_2; - uint32_t EmcPmacroObDdllLongDqsRank1_3; - uint32_t EmcPmacroObDdllLongDqsRank1_4; - uint32_t EmcPmacroObDdllLongDqsRank1_5; - uint32_t EmcPmacroIbDdllLongDqsRank0_0; - uint32_t EmcPmacroIbDdllLongDqsRank0_1; - uint32_t EmcPmacroIbDdllLongDqsRank0_2; - uint32_t EmcPmacroIbDdllLongDqsRank0_3; - uint32_t EmcPmacroIbDdllLongDqsRank1_0; - uint32_t EmcPmacroIbDdllLongDqsRank1_1; - uint32_t EmcPmacroIbDdllLongDqsRank1_2; - uint32_t EmcPmacroIbDdllLongDqsRank1_3; - uint32_t EmcPmacroDdllLongCmd_0; - uint32_t EmcPmacroDdllLongCmd_1; - uint32_t EmcPmacroDdllLongCmd_2; - uint32_t EmcPmacroDdllLongCmd_3; - uint32_t EmcPmacroDdllLongCmd_4; - uint32_t EmcPmacroDdllShortCmd_0; - uint32_t EmcPmacroDdllShortCmd_1; - uint32_t EmcPmacroDdllShortCmd_2; - uint32_t EmcPmacroDdllPeriodicOffset; - uint32_t WarmBootWait; - uint32_t EmcOdtWrite; - uint32_t EmcZcalInterval; - uint32_t EmcZcalWaitCnt; - uint32_t EmcZcalMrwCmd; - uint32_t EmcMrsResetDll; - uint32_t EmcZcalInitDev0; - uint32_t EmcZcalInitDev1; - uint32_t EmcZcalInitWait; - uint32_t EmcZcalWarmColdBootEnables; - uint32_t EmcMrwLpddr2ZcalWarmBoot; - uint32_t EmcZqCalDdr3WarmBoot; - uint32_t EmcZqCalLpDdr4WarmBoot; - uint32_t EmcZcalWarmBootWait; - uint32_t EmcMrsWarmBootEnable; - uint32_t EmcMrsResetDllWait; - uint32_t EmcMrsExtra; - uint32_t EmcWarmBootMrsExtra; - uint32_t EmcEmrsDdr2DllEnable; - uint32_t EmcMrsDdr2DllReset; - uint32_t EmcEmrsDdr2OcdCalib; - uint32_t EmcDdr2Wait; - uint32_t EmcClkenOverride; - uint32_t EmcExtraRefreshNum; - uint32_t EmcClkenOverrideAllWarmBoot; - uint32_t McClkenOverrideAllWarmBoot; - uint32_t EmcCfgDigDllPeriodWarmBoot; - uint32_t PmcVddpSel; - uint32_t PmcVddpSelWait; - uint32_t PmcDdrCfg; - uint32_t PmcIoDpd3Req; - uint32_t PmcIoDpd3ReqWait; - uint32_t PmcIoDpd4ReqWait; - uint32_t PmcRegShort; - uint32_t PmcNoIoPower; - uint32_t PmcDdrCntrlWait; - uint32_t PmcDdrCntrl; - uint32_t EmcAcpdControl; - uint32_t EmcSwizzleRank0Byte0; - uint32_t EmcSwizzleRank0Byte1; - uint32_t EmcSwizzleRank0Byte2; - uint32_t EmcSwizzleRank0Byte3; - uint32_t EmcSwizzleRank1Byte0; - uint32_t EmcSwizzleRank1Byte1; - uint32_t EmcSwizzleRank1Byte2; - uint32_t EmcSwizzleRank1Byte3; - uint32_t EmcTxdsrvttgen; - uint32_t EmcDataBrlshft0; - uint32_t EmcDataBrlshft1; - uint32_t EmcDqsBrlshft0; - uint32_t EmcDqsBrlshft1; - uint32_t EmcCmdBrlshft0; - uint32_t EmcCmdBrlshft1; - uint32_t EmcCmdBrlshft2; - uint32_t EmcCmdBrlshft3; - uint32_t EmcQuseBrlshft0; - uint32_t EmcQuseBrlshft1; - uint32_t EmcQuseBrlshft2; - uint32_t EmcQuseBrlshft3; - uint32_t EmcPmacroDllCfg0; - uint32_t EmcPmacroDllCfg1; - uint32_t EmcPmcScratch1; - uint32_t EmcPmcScratch2; - uint32_t EmcPmcScratch3; - uint32_t EmcPmacroPadCfgCtrl; - uint32_t EmcPmacroVttgenCtrl0; - uint32_t EmcPmacroVttgenCtrl1; - uint32_t EmcPmacroVttgenCtrl2; - uint32_t EmcPmacroDsrVttgenCtrl0; - uint32_t EmcPmacroBrickCtrlRfu1; - uint32_t EmcPmacroCmdBrickCtrlFdpd; - uint32_t EmcPmacroBrickCtrlRfu2; - uint32_t EmcPmacroDataBrickCtrlFdpd; - uint32_t EmcPmacroBgBiasCtrl0; - uint32_t EmcPmacroDataPadRxCtrl; - uint32_t EmcPmacroCmdPadRxCtrl; - uint32_t EmcPmacroDataRxTermMode; - uint32_t EmcPmacroCmdRxTermMode; - uint32_t EmcPmacroDataPadTxCtrl; - uint32_t EmcPmacroCmdPadTxCtrl; - uint32_t EmcCfg3; - uint32_t EmcPmacroTxPwrd0; - uint32_t EmcPmacroTxPwrd1; - uint32_t EmcPmacroTxPwrd2; - uint32_t EmcPmacroTxPwrd3; - uint32_t EmcPmacroTxPwrd4; - uint32_t EmcPmacroTxPwrd5; - uint32_t EmcConfigSampleDelay; - uint32_t EmcPmacroBrickMapping0; - uint32_t EmcPmacroBrickMapping1; - uint32_t EmcPmacroBrickMapping2; - uint32_t EmcPmacroTxSelClkSrc0; - uint32_t EmcPmacroTxSelClkSrc1; - uint32_t EmcPmacroTxSelClkSrc2; - uint32_t EmcPmacroTxSelClkSrc3; - uint32_t EmcPmacroTxSelClkSrc4; - uint32_t EmcPmacroTxSelClkSrc5; - uint32_t EmcPmacroPerbitFgcgCtrl0; - uint32_t EmcPmacroPerbitFgcgCtrl1; - uint32_t EmcPmacroPerbitFgcgCtrl2; - uint32_t EmcPmacroPerbitFgcgCtrl3; - uint32_t EmcPmacroPerbitFgcgCtrl4; - uint32_t EmcPmacroPerbitFgcgCtrl5; - uint32_t EmcPmacroPerbitRfuCtrl0; - uint32_t EmcPmacroPerbitRfuCtrl1; - uint32_t EmcPmacroPerbitRfuCtrl2; - uint32_t EmcPmacroPerbitRfuCtrl3; - uint32_t EmcPmacroPerbitRfuCtrl4; - uint32_t EmcPmacroPerbitRfuCtrl5; - uint32_t EmcPmacroPerbitRfu1Ctrl0; - uint32_t EmcPmacroPerbitRfu1Ctrl1; - uint32_t EmcPmacroPerbitRfu1Ctrl2; - uint32_t EmcPmacroPerbitRfu1Ctrl3; - uint32_t EmcPmacroPerbitRfu1Ctrl4; - uint32_t EmcPmacroPerbitRfu1Ctrl5; - uint32_t EmcPmacroDataPiCtrl; - uint32_t EmcPmacroCmdPiCtrl; - uint32_t EmcPmacroDdllBypass; - uint32_t EmcPmacroDdllPwrd0; - uint32_t EmcPmacroDdllPwrd1; - uint32_t EmcPmacroDdllPwrd2; - uint32_t EmcPmacroCmdCtrl0; - uint32_t EmcPmacroCmdCtrl1; - uint32_t EmcPmacroCmdCtrl2; - uint32_t McEmemAdrCfg; - uint32_t McEmemAdrCfgDev0; - uint32_t McEmemAdrCfgDev1; - uint32_t McEmemAdrCfgChannelMask; - uint32_t McEmemAdrCfgBankMask0; - uint32_t McEmemAdrCfgBankMask1; - uint32_t McEmemAdrCfgBankMask2; - uint32_t McEmemCfg; - uint32_t McEmemArbCfg; - uint32_t McEmemArbOutstandingReq; - uint32_t McEmemArbRefpbHpCtrl; - uint32_t McEmemArbRefpbBankCtrl; - uint32_t McEmemArbTimingRcd; - uint32_t McEmemArbTimingRp; - uint32_t McEmemArbTimingRc; - uint32_t McEmemArbTimingRas; - uint32_t McEmemArbTimingFaw; - uint32_t McEmemArbTimingRrd; - uint32_t McEmemArbTimingRap2Pre; - uint32_t McEmemArbTimingWap2Pre; - uint32_t McEmemArbTimingR2R; - uint32_t McEmemArbTimingW2W; - uint32_t McEmemArbTimingR2W; - uint32_t McEmemArbTimingW2R; - uint32_t McEmemArbTimingRFCPB; - uint32_t McEmemArbDaTurns; - uint32_t McEmemArbDaCovers; - uint32_t McEmemArbMisc0; - uint32_t McEmemArbMisc1; - uint32_t McEmemArbMisc2; - uint32_t McEmemArbRing1Throttle; - uint32_t McEmemArbOverride; - uint32_t McEmemArbOverride1; - uint32_t McEmemArbRsv; - uint32_t McDaCfg0; - uint32_t McEmemArbTimingCcdmw; - uint32_t McClkenOverride; - uint32_t McStatControl; - uint32_t McVideoProtectBom; - uint32_t McVideoProtectBomAdrHi; - uint32_t McVideoProtectSizeMb; - uint32_t McVideoProtectVprOverride; - uint32_t McVideoProtectVprOverride1; - uint32_t McVideoProtectGpuOverride0; - uint32_t McVideoProtectGpuOverride1; - uint32_t McSecCarveoutBom; - uint32_t McSecCarveoutAdrHi; - uint32_t McSecCarveoutSizeMb; - uint32_t McVideoProtectWriteAccess; - uint32_t McSecCarveoutProtectWriteAccess; - uint32_t McGeneralizedCarveout1Bom; - uint32_t McGeneralizedCarveout1BomHi; - uint32_t McGeneralizedCarveout1Size128kb; - uint32_t McGeneralizedCarveout1Access0; - uint32_t McGeneralizedCarveout1Access1; - uint32_t McGeneralizedCarveout1Access2; - uint32_t McGeneralizedCarveout1Access3; - uint32_t McGeneralizedCarveout1Access4; - uint32_t McGeneralizedCarveout1ForceInternalAccess0; - uint32_t McGeneralizedCarveout1ForceInternalAccess1; - uint32_t McGeneralizedCarveout1ForceInternalAccess2; - uint32_t McGeneralizedCarveout1ForceInternalAccess3; - uint32_t McGeneralizedCarveout1ForceInternalAccess4; - uint32_t McGeneralizedCarveout1Cfg0; - uint32_t McGeneralizedCarveout2Bom; - uint32_t McGeneralizedCarveout2BomHi; - uint32_t McGeneralizedCarveout2Size128kb; - uint32_t McGeneralizedCarveout2Access0; - uint32_t McGeneralizedCarveout2Access1; - uint32_t McGeneralizedCarveout2Access2; - uint32_t McGeneralizedCarveout2Access3; - uint32_t McGeneralizedCarveout2Access4; - uint32_t McGeneralizedCarveout2ForceInternalAccess0; - uint32_t McGeneralizedCarveout2ForceInternalAccess1; - uint32_t McGeneralizedCarveout2ForceInternalAccess2; - uint32_t McGeneralizedCarveout2ForceInternalAccess3; - uint32_t McGeneralizedCarveout2ForceInternalAccess4; - uint32_t McGeneralizedCarveout2Cfg0; - uint32_t McGeneralizedCarveout3Bom; - uint32_t McGeneralizedCarveout3BomHi; - uint32_t McGeneralizedCarveout3Size128kb; - uint32_t McGeneralizedCarveout3Access0; - uint32_t McGeneralizedCarveout3Access1; - uint32_t McGeneralizedCarveout3Access2; - uint32_t McGeneralizedCarveout3Access3; - uint32_t McGeneralizedCarveout3Access4; - uint32_t McGeneralizedCarveout3ForceInternalAccess0; - uint32_t McGeneralizedCarveout3ForceInternalAccess1; - uint32_t McGeneralizedCarveout3ForceInternalAccess2; - uint32_t McGeneralizedCarveout3ForceInternalAccess3; - uint32_t McGeneralizedCarveout3ForceInternalAccess4; - uint32_t McGeneralizedCarveout3Cfg0; - uint32_t McGeneralizedCarveout4Bom; - uint32_t McGeneralizedCarveout4BomHi; - uint32_t McGeneralizedCarveout4Size128kb; - uint32_t McGeneralizedCarveout4Access0; - uint32_t McGeneralizedCarveout4Access1; - uint32_t McGeneralizedCarveout4Access2; - uint32_t McGeneralizedCarveout4Access3; - uint32_t McGeneralizedCarveout4Access4; - uint32_t McGeneralizedCarveout4ForceInternalAccess0; - uint32_t McGeneralizedCarveout4ForceInternalAccess1; - uint32_t McGeneralizedCarveout4ForceInternalAccess2; - uint32_t McGeneralizedCarveout4ForceInternalAccess3; - uint32_t McGeneralizedCarveout4ForceInternalAccess4; - uint32_t McGeneralizedCarveout4Cfg0; - uint32_t McGeneralizedCarveout5Bom; - uint32_t McGeneralizedCarveout5BomHi; - uint32_t McGeneralizedCarveout5Size128kb; - uint32_t McGeneralizedCarveout5Access0; - uint32_t McGeneralizedCarveout5Access1; - uint32_t McGeneralizedCarveout5Access2; - uint32_t McGeneralizedCarveout5Access3; - uint32_t McGeneralizedCarveout5Access4; - uint32_t McGeneralizedCarveout5ForceInternalAccess0; - uint32_t McGeneralizedCarveout5ForceInternalAccess1; - uint32_t McGeneralizedCarveout5ForceInternalAccess2; - uint32_t McGeneralizedCarveout5ForceInternalAccess3; - uint32_t McGeneralizedCarveout5ForceInternalAccess4; - uint32_t McGeneralizedCarveout5Cfg0; - uint32_t EmcCaTrainingEnable; - uint32_t SwizzleRankByteEncode; - uint32_t BootRomPatchControl; - uint32_t BootRomPatchData; - uint32_t McMtsCarveoutBom; - uint32_t McMtsCarveoutAdrHi; - uint32_t McMtsCarveoutSizeMb; - uint32_t McMtsCarveoutRegCtrl; - uint32_t McUntranslatedRegionCheck; - uint32_t BCT_NA; -} sdram_params_mariko_t; - -#endif diff --git a/sept/sept-secondary/src/se.c b/sept/sept-secondary/src/se.c deleted file mode 100644 index 8368ab529..000000000 --- a/sept/sept-secondary/src/se.c +++ /dev/null @@ -1,800 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "utils.h" -#include "se.h" - -void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size); - -/* Globals for driver. */ -static unsigned int g_se_modulus_sizes[KEYSLOT_RSA_MAX]; -static unsigned int g_se_exp_sizes[KEYSLOT_RSA_MAX]; - -/* Initialize a SE linked list. */ -void NOINLINE ll_init(volatile se_ll_t *ll, void *buffer, size_t size) { - ll->num_entries = 0; /* 1 Entry. */ - - if (buffer != NULL) { - ll->addr_info.address = (uint32_t) get_physical_address(buffer); - ll->addr_info.size = (uint32_t) size; - } else { - ll->addr_info.address = 0; - ll->addr_info.size = 0; - } -} - -void se_check_error_status_reg(void) { - if (se_get_regs()->SE_ERR_STATUS) { - generic_panic(); - } -} - -void se_check_for_error(void) { - volatile tegra_se_t *se = se_get_regs(); - if (se->SE_INT_STATUS & 0x10000 || se->SE_STATUS & 3 || se->SE_ERR_STATUS) { - generic_panic(); - } -} - -void se_verify_flags_cleared(void) { - if (se_get_regs()->SE_STATUS & 3) { - generic_panic(); - } -} - -/* Set the flags for an AES keyslot. */ -void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Misc flags. */ - if (flags & ~0x80) { - se->SE_CRYPTO_KEYTABLE_ACCESS[keyslot] = ~flags; - } - - /* Disable keyslot reads. */ - if (flags & 0x80) { - se->SE_CRYPTO_SECURITY_PERKEY &= ~(1 << keyslot); - } -} - -/* Set the flags for an RSA keyslot. */ -void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_RSA_MAX) { - generic_panic(); - } - - /* Misc flags. */ - if (flags & ~0x80) { - /* TODO: Why are flags assigned this way? */ - se->SE_RSA_KEYTABLE_ACCESS[keyslot] = (((flags >> 4) & 4) | (flags & 3)) ^ 7; - } - - /* Disable keyslot reads. */ - if (flags & 0x80) { - se->SE_RSA_SECURITY_PERKEY &= ~(1 << keyslot); - } -} - -void clear_aes_keyslot(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Zero out the whole keyslot and IV. */ - for (unsigned int i = 0; i < 0x10; i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | i; - se->SE_CRYPTO_KEYTABLE_DATA = 0; - } -} - -void clear_rsa_keyslot(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_RSA_MAX) { - generic_panic(); - } - - /* Zero out the whole keyslot. */ - for (unsigned int i = 0; i < 0x40; i++) { - /* Select Keyslot Modulus[i] */ - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i | 0x40; - se->SE_RSA_KEYTABLE_DATA = 0; - } - for (unsigned int i = 0; i < 0x40; i++) { - /* Select Keyslot Expontent[i] */ - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i; - se->SE_RSA_KEYTABLE_DATA = 0; - } -} - -void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || key_size > KEYSIZE_AES_MAX) { - generic_panic(); - } - - for (size_t i = 0; i < (key_size >> 2); i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | i; - se->SE_CRYPTO_KEYTABLE_DATA = read32le(key, 4 * i); - } -} - -void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_RSA_MAX || modulus_size > KEYSIZE_RSA_MAX || exp_size > KEYSIZE_RSA_MAX) { - generic_panic(); - } - - for (size_t i = 0; i < (modulus_size >> 2); i++) { - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | 0x40 | i; - se->SE_RSA_KEYTABLE_DATA = read32be(modulus, (4 * (modulus_size >> 2)) - (4 * i) - 4); - } - - for (size_t i = 0; i < (exp_size >> 2); i++) { - se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i; - se->SE_RSA_KEYTABLE_DATA = read32be(exponent, (4 * (exp_size >> 2)) - (4 * i) - 4); - } - - g_se_modulus_sizes[keyslot] = modulus_size; - g_se_exp_sizes[keyslot] = exp_size; -} - -void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || iv_size > 0x10) { - generic_panic(); - } - - for (size_t i = 0; i < (iv_size >> 2); i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; - se->SE_CRYPTO_KEYTABLE_DATA = read32le(iv, 4 * i); - } -} - -void clear_aes_keyslot_iv(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - for (size_t i = 0; i < (0x10 >> 2); i++) { - se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | 8 | i; - se->SE_CRYPTO_KEYTABLE_DATA = 0; - } -} - -void set_se_ctr(const void *ctr) { - for (unsigned int i = 0; i < 4; i++) { - se_get_regs()->SE_CRYPTO_LINEAR_CTR[i] = read32le(ctr, i * 4); - } -} - -void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot_dst >= KEYSLOT_AES_MAX || keyslot_src >= KEYSLOT_AES_MAX || wrapped_key_size > KEYSIZE_AES_MAX) { - generic_panic(); - } - - se->SE_CONFIG = (ALG_AES_DEC | DST_KEYTAB); - se->SE_CRYPTO_CONFIG = keyslot_src << 24; - se->SE_CRYPTO_LAST_BLOCK = 0; - se->SE_CRYPTO_KEYTABLE_DST = keyslot_dst << 8; - - trigger_se_blocking_op(OP_START, NULL, 0, wrapped_key, wrapped_key_size); -} - -void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - uint8_t ALIGN(16) stack_buf[KEYSIZE_RSA_MAX]; - - if (keyslot >= KEYSLOT_RSA_MAX || src_size > KEYSIZE_RSA_MAX || dst_size > KEYSIZE_RSA_MAX) { - generic_panic(); - } - - /* Endian swap the input. */ - for (size_t i = 0; i < src_size; i++) { - stack_buf[i] = *((uint8_t *)src + src_size - i - 1); - } - - se->SE_CONFIG = (ALG_RSA | DST_RSAREG); - se->SE_RSA_CONFIG = keyslot << 24; - se->SE_RSA_KEY_SIZE = (g_se_modulus_sizes[keyslot] >> 6) - 1; - se->SE_RSA_EXP_SIZE = g_se_exp_sizes[keyslot] >> 2; - - trigger_se_blocking_op(OP_START, NULL, 0, stack_buf, src_size); - se_get_exp_mod_output(dst, dst_size); -} - -void se_get_exp_mod_output(void *buf, size_t size) { - size_t num_dwords = (size >> 2); - - if (num_dwords < 1) { - return; - } - - uint32_t *p_out = ((uint32_t *)buf) + num_dwords - 1; - uint32_t offset = 0; - - /* Copy endian swapped output. */ - while (num_dwords) { - *p_out = read32be(se_get_regs()->SE_RSA_OUTPUT, offset); - offset += 4; - p_out--; - num_dwords--; - } -} - -bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const void *modulus, size_t modulus_size, const void *data, size_t data_size) { - uint8_t message[RSA_2048_BYTES]; - uint8_t h_buf[0x24]; - - /* Hardcode RSA with keyslot 0. */ - const uint8_t public_exponent[4] = {0x00, 0x01, 0x00, 0x01}; - set_rsa_keyslot(0, modulus, modulus_size, public_exponent, sizeof(public_exponent)); - se_synchronous_exp_mod(0, message, sizeof(message), signature, signature_size); - - /* Validate sanity byte. */ - if (message[RSA_2048_BYTES - 1] != 0xBC) { - return false; - } - - /* Copy Salt into MGF1 Hash Buffer. */ - memset(h_buf, 0, sizeof(h_buf)); - memcpy(h_buf, message + RSA_2048_BYTES - 0x20 - 0x1, 0x20); - - /* Decrypt maskedDB (via inline MGF1). */ - uint8_t seed = 0; - uint8_t mgf1_buf[0x20]; - for (unsigned int ofs = 0; ofs < RSA_2048_BYTES - 0x20 - 1; ofs += 0x20) { - h_buf[sizeof(h_buf) - 1] = seed++; - se_calculate_sha256(mgf1_buf, h_buf, sizeof(h_buf)); - for (unsigned int i = ofs; i < ofs + 0x20 && i < RSA_2048_BYTES - 0x20 - 1; i++) { - message[i] ^= mgf1_buf[i - ofs]; - } - } - - /* Constant lmask for rsa-2048-pss. */ - message[0] &= 0x7F; - - /* Validate DB is of the form 0000...0001. */ - for (unsigned int i = 0; i < RSA_2048_BYTES - 0x20 - 0x20 - 1 - 1; i++) { - if (message[i] != 0) { - return false; - } - } - if (message[RSA_2048_BYTES - 0x20 - 0x20 - 1 - 1] != 1) { - return false; - } - - /* Check hash correctness. */ - uint8_t validate_buf[8 + 0x20 + 0x20]; - uint8_t validate_hash[0x20]; - - memset(validate_buf, 0, sizeof(validate_buf)); - se_calculate_sha256(&validate_buf[8], data, data_size); - memcpy(&validate_buf[0x28], &message[RSA_2048_BYTES - 0x20 - 0x20 - 1], 0x20); - se_calculate_sha256(validate_hash, validate_buf, sizeof(validate_buf)); - return memcmp(h_buf, validate_hash, 0x20) == 0; -} - -void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - se_ll_t in_ll; - se_ll_t out_ll; - - ll_init(&in_ll, (void *)src, src_size); - ll_init(&out_ll, dst, dst_size); - - /* Set the LLs. */ - se->SE_IN_LL_ADDR = (uint32_t) get_physical_address(&in_ll); - se->SE_OUT_LL_ADDR = (uint32_t) get_physical_address(&out_ll); - - /* Set registers for operation. */ - se->SE_ERR_STATUS = se->SE_ERR_STATUS; - se->SE_INT_STATUS = se->SE_INT_STATUS; - se->SE_OPERATION = op; - - while (!(se->SE_INT_STATUS & 0x10)) { /* Wait a while */ } - se_check_for_error(); -} - -/* Secure AES Functionality. */ -void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, size_t src_size) { - uint8_t block[0x10] = {0}; - - if (src_size > sizeof(block) || dst_size > sizeof(block)) { - generic_panic(); - } - - /* Load src data into block. */ - if (src_size != 0) { - memcpy(block, src, src_size); - } - - /* Trigger AES operation. */ - se_get_regs()->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, block, sizeof(block), block, sizeof(block)); - - /* Copy output data into dst. */ - if (dst_size != 0) { - memcpy(dst, block, dst_size); - } -} - -void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || ctr_size != 0x10) { - generic_panic(); - } - unsigned int num_blocks = src_size >> 4; - - /* Unknown what this write does, but official code writes it for CTR mode. */ - se->SE_SPARE = 1; - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x91E; - set_se_ctr(ctr); - - /* Handle any aligned blocks. */ - size_t aligned_size = (size_t)num_blocks << 4; - if (aligned_size) { - se->SE_CRYPTO_LAST_BLOCK = num_blocks - 1; - trigger_se_blocking_op(OP_START, dst, dst_size, src, aligned_size); - } - - /* Handle final, unaligned block. */ - if (aligned_size < dst_size && aligned_size < src_size) { - size_t last_block_size = dst_size - aligned_size; - if (src_size < dst_size) { - last_block_size = src_size - aligned_size; - } - se_perform_aes_block_operation(dst + aligned_size, last_block_size, (uint8_t *)src + aligned_size, src_size - aligned_size); - } -} - -void se_aes_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, unsigned int config_high) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) { - generic_panic(); - } - - /* Set configuration high (256-bit vs 128-bit) based on parameter. */ - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY) | (config_high << 16); - se->SE_CRYPTO_CONFIG = keyslot << 24 | 0x100; - se_perform_aes_block_operation(dst, 0x10, src, 0x10); -} - -void se_aes_128_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - se_aes_ecb_encrypt_block(keyslot, dst, dst_size, src, src_size, 0); -} - -void se_aes_256_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - se_aes_ecb_encrypt_block(keyslot, dst, dst_size, src, src_size, 0x202); -} - -void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) { - generic_panic(); - } - - se->SE_CONFIG = (ALG_AES_DEC | DST_MEMORY); - se->SE_CRYPTO_CONFIG = keyslot << 24; - se_perform_aes_block_operation(dst, 0x10, src, 0x10); -} - -void shift_left_xor_rb(uint8_t *key) { - uint8_t prev_high_bit = 0; - for (unsigned int i = 0; i < 0x10; i++) { - uint8_t cur_byte = key[0xF - i]; - key[0xF - i] = (cur_byte << 1) | (prev_high_bit); - prev_high_bit = cur_byte >> 7; - } - if (prev_high_bit) { - key[0xF] ^= 0x87; - } -} - -void shift_left_xor_rb_le(uint8_t *key) { - uint8_t prev_high_bit = 0; - for (unsigned int i = 0; i < 0x10; i++) { - uint8_t cur_byte = key[i]; - key[i] = (cur_byte << 1) | (prev_high_bit); - prev_high_bit = cur_byte >> 7; - } - if (prev_high_bit) { - key[0x0] ^= 0x87; - } -} - -void aes_128_xts_nintendo_get_tweak(uint8_t *tweak, size_t sector) { - for (int i = 0xF; i >= 0; i--) { /* Nintendo LE custom tweak... */ - tweak[i] = (unsigned char)(sector & 0xFF); - sector >>= 8; - } -} - -void aes_128_xts_nintendo_xor_with_tweak(unsigned int keyslot, size_t sector, uint8_t *dst, const uint8_t *src, size_t size) { - if ((size & 0xF) || size == 0) { - generic_panic(); - } - uint8_t tweak[0x10]; - aes_128_xts_nintendo_get_tweak(tweak, sector); - se_aes_128_ecb_encrypt_block(keyslot, tweak, sizeof(tweak), tweak, sizeof(tweak)); - - for (unsigned int block = 0; block < (size >> 4); block++) { - for (unsigned int i = 0; i < 0x10; i++) { - dst[(block << 4) | i] = src[(block << 4) | i] ^ tweak[i]; - } - shift_left_xor_rb_le(tweak); - } -} - -void aes_128_xts_nintendo_crypt_sector(unsigned int keyslot_1, unsigned int keyslot_2, size_t sector, bool encrypt, void *dst, const void *src, size_t size) { - volatile tegra_se_t *se = se_get_regs(); - - if ((size & 0xF) || size == 0) { - generic_panic(); - } - - /* XOR. */ - aes_128_xts_nintendo_xor_with_tweak(keyslot_2, sector, dst, src, size); - - /* Encrypt/Decrypt. */ - if (encrypt) { - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY); - se->SE_CRYPTO_CONFIG = keyslot_1 << 24 | 0x100; - } else { - se->SE_CONFIG = (ALG_AES_DEC | DST_MEMORY); - se->SE_CRYPTO_CONFIG = keyslot_1 << 24; - } - se->SE_CRYPTO_LAST_BLOCK = (size >> 4) - 1; - trigger_se_blocking_op(OP_START, dst, size, src, size); - - /* XOR. */ - aes_128_xts_nintendo_xor_with_tweak(keyslot_2, sector, dst, dst, size); -} - -/* Encrypt with AES-XTS (Nintendo's custom tweak). */ -void se_aes_128_xts_nintendo_encrypt(unsigned int keyslot_1, unsigned int keyslot_2, size_t base_sector, void *dst, const void *src, size_t size, unsigned int sector_size) { - if ((size & 0xF) || size == 0) { - generic_panic(); - } - size_t sector = base_sector; - for (size_t ofs = 0; ofs < size; ofs += sector_size) { - aes_128_xts_nintendo_crypt_sector(keyslot_1, keyslot_2, sector, true, dst + ofs, src + ofs, sector_size); - sector++; - } -} - -/* Decrypt with AES-XTS (Nintendo's custom tweak). */ -void se_aes_128_xts_nintendo_decrypt(unsigned int keyslot_1, unsigned int keyslot_2, size_t base_sector, void *dst, const void *src, size_t size, unsigned int sector_size) { - if ((size & 0xF) || size == 0) { - generic_panic(); - } - size_t sector = base_sector; - for (size_t ofs = 0; ofs < size; ofs += sector_size) { - aes_128_xts_nintendo_crypt_sector(keyslot_1, keyslot_2, sector, false, dst + ofs, src + ofs, sector_size); - sector++; - } -} - -void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size, unsigned int config_high) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Generate the derived key, to be XOR'd with final output block. */ - uint8_t ALIGN(16) derived_key[0x10] = {0}; - se_aes_ecb_encrypt_block(keyslot, derived_key, sizeof(derived_key), derived_key, sizeof(derived_key), config_high); - shift_left_xor_rb(derived_key); - if (data_size & 0xF) { - shift_left_xor_rb(derived_key); - } - - se->SE_CONFIG = (ALG_AES_ENC | DST_HASHREG) | (config_high << 16); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | (0x145); - clear_aes_keyslot_iv(keyslot); - - unsigned int num_blocks = (data_size + 0xF) >> 4; - /* Handle aligned blocks. */ - if (num_blocks > 1) { - se->SE_CRYPTO_LAST_BLOCK = num_blocks - 2; - trigger_se_blocking_op(OP_START, NULL, 0, data, data_size); - se->SE_CRYPTO_CONFIG |= 0x80; - } - - /* Create final block. */ - uint8_t ALIGN(16) last_block[0x10] = {0}; - if (data_size & 0xF) { - memcpy(last_block, data + (data_size & ~0xF), data_size & 0xF); - last_block[data_size & 0xF] = 0x80; /* Last block = data || 100...0 */ - } else if (data_size >= 0x10) { - memcpy(last_block, data + data_size - 0x10, 0x10); - } - - for (unsigned int i = 0; i < 0x10; i++) { - last_block[i] ^= derived_key[i]; - } - - /* Perform last operation. */ - se->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, NULL, 0, last_block, sizeof(last_block)); - - /* Copy output CMAC. */ - for (unsigned int i = 0; i < (cmac_size >> 2); i++) { - ((uint32_t *)cmac)[i] = read32le(se->SE_HASH_RESULT, i << 2); - } -} - -void se_compute_aes_128_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size) { - se_compute_aes_cmac(keyslot, cmac, cmac_size, data, data_size, 0); -} -void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size) { - se_compute_aes_cmac(keyslot, cmac, cmac_size, data, data_size, 0x202); -} - -void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || src_size < 0x10) { - generic_panic(); - } - - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY) | (0x202 << 16); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x144; - set_aes_keyslot_iv(keyslot, iv, 0x10); - se->SE_CRYPTO_LAST_BLOCK = (src_size >> 4) - 1; - trigger_se_blocking_op(OP_START, dst, dst_size, src, src_size); -} - -void se_aes_128_cbc_decrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX || src_size < 0x10) { - generic_panic(); - } - - se->SE_CONFIG = (ALG_AES_DEC | DST_MEMORY) | (0x000 << 16); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x66; - clear_aes_keyslot_iv(keyslot); - se->SE_CRYPTO_LAST_BLOCK = (src_size >> 4) - 1; - trigger_se_blocking_op(OP_START, dst, dst_size, src, src_size); -} - -/* SHA256 Implementation. */ -void se_calculate_sha256(void *dst, const void *src, size_t src_size) { - volatile tegra_se_t *se = se_get_regs(); - - /* Setup config for SHA256, size = BITS(src_size) */ - se->SE_CONFIG = (ENCMODE_SHA256 | ALG_SHA | DST_HASHREG); - se->SE_SHA_CONFIG = 1; - se->SE_SHA_MSG_LENGTH[0] = (uint32_t)(src_size << 3); - se->SE_SHA_MSG_LENGTH[1] = 0; - se->SE_SHA_MSG_LENGTH[2] = 0; - se->SE_SHA_MSG_LENGTH[3] = 0; - se->SE_SHA_MSG_LEFT[0] = (uint32_t)(src_size << 3); - se->SE_SHA_MSG_LEFT[1] = 0; - se->SE_SHA_MSG_LEFT[2] = 0; - se->SE_SHA_MSG_LEFT[3] = 0; - - /* Trigger the operation. */ - trigger_se_blocking_op(OP_START, NULL, 0, src, src_size); - - /* Copy output hash. */ - for (unsigned int i = 0; i < (0x20 >> 2); i++) { - ((uint32_t *)dst)[i] = read32be(se->SE_HASH_RESULT, i << 2); - } -} - -/* RNG API */ -void se_initialize_rng(unsigned int keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* To initialize the RNG, we'll perform an RNG operation into an output buffer. */ - /* This will be discarded, when done. */ - uint8_t ALIGN(16) output_buf[0x10]; - - se->SE_RNG_SRC_CONFIG = 3; /* Entropy enable + Entropy lock enable */ - se->SE_RNG_RESEED_INTERVAL = 70001; - se->SE_CONFIG = (ALG_RNG | DST_MEMORY); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x108; - se->SE_RNG_CONFIG = 5; - se->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, output_buf, 0x10, NULL, 0); -} - -void se_generate_random(unsigned int keyslot, void *dst, size_t size) { - volatile tegra_se_t *se = se_get_regs(); - - if (keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - uint32_t num_blocks = size >> 4; - size_t aligned_size = num_blocks << 4; - se->SE_CONFIG = (ALG_RNG | DST_MEMORY); - se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x108; - se->SE_RNG_CONFIG = 4; - - if (num_blocks >= 1) { - se->SE_CRYPTO_LAST_BLOCK = num_blocks - 1; - trigger_se_blocking_op(OP_START, dst, aligned_size, NULL, 0); - } - if (size > aligned_size) { - se_perform_aes_block_operation(dst + aligned_size, size - aligned_size, NULL, 0); - } -} - -void se_generate_random_key(unsigned int dst_keyslot, unsigned int rng_keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - if (dst_keyslot >= KEYSLOT_AES_MAX || rng_keyslot >= KEYSLOT_AES_MAX) { - generic_panic(); - } - - /* Setup Config. */ - se->SE_CONFIG = (ALG_RNG | DST_KEYTAB); - se->SE_CRYPTO_CONFIG = (rng_keyslot << 24) | 0x108; - se->SE_RNG_CONFIG = 4; - se->SE_CRYPTO_LAST_BLOCK = 0; - - /* Generate low part of key. */ - se->SE_CRYPTO_KEYTABLE_DST = (dst_keyslot << 8); - trigger_se_blocking_op(OP_START, NULL, 0, NULL, 0); - /* Generate high part of key. */ - se->SE_CRYPTO_KEYTABLE_DST = (dst_keyslot << 8) | 1; - trigger_se_blocking_op(OP_START, NULL, 0, NULL, 0); -} - -/* SE context save API. */ -void se_set_in_context_save_mode(bool is_context_save_mode) { - volatile tegra_se_t *se = se_get_regs(); - - uint32_t val = se->SE_SE_SECURITY; - if (is_context_save_mode) { - val |= 0x10000; - } else { - val &= 0xFFFEFFFF; - } - se->SE_SE_SECURITY = val; - /* Perform a useless read from flags reg. */ - (void)(se->SE_STATUS); -} - -void se_generate_srk(unsigned int srkgen_keyslot) { - volatile tegra_se_t *se = se_get_regs(); - - se->SE_CONFIG = (ALG_RNG | DST_SRK); - se->SE_CRYPTO_CONFIG = (srkgen_keyslot << 24) | 0x108; - se->SE_RNG_CONFIG = 6; - se->SE_CRYPTO_LAST_BLOCK = 0; - trigger_se_blocking_op(OP_START, NULL, 0, NULL, 0); -} - -void se_encrypt_with_srk(void *dst, size_t dst_size, const void *src, size_t src_size) { - uint8_t output[0x80]; - uint8_t *aligned_out = (uint8_t *)(((uintptr_t)output + 0x7F) & ~0x3F); - if (dst_size > 0x10) { - generic_panic(); - } - - if (dst_size) { - trigger_se_blocking_op(OP_CTX_SAVE, aligned_out, dst_size, src, src_size); - memcpy(dst, aligned_out, dst_size); - } else { - trigger_se_blocking_op(OP_CTX_SAVE, aligned_out, 0, src, src_size); - } -} - -void se_save_context(unsigned int srkgen_keyslot, unsigned int rng_keyslot, void *dst) { - volatile tegra_se_t *se = se_get_regs(); - uint8_t _work_buf[0x80]; - uint8_t *work_buf = (uint8_t *)(((uintptr_t)_work_buf + 0x7F) & ~0x3F); - - /* Generate the SRK (context save encryption key). */ - se_generate_random_key(srkgen_keyslot, rng_keyslot); - se_generate_srk(srkgen_keyslot); - - se_generate_random(rng_keyslot, work_buf, 0x10); - - /* Save random initial block. */ - se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY); - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_MEM); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst, 0x10, work_buf, 0x10); - - /* Save Sticky Bits. */ - for (unsigned int i = 0; i < 0x2; i++) { - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_STICKY_BITS) | (i << CTX_SAVE_STICKY_BIT_INDEX_SHIFT); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x10 + (i * 0x10), 0x10, NULL, 0); - } - - /* Save AES Key Table. */ - for (unsigned int i = 0; i < KEYSLOT_AES_MAX; i++) { - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_LOW_BITS); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x30 + (i * 0x20), 0x10, NULL, 0); - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_HIGH_BITS); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x40 + (i * 0x20), 0x10, NULL, 0); - } - - /* Save AES Original IVs. */ - for (unsigned int i = 0; i < KEYSLOT_AES_MAX; i++) { - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_ORIGINAL_IV); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x230 + (i * 0x10), 0x10, NULL, 0); - } - - /* Save AES Updated IVs */ - for (unsigned int i = 0; i < KEYSLOT_AES_MAX; i++) { - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_KEYTABLE_AES) | (i << CTX_SAVE_KEY_INDEX_SHIFT) | (CTX_SAVE_KEY_UPDATED_IV); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x330 + (i * 0x10), 0x10, NULL, 0); - } - - /* Save RSA Keytable. */ - uint8_t *rsa_ctx_out = (uint8_t *)dst + 0x430; - for (unsigned int rsa_key = 0; rsa_key < KEYSLOT_RSA_MAX; rsa_key++) { - for (unsigned int mod_exp = 0; mod_exp < 2; mod_exp++) { - for (unsigned int sub_block = 0; sub_block < 0x10; sub_block++) { - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_KEYTABLE_RSA) | ((2 * rsa_key + (1 - mod_exp)) << CTX_SAVE_RSA_KEY_INDEX_SHIFT) | (sub_block << CTX_SAVE_RSA_KEY_BLOCK_INDEX_SHIFT); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(rsa_ctx_out, 0x10, NULL, 0); - rsa_ctx_out += 0x10; - } - } - } - - /* Save "Known Pattern. " */ - static const uint8_t context_save_known_pattern[0x10] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f}; - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_MEM); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(dst + 0x830, 0x10, context_save_known_pattern, 0x10); - - /* Save SRK into PMC registers. */ - se->SE_CTX_SAVE_CONFIG = (CTX_SAVE_SRC_SRK); - se->SE_CRYPTO_LAST_BLOCK = 0; - se_encrypt_with_srk(work_buf, 0, NULL, 0); - se->SE_CONFIG = 0; - se_encrypt_with_srk(work_buf, 0, NULL, 0); -} - diff --git a/sept/sept-secondary/src/se.h b/sept/sept-secondary/src/se.h deleted file mode 100644 index a29877177..000000000 --- a/sept/sept-secondary/src/se.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_SE_H -#define FUSEE_SE_H - -#define SE_BASE 0x70012000 -#define MAKE_SE_REG(n) MAKE_REG32(SE_BASE + n) - -#define KEYSLOT_SWITCH_LP0TZRAMKEY 0x2 -#define KEYSLOT_SWITCH_SRKGENKEY 0x8 -#define KEYSLOT_SWITCH_PACKAGE2KEY 0x8 -#define KEYSLOT_SWITCH_TEMPKEY 0x9 -#define KEYSLOT_SWITCH_SESSIONKEY 0xA -#define KEYSLOT_SWITCH_RNGKEY 0xB -#define KEYSLOT_SWITCH_MASTERKEY 0xC -#define KEYSLOT_SWITCH_DEVICEKEY 0xD - -/* This keyslot was added in 4.0.0. */ -#define KEYSLOT_SWITCH_4XNEWDEVICEKEYGENKEY 0xD -#define KEYSLOT_SWITCH_4XNEWCONSOLEKEYGENKEY 0xE -#define KEYSLOT_SWITCH_4XOLDDEVICEKEY 0xF - -/* This keyslot was added in 5.0.0. */ -#define KEYSLOT_SWITCH_5XNEWDEVICEKEYGENKEY 0xA - -/* Mariko keyslots. */ -#define KEYSLOT_SWITCH_MASTERKEY_MARIKO 0x7 - -#define KEYSLOT_AES_MAX 0x10 -#define KEYSLOT_RSA_MAX 0x2 - -#define KEYSIZE_AES_MAX 0x20 -#define KEYSIZE_RSA_MAX 0x100 - -#define ALG_SHIFT (12) -#define ALG_DEC_SHIFT (8) -#define ALG_NOP (0 << ALG_SHIFT) -#define ALG_AES_ENC (1 << ALG_SHIFT) -#define ALG_AES_DEC ((1 << ALG_DEC_SHIFT) | ALG_NOP) -#define ALG_RNG (2 << ALG_SHIFT) -#define ALG_SHA (3 << ALG_SHIFT) -#define ALG_RSA (4 << ALG_SHIFT) - -#define DST_SHIFT (2) -#define DST_MEMORY (0 << DST_SHIFT) -#define DST_HASHREG (1 << DST_SHIFT) -#define DST_KEYTAB (2 << DST_SHIFT) -#define DST_SRK (3 << DST_SHIFT) -#define DST_RSAREG (4 << DST_SHIFT) - -#define ENCMODE_SHIFT (24) -#define DECMODE_SHIFT (16) -#define ENCMODE_SHA256 (5 << ENCMODE_SHIFT) - -#define HASH_DISABLE (0x0) -#define HASH_ENABLE (0x1) - -#define OP_ABORT 0 -#define OP_START 1 -#define OP_RESTART 2 -#define OP_CTX_SAVE 3 -#define OP_RESTART_IN 4 - -#define CTX_SAVE_SRC_SHIFT 29 -#define CTX_SAVE_SRC_STICKY_BITS (0 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_KEYTABLE_AES (2 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_KEYTABLE_RSA (1 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_MEM (4 << CTX_SAVE_SRC_SHIFT) -#define CTX_SAVE_SRC_SRK (6 << CTX_SAVE_SRC_SHIFT) - -#define CTX_SAVE_KEY_LOW_BITS 0 -#define CTX_SAVE_KEY_HIGH_BITS 1 -#define CTX_SAVE_KEY_ORIGINAL_IV 2 -#define CTX_SAVE_KEY_UPDATED_IV 3 - -#define CTX_SAVE_STICKY_BIT_INDEX_SHIFT 24 -#define CTX_SAVE_KEY_INDEX_SHIFT 8 -#define CTX_SAVE_RSA_KEY_INDEX_SHIFT 16 -#define CTX_SAVE_RSA_KEY_BLOCK_INDEX_SHIFT 12 - -#define RSA_2048_BYTES 0x100 - -typedef struct { - uint32_t SE_SE_SECURITY; - uint32_t SE_TZRAM_SECURITY; - uint32_t SE_OPERATION; - uint32_t SE_INT_ENABLE; - uint32_t SE_INT_STATUS; - uint32_t SE_CONFIG; - uint32_t SE_IN_LL_ADDR; - uint32_t SE_IN_CUR_BYTE_ADDR; - uint32_t SE_IN_CUR_LL_ID; - uint32_t SE_OUT_LL_ADDR; - uint32_t SE_OUT_CUR_BYTE_ADDR; - uint32_t SE_OUT_CUR_LL_ID; - uint32_t SE_HASH_RESULT[0x10]; - uint32_t SE_CTX_SAVE_CONFIG; - uint32_t _0x74[0x63]; - uint32_t SE_SHA_CONFIG; - uint32_t SE_SHA_MSG_LENGTH[0x4]; - uint32_t SE_SHA_MSG_LEFT[0x4]; - uint32_t _0x224[0x17]; - uint32_t SE_CRYPTO_SECURITY_PERKEY; - uint32_t SE_CRYPTO_KEYTABLE_ACCESS[0x10]; - uint32_t _0x2C4[0x10]; - uint32_t SE_CRYPTO_CONFIG; - uint32_t SE_CRYPTO_LINEAR_CTR[0x4]; - uint32_t SE_CRYPTO_LAST_BLOCK; - uint32_t SE_CRYPTO_KEYTABLE_ADDR; - uint32_t SE_CRYPTO_KEYTABLE_DATA; - uint32_t _0x324[0x3]; - uint32_t SE_CRYPTO_KEYTABLE_DST; - uint32_t _0x334[0x3]; - uint32_t SE_RNG_CONFIG; - uint32_t SE_RNG_SRC_CONFIG; - uint32_t SE_RNG_RESEED_INTERVAL; - uint32_t _0x34C[0x2D]; - uint32_t SE_RSA_CONFIG; - uint32_t SE_RSA_KEY_SIZE; - uint32_t SE_RSA_EXP_SIZE; - uint32_t SE_RSA_SECURITY_PERKEY; - uint32_t SE_RSA_KEYTABLE_ACCESS[0x2]; - uint32_t _0x418[0x2]; - uint32_t SE_RSA_KEYTABLE_ADDR; - uint32_t SE_RSA_KEYTABLE_DATA; - uint32_t SE_RSA_OUTPUT[0x40]; - uint32_t _0x528[0xB6]; - uint32_t SE_STATUS; - uint32_t SE_ERR_STATUS; - uint32_t SE_MISC; - uint32_t SE_SPARE; - uint32_t SE_ENTROPY_DEBUG_COUNTER; - uint32_t _0x814; - uint32_t _0x818; - uint32_t _0x81C; - uint32_t _0x820[0x5F8]; -} tegra_se_t; - -typedef struct { - uint32_t address; - uint32_t size; -} se_addr_info_t; - -typedef struct { - uint32_t num_entries; /* Set to total entries - 1 */ - se_addr_info_t addr_info; /* This should really be an array...but for our use case it works. */ -} se_ll_t; - -static inline volatile tegra_se_t *se_get_regs(void) { - return (volatile tegra_se_t *)SE_BASE; -} - -void se_check_error_status_reg(void); -void se_check_for_error(void); -void se_trigger_interrupt(void); - -void se_validate_stored_vector(void); -void se_generate_stored_vector(void); - -void se_verify_flags_cleared(void); - -void set_aes_keyslot_flags(unsigned int keyslot, unsigned int flags); -void set_rsa_keyslot_flags(unsigned int keyslot, unsigned int flags); -void clear_aes_keyslot(unsigned int keyslot); -void clear_rsa_keyslot(unsigned int keyslot); - -void set_aes_keyslot(unsigned int keyslot, const void *key, size_t key_size); -void decrypt_data_into_keyslot(unsigned int keyslot_dst, unsigned int keyslot_src, const void *wrapped_key, size_t wrapped_key_size); -void set_rsa_keyslot(unsigned int keyslot, const void *modulus, size_t modulus_size, const void *exponent, size_t exp_size); -void set_aes_keyslot_iv(unsigned int keyslot, const void *iv, size_t iv_size); -void set_se_ctr(const void *ctr); - -/* Secure AES API */ -void se_aes_128_xts_nintendo_decrypt(unsigned int keyslot_1, unsigned int keyslot_2, unsigned int base_sector, void *dst, const void *src, size_t size, unsigned int sector_size); -void se_aes_128_xts_nintendo_encrypt(unsigned int keyslot_1, unsigned int keyslot_2, unsigned int base_sector, void *dst, const void *src, size_t size, unsigned int sector_size); -void se_compute_aes_128_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size); -void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size); -void se_aes_128_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -void se_aes_256_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -void se_aes_ctr_crypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *ctr, size_t ctr_size); -void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -void se_aes_256_cbc_encrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, const void *iv); -void se_aes_128_cbc_decrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); - -/* Hash API */ -void se_calculate_sha256(void *dst, const void *src, size_t src_size); - -/* RSA API */ -void se_get_exp_mod_output(void *buf, size_t size); -void se_synchronous_exp_mod(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size); -bool se_rsa2048_pss_verify(const void *signature, size_t signature_size, const void *modulus, size_t modulus_size, const void *data, size_t data_size); - -/* RNG API */ -void se_initialize_rng(unsigned int keyslot); -void se_generate_random(unsigned int keyslot, void *dst, size_t size); - -/* SE context save API. */ -void se_generate_srk(unsigned int srkgen_keyslot); -void se_set_in_context_save_mode(bool is_context_save_mode); -void se_generate_random_key(unsigned int dst_keyslot, unsigned int rng_keyslot); -void se_save_context(unsigned int srk_keyslot, unsigned int rng_keyslot, void *dst); - -#endif diff --git a/sept/sept-secondary/src/splash.c b/sept/sept-secondary/src/splash.c deleted file mode 100644 index bdfa64ebc..000000000 --- a/sept/sept-secondary/src/splash.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018 xamanthas - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include "splash.h" -#include "utils.h" -#include "../../../fusee/common/lz.h" - -static const uint8_t s_splash[] = {0x00, 0x34, 0x36, 0x4B, 0x34, 0x36, 0x4B, 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00, 0x30, 0x30, 0x00, 0x60, 0x60, 0x00, 0x81, 0x40, 0x81, 0x40, 0x00, 0x83, 0x00, 0x83, 0x00, 0x00, 0x86, 0x00, 0x86, 0x00, 0x00, 0x8C, 0x00, 0x8C, 0x00, 0x00, 0x84, 0x46, 0x84, 0x46, 0x4D, 0x4F, 0x62, 0x8D, 0x8E, 0x9A, 0xB3, 0xB4, 0xBC, 0xCC, 0xCD, 0xD2, 0xA6, 0xA7, 0xB0, 0x00, 0x75, 0x81, 0x04, 0x67, 0x68, 0x78, 0xC0, 0xC0, 0xC7, 0xF2, 0xF2, 0xF4, 0xFF, 0xFF, 0xFF, 0x00, 0x09, 0x15, 0x73, 0x75, 0x83, 0x00, 0x86, 0x24, 0x87, 0x40, 0x5A, 0x5C, 0x6D, 0xCC, 0xCD, 0xD2, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x04, 0x04, 0x00, 0x04, 0x04, 0xCC, 0xCD, 0xD2, 0x00, 0x15, 0x27, 0x00, 0x5D, 0x81, 0x07, 0xB3, 0xB4, 0xBC, 0xF2, 0xF2, 0xF4, 0xA6, 0xA7, 0xB0, 0x67, 0x68, 0x78, 0x00, 0x0C, 0x87, 0x46, 0xB3, 0xB4, 0xBC, 0xB3, 0xB4, 0xBC, 0x00, 0x86, 0x1E, 0x87, 0x43, 0x80, 0x81, 0x8F, 0x00, 0x06, 0x87, 0x3A, 0x00, 0x06, 0x86, 0x42, 0x80, 0x81, 0x8F, 0xD9, 0xD9, 0xDD, 0x00, 0x12, 0x87, 0x46, 0x5A, 0x5C, 0x6D, 0xF2, 0xF2, 0xF4, 0x00, 0x5A, 0x86, 0x4E, 0x9A, 0x9B, 0xA5, 0xD9, 0xD9, 0xDD, 0x41, 0x43, 0x56, 0x00, 0x06, 0x0F, 0x00, 0x0C, 0x87, 0x46, 0x41, 0x43, 0x56, 0xD9, 0xD9, 0xDD, 0x67, 0x68, 0x78, 0x00, 0x86, 0x18, 0x87, 0x43, 0x8D, 0x8E, 0x9A, 0x00, 0x06, 0x87, 0x43, 0x9A, 0x9B, 0xA5, 0x00, 0x09, 0x15, 0xCC, 0xCD, 0xD2, 0x00, 0x12, 0x87, 0x46, 0x00, 0x06, 0x86, 0x4B, 0xFF, 0xFF, 0xFF, 0x8D, 0x8E, 0x9A, 0x00, 0x51, 0x81, 0x07, 0x41, 0x43, 0x56, 0xF2, 0xF2, 0xF4, 0x4D, 0x4F, 0x62, 0x00, 0x09, 0x12, 0x00, 0x0C, 0x87, 0x46, 0x00, 0x06, 0x88, 0x6B, 0xC0, 0xC0, 0xC7, 0x00, 0x86, 0x15, 0x87, 0x43, 0x00, 0x06, 0x95, 0x39, 0xF2, 0xF2, 0xF4, 0x00, 0x0F, 0x96, 0x2B, 0x00, 0x15, 0x87, 0x46, 0x00, 0x06, 0x9E, 0x39, 0xF2, 0xF2, 0xF4, 0xF2, 0xF2, 0xF4, 0x00, 0x09, 0x8E, 0x32, 0x00, 0x4E, 0x9E, 0x0F, 0x00, 0x0C, 0x12, 0x00, 0x0F, 0x87, 0x46, 0x41, 0x43, 0x56, 0xE6, 0xE6, 0xE9, 0x00, 0x86, 0x15, 0x87, 0x46, 0xE6, 0xE6, 0xE9, 0xFF, 0xFF, 0xFF, 0x00, 0x12, 0x95, 0x2A, 0x00, 0x18, 0x87, 0x46, 0x00, 0x06, 0x95, 0x78, 0xFF, 0xFF, 0xFF, 0x80, 0x81, 0x8F, 0x00, 0x51, 0x96, 0x4F, 0x00, 0x0C, 0x90, 0x0D, 0x00, 0x12, 0x87, 0x46, 0x00, 0x12, 0x12, 0x00, 0x86, 0x0C, 0x9E, 0x0F, 0x00, 0x15, 0x9D, 0x68, 0x00, 0x1B, 0x87, 0x46, 0x4D, 0x4F, 0x62, 0xFF, 0xFF, 0xFF, 0x00, 0x51, 0x95, 0x5D, 0x8D, 0x8E, 0x9A, 0x00, 0x0F, 0xAE, 0x16, 0x00, 0x86, 0x27, 0x8F, 0x0C, 0xC0, 0xC0, 0xC7, 0xFF, 0xFF, 0xFF, 0x00, 0x0C, 0x9D, 0x0B, 0x00, 0x24, 0x87, 0x46, 0x00, 0x06, 0x8F, 0x42, 0xF2, 0xF2, 0xF4, 0x00, 0x51, 0xAE, 0x25, 0x00, 0x0F, 0x87, 0x25, 0x00, 0x12, 0x9E, 0x18, 0x00, 0x86, 0x15, 0xAD, 0x27, 0xF2, 0xF2, 0xF4, 0x00, 0x18, 0x8D, 0x5E, 0x00, 0x1E, 0x87, 0x46, 0x00, 0x06, 0xB5, 0x14, 0x00, 0x51, 0x81, 0x10, 0xCC, 0xCD, 0xD2, 0x00, 0x0C, 0x97, 0x29, 0x00, 0x0F, 0xAD, 0x24, 0xE6, 0xE6, 0xE9, 0x00, 0x86, 0x15, 0xAD, 0x24, 0x00, 0x18, 0xBC, 0x15, 0x00, 0x21, 0x87, 0x46, 0xB3, 0xB4, 0xBC, 0xFF, 0xFF, 0xFF, 0x00, 0x51, 0xA5, 0x61, 0x00, 0x06, 0xB5, 0x4A, 0x00, 0x09, 0xAE, 0x01, 0x00, 0x09, 0x87, 0x46, 0x4D, 0x4F, 0x62, 0xCC, 0xCD, 0xD2, 0x00, 0x86, 0x15, 0x8F, 0x09, 0x5A, 0x5C, 0x6D, 0xFF, 0xFF, 0xFF, 0x00, 0x18, 0xCB, 0x21, 0x00, 0x1E, 0x87, 0x46, 0x00, 0x06, 0x97, 0x0B, 0x00, 0x57, 0x81, 0x16, 0xE6, 0xE6, 0xE9, 0xE6, 0xE6, 0xE9, 0x00, 0x06, 0x88, 0x29, 0x9A, 0x9B, 0xA5, 0x00, 0x06, 0xCB, 0x48, 0x00, 0x78, 0xCC, 0x49, 0x00, 0x85, 0x20, 0x87, 0x46, 0x41, 0x43, 0x56, 0x00, 0x1B, 0xA5, 0x25, 0x00, 0x75, 0x96, 0x52, 0x00, 0x0F, 0x9E, 0x03, 0x00, 0x06, 0x81, 0x04, 0x9A, 0x9B, 0xA5, 0x00, 0x15, 0x9F, 0x3A, 0x00, 0x86, 0x42, 0x96, 0x52, 0x00, 0x1B, 0x9E, 0x51, 0x00, 0x86, 0x72, 0xE1, 0x7C, 0x00, 0x06, 0xCB, 0x09, 0x00, 0x15, 0x9D, 0x5F, 0x00, 0x1B, 0x87, 0x46, 0x00, 0x06, 0xC4, 0x29, 0x00, 0x86, 0x21, 0xD9, 0x56, 0x00, 0x6F, 0xD2, 0x7C, 0x00, 0x15, 0xC3, 0x40, 0x00, 0x1B, 0x87, 0x46, 0x00, 0x06, 0x9E, 0x15, 0x00, 0x86, 0x27, 0xE8, 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0x00, 0x12, 0x81, 0xDB, 0x57, 0x00, 0x06, 0x81, 0xE2, 0x37, 0x00, 0x81, 0x4F, 0x84, 0xAE, 0x3C, 0x00, 0x84, 0x61, 0xF1, 0x1D, 0x00, 0x1B, 0x82, 0x99, 0x65, 0x00, 0x0F, 0xF8, 0x7B, 0x00, 0x4E, 0x84, 0xF4, 0x52, 0x00, 0x09, 0x84, 0xDF, 0x01, 0x00, 0x7B, 0x85, 0xF2, 0x58, 0x00, 0x85, 0x6B, 0x87, 0x67, 0x00, 0x06, 0xF0, 0x19, 0x00, 0x86, 0x42, 0xC3, 0x22, 0x00, 0x91, 0x44, 0x81, 0xA0, 0x16}; -static bool g_has_uncompressed = false; - -static unsigned char *get_uncompressed_splash(void) { - unsigned char *splash = (unsigned char *)0xE0000000; - if (!g_has_uncompressed) { - LZ_Uncompress(s_splash, splash, sizeof(s_splash)); - g_has_uncompressed = true; - } - return splash; -} - -void draw_splash(volatile uint32_t *fb) { - unsigned char *splash = get_uncompressed_splash(); - - /* Set display background color. */ - for (size_t i = 0; i < 1280 * 768; i++) { - fb[i] = 0x34364B; - } - - /* Draw actual splash. */ - const size_t x_res = 322; - const size_t y_res = 276; - const size_t x_start = (768 - x_res) / 2; - const size_t y_start = (1280 - y_res) / 2; - - size_t pos = 0; - for (size_t y = y_start; y < (y_start + y_res); y++) - { - for (size_t x = x_start; x < (x_start + x_res); x++) - { - fb[x + y*768] = splash[pos + 2] | (splash[pos + 1] << 8) | (splash[pos] << 16); - pos += 3; - } - } -} \ No newline at end of file diff --git a/sept/sept-secondary/src/splash.h b/sept/sept-secondary/src/splash.h deleted file mode 100644 index 240d3a660..000000000 --- a/sept/sept-secondary/src/splash.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2018 CTCaer - * Copyright (c) 2018 xamanthas - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef SEPT_SPLASH_H -#define SEPT_SPLASH_H - -void draw_splash(volatile uint32_t *fb); - -#endif diff --git a/sept/sept-secondary/src/stage2.c b/sept/sept-secondary/src/stage2.c deleted file mode 100644 index 4f806a487..000000000 --- a/sept/sept-secondary/src/stage2.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "stage2.h" -#include "chainloader.h" -#include "fs_utils.h" -#include "utils.h" - -char g_stage2_path[0x100] = {0}; - -const char *stage2_get_program_path(void) { - return g_stage2_path; -} - -static bool run_mtc(const char *mtc_path, uintptr_t mtc_address) { - FILINFO info; - size_t size; - - /* Check if the MTC binary is present. */ - if (f_stat(mtc_path, &info) != FR_OK) { - print(SCREEN_LOG_LEVEL_WARNING, "Stage2's MTC binary not found!\n"); - return false; - } - - size = (size_t)info.fsize; - - /* Try to read the MTC binary. */ - if (read_from_file((void *)mtc_address, size, mtc_path) != size) { - print(SCREEN_LOG_LEVEL_WARNING, "Failed to read stage2's MTC binary (%s)!\n", mtc_path); - return false; - } - - ScreenLogLevel mtc_log_level = log_get_log_level(); - bool mtc_res = false; - int mtc_argc = 1; - char mtc_arg_data[CHAINLOADER_ARG_DATA_MAX_SIZE] = {0}; - stage2_mtc_args_t *mtc_args = (stage2_mtc_args_t *)mtc_arg_data; - - /* Setup argument data. */ - memcpy(&mtc_args->log_level, &mtc_log_level, sizeof(mtc_log_level)); - - /* Run the MTC binary. */ - mtc_res = (((int (*)(int, void *))mtc_address)(mtc_argc, mtc_arg_data) == 0); - - /* Cleanup right away. */ - memset((void *)mtc_address, 0, size); - - return mtc_res; -} - -/* We get the luxury of assuming a constant filename/load address. */ -void load_stage2(void) { - FILINFO info; - size_t size; - uintptr_t tmp_addr; - stage2_config_t config = { - .path = "sept/payload.bin", - .mtc_path = "atmosphere/fusee-mtc.bin", - .load_address = 0xF0000000, - .entrypoint = 0xF0000000, - }; - - print(SCREEN_LOG_LEVEL_DEBUG, "Stage 2 Config:\n"); - print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, " File Path: %s\n", config.path); - print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, " MTC File Path: %s\n", config.mtc_path); - print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, " Load Address: 0x%08x\n", config.load_address); - print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, " Entrypoint: 0x%p\n", config.entrypoint); - - /* Run the MTC binary. */ - if (!run_mtc(config.mtc_path, config.load_address)) { - print(SCREEN_LOG_LEVEL_WARNING, "DRAM training failed! Continuing with untrained DRAM.\n"); - } - - if (f_stat(config.path, &info) != FR_OK) { - fatal_error("Failed to stat stage2 (%s)!\n", config.path); - } - - size = (size_t)info.fsize; - - /* the LFB is located at 0xC0000000 atm */ - if (size > 0xC0000000u - 0x80000000u) { - fatal_error("Stage2 is way too big!\n"); - } - - if (!check_32bit_address_range_loadable(config.load_address, size)) { - fatal_error("Stage2 has an invalid load address & size combination (0x%08x 0x%08x)!\n", config.load_address, size); - } - - if (config.entrypoint < config.load_address || config.entrypoint >= config.load_address + size) { - fatal_error("Stage2's entrypoint is outside Stage2!\n"); - } - - if (check_32bit_address_range_in_program(config.load_address, size)) { - tmp_addr = 0x80000000u; - } else { - tmp_addr = config.load_address; - } - - /* Try to read stage2. */ - if (read_from_file((void *)tmp_addr, size, config.path) != size) { - fatal_error("Failed to read stage2 (%s)!\n", config.path); - } - - g_chainloader_num_entries = 1; - g_chainloader_entries[0].load_address = config.load_address; - g_chainloader_entries[0].src_address = tmp_addr; - g_chainloader_entries[0].size = size; - g_chainloader_entries[0].num = 0; - g_chainloader_entrypoint = config.entrypoint; - - strncpy(g_stage2_path, config.path, sizeof(g_stage2_path) - 1); - g_stage2_path[sizeof(g_stage2_path) - 1] = '\0'; -} diff --git a/sept/sept-secondary/src/stage2.h b/sept/sept-secondary/src/stage2.h deleted file mode 100644 index 55465b0b8..000000000 --- a/sept/sept-secondary/src/stage2.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_STAGE2_H -#define FUSEE_STAGE2_H - -#include -#include - -#include "../../../fusee/common/display/video_fb.h" -#include "../../../fusee/common/log.h" -#include "../../../fusee/common/vsprintf.h" -#include "../../../fusee/common/ini.h" -#include "../../../fusee/common/fatfs/ff.h" - -/* TODO: Is there a more concise way to do this? */ -#define STAGE2_ARGV_PROGRAM_PATH 0 -#define STAGE2_ARGV_ARGUMENT_STRUCT 1 -#define STAGE2_ARGC 2 - -#define STAGE2_NAME_KEY "stage2_path" -#define STAGE2_MTC_NAME_KEY "stage2_mtc_path" -#define STAGE2_ADDRESS_KEY "stage2_addr" -#define STAGE2_ENTRYPOINT_KEY "stage2_entrypoint" - -#define BCTO_MAX_SIZE 0x5800 - -typedef struct { - char path[0x100]; - char mtc_path[0x100]; - uintptr_t load_address; - uintptr_t entrypoint; -} stage2_config_t; - -typedef struct { - uint32_t version; - ScreenLogLevel log_level; - char bct0[BCTO_MAX_SIZE]; -} stage2_args_t; - -typedef struct { - ScreenLogLevel log_level; -} stage2_mtc_args_t; - -const char *stage2_get_program_path(void); -void load_stage2(void); - -#endif \ No newline at end of file diff --git a/sept/sept-secondary/src/start.s b/sept/sept-secondary/src/start.s deleted file mode 100644 index 207067dbf..000000000 --- a/sept/sept-secondary/src/start.s +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -.macro CLEAR_GPR_REG_ITER - mov r\@, #0 -.endm - -.section .text.start, "ax", %progbits -.arm -.align 5 -.global _start -.type _start, %function -_start: - /* Switch to system mode, mask all interrupts, clear all flags */ - msr cpsr_cxsf, #0xDF - b begin_relocation_loop - _version: - .word 0x00000000 /* Version. */ - .word 0x00000000 /* Reserved. */ - - begin_relocation_loop: - - /* Relocate ourselves if necessary */ - ldr r2, =__start__ - adr r3, _start - cmp r2, r3 - beq _relocation_loop_end - - /* If we are relocating, we are not rebooting to ourselves. Note that. */ - ldr r0, =0x4003FFFC - mov r1, #0x0 - str r1, [r0] - - mov r4, #0x1000 - mov r1, #0x0 - _relocation_loop: - ldmia r3!, {r5-r12} - stmia r2!, {r5-r12} - add r1, r1, #0x20 - cmp r1, r4 - bne _relocation_loop - - ldr r12, =_second_relocation_start - bx r12 - - _second_relocation_start: - ldr r4, =__bss_start__ - sub r4, r4, r2 - mov r1, #0x0 - - _second_relocation_loop: - ldmia r3!, {r5-r12} - stmia r2!, {r5-r12} - add r1, r1, #0x20 - cmp r1, r4 - bne _second_relocation_loop - - ldr r12, =_relocation_loop_end - bx r12 - - _relocation_loop_end: - - /* Set the stack pointer */ - ldr sp, =__stack_top__ - mov fp, #0 - bl __program_init - - /* Set r0 to r12 to 0 (for debugging) & call main */ - .rept 13 - CLEAR_GPR_REG_ITER - .endr - ldr lr, =__program_exit - ldr r0, =_version - ldr r0, [r0] - b sept_main - -/* No need to include this in normal programs: */ -.section .chainloader.text.start, "ax", %progbits -.arm -.align 5 -.global relocate_and_chainload -.type relocate_and_chainload, %function -relocate_and_chainload: - ldr sp, =__stack_top__ - b relocate_and_chainload_main diff --git a/sept/sept-secondary/src/sysctr0.h b/sept/sept-secondary/src/sysctr0.h deleted file mode 100644 index 39a0196b3..000000000 --- a/sept/sept-secondary/src/sysctr0.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_SYSCTR0_H -#define FUSEE_SYSCTR0_H - -#include - -#define SYSCTR0_BASE 0x700F0000 -#define MAKE_SYSCTR0_REG(n) MAKE_REG32(SYSCTR0_BASE + n) - -#define SYSCTR0_CNTCR_0 MAKE_SYSCTR0_REG(0x00) -#define SYSCTR0_CNTSR_0 MAKE_SYSCTR0_REG(0x04) -#define SYSCTR0_CNTCV0_0 MAKE_SYSCTR0_REG(0x08) -#define SYSCTR0_CNTCV1_0 MAKE_SYSCTR0_REG(0x0C) -#define SYSCTR0_CNTFID0_0 MAKE_SYSCTR0_REG(0x20) -#define SYSCTR0_CNTFID1_0 MAKE_SYSCTR0_REG(0x24) -#define SYSCTR0_COUNTERID4_0 MAKE_SYSCTR0_REG(0xFD0) -#define SYSCTR0_COUNTERID5_0 MAKE_SYSCTR0_REG(0xFD4) -#define SYSCTR0_COUNTERID6_0 MAKE_SYSCTR0_REG(0xFD8) -#define SYSCTR0_COUNTERID7_0 MAKE_SYSCTR0_REG(0xFDC) -#define SYSCTR0_COUNTERID0_0 MAKE_SYSCTR0_REG(0xFE0) -#define SYSCTR0_COUNTERID1_0 MAKE_SYSCTR0_REG(0xFE4) -#define SYSCTR0_COUNTERID2_0 MAKE_SYSCTR0_REG(0xFE8) -#define SYSCTR0_COUNTERID3_0 MAKE_SYSCTR0_REG(0xFEC) -#define SYSCTR0_COUNTERID8_0 MAKE_SYSCTR0_REG(0xFF0) -#define SYSCTR0_COUNTERID9_0 MAKE_SYSCTR0_REG(0xFF4) -#define SYSCTR0_COUNTERID10_0 MAKE_SYSCTR0_REG(0xFF8) -#define SYSCTR0_COUNTERID11_0 MAKE_SYSCTR0_REG(0xFFC) - -#endif diff --git a/sept/sept-secondary/src/sysreg.h b/sept/sept-secondary/src/sysreg.h deleted file mode 100644 index 311945b4e..000000000 --- a/sept/sept-secondary/src/sysreg.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_SYSREG_H -#define FUSEE_SYSREG_H - -#include - -#define SYSREG_BASE 0x6000C000 -#define SB_BASE (SYSREG_BASE + 0x200) -#define EXCP_VEC_BASE 0x6000F000 - -#define MAKE_SYSREG(n) MAKE_REG32(SYSREG_BASE + n) -#define MAKE_SB_REG(n) MAKE_REG32(SB_BASE + n) -#define MAKE_EXCP_VEC_REG(n) MAKE_REG32(EXCP_VEC_BASE + n) - -#define AHB_ARBITRATION_DISABLE_0 MAKE_SYSREG(0x004) -#define AHB_ARBITRATION_XBAR_CTRL_0 MAKE_SYSREG(0x0E0) -#define AHB_AHB_SPARE_REG_0 MAKE_SYSREG(0x110) - -#define SB_CSR_0 MAKE_SB_REG(0x00) -#define SB_PIROM_START_0 MAKE_SB_REG(0x04) -#define SB_PFCFG_0 MAKE_SB_REG(0x08) -#define SB_SECURE_SPAREREG_0_0 MAKE_SB_REG(0x0C) -#define SB_SECURE_SPAREREG_1_0 MAKE_SB_REG(0x10) -#define SB_SECURE_SPAREREG_2_0 MAKE_SB_REG(0x14) -#define SB_SECURE_SPAREREG_3_0 MAKE_SB_REG(0x18) -#define SB_SECURE_SPAREREG_4_0 MAKE_SB_REG(0x1C) -#define SB_SECURE_SPAREREG_5_0 MAKE_SB_REG(0x20) -#define SB_SECURE_SPAREREG_6_0 MAKE_SB_REG(0x24) -#define SB_SECURE_SPAREREG_7_0 MAKE_SB_REG(0x28) -#define SB_AA64_RESET_LOW_0 MAKE_SB_REG(0x30) -#define SB_AA64_RESET_HIGH_0 MAKE_SB_REG(0x34) - -#endif diff --git a/sept/sept-secondary/src/timers.h b/sept/sept-secondary/src/timers.h deleted file mode 100644 index 7d5ce4781..000000000 --- a/sept/sept-secondary/src/timers.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_TIMERS_H -#define FUSEE_TIMERS_H - -#include "utils.h" - -#define TIMERS_BASE 0x60005000 -#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n) - -#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10) -#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14) -#define SHARED_INTR_STATUS_0 MAKE_TIMERS_REG(0x1A0) -#define SHARED_TIMER_SECURE_CFG_0 MAKE_TIMERS_REG(0x1A4) - -#define RTC_BASE 0x7000E000 -#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n) - -#define RTC_SECONDS MAKE_RTC_REG(0x08) -#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C) -#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10) - -typedef struct { - uint32_t CONFIG; - uint32_t STATUS; - uint32_t COMMAND; - uint32_t PATTERN; -} watchdog_timers_t; - -#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n)) -#define WDT_REBOOT_PATTERN 0xC45A -#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8 * n) - -void wait(uint32_t microseconds); - -static inline uint32_t get_time_s(void) { - return RTC_SECONDS; -} - -static inline uint32_t get_time_ms(void) { - return (RTC_MILLI_SECONDS | (RTC_SHADOW_SECONDS << 10)); -} - -static inline uint32_t get_time_us(void) { - return TIMERUS_CNTR_1US_0; -} - -/** - * Returns the time in microseconds. - */ -static inline uint32_t get_time(void) { - return get_time_us(); -} - -/** - * Returns the number of microseconds that have passed since a given get_time(). - */ -static inline uint32_t get_time_since(uint32_t base) { - return get_time_us() - base; -} - -/** - * Delays for a given number of microseconds. - */ -static inline void udelay(uint32_t usecs) { - uint32_t start = get_time_us(); - while (get_time_us() - start < usecs); -} - -/** - * Delays for a given number of milliseconds. - */ -static inline void mdelay(uint32_t msecs) { - uint32_t start = get_time_ms(); - while (get_time_ms() - start < msecs); -} - -__attribute__ ((noreturn)) void watchdog_reboot(void); - -#endif diff --git a/sept/sept-secondary/src/uart.c b/sept/sept-secondary/src/uart.c deleted file mode 100644 index 020dbd583..000000000 --- a/sept/sept-secondary/src/uart.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "uart.h" -#include "timers.h" -#include "pinmux.h" - -static inline void uart_wait_cycles(uint32_t baud, uint32_t num) -{ - udelay((num * 1000000 + 16 * baud - 1) / (16 * baud)); -} - -static inline void uart_wait_syms(uint32_t baud, uint32_t num) -{ - udelay((num * 1000000 + baud - 1) / baud); -} - -void uart_config(UartDevice dev) { - volatile tegra_pinmux_t *pinmux = pinmux_get_regs(); - - switch (dev) { - case UART_A: - pinmux->uart1_tx = (0 | 0 | PINMUX_PULL_NONE | PINMUX_SELECT_FUNCTION0); - pinmux->uart1_rx = (PINMUX_INPUT | PINMUX_TRISTATE | PINMUX_PULL_UP | PINMUX_SELECT_FUNCTION0); - pinmux->uart1_rts = (0 | 0 | PINMUX_PULL_NONE | PINMUX_SELECT_FUNCTION0); - pinmux->uart1_cts = (PINMUX_INPUT | PINMUX_TRISTATE | PINMUX_PULL_DOWN | PINMUX_SELECT_FUNCTION0); - break; - case UART_B: - pinmux->uart2_tx = (0 | 0 | PINMUX_PULL_NONE | PINMUX_SELECT_FUNCTION0); - pinmux->uart2_rx = (PINMUX_INPUT | PINMUX_TRISTATE | PINMUX_PULL_NONE | PINMUX_SELECT_FUNCTION0); - pinmux->uart2_rts = (0 | 0 | PINMUX_PULL_DOWN | PINMUX_SELECT_FUNCTION0); - pinmux->uart2_cts = (PINMUX_INPUT | PINMUX_TRISTATE | PINMUX_PULL_NONE | PINMUX_SELECT_FUNCTION0); - break; - case UART_C: - pinmux->uart3_tx = (0 | 0 | PINMUX_PULL_NONE | PINMUX_SELECT_FUNCTION0); - pinmux->uart3_rx = (PINMUX_INPUT | PINMUX_TRISTATE | PINMUX_PULL_NONE | PINMUX_SELECT_FUNCTION0); - pinmux->uart3_rts = (0 | 0 | PINMUX_PULL_DOWN | PINMUX_SELECT_FUNCTION0); - pinmux->uart3_cts = (PINMUX_INPUT | PINMUX_TRISTATE | PINMUX_PULL_NONE | PINMUX_SELECT_FUNCTION0); - break; - case UART_D: - pinmux->uart4_tx = (0 | 0 | PINMUX_PULL_DOWN | PINMUX_SELECT_FUNCTION0); - pinmux->uart4_rx = (PINMUX_INPUT | PINMUX_TRISTATE | PINMUX_PULL_DOWN | PINMUX_SELECT_FUNCTION0); - pinmux->uart4_rts = (0 | 0 | PINMUX_PULL_DOWN | PINMUX_SELECT_FUNCTION0); - pinmux->uart4_cts = (PINMUX_INPUT | PINMUX_TRISTATE | PINMUX_PULL_DOWN | PINMUX_SELECT_FUNCTION0); - break; - case UART_E: - /* Unused. */ - break; - default: break; - } -} - -void uart_init(UartDevice dev, uint32_t baud) { - volatile tegra_uart_t *uart = uart_get_regs(dev); - - /* Wait for idle state. */ - uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE); - - /* Calculate baud rate, round to nearest. */ - uint32_t rate = (8 * baud + 408000000) / (16 * baud); - - /* Setup UART in FIFO mode. */ - uart->UART_IER_DLAB = 0; - uart->UART_MCR = 0; - uart->UART_LCR = (UART_LCR_DLAB | UART_LCR_WD_LENGTH_8); /* Enable DLAB and set word length 8. */ - uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */ - uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */ - uart->UART_LCR &= ~(UART_LCR_DLAB); /* Disable DLAB. */ - uart->UART_SPR; /* Dummy read. */ - uart_wait_syms(baud, 3); /* Wait for 3 symbols at the new baudrate. */ - - /* Enable FIFO with default settings. */ - uart->UART_IIR_FCR = UART_FCR_FCR_EN_FIFO; - uart->UART_SPR; /* Dummy read as mandated by TRM. */ - uart_wait_cycles(baud, 3); /* Wait for 3 baud cycles, as mandated by TRM (erratum). */ - - /* Flush FIFO. */ - uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE); /* Make sure there's no data being written in TX FIFO (TRM). */ - uart->UART_IIR_FCR |= UART_FCR_RX_CLR | UART_FCR_TX_CLR; /* Clear TX and RX FIFOs. */ - uart_wait_cycles(baud, 32); /* Wait for 32 baud cycles (TRM, erratum). */ - /* Wait for idle state (TRM). */ - uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE); -} - -/* This function blocks until the UART device is in the desired state. */ -void uart_wait_idle(UartDevice dev, UartVendorStatus status) { - volatile tegra_uart_t *uart = uart_get_regs(dev); - - if (status & UART_VENDOR_STATE_TX_IDLE) { - while (!(uart->UART_LSR & UART_LSR_TMTY)) { - /* Wait */ - } - } - if (status & UART_VENDOR_STATE_RX_IDLE) { - while (uart->UART_LSR & UART_LSR_RDR) { - /* Wait */ - } - } -} - -void uart_send(UartDevice dev, const void *buf, size_t len) { - volatile tegra_uart_t *uart = uart_get_regs(dev); - - for (size_t i = 0; i < len; i++) { - while (!(uart->UART_LSR & UART_LSR_THRE)) { - /* Wait until it's possible to send data. */ - } - uart->UART_THR_DLAB = *((const uint8_t *)buf + i); - } -} - -void uart_recv(UartDevice dev, void *buf, size_t len) { - volatile tegra_uart_t *uart = uart_get_regs(dev); - - for (size_t i = 0; i < len; i++) { - while (!(uart->UART_LSR & UART_LSR_RDR)) { - /* Wait until it's possible to receive data. */ - } - *((uint8_t *)buf + i) = uart->UART_THR_DLAB; - } -} diff --git a/sept/sept-secondary/src/uart.h b/sept/sept-secondary/src/uart.h deleted file mode 100644 index 20b26f04c..000000000 --- a/sept/sept-secondary/src/uart.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_UART_H -#define FUSEE_UART_H - -#include - -#define UART_BASE 0x70006000 - -#define BAUD_115200 115200 - -/* UART devices */ -typedef enum { - UART_A = 0, - UART_B = 1, - UART_C = 2, - UART_D = 3, - UART_E = 4, -} UartDevice; - -/* 36.3.12 UART_VENDOR_STATUS_0_0 */ -typedef enum { - UART_VENDOR_STATE_TX_IDLE = 1 << 0, - UART_VENDOR_STATE_RX_IDLE = 1 << 1, - - /* This bit is set to 1 when a read is issued to an empty FIFO and gets cleared on register read (sticky bit until read) - 0 = NO_UNDERRUN - 1 = UNDERRUN - */ - UART_VENDOR_STATE_RX_UNDERRUN = 1 << 2, - - /* This bit is set to 1 when write data is issued to the TX FIFO when it is already full and gets cleared on register read (sticky bit until read) - 0 = NO_OVERRUN - 1 = OVERRUN - */ - UART_VENDOR_STATE_TX_OVERRUN = 1 << 3, - - UART_VENDOR_STATE_RX_FIFO_COUNTER = 0b111111 << 16, /* reflects number of current entries in RX FIFO */ - UART_VENDOR_STATE_TX_FIFO_COUNTER = 0b111111 << 24 /* reflects number of current entries in TX FIFO */ -} UartVendorStatus; - -/* 36.3.6 UART_LSR_0 */ -typedef enum { - UART_LSR_RDR = 1 << 0, /* Receiver Data Ready */ - UART_LSR_OVRF = 1 << 1, /* Receiver Overrun Error */ - UART_LSR_PERR = 1 << 2, /* Parity Error */ - UART_LSR_FERR = 1 << 3, /* Framing Error */ - UART_LSR_BRK = 1 << 4, /* BREAK condition detected on line */ - UART_LSR_THRE = 1 << 5, /* Transmit Holding Register is Empty -- OK to write data */ - UART_LSR_TMTY = 1 << 6, /* Transmit Shift Register empty status */ - UART_LSR_FIFOE = 1 << 7, /* Receive FIFO Error */ - UART_LSR_TX_FIFO_FULL = 1 << 8, /* Transmitter FIFO full status */ - UART_LSR_RX_FIFO_EMPTY = 1 << 9, /* Receiver FIFO empty status */ -} UartLineStatus; - -/* 36.3.4 UART_LCR_0 */ -typedef enum { - UART_LCR_WD_LENGTH_5 = 0, /* word length 5 */ - UART_LCR_WD_LENGTH_6 = 1, /* word length 6 */ - UART_LCR_WD_LENGTH_7 = 2, /* word length 7 */ - UART_LCR_WD_LENGTH_8 = 3, /* word length 8 */ - - /* STOP: - 0 = Transmit 1 stop bit - 1 = Transmit 2 stop bits (receiver always checks for 1 stop bit) - */ - UART_LCR_STOP = 1 << 2, - UART_LCR_PAR = 1 << 3, /* Parity enabled */ - UART_LCR_EVEN = 1 << 4, /* Even parity format. There will always be an even number of 1s in the binary representation (PAR = 1) */ - UART_LCR_SET_P = 1 << 5, /* Set (force) parity to value in LCR[4] */ - UART_LCR_SET_B = 1 << 6, /* Set BREAK condition -- Transmitter sends all zeroes to indicate BREAK */ - UART_LCR_DLAB = 1 << 7, /* Divisor Latch Access Bit (set to allow programming of the DLH, DLM Divisors) */ -} UartLineControl; - -/* 36.3.3 UART_IIR_FCR_0 */ -typedef enum { - UART_FCR_FCR_EN_FIFO = 1 << 0, /* Enable the transmit and receive FIFOs. This bit should be enabled */ - UART_FCR_RX_CLR = 1 << 1, /* Clears the contents of the receive FIFO and resets its counter logic to 0 (the receive shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */ - UART_FCR_TX_CLR = 1 << 2, /* Clears the contents of the transmit FIFO and resets its counter logic to 0 (the transmit shift register is not cleared or altered). This bit returns to 0 after clearing the FIFOs */ - - /* DMA: - 0 = DMA_MODE_0 - 1 = DMA_MODE_1 - */ - UART_FCR_DMA = 1 << 3, - - /* TX_TRIG - 0 = FIFO_COUNT_GREATER_16 - 1 = FIFO_COUNT_GREATER_8 - 2 = FIFO_COUNT_GREATER_4 - 3 = FIFO_COUNT_GREATER_1 - */ - UART_FCR_TX_TRIG = 3 << 4, - UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_16 = 0 << 4, - UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_8 = 1 << 4, - UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_4 = 2 << 4, - UART_FCR_TX_TRIG_FIFO_COUNT_GREATER_1 = 3 << 4, - - /* RX_TRIG - 0 = FIFO_COUNT_GREATER_1 - 1 = FIFO_COUNT_GREATER_4 - 2 = FIFO_COUNT_GREATER_8 - 3 = FIFO_COUNT_GREATER_16 - */ - UART_FCR_RX_TRIG = 3 << 6, - UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_1 = 0 << 6, - UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_4 = 1 << 6, - UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_8 = 2 << 6, - UART_FCR_RX_TRIG_FIFO_COUNT_GREATER_16 = 3 << 6, -} UartFifoControl; - -/* 36.3.3 UART_IIR_FCR_0 */ -typedef enum { - UART_IIR_IS_STA = 1 << 0, /* Interrupt Pending if ZERO */ - UART_IIR_IS_PRI0 = 1 << 1, /* Encoded Interrupt ID Refer to IIR[3:0] table [36.3.3] */ - UART_IIR_IS_PRI1 = 1 << 2, /* Encoded Interrupt ID Refer to IIR[3:0] table */ - UART_IIR_IS_PRI2 = 1 << 3, /* Encoded Interrupt ID Refer to IIR[3:0] table */ - - /* FIFO Mode Status - 0 = 16450 mode (no FIFO) - 1 = 16550 mode (FIFO) - */ - UART_IIR_EN_FIFO = 3 << 6, - UART_IIR_MODE_16450 = 0 << 6, - UART_IIR_MODE_16550 = 1 << 6, -} UartInterruptIdentification; - -typedef struct { - uint32_t UART_THR_DLAB; - uint32_t UART_IER_DLAB; - uint32_t UART_IIR_FCR; - uint32_t UART_LCR; - uint32_t UART_MCR; - uint32_t UART_LSR; - uint32_t UART_MSR; - uint32_t UART_SPR; - uint32_t UART_IRDA_CSR; - uint32_t UART_RX_FIFO_CFG; - uint32_t UART_MIE; - uint32_t UART_VENDOR_STATUS; - uint8_t _0x30[0x0C]; - uint32_t UART_ASR; -} tegra_uart_t; - -void uart_config(UartDevice dev); -void uart_init(UartDevice dev, uint32_t baud); -void uart_wait_idle(UartDevice dev, UartVendorStatus status); -void uart_send(UartDevice dev, const void *buf, size_t len); -void uart_recv(UartDevice dev, void *buf, size_t len); - -static inline void uart_send_text(UartDevice dev, const char *str) { - uart_send(dev, str, strlen(str)); - uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE); -} - -static inline volatile tegra_uart_t *uart_get_regs(UartDevice dev) { - static const size_t offsets[] = {0, 0x40, 0x200, 0x300, 0x400}; - return (volatile tegra_uart_t *)(UART_BASE + offsets[dev]); -} - -#endif diff --git a/sept/sept-secondary/src/utils.c b/sept/sept-secondary/src/utils.c deleted file mode 100644 index 6bab54d21..000000000 --- a/sept/sept-secondary/src/utils.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include "utils.h" -#include "se.h" -#include "fuse.h" -#include "pmc.h" -#include "timers.h" -#include "panic.h" -#include "car.h" -#include "btn.h" -#include "../../../fusee/common/log.h" - -#include - -#define u8 uint8_t -#define u32 uint32_t -#include "rebootstub_bin.h" -#undef u8 -#undef u32 - -void wait(uint32_t microseconds) { - uint32_t old_time = TIMERUS_CNTR_1US_0; - while (TIMERUS_CNTR_1US_0 - old_time <= microseconds) { - /* Spin-lock. */ - } -} - -__attribute__((noreturn)) void watchdog_reboot(void) { - volatile watchdog_timers_t *wdt = GET_WDT(4); - wdt->PATTERN = WDT_REBOOT_PATTERN; - wdt->COMMAND = 2; /* Disable Counter. */ - GET_WDT_REBOOT_CFG_REG(4) = 0xC0000000; - wdt->CONFIG = 0x8019; /* Full System Reset after Fourth Counter expires, using TIMER(9). */ - wdt->COMMAND = 1; /* Enable Counter. */ - while (true) { - /* Wait for reboot. */ - } -} - -__attribute__((noreturn)) void pmc_reboot(uint32_t scratch0) { - APBDEV_PMC_SCRATCH0_0 = scratch0; - - /* Reset the processor. */ - APBDEV_PMC_CONTROL = BIT(4); - - while (true) { - /* Wait for reboot. */ - } -} - -void prepare_for_reboot_to_self(void) { - /* Write warmboot to scratch0. */ - APBDEV_PMC_SCRATCH0_0 = 0x00000001; - - /* Patch SDRAM init to perform an SVC immediately after second write */ - APBDEV_PMC_SCRATCH45_0 = 0x2E38DFFF; - APBDEV_PMC_SCRATCH46_0 = 0x6001DC28; - /* Set SVC handler to jump to reboot stub in IRAM. */ - APBDEV_PMC_SCRATCH33_0 = 0x4003F000; - APBDEV_PMC_SCRATCH40_0 = 0x6000F208; - - /* Copy reboot stub into IRAM high. */ - for (size_t i = 0; i < rebootstub_bin_size; i += sizeof(uint32_t)) { - write32le((void *)0x4003F000, i, read32le(rebootstub_bin, i)); - } -} - -__attribute__((noreturn)) void reboot_to_self(void) { - /* Prep IRAM for reboot. */ - prepare_for_reboot_to_self(); - - /* Trigger warm reboot. */ - pmc_reboot(1 << 0); -} - -__attribute__((noreturn)) void wait_for_button_and_reboot(void) { - uint32_t button; - while (true) { - button = btn_read(); - if (button & BTN_POWER) { - reboot_to_self(); - } - } -} - -__attribute__ ((noreturn)) void generic_panic(void) { - panic(0xFF000006); -} - -__attribute__((noreturn)) void fatal_error(const char *fmt, ...) { - /* Override the global logging level. */ - log_set_log_level(SCREEN_LOG_LEVEL_ERROR); - - /* Display fatal error. */ - va_list args; - print(SCREEN_LOG_LEVEL_ERROR, "Fatal error: "); - va_start(args, fmt); - vprint(SCREEN_LOG_LEVEL_ERROR, fmt, args); - va_end(args); - print(SCREEN_LOG_LEVEL_ERROR | SCREEN_LOG_LEVEL_NO_PREFIX, "\n Press POWER to reboot.\n"); - - /* Wait for button and reboot. */ - wait_for_button_and_reboot(); -} - -__attribute__((noinline)) bool overlaps(uint64_t as, uint64_t ae, uint64_t bs, uint64_t be) -{ - if(as <= bs && bs <= ae) - return true; - if(bs <= as && as <= be) - return true; - return false; -} diff --git a/sept/sept-secondary/src/utils.h b/sept/sept-secondary/src/utils.h deleted file mode 100644 index 457df7602..000000000 --- a/sept/sept-secondary/src/utils.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2018-2020 Atmosphère-NX - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef FUSEE_UTILS_H -#define FUSEE_UTILS_H - -#include -#include -#include -#include - -#define BIT(n) (1u << (n)) -#define BITL(n) (1ull << (n)) -#define MASK(n) (BIT(n) - 1) -#define MASKL(n) (BITL(n) - 1) -#define MASK2(a,b) (MASK(a) & ~MASK(b)) -#define MASK2L(a,b) (MASKL(a) & ~MASKL(b)) - -#define MAKE_REG32(a) (*(volatile uint32_t *)(a)) - -#define ALIGN(m) __attribute__((aligned(m))) -#define PACKED __attribute__((packed)) - -#define ALINLINE __attribute__((always_inline)) -#define NOINLINE __attribute__((noinline)) - -#define SET_SYSREG(reg, val) do { temp_reg = (val); __asm__ __volatile__ ("msr " #reg ", %0" :: "r"(temp_reg) : "memory"); } while(false) - -static inline uintptr_t get_physical_address(const void *addr) { - return (uintptr_t)addr; -} - -static inline uint32_t read32le(const volatile void *dword, size_t offset) { - uintptr_t addr = (uintptr_t)dword + offset; - volatile uint32_t *target = (uint32_t *)addr; - return *target; -} - -static inline uint32_t read32be(const volatile void *dword, size_t offset) { - return __builtin_bswap32(read32le(dword, offset)); -} - -static inline uint64_t read64le(const volatile void *qword, size_t offset) { - uintptr_t addr = (uintptr_t)qword + offset; - volatile uint64_t *target = (uint64_t *)addr; - return *target; -} - -static inline uint64_t read64be(const volatile void *qword, size_t offset) { - return __builtin_bswap64(read64le(qword, offset)); -} - -static inline void write32le(volatile void *dword, size_t offset, uint32_t value) { - uintptr_t addr = (uintptr_t)dword + offset; - volatile uint32_t *target = (uint32_t *)addr; - *target = value; -} - -static inline void write32be(volatile void *dword, size_t offset, uint32_t value) { - write32le(dword, offset, __builtin_bswap32(value)); -} - -static inline void write64le(volatile void *qword, size_t offset, uint64_t value) { - uintptr_t addr = (uintptr_t)qword + offset; - volatile uint64_t *target = (uint64_t *)addr; - *target = value; -} - -static inline void write64be(volatile void *qword, size_t offset, uint64_t value) { - write64le(qword, offset, __builtin_bswap64(value)); -} - -static inline bool check_32bit_additive_overflow(uint32_t a, uint32_t b) { - return __builtin_add_overflow_p(a, b, (uint32_t)0); -} - -static inline bool check_32bit_address_loadable(uintptr_t addr) { - /* FWIW the bootROM forbids loading anything between 0x40000000 and 0x40010000, using it for itself... */ - return (addr >= 0x40010000u && addr < 0x40040000u) || addr >= 0x80000000u; -} - -static inline bool check_32bit_address_range_loadable(uintptr_t addr, size_t size) { - return - !__builtin_add_overflow_p(addr, size, (uintptr_t)0) && /* the range doesn't overflow */ - check_32bit_address_loadable(addr) && check_32bit_address_loadable(addr + size) && /* bounds are valid */ - !(addr >= 0x40010000u && addr < 0x40040000u && addr + size >= 0x40040000u) /* the range doesn't cross MMIO */ - ; -} - -bool overlaps(uint64_t as, uint64_t ae, uint64_t bs, uint64_t be); -static inline bool overlaps_a(const void *as, const void *ae, const void *bs, const void *be) { - return overlaps((uint64_t)(uintptr_t)as, (uint64_t)(uintptr_t)ae, (uint64_t)(uintptr_t)bs, (uint64_t)(uintptr_t)be); -} - -static inline bool check_32bit_address_range_in_program(uintptr_t addr, size_t size) { - extern uint8_t __chainloader_start__[], __chainloader_end__[]; - extern uint8_t __stack_bottom__[], __stack_top__[]; - extern uint8_t __start__[], __end__[]; - uint8_t *start = (uint8_t *)addr, *end = start + size; - - return overlaps_a(start, end, __chainloader_start__, __chainloader_end__) || - overlaps_a(start, end, __stack_bottom__, __stack_top__) || - overlaps_a(start, end, (void *)0xC0000000, (void *)0xC03C0000) || /* framebuffer */ - overlaps_a(start, end, __start__, __end__); -} - -__attribute__((noreturn)) void watchdog_reboot(void); -__attribute__((noreturn)) void pmc_reboot(uint32_t scratch0); -void prepare_for_reboot_to_self(void); -__attribute__((noreturn)) void reboot_to_self(void); -__attribute__((noreturn)) void wait_for_button_and_reboot(void); - -__attribute__((noreturn)) void generic_panic(void); -__attribute__((noreturn)) void fatal_error(const char *fmt, ...); - -#endif diff --git a/stratosphere/ams_mitm/source/amsmitm_initialization.cpp b/stratosphere/ams_mitm/source/amsmitm_initialization.cpp index c2b1a517c..efc41d600 100644 --- a/stratosphere/ams_mitm/source/amsmitm_initialization.cpp +++ b/stratosphere/ams_mitm/source/amsmitm_initialization.cpp @@ -67,7 +67,6 @@ namespace ams::mitm { /* Maintain exclusive access to the fusee-secondary archive. */ FsFile g_stratosphere_file; FsFile g_secondary_file; - FsFile g_sept_payload_file; constexpr inline bool IsHexadecimal(const char *str) { while (*str) { @@ -142,7 +141,6 @@ namespace ams::mitm { { R_ABORT_UNLESS(mitm::fs::OpenSdFile(std::addressof(g_secondary_file), "/atmosphere/fusee-secondary.bin", ams::fs::OpenMode_Read)); R_ABORT_UNLESS(mitm::fs::OpenSdFile(std::addressof(g_stratosphere_file), "/atmosphere/stratosphere.romfs", ams::fs::OpenMode_Read)); - R_ABORT_UNLESS(mitm::fs::OpenSdFile(std::addressof(g_sept_payload_file), "/sept/payload.bin", ams::fs::OpenMode_Read)); } } diff --git a/troposphere/daybreak/nanovg/.gitignore b/troposphere/daybreak/nanovg/.gitignore index 50b6c6179..b0b4735b5 100644 --- a/troposphere/daybreak/nanovg/.gitignore +++ b/troposphere/daybreak/nanovg/.gitignore @@ -79,9 +79,8 @@ dkms.conf *.nam *.til -# KEYS file for sept-secondary. +# Compiled python files. *.pyc -sept/sept-secondary/KEYS.py .**/