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Cleanup TODOs, implement bootconfig SCR_EL3 bit setting

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This commit is contained in:
Michael Scire 2018-03-02 15:04:16 -08:00
parent bf63a077b1
commit 102fb5004f
7 changed files with 26 additions and 8 deletions
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4
exosphere/src/bootconfig.c
View file

@ -64,6 +64,10 @@ bool bootconfig_is_debug_mode(void) {
return (LOADED_BOOTCONFIG->unsigned_config.data[0x10] & 2) != 0;
}
bool bootconfig_should_set_scr_el3_bit(void) {
return (LOADED_BOOTCONFIG->unsigned_config.data[0x10] & 6) != 6;
}
uint64_t bootconfig_get_memory_arrangement(void) {
if (bootconfig_is_debug_mode()) {
if (fuse_get_dram_id() == 4) {

2
exosphere/src/bootconfig.h
View file

@ -43,6 +43,8 @@ bool bootconfig_is_package2_unsigned(void);
bool bootconfig_disable_program_verification(void);
bool bootconfig_is_debug_mode(void);
bool bootconfig_should_set_scr_el3_bit(void);
uint64_t bootconfig_get_memory_arrangement(void);
uint64_t bootconfig_get_kernel_memory_configuration(void);

1
exosphere/src/coldboot_init.c
View file

@ -171,7 +171,6 @@ void coldboot_init(coldboot_crt0_reloc_list_t *reloc_list, boot_func_list_t *fun
/* TODO: 4.x does slightly different init. How should we handle this? We can't detect master key revision yet. */
coldboot_init_dma_controllers();
/* TODO: initialize DMA controllers, etc. */
configure_ttbls();
func_list->funcs.set_memory_registers_enable_mmu();

2
exosphere/src/interrupt.c
View file

@ -14,7 +14,7 @@ static unsigned int get_interrupt_id(void) {
return GICC_IAR;
}
/* Initializes the GIC. TODO: This must be called during wakeup. */
/* Initializes the GIC. This must be called during wakeup. */
void intr_initialize_gic(void) {
/* Setup interrupts 0-0x1F as nonsecure with highest non-secure priority. */
GICD_IGROUPR[0] = 0xFFFFFFFF;

2
exosphere/src/interrupt.h
View file

@ -47,7 +47,7 @@ static inline uintptr_t get_gicc_base(void) {
/* To be called by FIQ handler. */
void handle_registered_interrupt(void);
/* Initializes the GIC. TODO: This must be called during wakeup. */
/* Initializes the GIC. This must be called during wakeup. */
void intr_initialize_gic(void);
void intr_initialize_gic_nonsecure(void);

3
exosphere/src/lp0.c
View file

@ -17,6 +17,7 @@
#include "se.h"
#include "smc_api.h"
#include "timers.h"
#include "misc.h"
extern const uint8_t bpmpfw_bin[];
extern const uint32_t bpmpfw_bin_size;
@ -144,7 +145,7 @@ uint32_t cpu_suspend(uint64_t power_state, uint64_t entrypoint, uint64_t argumen
/* Prepare to boot the BPMP running our deep sleep firmware. */
/* Mark PMC registers as not secure-world only, so BPMP can access them. */
(*((volatile uint32_t *)(MMIO_GET_DEVICE_ADDRESS(MMIO_DEVID_MISC) + 0xC00))) &= 0xFFFFDFFF; /* TODO: macro */
APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 &= 0xFFFFDFFF;
/* Setup BPMP vectors. */
BPMP_VECTOR_RESET = 0x40003000; /* lp0_entry_firmware_crt0 */

20
exosphere/src/package2.c
View file

@ -441,16 +441,28 @@ void load_package2(coldboot_crt0_reloc_list_t *reloc_list) {
/* Synchronize with NX BOOTLOADER. */
sync_with_nx_bootloader(NX_BOOTLOADER_STATE_FINISHED);
/* TODO: lots of boring MMIO */
if (mkey_get_revision() >= MASTERKEY_REVISION_400_CURRENT) {
sync_with_nx_bootloader(NX_BOOTLOADER_STATE_FINISHED_4X);
setup_4x_mmio();
setup_4x_mmio(); /* TODO */
} else {
sync_with_nx_bootloader(NX_BOOTLOADER_STATE_FINISHED);
}
/* TODO: Update SCR_EL3 depending on value in Bootconfig. */
/* Update SCR_EL3 depending on value in Bootconfig. */
do {
uint64_t temp_scr_el3;
__asm__ __volatile__ ("mrs %0, scr_el3" : "=r"(temp_scr_el3) :: "memory");
temp_scr_el3 &= 0xFFFFFFF7;
if (bootconfig_should_set_scr_el3_bit()) {
temp_scr_el3 |= 8;
}
__asm__ __volatile__ ("msr scr_el3, %0" :: "r"(temp_scr_el3) : "memory");
__asm__ __volatile__("isb");
} while(false);
if (MAILBOX_NX_BOOTLOADER_IS_SECMON_AWAKE) {
panic(0x7A700001);