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exo2: add a number of minor configuration fixes

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This commit is contained in:
Michael Scire 2020-06-05 04:07:56 -07:00 committed by SciresM
parent 8e401f4daa
commit 068c25ce66
5 changed files with 25 additions and 5 deletions
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8
exosphere2/program/source/secmon_setup.cpp
View file

@ -29,6 +29,7 @@ namespace ams::secmon {
namespace { namespace {
constexpr inline const uintptr_t TIMER = secmon::MemoryRegionVirtualDeviceTimer.GetAddress(); constexpr inline const uintptr_t TIMER = secmon::MemoryRegionVirtualDeviceTimer.GetAddress();
constexpr inline const uintptr_t SYSTEM = secmon::MemoryRegionVirtualDeviceSystem.GetAddress();
constexpr inline const uintptr_t APB_MISC = secmon::MemoryRegionVirtualDeviceApbMisc.GetAddress(); constexpr inline const uintptr_t APB_MISC = secmon::MemoryRegionVirtualDeviceApbMisc.GetAddress();
constexpr inline const uintptr_t FLOW_CTLR = secmon::MemoryRegionVirtualDeviceFlowController.GetAddress(); constexpr inline const uintptr_t FLOW_CTLR = secmon::MemoryRegionVirtualDeviceFlowController.GetAddress();
constexpr inline const uintptr_t PMC = secmon::MemoryRegionVirtualDevicePmc.GetAddress(); constexpr inline const uintptr_t PMC = secmon::MemoryRegionVirtualDevicePmc.GetAddress();
@ -784,12 +785,12 @@ namespace ams::secmon {
reg::Write(MC + MC_IRAM_TOM, ( 0u) & MC_IRAM_TOM_WRITE_MASK); reg::Write(MC + MC_IRAM_TOM, ( 0u) & MC_IRAM_TOM_WRITE_MASK);
/* Lock the IRAM aperture. */ /* Lock the IRAM aperture. */
reg::Write(MC + MC_IRAM_REG_CTRL, MC_REG_BITS_ENUM(IRAM_REG_CTRL_IRAM_CFG_WRITE_ACCESS, DISABLED)); reg::ReadWrite(MC + MC_IRAM_REG_CTRL, MC_REG_BITS_ENUM(IRAM_REG_CTRL_IRAM_CFG_WRITE_ACCESS, DISABLED));
/* Disable the ARC clock gate override. */ /* Disable the ARC clock gate override. */
reg::ReadWrite(CLK_RST + CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD, CLK_RST_REG_BITS_ENUM(LVL2_CLK_GATE_OVRD_ARC_CLK_OVR_ON, OFF)); reg::ReadWrite(CLK_RST + CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD, CLK_RST_REG_BITS_ENUM(LVL2_CLK_GATE_OVRD_ARC_CLK_OVR_ON, OFF));
/* Rea IRAM REG CTRL to make sure our writes take. */ /* Read IRAM REG CTRL to make sure our writes take. */
reg::Read(MC + MC_IRAM_REG_CTRL); reg::Read(MC + MC_IRAM_REG_CTRL);
} }
@ -1126,6 +1127,9 @@ namespace ams::secmon {
reg::Write(EVP + EVP_COP_IRQ_VECTOR, BpmpExceptionVector); reg::Write(EVP + EVP_COP_IRQ_VECTOR, BpmpExceptionVector);
reg::Write(EVP + EVP_COP_FIQ_VECTOR, BpmpExceptionVector); reg::Write(EVP + EVP_COP_FIQ_VECTOR, BpmpExceptionVector);
/* Disable arbitration for the bpmp. */
reg::ReadWrite(SYSTEM + AHB_ARBITRATION_DISABLE, AHB_REG_BITS_ENUM(ARBITRATION_DISABLE_COP, DISABLE));
/* Turn on the SMMU for the BPMP. */ /* Turn on the SMMU for the BPMP. */
EnableBpmpSmmu(); EnableBpmpSmmu();

2
exosphere2/program/source/smc/secmon_smc_power_management.cpp
View file

@ -111,7 +111,7 @@ namespace ams::secmon::smc {
const auto core_id = hw::GetCurrentCoreId(); const auto core_id = hw::GetCurrentCoreId();
/* Configure the flow controller to prepare for shutting down the current core. */ /* Configure the flow controller to prepare for shutting down the current core. */
flow::SetCpuCsr(core_id, FLOW_CTLR_CPUN_CSR_ENABLE_EXT_DISABLE); flow::SetCpuCsr(core_id, FLOW_CTLR_CPUN_CSR_ENABLE_EXT_POWERGATE_CPU_ONLY);
flow::SetHaltCpuEvents(core_id, false); flow::SetHaltCpuEvents(core_id, false);
flow::SetCc4Ctrl(core_id, 0); flow::SetCc4Ctrl(core_id, 0);

12
libraries/libexosphere/include/exosphere/tegra/tegra_ahb_arbc.hpp
View file

@ -24,3 +24,15 @@
#define AHB_MASTER_SWID_1 (0x038) #define AHB_MASTER_SWID_1 (0x038)
#define AHB_GIZMO_TZRAM (0x054) #define AHB_GIZMO_TZRAM (0x054)
#define AHB_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (AHB_, NAME)
#define AHB_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (AHB_, NAME, VALUE)
#define AHB_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (AHB_, NAME, ENUM)
#define AHB_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(AHB_, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
#define DEFINE_AHB_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (AHB_, NAME, __OFFSET__, __WIDTH__)
#define DEFINE_AHB_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE)
#define DEFINE_AHB_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
#define DEFINE_AHB_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
#define DEFINE_AHB_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_COP, 1, ENABLE, DISABLE);

2
libraries/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp
View file

@ -49,7 +49,7 @@
DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_ENABLE, 0, DISABLE, ENABLE); DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_ENABLE, 0, DISABLE, ENABLE);
DEFINE_FLOW_REG(CPUN_CSR_WAIT_WFI_BITMAP, 8, 4); DEFINE_FLOW_REG(CPUN_CSR_WAIT_WFI_BITMAP, 8, 4);
DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_ENABLE_EXT, 12, DISABLE, ENABLE); DEFINE_FLOW_REG_TWO_BIT_ENUM(CPUN_CSR_ENABLE_EXT, 12, POWERGATE_CPU_ONLY, POWERGATE_BOTH_CPU_NONCPU, POWERGATE_CPU_TURNOFF_CPURAIL, PG_EMULATION);
DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_EVENT_FLAG, 14, FALSE, TRUE); DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_EVENT_FLAG, 14, FALSE, TRUE);
DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_INTR_FLAG, 15, FALSE, TRUE); DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_INTR_FLAG, 15, FALSE, TRUE);

6
libraries/libexosphere/source/gic/gic_api.cpp
View file

@ -124,7 +124,11 @@ namespace ams::gic {
const int word = i / scale; const int word = i / scale;
const int bit = (i % scale) * width; const int bit = (i % scale) * width;
reg::ReadWrite(address + sizeof(u32) * word, REG_BITS_VALUE(bit, width, value)); const u32 mask = ((1u << width) - 1) << bit;
const uintptr_t reg_addr = address + sizeof(u32) * word;
const u32 old = reg::Read(reg_addr) & ~mask;
reg::Write(reg_addr, old | ((value << bit) & mask));
} }
void Write(uintptr_t address, int width, int i, u32 value) { void Write(uintptr_t address, int width, int i, u32 value) {