mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-09-19 22:59:00 +00:00
[exosphere] Rewrite crt0/init and ld script
This commit is contained in:
TuxSH
parent
02e01360fd
commit
05b8b42164
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@ -3,7 +3,9 @@ ENTRY(__start_cold)
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MEMORY
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{
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fake : ORIGIN = 0, LENGTH = 4096M
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NULL : ORIGIN = 0, LENGTH = 4K
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ccrt0 : ORIGIN = 0x040006000, LENGTH = 4K
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glob : ORIGIN = 0x040020000, LENGTH = 128K
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tzram : ORIGIN = 0x07C010000, LENGTH = 64K
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/*
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The warmboot crt0 is preceeded by the exception vector page and the L2 and L3 translation tables.
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@ -12,7 +14,7 @@ MEMORY
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*/
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warmboot_crt0 : ORIGIN = ORIGIN(tzram) + 12K, LENGTH = 2K
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/* 8K are the MMU L2 and L3 tables & 2K from the evt page */
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/* 8K are the MMU L2 and L3 tables & 2K from the evt page */
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main : ORIGIN = 0x1F01E0000 + LENGTH(warmboot_crt0), LENGTH = LENGTH(tzram) - LENGTH(pk2ldr) - LENGTH(evt) - LENGTH(warmboot_crt0) - 10K
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pk2ldr : ORIGIN = ORIGIN(main) - LENGTH(warmboot_crt0) + LENGTH(tzram), LENGTH = 8K
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/* The first half of the page are exception entry stacks, the other half are the vectors themselves */
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@ -21,12 +23,14 @@ MEMORY
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SECTIONS
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{
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PROVIDE(__start__ = 0x0);
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PROVIDE(__start__ = 0x040006000);
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. = __start__;
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.cold_crt0 :
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{
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. = ALIGN(64);
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__cold_crt0_start__ = ABSOLUTE(.);
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__glob_origin__ = ORIGIN(glob);
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KEEP (*(.cold_crt0.text.start)) /* MUST be first */
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KEEP (*(.cold_crt0.text*))
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KEEP (build/coldboot_init.o(.text*))
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@ -36,9 +40,10 @@ SECTIONS
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build/coldboot_init.o(.data*)
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. = ALIGN(8);
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*(.cold_crt0.bss*)
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build/coldboot_init.o(.bss*)
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build/coldboot_init.o(.bss* COMMON)
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. = ALIGN(64);
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} >fake AT>fake
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__cold_crt0_end__ = ABSOLUTE(.);
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} >ccrt0 AT>glob
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.pk2ldr :
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{
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@ -49,16 +54,16 @@ SECTIONS
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build/package2.o(.rodata*)
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build/package2.o(.data*)
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. = ALIGN(8);
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} >pk2ldr AT>fake
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} >pk2ldr AT>glob
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.pk2ldr.bss :
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{
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. = ALIGN(8);
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__pk2ldr_bss_start__ = ABSOLUTE(.);
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build/package2.o(.bss*)
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build/package2.o(.bss* COMMON)
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. = ALIGN(8);
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__pk2ldr_end__ = ABSOLUTE(.);
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} >pk2ldr AT>fake
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} >pk2ldr AT>glob
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.vectors :
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{
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@ -68,7 +73,7 @@ SECTIONS
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KEEP (*(.vectors*))
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. = ALIGN(8);
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__vectors_end__ = ABSOLUTE(.);
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} >evt AT>fake
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} >evt AT>glob
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.warm_crt0 :
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{
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@ -87,7 +92,7 @@ SECTIONS
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build/warmboot_init.o(.bss*)
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. = ALIGN(64);
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__warmboot_crt0_end__ = ABSOLUTE(.);
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} >warmboot_crt0 AT>fake
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} >warmboot_crt0 AT>glob
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.text :
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{
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@ -100,37 +105,37 @@ SECTIONS
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*(.text.hot .text.hot.*)
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*(.text .stub .text.* .gnu.linkonce.t.*)
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. = ALIGN(8);
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} >main AT>fake
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} >main AT>glob
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.init :
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{
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KEEP( *(.init) )
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. = ALIGN(8);
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} >main AT>fake
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} >main AT>glob
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.plt :
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{
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*(.plt)
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*(.iplt)
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. = ALIGN(8);
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} >main AT>fake
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} >main AT>glob
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.fini :
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{
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KEEP( *(.fini) )
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. = ALIGN(8);
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} >main AT>fake
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} >main AT>glob
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.rodata :
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{
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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SORT(CONSTRUCTORS)
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. = ALIGN(8);
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} >main AT>fake
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} >main AT>glob
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.got : { __got_start__ = ABSOLUTE(.); *(.got) *(.igot) } >main AT>fake
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.got.plt : { *(.got.plt) *(.igot.plt) __got_end__ = ABSOLUTE(.);} >main AT>fake
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.got : { __got_start__ = ABSOLUTE(.); *(.got) *(.igot) } >main AT>glob
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.got.plt : { *(.got.plt) *(.igot.plt) __got_end__ = ABSOLUTE(.);} >main AT>glob
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.preinit_array :
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{
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@ -139,7 +144,7 @@ SECTIONS
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KEEP (*(.preinit_array))
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PROVIDE (__preinit_array_end = .);
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. = ALIGN(8);
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} >main AT>fake
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} >main AT>glob
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.init_array :
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{
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@ -147,7 +152,7 @@ SECTIONS
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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PROVIDE (__init_array_end = .);
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} >main AT>fake
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} >main AT>glob
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.fini_array :
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{
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@ -157,7 +162,7 @@ SECTIONS
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KEEP (*(SORT(.fini_array.*)))
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PROVIDE (__fini_array_end = .);
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. = ALIGN(8);
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} >main AT>fake
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} >main AT>glob
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.ctors :
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{
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@ -167,7 +172,7 @@ SECTIONS
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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. = ALIGN(8);
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} >main AT>fake
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} >main AT>glob
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.dtors ALIGN(8) :
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{
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@ -177,33 +182,33 @@ SECTIONS
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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. = ALIGN(8);
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} >main AT>fake
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} >main AT>glob
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.data ALIGN(8) :
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{
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*(.data .data.* .gnu.linkonce.d.*)
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CONSTRUCTORS
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. = ALIGN(8);
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} >main AT>fake
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} >main AT>glob
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.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } >main AT>fake
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.eh_frame : { KEEP (*(.eh_frame)) *(.eh_frame.*) } >main AT>fake
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.gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) } >main AT>fake
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.gnu_extab : { *(.gnu_extab*) } >main AT>fake
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.exception_ranges : { *(.exception_ranges .exception_ranges*) } >main AT>fake
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.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } >main AT>glob
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.eh_frame : { KEEP (*(.eh_frame)) *(.eh_frame.*) } >main AT>glob
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.gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) } >main AT>glob
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.gnu_extab : { *(.gnu_extab*) } >main AT>glob
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.exception_ranges : { *(.exception_ranges .exception_ranges*) } >main AT>glob
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.dynamic : { *(.dynamic) } >main AT>fake
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.interp : { *(.interp) } >main AT>fake
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.note.gnu.build-id : { *(.note.gnu.build-id) } >main AT>fake
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.hash : { *(.hash) } >main AT>fake
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.gnu.hash : { *(.gnu.hash) } >main AT>fake
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.gnu.version : { *(.gnu.version) } >main AT>fake
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.gnu.version_d : { *(.gnu.version_d) } >main AT>fake
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.gnu.version_r : { *(.gnu.version_r) } >main AT>fake
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.dynsym : { *(.dynsym) } >main AT>fake
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.dynstr : { *(.dynstr) } >main AT>fake
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.rela.dyn : { *(.rela.*); __main_end__ = ABSOLUTE(.);} >main AT>fake
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.dynamic : { *(.dynamic) } >main AT>glob
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.interp : { *(.interp) } >main AT>glob
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.note.gnu.build-id : { *(.note.gnu.build-id) } >main AT>glob
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.hash : { *(.hash) } >main AT>glob
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.gnu.hash : { *(.gnu.hash) } >main AT>glob
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.gnu.version : { *(.gnu.version) } >main AT>glob
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.gnu.version_d : { *(.gnu.version_d) } >main AT>glob
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.gnu.version_r : { *(.gnu.version_r) } >main AT>glob
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.dynsym : { *(.dynsym) } >main AT>glob
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.dynstr : { *(.dynstr) } >main AT>glob
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.rela.dyn : { *(.rela.*); __main_end__ = ABSOLUTE(.);} >main AT>glob
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.bss :
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{
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@ -215,7 +220,7 @@ SECTIONS
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*(COMMON)
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. = ALIGN(8);
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__main_end__ = ABSOLUTE(.);
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} >main AT>fake
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} >main AT>glob
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__end__ = ABSOLUTE(.) ;
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@ -230,35 +235,35 @@ SECTIONS
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/DISCARD/ : { *(.group .comment .note) }
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.stab 0 : { *(.stab) } AT>glob
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.stabstr 0 : { *(.stabstr) } AT>glob
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.stab.excl 0 : { *(.stab.excl) } AT>glob
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.stab.exclstr 0 : { *(.stab.exclstr) } AT>glob
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.stab.index 0 : { *(.stab.index) } AT>glob
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.stab.indexstr 0 : { *(.stab.indexstr) } AT>glob
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/* DWARF debug sections.
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Symbols in the DWARF debugging sections are relative to the beginning
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of the section so we begin them at 0. */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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.debug 0 : { *(.debug) } AT>glob
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.line 0 : { *(.line) } AT>glob
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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.debug_srcinfo 0 : { *(.debug_srcinfo) } AT>glob
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.debug_sfnames 0 : { *(.debug_sfnames) } AT>glob
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) } AT>glob
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.debug_pubnames 0 : { *(.debug_pubnames) } AT>glob
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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.debug_info 0 : { *(.debug_info) } AT>glob
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.debug_abbrev 0 : { *(.debug_abbrev) } AT>glob
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.debug_line 0 : { *(.debug_line) } AT>glob
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.debug_frame 0 : { *(.debug_frame) } AT>glob
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.debug_str 0 : { *(.debug_str) } AT>glob
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.debug_loc 0 : { *(.debug_loc) } AT>glob
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.debug_macinfo 0 : { *(.debug_macinfo) } AT>glob
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}
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@ -63,7 +63,7 @@ tlb_invalidate_page_inner_shareable:
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* x1: 0 clean & invalidate, 1 invalidate only
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* x2~x9: clobbered
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*/
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.section .text.__asm_dcache_level, "ax", %progbits
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.section .warm_crt0.text.__asm_dcache_level, "ax", %progbits
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.type __asm_dcache_level, %function
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__asm_dcache_level:
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lsl x12, x0, #1
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@ -108,7 +108,7 @@ loop_way:
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*
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* flush or invalidate all data cache by SET/WAY.
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*/
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.section .text.__asm_dcache_all, "ax", %progbits
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.section .warm_crt0.text.__asm_dcache_all, "ax", %progbits
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.type __asm_dcache_all, %function
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__asm_dcache_all:
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mov x1, x0
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@ -146,14 +146,14 @@ skip:
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finished:
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ret
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.section .text.flush_dcache_all, "ax", %progbits
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.section .warm_crt0.text.flush_dcache_all, "ax", %progbits
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.type flush_dcache_all, %function
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.global flush_dcache_all
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flush_dcache_all:
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mov x0, #0
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b __asm_dcache_all
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.section .text.invalidate_dcache_all, "ax", %progbits
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.section .warm_crt0.text.invalidate_dcache_all, "ax", %progbits
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.type invalidate_dcache_all, %function
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.global invalidate_dcache_all
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invalidate_dcache_all:
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@ -168,7 +168,7 @@ invalidate_dcache_all:
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* x0: start address
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* x1: end address
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*/
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.section .text.flush_dcache_range, "ax", %progbits
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.section .warm_crt0.text.flush_dcache_range, "ax", %progbits
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.type flush_dcache_range, %function
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.global flush_dcache_range
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flush_dcache_range:
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@ -196,7 +196,7 @@ flush_dcache_range:
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* x0: start address
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* x1: end address
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*/
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.section .text.invalidate_dcache_range, "ax", %progbits
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.section .warm_crt0.text.invalidate_dcache_range, "ax", %progbits
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.type invalidate_dcache_range, %function
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.global invalidate_dcache_range
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invalidate_dcache_range:
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@ -220,7 +220,7 @@ invalidate_dcache_range:
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*
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* invalidate all icache entries.
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*/
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.section .text.invalidate_icache_all_inner_shareable, "ax", %progbits
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.section .warm_crt0.text.invalidate_icache_all_inner_shareable, "ax", %progbits
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.type invalidate_icache_all_inner_shareable, %function
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.global invalidate_icache_all_inner_shareable
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invalidate_icache_all_inner_shareable:
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@ -231,7 +231,7 @@ invalidate_icache_all_inner_shareable:
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isb
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ret
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.section .text.invalidate_icache_all, "ax", %progbits
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.section .warm_crt0.text.invalidate_icache_all, "ax", %progbits
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.type invalidate_icache_all, %function
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.global invalidate_icache_all
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invalidate_icache_all:
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@ -266,17 +266,17 @@ void setup_current_core_state(void) {
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void identity_unmap_iram_cd_tzram(void) {
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/* See also: configure_ttbls (in coldboot_init.c). */
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uintptr_t *mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_ADDRESS(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64);
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uintptr_t *mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_ADDRESS(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE);
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/*uintptr_t *mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_ADDRESS(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64);
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uintptr_t *mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_ADDRESS(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE);*/
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uintptr_t *mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_ADDRESS(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE);
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mmu_unmap_range(3, mmu_l3_tbl, IDENTITY_GET_MAPPING_ADDRESS(IDENTITY_MAPPING_IRAM_CD), IDENTITY_GET_MAPPING_SIZE(IDENTITY_MAPPING_IRAM_CD));
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mmu_unmap_range(3, mmu_l3_tbl, IDENTITY_GET_MAPPING_ADDRESS(IDENTITY_MAPPING_TZRAM), IDENTITY_GET_MAPPING_SIZE(IDENTITY_MAPPING_TZRAM));
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/*mmu_unmap_range(3, mmu_l3_tbl, IDENTITY_GET_MAPPING_ADDRESS(IDENTITY_MAPPING_TZRAM), IDENTITY_GET_MAPPING_SIZE(IDENTITY_MAPPING_TZRAM));
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mmu_unmap(2, mmu_l2_tbl, 0x40000000);
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mmu_unmap(2, mmu_l2_tbl, 0x7C000000);
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mmu_unmap(1, mmu_l1_tbl, 0x40000000);
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mmu_unmap(1, mmu_l1_tbl, 0x40000000);*/
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tlb_invalidate_all_inner_shareable();
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}
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@ -1,5 +1,6 @@
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#include <string.h>
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#include "utils.h"
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#include "arm.h"
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#include "mmu.h"
|
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#include "memory_map.h"
|
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#include "arm.h"
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@ -14,6 +15,11 @@
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extern const uint8_t __start_cold[];
|
||||
|
||||
/* warboot_init.c */
|
||||
extern unsigned int g_exosphere_target_firmware_for_init;
|
||||
void init_dma_controllers(unsigned int target_firmware);
|
||||
void set_memory_registers_enable_mmu(void);
|
||||
|
||||
static void identity_map_all_mappings(uintptr_t *mmu_l1_tbl, uintptr_t *mmu_l3_tbl) {
|
||||
static const uintptr_t addrs[] = { TUPLE_FOLD_LEFT_0(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
|
||||
static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
|
||||
|
|
@ -98,32 +104,15 @@ static void configure_ttbls(void) {
|
|||
tzram_map_all_segments(mmu_l3_tbl);
|
||||
}
|
||||
|
||||
static void translate_func_list(coldboot_crt0_reloc_list_t *reloc_list, boot_func_list_t *func_list, bool in_tzram) {
|
||||
coldboot_crt0_reloc_t *warmboot_crt0_reloc = &reloc_list->relocs[0];
|
||||
coldboot_crt0_reloc_t *main_reloc = &reloc_list->relocs[reloc_list->nb_relocs_pre_mmu_init];
|
||||
|
||||
uintptr_t main_pa;
|
||||
if (in_tzram) {
|
||||
/* The main segment immediately follows the warmboot crt0 in TZRAM, in the same page. */
|
||||
main_pa = (uintptr_t)warmboot_crt0_reloc->vma | ((uintptr_t)main_reloc->vma & 0xFFF);
|
||||
} else {
|
||||
main_pa = reloc_list->reloc_base + main_reloc->reloc_offset;
|
||||
}
|
||||
|
||||
for(size_t i = 0; i < func_list->nb_funcs; i++) {
|
||||
if(func_list->addrs[i] >= 0x1F0000000ull) {
|
||||
func_list->addrs[i] = main_pa + func_list->addrs[i] - (uintptr_t)main_reloc->vma;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void do_relocation(const coldboot_crt0_reloc_list_t *reloc_list, size_t index) {
|
||||
extern const uint8_t __glob_origin__[];
|
||||
uint64_t *p_vma = (uint64_t *)reloc_list->relocs[index].vma;
|
||||
const uint64_t *p_lma = (const uint64_t *)(reloc_list->reloc_base + reloc_list->relocs[index].reloc_offset);
|
||||
size_t offset = reloc_list->relocs[index].lma - (uintptr_t)__glob_origin__;
|
||||
const uint64_t *p_lma = (const uint64_t *)(reloc_list->reloc_base + offset);
|
||||
size_t size = reloc_list->relocs[index].end_vma - reloc_list->relocs[index].vma;
|
||||
|
||||
for(size_t i = 0; i < size / 8; i++) {
|
||||
p_vma[i] = reloc_list->relocs[index].reloc_offset != 0 ? p_lma[i] : 0;
|
||||
p_vma[i] = offset != 0 ? p_lma[i] : 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -131,14 +120,19 @@ uintptr_t get_coldboot_crt0_stack_address(void) {
|
|||
return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800;
|
||||
}
|
||||
|
||||
void coldboot_init(coldboot_crt0_reloc_list_t *reloc_list, boot_func_list_t *func_list, boot_func_list_t *func_list_warmboot, uintptr_t start_cold) {
|
||||
void coldboot_init(coldboot_crt0_reloc_list_t *reloc_list, uintptr_t start_cold) {
|
||||
//MAILBOX_NX_SECMON_BOOT_TIME = TIMERUS_CNTR_1US_0;
|
||||
|
||||
boot_func_list_t func_copy = *func_list;
|
||||
/* Custom approach */
|
||||
reloc_list->reloc_base = start_cold;
|
||||
translate_func_list(reloc_list, func_list, false);
|
||||
|
||||
|
||||
/* TODO: Set NX BOOTLOADER clock time field */
|
||||
|
||||
/* This at least copies .warm_crt0 to its VMA. */
|
||||
for(size_t i = 0; i < reloc_list->nb_relocs_pre_mmu_init; i++) {
|
||||
do_relocation(reloc_list, i);
|
||||
}
|
||||
/* At this point, we can (and will) access functions located in .warm_crt0 */
|
||||
|
||||
/*
|
||||
From https://events.static.linuxfound.org/sites/events/files/slides/slides_17.pdf :
|
||||
|
|
@ -149,37 +143,25 @@ void coldboot_init(coldboot_crt0_reloc_list_t *reloc_list, boot_func_list_t *fun
|
|||
|
||||
It should be fine to clear that here and not before.
|
||||
*/
|
||||
func_list->funcs.flush_dcache_all();
|
||||
func_list->funcs.invalidate_icache_all();
|
||||
|
||||
flush_dcache_all();
|
||||
invalidate_icache_all();
|
||||
|
||||
/* TODO: Set NX BOOTLOADER clock time field */
|
||||
|
||||
/* This at least copies .warm_crt0 to its VMA. */
|
||||
for(size_t i = 0; i < reloc_list->nb_relocs_pre_mmu_init; i++) {
|
||||
do_relocation(reloc_list, i);
|
||||
}
|
||||
/* At this point, we can (and will) access functions located in .warm_crt0 */
|
||||
|
||||
/* Set target firmware. */
|
||||
func_list->target_firmware = exosphere_get_target_firmware_physical();
|
||||
g_exosphere_target_firmware_for_init = exosphere_get_target_firmware_for_init();
|
||||
|
||||
/* Initialize DMA controllers, and write to AHB_GIZMO_TZRAM. */
|
||||
/* TZRAM accesses should work normally after this point. */
|
||||
func_list->funcs.init_dma_controllers(func_list->target_firmware);
|
||||
init_dma_controllers(g_exosphere_target_firmware_for_init);
|
||||
|
||||
configure_ttbls();
|
||||
func_list->funcs.set_memory_registers_enable_mmu();
|
||||
set_memory_registers_enable_mmu();
|
||||
|
||||
/* Copy or clear the remaining sections */
|
||||
for(size_t i = 0; i < reloc_list->nb_relocs_post_mmu_init; i++) {
|
||||
do_relocation(reloc_list, reloc_list->nb_relocs_pre_mmu_init + i);
|
||||
}
|
||||
|
||||
func_list->funcs.flush_dcache_all();
|
||||
func_list->funcs.invalidate_icache_all();
|
||||
flush_dcache_all();
|
||||
invalidate_icache_all();
|
||||
/* At this point we can access all the mapped segments (all other functions, data...) normally */
|
||||
|
||||
*func_list_warmboot = func_copy;
|
||||
translate_func_list(reloc_list, func_list_warmboot, true);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,9 +23,6 @@
|
|||
/* start.s */
|
||||
void __attribute__((noreturn)) __jump_to_lower_el(uint64_t arg, uintptr_t ep, uint32_t spsr);
|
||||
|
||||
/* See notes in start.s */
|
||||
critical_section_t g_boot_critical_section = {{{.ticket_number = 1}}};
|
||||
|
||||
static saved_cpu_context_t g_cpu_contexts[NUM_CPU_CORES] = {0};
|
||||
|
||||
void use_core_entrypoint_and_argument(uint32_t core, uintptr_t *entrypoint_addr, uint64_t *argument) {
|
||||
|
|
@ -47,15 +44,22 @@ void set_core_entrypoint_and_argument(uint32_t core, uintptr_t entrypoint_addr,
|
|||
g_cpu_contexts[core].argument = argument;
|
||||
}
|
||||
|
||||
static __attribute__((target("cmodel=large"), noinline))
|
||||
critical_section_t *get_boot_critical_section(void) {
|
||||
return &g_boot_critical_section;
|
||||
}
|
||||
|
||||
void __attribute__((noreturn)) core_jump_to_lower_el(void) {
|
||||
uintptr_t ep;
|
||||
uint64_t arg;
|
||||
unsigned int core_id = get_core_id();
|
||||
uint32_t spsr = get_spsr();
|
||||
critical_section_t *critsec = get_boot_critical_section();
|
||||
|
||||
use_core_entrypoint_and_argument(core_id, &ep, &arg);
|
||||
critical_section_leave(&g_boot_critical_section);
|
||||
flush_dcache_range(&g_boot_critical_section, (uint8_t *)&g_boot_critical_section + sizeof(g_boot_critical_section)); /* already does a dsb sy */
|
||||
critical_section_leave(critsec);
|
||||
flush_dcache_range(critsec, (uint8_t *)critsec + sizeof(critical_section_t));
|
||||
/* already does a dsb sy */
|
||||
__sev();
|
||||
|
||||
/* Nintendo hardcodes EL1, but we can boot fine using other EL1/EL2 modes as well */
|
||||
|
|
|
|||
|
|
@ -34,8 +34,8 @@ typedef struct {
|
|||
unsigned int exosphere_load_config(void);
|
||||
unsigned int exosphere_get_target_firmware(void);
|
||||
|
||||
static inline unsigned int exosphere_get_target_firmware_physical(void) {
|
||||
static inline unsigned int exosphere_get_target_firmware_for_init(void) {
|
||||
return MAILBOX_EXOSPHERE_CONFIG_PHYS.magic == MAGIC_EXOSPHERE_BOOTCONFIG ? MAILBOX_EXOSPHERE_CONFIG_PHYS.target_firmware : EXOSPHERE_TARGET_FIRMWARE_DEFAULT_FOR_DEBUG;
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ static void setup_se(void) {
|
|||
|
||||
/* Detect Master Key revision. */
|
||||
mkey_detect_revision();
|
||||
|
||||
|
||||
/* Derive new device keys. */
|
||||
switch (exosphere_get_target_firmware()) {
|
||||
case EXOSPHERE_TARGET_FIRMWARE_100:
|
||||
|
|
@ -294,7 +294,7 @@ static uint32_t decrypt_and_validate_header(package2_header_t *header) {
|
|||
}
|
||||
|
||||
/* Ensure we successfully decrypted the header. */
|
||||
if (mkey_rev > mkey_get_revision()) {
|
||||
if (mkey_rev > mkey_get_revision()) {
|
||||
panic(0xFAF00003);
|
||||
}
|
||||
} else if (!validate_package2_metadata(&header->metadata)) {
|
||||
|
|
@ -349,7 +349,7 @@ static void load_package2_sections(package2_meta_t *metadata, uint32_t master_ke
|
|||
memset(load_buf, 0, PACKAGE2_SIZE_MAX);
|
||||
load_buf = (void *)potential_base_start;
|
||||
}
|
||||
|
||||
|
||||
size_t cur_section_offset = 0;
|
||||
/* Copy each section to its appropriate location, decrypting if necessary. */
|
||||
for (unsigned int section = 0; section < PACKAGE2_SECTION_MAX; section++) {
|
||||
|
|
@ -395,7 +395,7 @@ uintptr_t get_pk2ldr_stack_address(void) {
|
|||
void load_package2(coldboot_crt0_reloc_list_t *reloc_list) {
|
||||
/* Load Exosphere-specific config. */
|
||||
exosphere_load_config();
|
||||
|
||||
|
||||
/* Setup the Security Engine. */
|
||||
setup_se();
|
||||
|
||||
|
|
@ -407,10 +407,10 @@ void load_package2(coldboot_crt0_reloc_list_t *reloc_list) {
|
|||
|
||||
/* Save boot reason to global. */
|
||||
bootconfig_load_boot_reason((volatile boot_reason_t *)(MAILBOX_NX_BOOTLOADER_BOOT_REASON));
|
||||
|
||||
|
||||
/* Initialize cache'd random bytes for kernel. */
|
||||
randomcache_init();
|
||||
|
||||
|
||||
/* memclear the initial copy of Exosphere running in IRAM (relocated to TZRAM by earlier code). */
|
||||
memset((void *)reloc_list->reloc_base, 0, reloc_list->loaded_bin_size);
|
||||
/* Let NX Bootloader know that we're running. */
|
||||
|
|
@ -438,6 +438,7 @@ void load_package2(coldboot_crt0_reloc_list_t *reloc_list) {
|
|||
secure_additional_devices();
|
||||
|
||||
/* Remove the identity mapping for iRAM-C+D & TZRAM */
|
||||
/* For our crt0 to work, this doesn't actually unmap TZRAM */
|
||||
identity_unmap_iram_cd_tzram();
|
||||
|
||||
/* Load header from NX_BOOTLOADER-initialized DRAM. */
|
||||
|
|
@ -451,7 +452,7 @@ void load_package2(coldboot_crt0_reloc_list_t *reloc_list) {
|
|||
if (header.signature[0] == 0 && memcmp(header.signature, header.signature + 1, sizeof(header.signature) - 1) == 0 && header.metadata.magic == MAGIC_PK21) {
|
||||
bootconfig_set_package2_plaintext_and_unsigned();
|
||||
}
|
||||
|
||||
|
||||
verify_header_signature(&header);
|
||||
|
||||
/* Decrypt header, get key revision required. */
|
||||
|
|
@ -484,7 +485,7 @@ void load_package2(coldboot_crt0_reloc_list_t *reloc_list) {
|
|||
} else {
|
||||
sync_with_nx_bootloader(NX_BOOTLOADER_STATE_FINISHED);
|
||||
}
|
||||
|
||||
|
||||
/* Prepare the SMC API with version-dependent SMCs. */
|
||||
set_version_specific_smcs();
|
||||
|
||||
|
|
|
|||
|
|
@ -81,6 +81,24 @@ __start_cold:
|
|||
However we'll initialize g_boot_critical_section so that it acts like core0 has entered it,
|
||||
for it to be in .data and for safety.
|
||||
*/
|
||||
|
||||
/* Relocate the crt0. Nintendo doesn't do it. */
|
||||
ldr x0, =__cold_crt0_start__
|
||||
adr x1, __start_cold
|
||||
ldr x2, =__cold_crt0_end__
|
||||
cmp x0, x1
|
||||
beq _post_cold_crt0_reloc
|
||||
1:
|
||||
ldp x3, x4, [x0], #0x10
|
||||
stp x3, x4, [x1], #0x10
|
||||
cmp x0, x2
|
||||
blo 1b
|
||||
|
||||
ldr x16, =_post_cold_crt0_reloc
|
||||
br x16
|
||||
|
||||
_post_cold_crt0_reloc:
|
||||
|
||||
msr spsel, #0
|
||||
bl get_coldboot_crt0_stack_address
|
||||
mov sp, x0
|
||||
|
|
@ -88,9 +106,7 @@ __start_cold:
|
|||
|
||||
adr x0, g_coldboot_crt0_relocation_list
|
||||
mov x19, x0
|
||||
adr x1, g_coldboot_crt0_main_func_list
|
||||
ldr x2, =g_warmboot_crt0_main_func_list
|
||||
adr x3, __start_cold
|
||||
adr x1, __start_cold
|
||||
bl coldboot_init
|
||||
|
||||
ldr x16, =__jump_to_main_cold
|
||||
|
|
@ -112,17 +128,12 @@ __start_warm:
|
|||
|
||||
/* PA(__main_start__) = __warmboot_crt0_start__ + 0x800 (refer to the linker script) */
|
||||
ldr x0, =g_boot_critical_section
|
||||
ldr x1, =__main_start__
|
||||
sub x0, x0, x1
|
||||
ldr x1, =(__start_warm + 0x800)
|
||||
add x0, x0, x1
|
||||
bl warmboot_crt0_critical_section_enter
|
||||
|
||||
bl get_warmboot_crt0_stack_address
|
||||
mov sp, x0
|
||||
mov fp, #0
|
||||
|
||||
adr x0, g_warmboot_crt0_main_func_list
|
||||
bl warmboot_init
|
||||
ldr x16, =__jump_to_main_warm
|
||||
br x16
|
||||
|
|
@ -238,20 +249,9 @@ g_coldboot_crt0_relocation_list:
|
|||
.quad __main_bss_start__, __main_end__, 0
|
||||
.quad __pk2ldr_bss_start__, __pk2ldr_end__, 0
|
||||
|
||||
.section .cold_crt0.data.g_coldboot_crt0_main_func_list, "aw", %progbits
|
||||
.align 3
|
||||
.global g_coldboot_crt0_main_func_list
|
||||
g_coldboot_crt0_main_func_list:
|
||||
.quad 4 /* Number of functions */
|
||||
.quad 0 /* Target firmware, overwritten in coldboot_init. */
|
||||
/* Functions */
|
||||
.quad init_dma_controllers
|
||||
.quad set_memory_registers_enable_mmu
|
||||
.quad flush_dcache_all
|
||||
.quad invalidate_icache_all
|
||||
|
||||
.section .warm_crt0.data.g_warmboot_crt0_main_func_list, "aw", %progbits
|
||||
.align 3
|
||||
.global g_warmboot_crt0_main_func_list
|
||||
g_warmboot_crt0_main_func_list:
|
||||
.space (6 * 8)
|
||||
/* Critical section */
|
||||
.section .warm_crt0.data.g_boot_critical_section, "aw", %progbits
|
||||
.align 2
|
||||
.global g_boot_critical_section
|
||||
g_boot_critical_section:
|
||||
.word 1 /* Core0 entered, by default. */
|
||||
|
|
|
|||
|
|
@ -25,26 +25,11 @@
|
|||
|
||||
/* Custom stuff below */
|
||||
|
||||
/* For warmboot (and coldboot crt0) */
|
||||
typedef struct {
|
||||
size_t nb_funcs;
|
||||
uint64_t target_firmware;
|
||||
union {
|
||||
struct {
|
||||
void (*init_dma_controllers)(unsigned int);
|
||||
void (*set_memory_registers_enable_mmu)(void);
|
||||
void (*flush_dcache_all)(void);
|
||||
void (*invalidate_icache_all)(void);
|
||||
} funcs;
|
||||
uintptr_t addrs[4];
|
||||
};
|
||||
} boot_func_list_t;
|
||||
|
||||
/* For coldboot */
|
||||
typedef struct {
|
||||
uint8_t *vma;
|
||||
uint8_t *end_vma;
|
||||
uintptr_t reloc_offset;
|
||||
uintptr_t lma;
|
||||
} coldboot_crt0_reloc_t;
|
||||
|
||||
typedef struct {
|
||||
|
|
|
|||
|
|
@ -12,6 +12,8 @@
|
|||
void __set_memory_registers(uintptr_t ttbr0, uintptr_t vbar, uint64_t cpuectlr, uint32_t scr,
|
||||
uint32_t tcr, uint32_t cptr, uint64_t mair, uint32_t sctlr);
|
||||
|
||||
unsigned int g_exosphere_target_firmware_for_init = 0;
|
||||
|
||||
uintptr_t get_warmboot_crt0_stack_address(void) {
|
||||
return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE012_STACK) + 0x800;
|
||||
}
|
||||
|
|
@ -140,6 +142,7 @@ void set_memory_registers_enable_mmu(void) {
|
|||
__set_memory_registers(ttbr0, vbar, cpuectlr, scr, tcr, cptr, mair, sctlr);
|
||||
}
|
||||
|
||||
#if 0 /* Since we decided not to identity-unmap TZRAM */
|
||||
static void identity_remap_tzram(void) {
|
||||
/* See also: configure_ttbls (in coldboot_init.c). */
|
||||
uintptr_t *mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64);
|
||||
|
|
@ -153,8 +156,9 @@ static void identity_remap_tzram(void) {
|
|||
IDENTITY_GET_MAPPING_SIZE(IDENTITY_MAPPING_TZRAM), IDENTITY_GET_MAPPING_ATTRIBS(IDENTITY_MAPPING_TZRAM),
|
||||
IDENTITY_IS_MAPPING_BLOCK_RANGE(IDENTITY_MAPPING_TZRAM));
|
||||
}
|
||||
#endif
|
||||
|
||||
void warmboot_init(boot_func_list_t *func_list) {
|
||||
void warmboot_init(void) {
|
||||
/*
|
||||
From https://events.static.linuxfound.org/sites/events/files/slides/slides_17.pdf :
|
||||
Caches may write back dirty lines at any time:
|
||||
|
|
@ -162,15 +166,15 @@ void warmboot_init(boot_func_list_t *func_list) {
|
|||
- Even if MMU is off
|
||||
- Even if Cacheable accesses are disabled (caches are never 'off')
|
||||
*/
|
||||
func_list->funcs.flush_dcache_all();
|
||||
func_list->funcs.invalidate_icache_all();
|
||||
flush_dcache_all();
|
||||
invalidate_icache_all();
|
||||
|
||||
/* On warmboot (not cpu_on) only */
|
||||
if (MC_SECURITY_CFG3_0 == 0) {
|
||||
init_dma_controllers(func_list->target_firmware);
|
||||
init_dma_controllers(g_exosphere_target_firmware_for_init);
|
||||
}
|
||||
|
||||
identity_remap_tzram();
|
||||
/*identity_remap_tzram();*/
|
||||
/* Nintendo pointlessly fully invalidate the TLB & invalidate the data cache on the modified ranges here */
|
||||
set_memory_registers_enable_mmu();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ void __attribute__((noreturn)) warmboot_main(void) {
|
|||
}
|
||||
|
||||
/* IRAM C+D identity mapping has actually been removed on coldboot but we don't really care */
|
||||
/* For our crt0 to work, this doesn't actually unmap TZRAM */
|
||||
identity_unmap_iram_cd_tzram();
|
||||
|
||||
/* On warmboot (not cpu_on) only */
|
||||
|
|
@ -60,7 +61,8 @@ void __attribute__((noreturn)) warmboot_main(void) {
|
|||
clear_user_smc_in_progress();
|
||||
|
||||
if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
|
||||
setup_4x_mmio(); }
|
||||
setup_4x_mmio();
|
||||
}
|
||||
}
|
||||
|
||||
setup_current_core_state();
|
||||
|
|
|
|||
Loading…
Reference in a new issue