2019-07-26 19:38:15 +00:00
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/*
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2020-01-24 10:10:40 +00:00
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* Copyright (c) 2018-2020 Atmosphère-NX
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2019-07-26 19:38:15 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef FUSEE_CAR_H
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#define FUSEE_CAR_H
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#include <stdint.h>
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#include <stdbool.h>
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#define CAR_BASE 0x60006000
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#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n)
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#define CLK_L_SDMMC1 (1 << 14)
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#define CLK_L_SDMMC2 (1 << 9)
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#define CLK_U_SDMMC3 (1 << 5)
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#define CLK_L_SDMMC4 (1 << 15)
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#define CLK_SOURCE_MASK (0b111 << 29)
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#define CLK_SOURCE_FIRST (0b000 << 29)
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#define CLK_DIVIDER_MASK (0xff << 0)
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#define CLK_DIVIDER_UNITY (0x00 << 0)
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#define NUM_CAR_BANKS 7
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/* Clock and reset devices. */
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typedef enum {
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2020-12-06 19:08:07 +00:00
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CARDEVICE_BPMP = ((0 << 5) | 0x1),
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CARDEVICE_UARTA = ((0 << 5) | 0x6),
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CARDEVICE_UARTB = ((0 << 5) | 0x7),
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CARDEVICE_I2C1 = ((0 << 5) | 0xC),
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CARDEVICE_USBD = ((0 << 5) | 0x16),
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CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
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CARDEVICE_AHBDMA = ((1 << 5) | 0x1),
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CARDEVICE_APBDMA = ((1 << 5) | 0x2),
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CARDEVICE_KFUSE = ((1 << 5) | 0x8),
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CARDEVICE_I2C5 = ((1 << 5) | 0xF),
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CARDEVICE_UARTC = ((1 << 5) | 0x17),
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CARDEVICE_USB2 = ((1 << 5) | 0x1A),
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2019-07-26 19:38:15 +00:00
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CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
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2020-12-06 19:08:07 +00:00
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CARDEVICE_TSEC = ((2 << 5) | 0x13),
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2020-12-07 18:39:23 +00:00
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CARDEVICE_MSELECT = ((3 << 5) | 0x8),
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2020-12-06 19:08:07 +00:00
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CARDEVICE_ACTMON = ((3 << 5) | 0x17),
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CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
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CARDEVICE_SE = ((3 << 5) | 0x1F),
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CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
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CARDEVICE_SOR0 = ((5 << 5) | 0x16),
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CARDEVICE_SOR1 = ((5 << 5) | 0x17),
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CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
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2019-07-26 19:38:15 +00:00
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} CarDevice;
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/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
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typedef struct {
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uint32_t rst_src; /* _RST_SOURCE_0, 0x00 */
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/* _RST_DEVICES_L/H/U_0 0x4-0xc */
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uint32_t rst_dev_l;
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uint32_t rst_dev_h;
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uint32_t rst_dev_u;
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/* _CLK_OUT_ENB_L/H/U_0 0x10-0x18 */
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uint32_t clk_out_enb_l;
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uint32_t clk_out_enb_h;
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uint32_t clk_out_enb_u;
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uint32_t _0x1C;
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uint32_t cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
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uint32_t super_cclk_div; /* _SUPER_CCLK_DIVIDER_0, 0x24 */
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uint32_t sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
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uint32_t super_sclk_div; /* _SUPER_SCLK_DIVIDER_0, 0x2c */
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uint32_t clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
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uint32_t prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
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uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0, 0x38 */
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uint32_t _0x3C;
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uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0, 0x40 */
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uint32_t clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */
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uint32_t misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */
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uint32_t clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4c */
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uint32_t osc_ctrl; /* _OSC_CTRL_0, 0x50 */
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uint32_t pll_lfsr; /* _PLL_LFSR_0, 0x54 */
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uint32_t osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */
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uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0, 0x5c */
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uint32_t _0x60[2];
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uint32_t plle_ss_cntl; /* _PLLE_SS_CNTL_0, 0x68 */
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uint32_t plle_misc1; /* _PLLE_MISC1_0, 0x6c */
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uint32_t _0x70[4];
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/* PLLC 0x80-0x8c */
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uint32_t pllc_base;
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uint32_t pllc_out;
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uint32_t pllc_misc0;
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uint32_t pllc_misc1;
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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/* PLLM 0x90-0x9c */
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uint32_t pllm_base;
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uint32_t pllm_out;
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uint32_t pllm_misc1;
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uint32_t pllm_misc2;
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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/* PLLP 0xa0-0xac */
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uint32_t pllp_base;
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uint32_t pllp_outa;
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uint32_t pllp_outb;
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uint32_t pllp_misc;
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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/* PLLA 0xb0-0xbc */
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uint32_t plla_base;
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uint32_t plla_out;
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uint32_t plla_misc0;
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uint32_t plla_misc1;
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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/* PLLU 0xc0-0xcc */
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uint32_t pllu_base;
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uint32_t pllu_out;
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uint32_t pllu_misc1;
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uint32_t pllu_misc2;
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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/* PLLD 0xd0-0xdc */
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uint32_t plld_base;
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uint32_t plld_out;
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uint32_t plld_misc1;
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uint32_t plld_misc2;
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/* PLLX 0xe0-0xe4 */
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uint32_t pllx_base;
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uint32_t pllx_misc;
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/* PLLE 0xe8-0xf4 */
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uint32_t plle_base;
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uint32_t plle_misc;
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uint32_t plle_ss_cntl1;
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uint32_t plle_ss_cntl2;
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2019-07-26 19:38:15 +00:00
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uint32_t lvl2_clk_gate_ovra; /* _LVL2_CLK_GATE_OVRA_0, 0xf8 */
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uint32_t lvl2_clk_gate_ovrb; /* _LVL2_CLK_GATE_OVRB_0, 0xfc */
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uint32_t clk_source_i2s2; /* _CLK_SOURCE_I2S2_0, 0x100 */
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uint32_t clk_source_i2s3; /* _CLK_SOURCE_I2S3_0, 0x104 */
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uint32_t clk_source_spdif_out; /* _CLK_SOURCE_SPDIF_OUT_0, 0x108 */
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uint32_t clk_source_spdif_in; /* _CLK_SOURCE_SPDIF_IN_0, 0x10c */
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uint32_t clk_source_pwm; /* _CLK_SOURCE_PWM_0, 0x110 */
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uint32_t _0x114;
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uint32_t clk_source_spi2; /* _CLK_SOURCE_SPI2_0, 0x118 */
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uint32_t clk_source_spi3; /* _CLK_SOURCE_SPI3_0, 0x11c */
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uint32_t _0x120;
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uint32_t clk_source_i2c1; /* _CLK_SOURCE_I2C1_0, 0x124 */
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uint32_t clk_source_i2c5; /* _CLK_SOURCE_I2C5_0, 0x128 */
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uint32_t _0x12c[2];
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uint32_t clk_source_spi1; /* _CLK_SOURCE_SPI1_0, 0x134 */
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uint32_t clk_source_disp1; /* _CLK_SOURCE_DISP1_0, 0x138 */
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uint32_t clk_source_disp2; /* _CLK_SOURCE_DISP2_0, 0x13c */
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uint32_t _0x140;
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uint32_t clk_source_isp; /* _CLK_SOURCE_ISP_0, 0x144 */
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uint32_t clk_source_vi; /* _CLK_SOURCE_VI_0, 0x148 */
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uint32_t _0x14c;
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uint32_t clk_source_sdmmc1; /* _CLK_SOURCE_SDMMC1_0, 0x150 */
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uint32_t clk_source_sdmmc2; /* _CLK_SOURCE_SDMMC2_0, 0x154 */
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uint32_t _0x158[3];
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uint32_t clk_source_sdmmc4; /* _CLK_SOURCE_SDMMC4_0, 0x164 */
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uint32_t _0x168[4];
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uint32_t clk_source_uarta; /* _CLK_SOURCE_UARTA_0, 0x178 */
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uint32_t clk_source_uartb; /* _CLK_SOURCE_UARTB_0, 0x17c */
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uint32_t clk_source_host1x; /* _CLK_SOURCE_HOST1X_0, 0x180 */
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uint32_t _0x184[5];
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uint32_t clk_source_i2c2; /* _CLK_SOURCE_I2C2_0, 0x198 */
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uint32_t clk_source_emc; /* _CLK_SOURCE_EMC_0, 0x19c */
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uint32_t clk_source_uartc; /* _CLK_SOURCE_UARTC_0, 0x1a0 */
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uint32_t _0x1a4;
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uint32_t clk_source_vi_sensor; /* _CLK_SOURCE_VI_SENSOR_0, 0x1a8 */
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uint32_t _0x1ac[2];
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uint32_t clk_source_spi4; /* _CLK_SOURCE_SPI4_0, 0x1b4 */
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uint32_t clk_source_i2c3; /* _CLK_SOURCE_I2C3_0, 0x1b8 */
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uint32_t clk_source_sdmmc3; /* _CLK_SOURCE_SDMMC3_0, 0x1bc */
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uint32_t clk_source_uartd; /* _CLK_SOURCE_UARTD_0, 0x1c0 */
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uint32_t _0x1c4[2];
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uint32_t clk_source_owr; /* _CLK_SOURCE_OWR_0, 0x1cc */
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uint32_t _0x1d0;
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uint32_t clk_source_csite; /* _CLK_SOURCE_CSITE_0, 0x1d4 */
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uint32_t clk_source_i2s1; /* _CLK_SOURCE_I2S1_0, 0x1d8 */
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uint32_t clk_source_dtv; /* _CLK_SOURCE_DTV_0, 0x1dc */
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uint32_t _0x1e0[5];
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uint32_t clk_source_tsec; /* _CLK_SOURCE_TSEC_0, 0x1f4 */
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uint32_t _0x1f8;
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uint32_t clk_spare2; /* _CLK_SPARE2_0, 0x1fc */
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uint32_t _0x200[32];
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uint32_t clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */
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uint32_t clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */
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uint32_t clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */
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uint32_t rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */
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uint32_t rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
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uint32_t rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
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uint32_t clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
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uint32_t clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
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uint32_t clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
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uint32_t rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
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uint32_t rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
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uint32_t rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
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uint32_t _0x2b0[17];
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uint32_t dfll_base; /* _DFLL_BASE_0, 0x2f4 */
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uint32_t _0x2f8[2];
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/* _RST_DEV_L/H/U_SET_0 0x300-0x314 */
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uint32_t rst_dev_l_set;
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uint32_t rst_dev_l_clr;
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uint32_t rst_dev_h_set;
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uint32_t rst_dev_h_clr;
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uint32_t rst_dev_u_set;
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uint32_t rst_dev_u_clr;
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uint32_t _0x318[2];
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/* _CLK_ENB_L/H/U_CLR_0 0x320-0x334 */
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uint32_t clk_enb_l_set;
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uint32_t clk_enb_l_clr;
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uint32_t clk_enb_h_set;
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uint32_t clk_enb_h_clr;
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uint32_t clk_enb_u_set;
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uint32_t clk_enb_u_clr;
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uint32_t _0x338;
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uint32_t ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD_0, 0x33c */
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uint32_t rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
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uint32_t rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
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/* Additional (T30) registers */
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uint32_t clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
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uint32_t clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
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uint32_t _0x350[2];
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uint32_t rst_dev_v; /* _RST_DEVICES_V_0, 0x358 */
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uint32_t rst_dev_w; /* _RST_DEVICES_W_0, 0x35c */
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uint32_t clk_out_enb_v; /* _CLK_OUT_ENB_V_0, 0x360 */
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uint32_t clk_out_enb_w; /* _CLK_OUT_ENB_W_0, 0x364 */
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uint32_t cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
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uint32_t super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36c */
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uint32_t cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
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uint32_t super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
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uint32_t clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
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uint32_t clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37c */
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uint32_t cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
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uint32_t cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */
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uint32_t cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
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uint32_t _0x38c[5];
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uint32_t lvl2_clk_gate_ovrc; /* _LVL2_CLK_GATE_OVRC, 0x3a0 */
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uint32_t lvl2_clk_gate_ovrd; /* _LVL2_CLK_GATE_OVRD, 0x3a4 */
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uint32_t _0x3a8[2];
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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uint32_t _0x3b0;
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uint32_t clk_source_mselect; /* _CLK_SOURCE_MSELECT_0, 0x3b4 */
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uint32_t clk_source_tsensor; /* _CLK_SOURCE_TSENSOR_0, 0x3b8 */
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uint32_t clk_source_i2s4; /* _CLK_SOURCE_I2S4_0, 0x3bc */
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uint32_t clk_source_i2s5; /* _CLK_SOURCE_I2S5_0, 0x3c0 */
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uint32_t clk_source_i2c4; /* _CLK_SOURCE_I2C4_0, 0x3c4 */
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uint32_t _0x3c8[2];
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uint32_t clk_source_ahub; /* _CLK_SOURCE_AHUB_0, 0x3d0 */
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uint32_t _0x3d4[4];
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uint32_t clk_source_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X_0, 0x3e4 */
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uint32_t clk_source_actmon; /* _CLK_SOURCE_ACTMON_0, 0x3e8 */
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uint32_t clk_source_extperiph1; /* _CLK_SOURCE_EXTPERIPH1_0, 0x3ec */
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uint32_t clk_source_extperiph2; /* _CLK_SOURCE_EXTPERIPH2_0, 0x3f0 */
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uint32_t clk_source_extperiph3; /* _CLK_SOURCE_EXTPERIPH3_0, 0x3f4 */
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uint32_t _0x3f8;
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uint32_t clk_source_i2c_slow; /* _CLK_SOURCE_I2C_SLOW_0, 0x3fc */
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uint32_t clk_source_sys; /* _CLK_SOURCE_SYS_0, 0x400 */
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uint32_t clk_source_ispb; /* _CLK_SOURCE_ISPB_0, 0x404 */
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uint32_t _0x408[2];
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uint32_t clk_source_sor1; /* _CLK_SOURCE_SOR1_0, 0x410 */
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uint32_t clk_source_sor0; /* _CLK_SOURCE_SOR0_0, 0x414 */
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uint32_t _0x418[2];
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uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */
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uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */
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uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */
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2020-12-06 19:08:07 +00:00
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uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */
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2019-07-26 19:38:15 +00:00
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/* _RST_DEV_V/W_SET_0 0x430-0x43c */
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uint32_t rst_dev_v_set;
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uint32_t rst_dev_v_clr;
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uint32_t rst_dev_w_set;
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uint32_t rst_dev_w_clr;
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/* _CLK_ENB_V/W_CLR_0 0x440-0x44c */
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uint32_t clk_enb_v_set;
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uint32_t clk_enb_v_clr;
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uint32_t clk_enb_w_set;
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uint32_t clk_enb_w_clr;
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/* Additional (T114+) registers */
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uint32_t rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
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uint32_t rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
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uint32_t rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
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uint32_t rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45c */
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uint32_t clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */
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uint32_t clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */
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uint32_t clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
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uint32_t clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46c */
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uint32_t cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */
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uint32_t _0x474;
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uint32_t intstatus; /* _INTSTATUS_0, 0x478 */
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uint32_t intmask; /* _INTMASK_0, 0x47c */
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uint32_t utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */
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uint32_t utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */
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uint32_t utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */
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uint32_t plle_aux; /* _PLLE_AUX_0, 0x48c */
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uint32_t sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */
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uint32_t sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */
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uint32_t pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */
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uint32_t prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49c */
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uint32_t audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4a0 */
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uint32_t audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4a4 */
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uint32_t audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4a8 */
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uint32_t audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4ac */
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uint32_t audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4b0 */
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uint32_t audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4b4 */
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uint32_t plld2_base; /* _PLLD2_BASE_0, 0x4b8 */
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uint32_t plld2_misc; /* _PLLD2_MISC_0, 0x4bc */
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uint32_t utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4c0 */
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uint32_t pllrefe_base; /* _PLLREFE_BASE_0, 0x4c4 */
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uint32_t pllrefe_misc; /* _PLLREFE_MISC_0, 0x4c8 */
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uint32_t pllrefe_out; /* _PLLREFE_OUT_0, 0x4cc */
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uint32_t cpu_finetrim_byp; /* _CPU_FINETRIM_BYP_0, 0x4d0 */
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uint32_t cpu_finetrim_select; /* _CPU_FINETRIM_SELECT_0, 0x4d4 */
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uint32_t cpu_finetrim_dr; /* _CPU_FINETRIM_DR_0, 0x4d8 */
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uint32_t cpu_finetrim_df; /* _CPU_FINETRIM_DF_0, 0x4dc */
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uint32_t cpu_finetrim_f; /* _CPU_FINETRIM_F_0, 0x4e0 */
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uint32_t cpu_finetrim_r; /* _CPU_FINETRIM_R_0, 0x4e4 */
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uint32_t pllc2_base; /* _PLLC2_BASE_0, 0x4e8 */
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uint32_t pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4ec */
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uint32_t pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4f0 */
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uint32_t pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4f4 */
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uint32_t pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4f8 */
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uint32_t pllc3_base; /* _PLLC3_BASE_0, 0x4fc */
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uint32_t pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */
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uint32_t pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */
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uint32_t pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */
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uint32_t pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50c */
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uint32_t pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */
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uint32_t pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */
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uint32_t pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */
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uint32_t xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51c */
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uint32_t xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */
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uint32_t plle_aux1; /* _PLLE_AUX1_0, 0x524 */
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uint32_t pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */
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uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52c */
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uint32_t pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
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uint32_t xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */
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uint32_t _0x538;
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uint32_t clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53c */
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uint32_t clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */
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uint32_t clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */
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uint32_t pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */
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uint32_t pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54c */
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uint32_t pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
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uint32_t lvl2_clk_gate_ovre; /* _LVL2_CLK_GATE_OVRE, 0x554 */
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uint32_t super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
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uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55c */
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uint32_t audio_sync_clk_dmic1; /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */
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uint32_t audio_sync_clk_dmic2; /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */
|
2020-12-06 19:08:07 +00:00
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|
2019-07-26 19:38:15 +00:00
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uint32_t _0x568[2];
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uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG, 0x570 */
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uint32_t plld2_ss_ctrl1; /* _PLLD2_SS_CTRL1_0, 0x574 */
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uint32_t plld2_ss_ctrl2; /* _PLLD2_SS_CTRL2_0, 0x578 */
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uint32_t _0x57c[5];
|
2020-12-06 19:08:07 +00:00
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|
2019-07-26 19:38:15 +00:00
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uint32_t plldp_base; /* _PLLDP_BASE, 0x590*/
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uint32_t plldp_misc; /* _PLLDP_MISC, 0x594 */
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uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
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uint32_t plldp_ss_ctrl1; /* _PLLDP_SS_CTRL1_0, 0x59c */
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uint32_t plldp_ss_ctrl2; /* _PLLDP_SS_CTRL2_0, 0x5a0 */
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uint32_t pllc4_base; /* _PLLC4_BASE_0, 0x5a4 */
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uint32_t pllc4_misc; /* _PLLC4_MISC_0, 0x5a8 */
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uint32_t _0x5ac[6];
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uint32_t clk_spare0; /* _CLK_SPARE0_0, 0x5c4 */
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uint32_t clk_spare1; /* _CLK_SPARE1_0, 0x5c8 */
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uint32_t gpu_isob_ctrl; /* _GPU_ISOB_CTRL_0, 0x5cc */
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uint32_t pllc_misc2; /* _PLLC_MISC_2_0, 0x5d0 */
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uint32_t pllc_misc3; /* _PLLC_MISC_3_0, 0x5d4 */
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uint32_t plla_misc2; /* _PLLA_MISC2_0, 0x5d8 */
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uint32_t _0x5dc[2];
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uint32_t pllc4_out; /* _PLLC4_OUT_0, 0x5e4 */
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uint32_t pllmb_base; /* _PLLMB_BASE_0, 0x5e8 */
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uint32_t pllmb_misc1; /* _PLLMB_MISC1_0, 0x5ec */
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uint32_t pllx_misc4; /* _PLLX_MISC_4_0, 0x5f0 */
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uint32_t pllx_misc5; /* _PLLX_MISC_5_0, 0x5f4 */
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uint32_t _0x5f8[2];
|
2020-12-06 19:08:07 +00:00
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|
2019-07-26 19:38:15 +00:00
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uint32_t clk_source_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST_0, 0x600 */
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uint32_t clk_source_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON_0, 0x604 */
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uint32_t clk_source_xusb_fs; /* _CLK_SOURCE_XUSB_FS_0, 0x608 */
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uint32_t clk_source_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV_0, 0x60c */
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uint32_t clk_source_xusb_ss; /* _CLK_SOURCE_XUSB_SS_0, 0x610 */
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uint32_t clk_source_cilab; /* _CLK_SOURCE_CILAB_0, 0x614 */
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uint32_t clk_source_cilcd; /* _CLK_SOURCE_CILCD_0, 0x618 */
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uint32_t clk_source_cilef; /* _CLK_SOURCE_CILEF_0, 0x61c */
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uint32_t clk_source_dsia_lp; /* _CLK_SOURCE_DSIA_LP_0, 0x620 */
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uint32_t clk_source_dsib_lp; /* _CLK_SOURCE_DSIB_LP_0, 0x624 */
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uint32_t clk_source_entropy; /* _CLK_SOURCE_ENTROPY_0, 0x628 */
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uint32_t clk_source_dvfs_ref; /* _CLK_SOURCE_DVFS_REF_0, 0x62c */
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uint32_t clk_source_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC_0, 0x630 */
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uint32_t _0x634[3];
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uint32_t clk_source_emc_latency; /* _CLK_SOURCE_EMC_LATENCY_0, 0x640 */
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uint32_t clk_source_soc_therm; /* _CLK_SOURCE_SOC_THERM_0, 0x644 */
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uint32_t _0x648;
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uint32_t clk_source_dmic1; /* _CLK_SOURCE_DMIC1_0, 0x64c */
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uint32_t clk_source_dmic2; /* _CLK_SOURCE_DMIC2_0, 0x650 */
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uint32_t _0x654;
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uint32_t clk_source_vi_sensor2; /* _CLK_SOURCE_VI_SENSOR2_0, 0x658 */
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uint32_t clk_source_i2c6; /* _CLK_SOURCE_I2C6_0, 0x65c */
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uint32_t clk_source_mipibif; /* _CLK_SOURCE_MIPIBIF_0, 0x660 */
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uint32_t clk_source_emc_dll; /* _CLK_SOURCE_EMC_DLL_0, 0x664 */
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uint32_t _0x668;
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uint32_t clk_source_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIPI_CAL_0, 0x66c */
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uint32_t _0x670[2];
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uint32_t clk_source_vic; /* _CLK_SOURCE_VIC_0, 0x678 */
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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uint32_t pllp_outc; /* _PLLP_OUTC_0, 0x67c */
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uint32_t pllp_misc1; /* _PLLP_MISC1_0, 0x680 */
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uint32_t _0x684[2];
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uint32_t emc_div_clk_shaper_ctrl; /* _EMC_DIV_CLK_SHAPER_CTRL_0, 0x68c */
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uint32_t emc_pllc_shaper_ctrl; /* _EMC_PLLC_SHAPER_CTRL_0, 0x690 */
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uint32_t clk_source_sdmmc_legacy_tm; /* _CLK_SOURCE_SDMMC_LEGACY_TM_0, 0x694 */
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uint32_t clk_source_nvdec; /* _CLK_SOURCE_NVDEC_0, 0x698 */
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uint32_t clk_source_nvjpg; /* _CLK_SOURCE_NVJPG_0, 0x69c */
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uint32_t clk_source_nvenc; /* _CLK_SOURCE_NVENC_0, 0x6a0 */
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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uint32_t plla1_base; /* _PLLA1_BASE_0, 0x6a4 */
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uint32_t plla1_misc0; /* _PLLA1_MISC_0_0, 0x6a8 */
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uint32_t plla1_misc1; /* _PLLA1_MISC_1_0, 0x6ac */
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uint32_t plla1_misc2; /* _PLLA1_MISC_2_0, 0x6b0 */
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uint32_t plla1_misc3; /* _PLLA1_MISC_3_0, 0x6b4 */
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uint32_t audio_sync_clk_dmic3; /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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uint32_t clk_source_dmic3; /* _CLK_SOURCE_DMIC3_0, 0x6bc */
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uint32_t clk_source_ape; /* _CLK_SOURCE_APE_0, 0x6c0 */
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uint32_t clk_source_qspi; /* _CLK_SOURCE_QSPI_0, 0x6c4 */
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uint32_t clk_source_vi_i2c; /* _CLK_SOURCE_VI_I2C_0, 0x6c8 */
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uint32_t clk_source_usb2_hsic_trk; /* _CLK_SOURCE_USB2_HSIC_TRK_0, 0x6cc */
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uint32_t clk_source_pex_sata_usb_rx_byp; /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0, 0x6d0 */
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uint32_t clk_source_maud; /* _CLK_SOURCE_MAUD_0, 0x6d4 */
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uint32_t clk_source_tsecb; /* _CLK_SOURCE_TSECB_0, 0x6d8 */
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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uint32_t clk_cpug_misc1; /* _CLK_CPUG_MISC1_0, 0x6dc */
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uint32_t aclk_burst_policy; /* _ACLK_BURST_POLICY_0, 0x6e0 */
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uint32_t super_aclk_divider; /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */
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2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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uint32_t nvenc_super_clk_divider; /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */
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uint32_t vi_super_clk_divider; /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */
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uint32_t vic_super_clk_divider; /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */
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uint32_t nvdec_super_clk_divider; /* _NVDEC_SUPER_CLK_DIVIDER_0, 0x6f4 */
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uint32_t isp_super_clk_divider; /* _ISP_SUPER_CLK_DIVIDER_0, 0x6f8 */
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uint32_t ispb_super_clk_divider; /* _ISPB_SUPER_CLK_DIVIDER_0, 0x6fc */
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uint32_t nvjpg_super_clk_divider; /* _NVJPG_SUPER_CLK_DIVIDER_0, 0x700 */
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uint32_t se_super_clk_divider; /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */
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uint32_t tsec_super_clk_divider; /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */
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uint32_t tsecb_super_clk_divider; /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */
|
2020-12-06 19:08:07 +00:00
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2019-07-26 19:38:15 +00:00
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uint32_t clk_source_uartape; /* _CLK_SOURCE_UARTAPE_0, 0x710 */
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uint32_t clk_cpug_misc2; /* _CLK_CPUG_MISC2_0, 0x714 */
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uint32_t clk_source_dbgapb; /* _CLK_SOURCE_DBGAPB_0, 0x718 */
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uint32_t clk_ccplex_cc4_ret_clk_enb; /* _CLK_CCPLEX_CC4_RET_CLK_ENB_0, 0x71c */
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uint32_t actmon_cpu_clk; /* _ACTMON_CPU_CLK_0, 0x720 */
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uint32_t clk_source_emc_safe; /* _CLK_SOURCE_EMC_SAFE_0, 0x724 */
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uint32_t sdmmc2_pllc4_out0_shaper_ctrl; /* _SDMMC2_PLLC4_OUT0_SHAPER_CTRL_0, 0x728 */
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uint32_t sdmmc2_pllc4_out1_shaper_ctrl; /* _SDMMC2_PLLC4_OUT1_SHAPER_CTRL_0, 0x72c */
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uint32_t sdmmc2_pllc4_out2_shaper_ctrl; /* _SDMMC2_PLLC4_OUT2_SHAPER_CTRL_0, 0x730 */
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uint32_t sdmmc2_div_clk_shaper_ctrl; /* _SDMMC2_DIV_CLK_SHAPER_CTRL_0, 0x734 */
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uint32_t sdmmc4_pllc4_out0_shaper_ctrl; /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */
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uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
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uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
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uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */
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} tegra_car_t;
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static inline volatile tegra_car_t *car_get_regs(void) {
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return (volatile tegra_car_t *)CAR_BASE;
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}
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void clk_enable(CarDevice dev);
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void clk_disable(CarDevice dev);
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void rst_enable(CarDevice dev);
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void rst_disable(CarDevice dev);
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void clkrst_enable(CarDevice dev);
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void clkrst_disable(CarDevice dev);
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void clkrst_reboot(CarDevice dev);
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void clkrst_enable_fuse_regs(bool enable);
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#endif
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