mirror of
https://github.com/Atmosphere-NX/Atmosphere
synced 2024-12-23 12:51:13 +00:00
106 lines
3.3 KiB
C
106 lines
3.3 KiB
C
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#include <stdint.h>
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#include "lp0.h"
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#include "i2c.h"
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#include "pmc.h"
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#include "emc.h"
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#include "timer.h"
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#define CACHE_CTRL (*((volatile uint32_t *)0x50040000))
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#define PRI_ICTLR_COP_IER_CLR_0 (*((volatile uint32_t *)0x60004038))
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#define SEC_ICTLR_COP_IER_CLR_0 (*((volatile uint32_t *)0x60004138))
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#define TRI_ICTLR_COP_IER_CLR_0 (*((volatile uint32_t *)0x60004238))
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#define QUAD_ICTLR_COP_IER_CLR_0 (*((volatile uint32_t *)0x60004338))
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#define PENTA_ICTLR_COP_IER_CLR_0 (*((volatile uint32_t *)0x60004438))
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#define HEXA_ICTLR_COP_IER_CLR_0 (*((volatile uint32_t *)0x60004538))
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void reboot(void) {
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/* Write MAIN_RST */
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APBDEV_PMC_CNTRL_0 = 0x10;
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while (1) {
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/* Wait for reboot. */
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}
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}
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void set_pmc_dpd_io_pads(void) {
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/* Read val from EMC_PMC scratch, configure accordingly. */
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uint32_t emc_pmc_val = EMC_PMC_SCRATCH3_0;
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APBDEV_PMC_DDR_CNTRL_0 = emc_pmc_val & 0x7FFFF;
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if (emc_pmc_val & 0x40000000) {
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APBDEV_PMC_WEAK_BIAS_0 = 0x7FFF0000;
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}
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/* Request to put pads in Deep Power Down. */
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APBDEV_PMC_IO_DPD3_REQ_0 = 0x8FFFFFFF;
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while (APBDEV_PMC_IO_DPD3_STATUS_0 != 0xFFFFFFF) { /* Wait a while. */ }
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spinlock_wait(32);
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APBDEV_PMC_IO_DPD4_REQ_0 = 0x8FFFFFFF;
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while (APBDEV_PMC_IO_DPD4_STATUS_0 != 0xFFF1FFF) { /* Wait a while. */ }
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spinlock_wait(32);
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}
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void lp0_entry_main(void) {
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/* Disable the BPMP Cache. */
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CACHE_CTRL |= 0xC00;
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/* Wait until the CPU Rail is turned off. */
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while (APBDEV_PMC_PWRGATE_STATUS_0 & 1) { /* Wait for TrustZone to finish. */ }
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/* Clamp the CPU Rail. */
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APBDEV_PMC_SET_SW_CLAMP_0 |= 0x1;
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while (!(APBDEV_PMC_CLAMP_STATUS_0 & 1)) { /* Wait for CPU Rail to be clamped. */ }
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/* Waste some time. */
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spinlock_wait(10);
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/* Reset device 27 over I2C, then wait a while. */
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i2c_init();
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i2c_send_reset_cmd();
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timer_wait(700);
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/* Clear Interrupt Enable for BPMP in all ICTLRs. */
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PRI_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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SEC_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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TRI_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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QUAD_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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PENTA_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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HEXA_ICTLR_COP_IER_CLR_0 = 0xFFFFFFFF;
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/* Write EMC's DRAM op into PMC scratch. */
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if ((EMC_FBIO_CFG5_0 & 3) != 1) {
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/* If DRAM_TYPE != LPDDR4, something's gone wrong. Reboot. */
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reboot();
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}
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/* Write MRW3_OP into scratch. */
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APBDEV_PMC_SCRATCH18_0 = (APBDEV_PMC_SCRATCH18_0 & 0xFFFFFF3F) | (EMC_MRW3_0 & 0xC0);
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uint32_t mrw3_op = ((EMC_MRW3_0 & 0xC0) << 8) | (EMC_MRW3_0 & 0xC0);
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APBDEV_PMC_SCRATCH12_0 = (APBDEV_PMC_SCRATCH12_0 & 0xFFFF3F3F) | mrw3_op;
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APBDEV_PMC_SCRATCH13_0 = (APBDEV_PMC_SCRATCH13_0 & 0xFFFF3F3F) | mrw3_op;
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/* Ready DRAM for deep sleep. */
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emc_put_dram_in_self_refresh_mode();
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/* Setup LPDDR MRW based on device config. */
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EMC_MRW_0 = 0x88110000;
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if (EMC_ADR_CFG_0 & 1) {
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EMC_MRW_0 = 0x48110000;
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}
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/* Put IO pads in Deep Power Down. */
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set_pmc_dpd_io_pads();
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/* Enable pad sampling during deep sleep. */
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APBDEV_PMC_DPD_SAMPLE_0 |= 1;
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/* Waste some more time. */
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spinlock_wait(0x128);
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/* Enter deep sleep. */
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APBDEV_PMC_DPD_ENABLE_0 |= 1;
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while (1) { /* Wait until we're asleep. */ }
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}
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