2020-10-30 18:54:30 +00:00
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours.hpp>
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#include "sdmmc_sd_host_standard_controller.hpp"
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#include "sdmmc_clock_reset_controller.hpp"
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namespace ams::sdmmc::impl {
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bool IsSocMariko();
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constexpr inline size_t SdmmcRegistersSize = 0x200;
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constexpr inline dd::PhysicalAddress ApbMiscRegistersPhysicalAddress = UINT64_C(0x70000000);
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constexpr inline size_t ApbMiscRegistersSize = 16_KB;
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class SdmmcController : public SdHostStandardController {
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private:
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struct SdmmcRegisters {
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/* Standard registers. */
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volatile SdHostStandardRegisters sd_host_standard_registers;
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/* Vendor specific registers */
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volatile uint32_t vendor_clock_cntrl;
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volatile uint32_t vendor_sys_sw_cntrl;
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volatile uint32_t vendor_err_intr_status;
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volatile uint32_t vendor_cap_overrides;
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volatile uint32_t vendor_boot_cntrl;
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volatile uint32_t vendor_boot_ack_timeout;
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volatile uint32_t vendor_boot_dat_timeout;
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volatile uint32_t vendor_debounce_count;
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volatile uint32_t vendor_misc_cntrl;
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volatile uint32_t max_current_override;
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volatile uint32_t max_current_override_hi;
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volatile uint32_t _0x12c[0x20];
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volatile uint32_t vendor_io_trim_cntrl;
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/* Start of sdmmc2/sdmmc4 only */
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volatile uint32_t vendor_dllcal_cfg;
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volatile uint32_t vendor_dll_ctrl0;
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volatile uint32_t vendor_dll_ctrl1;
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volatile uint32_t vendor_dllcal_cfg_sta;
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/* End of sdmmc2/sdmmc4 only */
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volatile uint32_t vendor_tuning_cntrl0;
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volatile uint32_t vendor_tuning_cntrl1;
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volatile uint32_t vendor_tuning_status0;
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volatile uint32_t vendor_tuning_status1;
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volatile uint32_t vendor_clk_gate_hysteresis_count;
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volatile uint32_t vendor_preset_val0;
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volatile uint32_t vendor_preset_val1;
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volatile uint32_t vendor_preset_val2;
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volatile uint32_t sdmemcomppadctrl;
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volatile uint32_t auto_cal_config;
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volatile uint32_t auto_cal_interval;
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volatile uint32_t auto_cal_status;
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volatile uint32_t io_spare;
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volatile uint32_t sdmmca_mccif_fifoctrl;
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volatile uint32_t timeout_wcoal_sdmmca;
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volatile uint32_t _0x1fc;
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};
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static_assert(sizeof(SdmmcRegisters) == SdmmcRegistersSize);
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private:
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SdmmcRegisters *sdmmc_registers;
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bool is_shutdown;
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bool is_awake;
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SpeedMode current_speed_mode;
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BusPower bus_power_before_sleep;
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BusWidth bus_width_before_sleep;
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SpeedMode speed_mode_before_sleep;
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u8 tap_value_before_sleep;
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bool is_powersaving_enable_before_sleep;
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u8 tap_value_for_hs_400;
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bool is_valid_tap_value_for_hs_400;
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Result drive_strength_calibration_status;
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private:
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void ReleaseReset(SpeedMode speed_mode);
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void AssertReset();
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Result StartupCore(BusPower bus_power);
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Result SetClockTrimmer(SpeedMode speed_mode, u8 tap_value);
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u8 GetCurrentTapValue();
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Result CalibrateDll();
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Result SetSpeedModeWithTapValue(SpeedMode speed_mode, u8 tap_value);
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Result IssueTuningCommand(u32 command_index);
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protected:
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void SetDriveCodeOffsets(BusPower bus_power);
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void CalibrateDriveStrength(BusPower bus_power);
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virtual void SetPad() = 0;
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virtual ClockResetController::Module GetClockResetModule() const = 0;
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#if defined(AMS_SDMMC_USE_OS_EVENTS)
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virtual int GetInterruptNumber() const = 0;
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virtual os::InterruptEventType *GetInterruptEvent() const = 0;
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#endif
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virtual bool IsNeedPeriodicDriveStrengthCalibration() = 0;
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virtual void ClearPadParked() = 0;
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virtual Result PowerOn(BusPower bus_power) = 0;
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virtual void PowerOff() = 0;
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virtual Result LowerBusPower() = 0;
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virtual void SetSchmittTrigger(BusPower bus_power) = 0;
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virtual u8 GetOutboundTapValue() const = 0;
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virtual u8 GetDefaultInboundTapValue() const = 0;
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virtual u8 GetVrefSelValue() const = 0;
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virtual void SetSlewCodes() = 0;
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virtual void GetAutoCalOffsets(u8 *out_auto_cal_pd_offset, u8 *out_auto_cal_pu_offset, BusPower bus_power) const = 0;
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virtual void SetDriveStrengthToDefaultValues(BusPower bus_power) = 0;
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public:
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explicit SdmmcController(dd::PhysicalAddress registers_phys_addr) : SdHostStandardController(registers_phys_addr, SdmmcRegistersSize) {
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/* Set sdmmc registers. */
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static_assert(offsetof(SdmmcRegisters, sd_host_standard_registers) == 0);
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this->sdmmc_registers = reinterpret_cast<SdmmcRegisters *>(this->registers);
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this->is_shutdown = true;
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this->is_awake = true;
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this->is_valid_tap_value_for_hs_400 = false;
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this->drive_strength_calibration_status = sdmmc::ResultDriveStrengthCalibrationNotCompleted();
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this->tap_value_for_hs_400 = 0;
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this->current_speed_mode = SpeedMode_MmcIdentification;
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this->bus_power_before_sleep = BusPower_Off;
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this->bus_width_before_sleep = BusWidth_1Bit;
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this->speed_mode_before_sleep = SpeedMode_MmcIdentification;
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this->tap_value_before_sleep = 0;
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this->is_powersaving_enable_before_sleep = false;
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}
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virtual void Initialize() override {
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/* Set pad. */
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this->SetPad();
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/* Initialize our clock/reset module. */
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ClockResetController::Initialize(this->GetClockResetModule());
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/* If necessary, initialize our interrupt event. */
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#if defined(AMS_SDMMC_USE_OS_EVENTS)
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{
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os::InterruptEventType *interrupt_event = this->GetInterruptEvent();
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os::InitializeInterruptEvent(interrupt_event, this->GetInterruptNumber(), os::EventClearMode_ManualClear);
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SdHostStandardController::PreSetInterruptEvent(interrupt_event);
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}
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#endif
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/* Perform base initialization. */
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SdHostStandardController::Initialize();
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}
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virtual void Finalize() override {
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/* Perform base finalization. */
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SdHostStandardController::Finalize();
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/* If necessary, finalize our interrupt event. */
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#if defined(AMS_SDMMC_USE_OS_EVENTS)
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{
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os::FinalizeInterruptEvent(this->GetInterruptEvent());
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}
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#endif
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/* Finalize our clock/reset module. */
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ClockResetController::Finalize(this->GetClockResetModule());
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}
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virtual Result Startup(BusPower bus_power, BusWidth bus_width, SpeedMode speed_mode, bool power_saving_enable) override;
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virtual void Shutdown() override;
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virtual void PutToSleep() override;
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virtual Result Awaken() override;
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virtual Result SwitchToSdr12() override;
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virtual Result SetSpeedMode(SpeedMode speed_mode) override;
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virtual SpeedMode GetSpeedMode() const override {
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return this->current_speed_mode;
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}
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virtual void SetPowerSaving(bool en) override;
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virtual void EnableDeviceClock() override;
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virtual Result IssueCommand(const Command *command, TransferData *xfer_data, u32 *out_num_transferred_blocks) override;
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virtual Result IssueStopTransmissionCommand(u32 *out_response) override;
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virtual bool IsSupportedTuning() const override {
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return true;
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}
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virtual Result Tuning(SpeedMode speed_mode, u32 command_index) override;
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virtual void SaveTuningStatusForHs400() override;
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virtual Result GetInternalStatus() const override {
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return this->drive_strength_calibration_status;
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}
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};
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constexpr inline dd::PhysicalAddress Sdmmc1RegistersPhysicalAddress = UINT64_C(0x700B0000);
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class Sdmmc1Controller : public SdmmcController {
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private:
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#if defined(AMS_SDMMC_USE_OS_EVENTS)
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static constinit inline os::InterruptEventType s_interrupt_event{};
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#endif
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/* NOTE: This is a fascimile of pcv's Sdmmc1PowerController. */
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class PowerController {
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NON_COPYABLE(PowerController);
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NON_MOVEABLE(PowerController);
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private:
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BusPower current_bus_power;
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private:
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Result ControlVddioSdmmc1(BusPower bus_power);
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void SetSdmmcIoMode(bool is_3_3V);
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void ControlRailSdmmc1Io(bool is_power_on);
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public:
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PowerController();
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~PowerController();
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Result PowerOn(BusPower bus_power);
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Result PowerOff();
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Result LowerBusPower();
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};
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private:
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#if defined(AMS_SDMMC_USE_PCV_CLOCK_RESET_CONTROL)
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/* TODO: pinmux::PinmuxSession pinmux_session; */
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#endif
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BusPower current_bus_power;
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#if defined(AMS_SDMMC_USE_PCV_CLOCK_RESET_CONTROL)
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bool is_pcv_control;
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#endif
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TYPED_STORAGE(PowerController) power_controller_storage;
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PowerController *power_controller;
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private:
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Result PowerOnForRegisterControl(BusPower bus_power);
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void PowerOffForRegisterControl();
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Result LowerBusPowerForRegisterControl();
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void SetSchmittTriggerForRegisterControl(BusPower bus_power);
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#if defined(AMS_SDMMC_USE_PCV_CLOCK_RESET_CONTROL)
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Result PowerOnForPcvControl(BusPower bus_power);
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void PowerOffForPcvControl();
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Result LowerBusPowerForPcvControl();
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void SetSchmittTriggerForPcvControl(BusPower bus_power);
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#endif
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protected:
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virtual void SetPad() override {
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/* Nothing is needed here. */
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}
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virtual ClockResetController::Module GetClockResetModule() const override {
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return ClockResetController::Module_Sdmmc1;
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}
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#if defined(AMS_SDMMC_USE_OS_EVENTS)
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virtual int GetInterruptNumber() const override {
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return 46;
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}
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virtual os::InterruptEventType *GetInterruptEvent() const override {
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return std::addressof(s_interrupt_event);
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}
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#endif
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virtual bool IsNeedPeriodicDriveStrengthCalibration() override {
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return !IsSocMariko();
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}
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virtual void ClearPadParked() override {
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/* Nothing is needed here. */
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}
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virtual Result PowerOn(BusPower bus_power) override;
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virtual void PowerOff() override;
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virtual Result LowerBusPower() override;
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virtual void SetSchmittTrigger(BusPower bus_power) override;
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virtual u8 GetOutboundTapValue() const override {
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if (IsSocMariko()) {
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return 0xE;
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} else {
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return 0x2;
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}
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}
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virtual u8 GetDefaultInboundTapValue() const override {
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if (IsSocMariko()) {
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return 0xB;
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} else {
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return 0x4;
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}
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}
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virtual u8 GetVrefSelValue() const override {
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if (IsSocMariko()) {
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return 0x0;
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} else {
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return 0x7;
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}
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}
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virtual void SetSlewCodes() override {
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if (IsSocMariko()) {
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/* Do nothing. */
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} else {
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/* Ensure that we can control registers. */
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SdHostStandardController::EnsureControl();
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/* Get the apb registers address. */
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const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
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|
|
|
|
|
|
/* Write the slew values to APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL. */
|
|
|
|
|
reg::ReadWrite(apb_address + APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_SDMMC1_PAD_CFGPADCTRL_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR, 0x1),
|
|
|
|
|
APB_MISC_REG_BITS_VALUE(GP_SDMMC1_PAD_CFGPADCTRL_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWF, 0x1));
|
|
|
|
|
|
|
|
|
|
/* Read to be sure our config takes. */
|
|
|
|
|
reg::Read(apb_address + APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual void GetAutoCalOffsets(u8 *out_auto_cal_pd_offset, u8 *out_auto_cal_pu_offset, BusPower bus_power) const override {
|
|
|
|
|
/* Ensure that we can write the offsets. */
|
|
|
|
|
AMS_ABORT_UNLESS(out_auto_cal_pd_offset != nullptr);
|
|
|
|
|
AMS_ABORT_UNLESS(out_auto_cal_pu_offset != nullptr);
|
|
|
|
|
|
|
|
|
|
/* Set the offsets. */
|
|
|
|
|
if (IsSocMariko()) {
|
|
|
|
|
switch (bus_power) {
|
|
|
|
|
case BusPower_1_8V:
|
|
|
|
|
*out_auto_cal_pd_offset = 6;
|
|
|
|
|
*out_auto_cal_pu_offset = 6;
|
|
|
|
|
break;
|
|
|
|
|
case BusPower_3_3V:
|
|
|
|
|
*out_auto_cal_pd_offset = 0;
|
|
|
|
|
*out_auto_cal_pu_offset = 0;
|
|
|
|
|
break;
|
|
|
|
|
case BusPower_Off:
|
|
|
|
|
AMS_UNREACHABLE_DEFAULT_CASE();
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
switch (bus_power) {
|
|
|
|
|
case BusPower_1_8V:
|
|
|
|
|
*out_auto_cal_pd_offset = 0x7B;
|
|
|
|
|
*out_auto_cal_pu_offset = 0x7B;
|
|
|
|
|
break;
|
|
|
|
|
case BusPower_3_3V:
|
|
|
|
|
*out_auto_cal_pd_offset = 0x7D;
|
|
|
|
|
*out_auto_cal_pu_offset = 0;
|
|
|
|
|
break;
|
|
|
|
|
case BusPower_Off:
|
|
|
|
|
AMS_UNREACHABLE_DEFAULT_CASE();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual void SetDriveStrengthToDefaultValues(BusPower bus_power) override {
|
|
|
|
|
/* Ensure that we can control registers. */
|
|
|
|
|
SdHostStandardController::EnsureControl();
|
|
|
|
|
|
|
|
|
|
/* Get the apb registers address. */
|
|
|
|
|
const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
|
|
|
|
|
|
|
|
|
|
/* Determine the drive code values. */
|
|
|
|
|
u8 drvdn, drvup;
|
|
|
|
|
if (IsSocMariko()) {
|
|
|
|
|
drvdn = 0x8;
|
|
|
|
|
drvup = 0x8;
|
|
|
|
|
} else {
|
|
|
|
|
switch (bus_power) {
|
|
|
|
|
case BusPower_1_8V:
|
|
|
|
|
drvdn = 0xF;
|
|
|
|
|
drvup = 0xB;
|
|
|
|
|
break;
|
|
|
|
|
case BusPower_3_3V:
|
|
|
|
|
drvdn = 0xC;
|
|
|
|
|
drvup = 0xC;
|
|
|
|
|
break;
|
|
|
|
|
case BusPower_Off:
|
|
|
|
|
AMS_UNREACHABLE_DEFAULT_CASE();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Write the drv up/down values to APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL. */
|
|
|
|
|
reg::ReadWrite(apb_address + APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_SDMMC1_PAD_CFGPADCTRL_CFG2TMC_SDMMC1_PAD_CAL_DRVDN, drvdn),
|
|
|
|
|
APB_MISC_REG_BITS_VALUE(GP_SDMMC1_PAD_CFGPADCTRL_CFG2TMC_SDMMC1_PAD_CAL_DRVUP, drvup));
|
|
|
|
|
|
|
|
|
|
/* Read to be sure our config takes. */
|
2020-11-18 02:01:38 +00:00
|
|
|
reg::Read(apb_address + APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL);
|
2020-10-30 18:54:30 +00:00
|
|
|
}
|
|
|
|
|
public:
|
|
|
|
|
Sdmmc1Controller() : SdmmcController(Sdmmc1RegistersPhysicalAddress) {
|
|
|
|
|
this->current_bus_power = BusPower_Off;
|
|
|
|
|
#if defined(AMS_SDMMC_USE_PCV_CLOCK_RESET_CONTROL)
|
|
|
|
|
this->is_pcv_control = false;
|
|
|
|
|
#endif
|
|
|
|
|
this->power_controller = nullptr;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual void Initialize() override;
|
|
|
|
|
virtual void Finalize() override;
|
|
|
|
|
|
|
|
|
|
void InitializeForRegisterControl();
|
|
|
|
|
void FinalizeForRegisterControl();
|
|
|
|
|
|
|
|
|
|
#if defined(AMS_SDMMC_USE_PCV_CLOCK_RESET_CONTROL)
|
|
|
|
|
void InitializeForPcvControl();
|
|
|
|
|
void FinalizeForPcvControl();
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
virtual bool IsSupportedBusPower(BusPower bus_power) const override {
|
|
|
|
|
switch (bus_power) {
|
|
|
|
|
case BusPower_Off: return true;
|
|
|
|
|
case BusPower_1_8V: return true;
|
|
|
|
|
case BusPower_3_3V: return true;
|
|
|
|
|
AMS_UNREACHABLE_DEFAULT_CASE();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual bool IsSupportedBusWidth(BusWidth bus_width) const override {
|
|
|
|
|
switch (bus_width) {
|
|
|
|
|
case BusWidth_1Bit: return true;
|
|
|
|
|
case BusWidth_4Bit: return true;
|
|
|
|
|
case BusWidth_8Bit: return false;
|
|
|
|
|
AMS_UNREACHABLE_DEFAULT_CASE();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
class Sdmmc2And4Controller : public SdmmcController {
|
|
|
|
|
protected:
|
|
|
|
|
virtual bool IsNeedPeriodicDriveStrengthCalibration() override {
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual Result PowerOn(BusPower bus_power) override {
|
|
|
|
|
/* Power for SDMMC2/4 is assumed on, so we don't need to do anything. */
|
|
|
|
|
AMS_UNUSED(bus_power);
|
|
|
|
|
return ResultSuccess();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual void PowerOff() override {
|
|
|
|
|
/* Power for SDMMC2/4 is assumed on, so we don't need to do anything. */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual Result LowerBusPower() override {
|
|
|
|
|
AMS_ABORT("Sdmmc2And4Controller cannot lower bus power\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual void SetSchmittTrigger(BusPower bus_power) override {
|
|
|
|
|
/* Do nothing. */
|
|
|
|
|
AMS_UNUSED(bus_power);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual u8 GetOutboundTapValue() const override {
|
|
|
|
|
if (IsSocMariko()) {
|
|
|
|
|
return 0xD;
|
|
|
|
|
} else {
|
|
|
|
|
return 0x8;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual u8 GetDefaultInboundTapValue() const override {
|
|
|
|
|
if (IsSocMariko()) {
|
|
|
|
|
return 0xB;
|
|
|
|
|
} else {
|
|
|
|
|
return 0x0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual u8 GetVrefSelValue() const override {
|
|
|
|
|
return 0x7;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual void SetSlewCodes() override {
|
|
|
|
|
/* Do nothing. */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual void GetAutoCalOffsets(u8 *out_auto_cal_pd_offset, u8 *out_auto_cal_pu_offset, BusPower bus_power) const override {
|
|
|
|
|
/* Ensure that we can write the offsets. */
|
|
|
|
|
AMS_ABORT_UNLESS(out_auto_cal_pd_offset != nullptr);
|
|
|
|
|
AMS_ABORT_UNLESS(out_auto_cal_pu_offset != nullptr);
|
|
|
|
|
|
|
|
|
|
/* Sdmmc2And4Controller only supports 1.8v. */
|
|
|
|
|
AMS_ABORT_UNLESS(bus_power == BusPower_1_8V);
|
|
|
|
|
|
|
|
|
|
/* Set the offsets. */
|
|
|
|
|
*out_auto_cal_pd_offset = 5;
|
|
|
|
|
*out_auto_cal_pu_offset = 5;
|
|
|
|
|
}
|
|
|
|
|
public:
|
|
|
|
|
explicit Sdmmc2And4Controller(dd::PhysicalAddress registers_phys_addr) : SdmmcController(registers_phys_addr) {
|
|
|
|
|
/* ... */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual bool IsSupportedBusPower(BusPower bus_power) const override {
|
|
|
|
|
switch (bus_power) {
|
|
|
|
|
case BusPower_Off: return true;
|
|
|
|
|
case BusPower_1_8V: return true;
|
|
|
|
|
case BusPower_3_3V: return false;
|
|
|
|
|
AMS_UNREACHABLE_DEFAULT_CASE();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual bool IsSupportedBusWidth(BusWidth bus_width) const override {
|
|
|
|
|
switch (bus_width) {
|
|
|
|
|
case BusWidth_1Bit: return true;
|
|
|
|
|
case BusWidth_4Bit: return true;
|
|
|
|
|
case BusWidth_8Bit: return true;
|
|
|
|
|
AMS_UNREACHABLE_DEFAULT_CASE();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
constexpr inline dd::PhysicalAddress Sdmmc2RegistersPhysicalAddress = UINT64_C(0x700B0200);
|
|
|
|
|
|
|
|
|
|
class Sdmmc2Controller : public Sdmmc2And4Controller {
|
|
|
|
|
private:
|
|
|
|
|
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
|
|
|
|
static constinit inline os::InterruptEventType s_interrupt_event{};
|
|
|
|
|
#endif
|
|
|
|
|
protected:
|
|
|
|
|
virtual void SetPad() override {
|
|
|
|
|
/* Nothing is needed here. */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual ClockResetController::Module GetClockResetModule() const override {
|
|
|
|
|
return ClockResetController::Module_Sdmmc2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
|
|
|
|
virtual int GetInterruptNumber() const override {
|
|
|
|
|
return 47;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual os::InterruptEventType *GetInterruptEvent() const override {
|
|
|
|
|
return std::addressof(s_interrupt_event);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
virtual void ClearPadParked() override {
|
|
|
|
|
if (IsSocMariko()) {
|
|
|
|
|
/* Nothing is needed here. */
|
|
|
|
|
} else {
|
|
|
|
|
/* Get the apb registers address. */
|
|
|
|
|
const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
|
|
|
|
|
|
|
|
|
|
/* Clear all MISC2PMC_EMMC2_*_PARK bits. */
|
|
|
|
|
reg::ReadWrite(apb_address + APB_MISC_GP_EMMC2_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_EMMC2_PAD_CFGPADCTRL_MISC2PMC_EMMC2_ALL_PARK, 0));
|
|
|
|
|
|
|
|
|
|
/* Read to be sure our config takes. */
|
|
|
|
|
reg::Read(apb_address + APB_MISC_GP_EMMC2_PAD_CFGPADCTRL);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
virtual void SetDriveStrengthToDefaultValues(BusPower bus_power) override {
|
|
|
|
|
/* SDMMC2 only supports 1.8v. */
|
|
|
|
|
AMS_ABORT_UNLESS(bus_power == BusPower_1_8V);
|
|
|
|
|
|
|
|
|
|
/* Ensure that we can control registers. */
|
|
|
|
|
SdHostStandardController::EnsureControl();
|
|
|
|
|
|
|
|
|
|
/* Get the apb registers address. */
|
|
|
|
|
const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
|
|
|
|
|
|
|
|
|
|
if (IsSocMariko()) {
|
|
|
|
|
/* Write the drv up/down values to APB_MISC_GP_SDMMC2_PAD_CFGPADCTRL. */
|
|
|
|
|
reg::ReadWrite(apb_address + APB_MISC_GP_SDMMC2_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_SDMMC2_PAD_CFGPADCTRL_CFG2TMC_SDMMC2_PAD_CAL_DRVDN, 0xA),
|
|
|
|
|
APB_MISC_REG_BITS_VALUE(GP_SDMMC2_PAD_CFGPADCTRL_CFG2TMC_SDMMC2_PAD_CAL_DRVUP, 0xA));
|
|
|
|
|
|
|
|
|
|
/* Read to be sure our config takes. */
|
|
|
|
|
reg::Read(apb_address + APB_MISC_GP_SDMMC2_PAD_CFGPADCTRL);
|
|
|
|
|
} else {
|
|
|
|
|
/* Write the drv up/down values to APB_MISC_GP_EMMC4_PAD_CFGPADCTRL. */
|
|
|
|
|
reg::ReadWrite(apb_address + APB_MISC_GP_EMMC2_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_EMMC2_PAD_CFGPADCTRL_CFG2TMC_EMMC2_PAD_DRVDN_COMP, 0x10),
|
|
|
|
|
APB_MISC_REG_BITS_VALUE(GP_EMMC2_PAD_CFGPADCTRL_CFG2TMC_EMMC2_PAD_DRVUP_COMP, 0x10));
|
|
|
|
|
|
|
|
|
|
/* Read to be sure our config takes. */
|
|
|
|
|
reg::Read(apb_address + APB_MISC_GP_EMMC2_PAD_CFGPADCTRL);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
public:
|
|
|
|
|
Sdmmc2Controller() : Sdmmc2And4Controller(Sdmmc2RegistersPhysicalAddress) {
|
|
|
|
|
/* ... */
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
constexpr inline dd::PhysicalAddress Sdmmc4RegistersPhysicalAddress = UINT64_C(0x700B0600);
|
|
|
|
|
|
|
|
|
|
class Sdmmc4Controller : public Sdmmc2And4Controller {
|
|
|
|
|
private:
|
|
|
|
|
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
|
|
|
|
static constinit inline os::InterruptEventType s_interrupt_event{};
|
|
|
|
|
#endif
|
|
|
|
|
protected:
|
|
|
|
|
virtual void SetPad() override {
|
|
|
|
|
if (IsSocMariko()) {
|
|
|
|
|
/* Get the apb registers address. */
|
|
|
|
|
const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
|
|
|
|
|
|
|
|
|
|
/* Enable Schmitt Trigger in emmc4 iobrick. */
|
|
|
|
|
reg::ReadWrite(apb_address + APB_MISC_GP_EMMC4_PAD_CFGPADCTRL, APB_MISC_REG_BITS_ENUM(GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_E_SCH, ENABLE));
|
|
|
|
|
|
|
|
|
|
/* Clear CMD_PULLU, CLK_PULLD, DQS_PULLD. */
|
|
|
|
|
reg::ReadWrite(apb_address + APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU, 0),
|
|
|
|
|
APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD, 0),
|
|
|
|
|
APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD, 0));
|
|
|
|
|
|
|
|
|
|
/* Read again to be sure our config takes. */
|
|
|
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reg::Read(apb_address + APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL);
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} else {
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/* On Erista, we can just leave the reset value intact. */
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}
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}
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virtual ClockResetController::Module GetClockResetModule() const override {
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return ClockResetController::Module_Sdmmc4;
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}
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#if defined(AMS_SDMMC_USE_OS_EVENTS)
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virtual int GetInterruptNumber() const override {
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return 63;
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}
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virtual os::InterruptEventType *GetInterruptEvent() const override {
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return std::addressof(s_interrupt_event);
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}
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#endif
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virtual void ClearPadParked() override {
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/* Get the apb registers address. */
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const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
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|
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/* Clear all MISC2PMC_EMMC4_*_PARK bits. */
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reg::ReadWrite(apb_address + APB_MISC_GP_EMMC4_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_CFGPADCTRL_MISC2PMC_EMMC4_ALL_PARK, 0));
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|
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|
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/* Read to be sure our config takes. */
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|
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reg::Read(apb_address + APB_MISC_GP_EMMC4_PAD_CFGPADCTRL);
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}
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virtual void SetDriveStrengthToDefaultValues(BusPower bus_power) override {
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|
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/* SDMMC4 only supports 1.8v. */
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AMS_ABORT_UNLESS(bus_power == BusPower_1_8V);
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/* Ensure that we can control registers. */
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|
|
SdHostStandardController::EnsureControl();
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|
|
|
|
|
/* Get the apb registers address. */
|
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|
|
|
const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
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|
|
/* Determine the drv up/down values. */
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|
|
u8 drvdn, drvup;
|
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|
|
if (IsSocMariko()) {
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|
|
drvdn = 0xA;
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|
|
drvup = 0xA;
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|
|
} else {
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|
|
drvdn = 0x10;
|
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|
|
drvup = 0x10;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Write the drv up/down values to APB_MISC_GP_EMMC4_PAD_CFGPADCTRL. */
|
|
|
|
|
reg::ReadWrite(apb_address + APB_MISC_GP_EMMC4_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DRVDN_COMP, drvdn),
|
|
|
|
|
APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DRVUP_COMP, drvup));
|
|
|
|
|
|
|
|
|
|
/* Read to be sure our config takes. */
|
|
|
|
|
reg::Read(apb_address + APB_MISC_GP_EMMC4_PAD_CFGPADCTRL);
|
|
|
|
|
}
|
|
|
|
|
public:
|
|
|
|
|
Sdmmc4Controller() : Sdmmc2And4Controller(Sdmmc4RegistersPhysicalAddress) {
|
|
|
|
|
/* ... */
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
}
|
